TWI758464B - Selective formation of silicon-containing spacer - Google Patents

Selective formation of silicon-containing spacer Download PDF

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TWI758464B
TWI758464B TW107113503A TW107113503A TWI758464B TW I758464 B TWI758464 B TW I758464B TW 107113503 A TW107113503 A TW 107113503A TW 107113503 A TW107113503 A TW 107113503A TW I758464 B TWI758464 B TW I758464B
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silicon
containing material
forming
substrate
semiconductor structure
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TW201903885A (en
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高拉夫 塔瑞加
吉鏞 李
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美商微材料有限責任公司
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Abstract

Processing methods may be performed to form semiconductor structures that may include nanowire structures. The methods may include forming a plasma of a fluorine-containing precursor in a remote plasma region of a processing chamber. The methods may include contacting a semiconductor substrate with effluents of the plasma, and the semiconductor substrate may be housed in a processing region of the processing chamber. The methods may include laterally recessing a silicon-containing material selectively from the semiconductor substrate. The methods may further include subsequently depositing a spacer material adjacent the silicon-containing material. The spacer material may be selectively deposited on the silicon-containing material relative to exposed regions of a gate formation and a nanowire material exposed on the substrate.

Description

含矽間隔物的選擇性形成Selective formation of silicon-containing spacers

本技術係關於半導體系統、處理、及裝備。更具體而言，本技術係關於用於在半導體裝置上選擇性蝕刻及選擇性沉積材料層的系統及方法。This technology relates to semiconductor systems, processes, and equipment. More specifically, the present technology relates to systems and methods for selectively etching and selectively depositing layers of materials on semiconductor devices.

可能藉由在基板表面上產生錯綜複雜圖案化的材料層的處理來製成積體電路。在基板上產生圖案化的材料需要用於移除暴露的材料的控制方法。化學蝕刻係用於多種目的，包括將光抗蝕劑中的圖案轉移到底下的層中、減薄層、或減薄已呈現於表面上的特徵的橫向尺寸。通常期望具有蝕刻一種材料比另一種更快的蝕刻處理，以促進例如圖案轉移處理或單獨材料移除。據說這種蝕刻處理對於第一材料具有選擇性。由於材料、電路、及處理的多樣性，已開發對多種材料具有選擇性的蝕刻處理。然而，通常使用毯覆塗層或保形填充而繼續跨越基板來執行沉積處理。Integrated circuits may be fabricated by processes that produce intricately patterned layers of material on the surface of the substrate. Creating a patterned material on a substrate requires a controlled method for removing the exposed material. Chemical etching is used for a variety of purposes, including transferring a pattern in a photoresist into an underlying layer, thinning a layer, or thinning the lateral dimensions of features already present on a surface. It is often desirable to have an etch process that etches one material faster than another to facilitate, for example, a pattern transfer process or individual material removal. This etching process is said to be selective to the first material. Due to the variety of materials, circuits, and processes, etching processes that are selective for a variety of materials have been developed. Typically, however, the deposition process continues across the substrate using a blanket coating or conformal fill.

隨著裝置尺寸在下一代裝置中持續縮小，當形成於特定層中的材料只有幾奈米時，選擇性可以發揮更大的作用（特別是當材料為電晶體形成中的關鍵時）。各種材料之間已開發許多不同的蝕刻處理選擇性，但是標準選擇性可能不再適用於當前及未來的裝置規模。此外，基於形成及保護跨越裝置的特徵的各種關鍵尺寸所需的屏蔽、形成、及移除操作的數量，處理的佇列時間繼續增加，同時在基板上的其他處執行圖案化及形成。As device dimensions continue to shrink in next-generation devices, selectivity can play a greater role when the material formed in a given layer is only a few nanometers (especially when the material is critical in transistor formation). Many different etch process selectivities have been developed between various materials, but standard selectivities may no longer apply at current and future device scales. Furthermore, based on the number of masking, forming, and removing operations required to form and protect various critical dimensions across features of the device, queue time for processing continues to increase while patterning and forming are performed elsewhere on the substrate.

因此，需要一種可用於生產高品質的裝置及結構改善的系統及方法。本技術解決了這些及其他需求。Accordingly, there is a need for a system and method that can be used to produce high quality devices and structural improvements. The present technology addresses these and other needs.

可以執行處理方法來形成可包括奈米線結構的半導體結構。該方法可以包括以下步驟：在處理腔室的遠端電漿區域中形成含氟前驅物的電漿。該方法可以包括以下步驟：使半導體基板與電漿的流出物接觸，而半導體基板可以容納在處理腔室的處理區域中。該方法可以包括以下步驟：從半導體基板選擇性橫向凹陷含矽材料。該方法可以進一步包括以下步驟：隨後相鄰於含矽材料而沉積間隔物材料。間隔物材料可以相對於暴露於基板上的閘極形成物與奈米線材料的暴露區域而選擇性沉積於含矽材料上。Processing methods can be performed to form semiconductor structures that can include nanowire structures. The method may include the step of forming a plasma of a fluorine-containing precursor in a distal plasma region of the processing chamber. The method may include the step of contacting a semiconductor substrate with the effluent of the plasma, while the semiconductor substrate may be contained in a processing region of a processing chamber. The method may include the step of selectively laterally recessing a silicon-containing material from a semiconductor substrate. The method may further include the step of subsequently depositing a spacer material adjacent to the silicon-containing material. The spacer material may be selectively deposited on the silicon-containing material relative to the exposed regions of the gate formation and nanowire material that are exposed on the substrate.

在一些實施例中，蝕刻可以在第一處理腔室中執行，而沉積可以在第二處理腔室中執行。該方法可以包括以下步驟：將半導體基板從第一處理腔室轉移到第二處理腔室，而轉移可以在不破壞真空的情況下執行。含矽材料可以包括鍺化矽。閘極形成物可以包括暴露的介電材料，而奈米線材料可以包括矽。間隔物材料可以包括金屬氮化物或金屬氧化物。該方法可以在不進行活性離子蝕刻操作的情況下執行。可以利用含矽材料相對於閘極形成物與奈米線材料大於或約10：1的選擇性來執行蝕刻。可以利用含矽材料相對於閘極形成物與奈米線材料大於或約2：1的選擇性來執行沉積。選擇性沉積間隔物材料之步驟可以包括以下步驟：在含矽材料上形成自組裝單層。自組裝單層可以與用於形成間隔物材料的一或更多個前驅物相互作用。In some embodiments, etching may be performed in a first processing chamber and deposition may be performed in a second processing chamber. The method may include the steps of transferring the semiconductor substrate from the first processing chamber to the second processing chamber, and the transfer may be performed without breaking the vacuum. The silicon-containing material may include silicon germanium. The gate formation may include exposed dielectric material, and the nanowire material may include silicon. Spacer materials may include metal nitrides or metal oxides. The method can be performed without a reactive ion etching operation. Etching may be performed with a selectivity of silicon-containing material relative to gate former and nanowire material greater than or about 10:1. Deposition may be performed with greater than or about a 2:1 selectivity of silicon-containing material to gate former and nanowire material. The step of selectively depositing the spacer material may include the step of forming a self-assembled monolayer on the silicon-containing material. The self-assembled monolayer can interact with one or more precursors used to form the spacer material.

本技術亦可包括一種形成半導體基板的方法。該方法可以包括以下步驟：相對於第二含矽材料橫向蝕刻第一含矽材料。第一含矽材料與第二含矽材料可以彼此垂直設置，而第一含矽材料可以垂直地定位於第二含矽材料的二個區域之間。該方法可以包括以下步驟：在藉由第二含矽材料的二個區域之間的橫向蝕刻而限定的凹部內形成間隔物材料。該方法亦可以包括以下步驟：選擇性使間隔物材料凹陷，以分離單獨的間隔物。The present technology may also include a method of forming a semiconductor substrate. The method may include the step of laterally etching the first silicon-containing material relative to the second silicon-containing material. The first silicon-containing material and the second silicon-containing material may be disposed perpendicular to each other, and the first silicon-containing material may be vertically positioned between the two regions of the second silicon-containing material. The method may include the step of forming a spacer material within a recess defined by lateral etching between two regions of the second silicon-containing material. The method may also include the step of selectively recessing the spacer material to separate individual spacers.

在一些實施例中，第二含矽材料包含矽。間隔物材料可以選自含碳材料、含氮材料、及含氧材料所組成的群組。第一含矽材料可以從閘極形成物的兩側而部分凹陷。第一含矽材料可以包括鍺化矽。蝕刻可以在第一處理腔室中執行，而沉積可以在第二處理腔室中執行。該方法亦可以包括以下步驟：將半導體基板從第一處理腔室轉移到第二處理腔室，而轉移可以在不破壞真空的情況下執行。該方法可以在不進行活性離子蝕刻操作的情況下執行。可以利用第一含矽材料相對於第二含矽材料大於或約10：1的選擇性來執行蝕刻。可以利用第一含矽材料相對於第二含矽材料大於或約2：1的選擇性來執行沉積。In some embodiments, the second silicon-containing material includes silicon. The spacer material may be selected from the group consisting of carbon-containing materials, nitrogen-containing materials, and oxygen-containing materials. The first silicon-containing material may be partially recessed from both sides of the gate formation. The first silicon-containing material may include silicon germanium. Etching can be performed in a first processing chamber and deposition can be performed in a second processing chamber. The method may also include the step of transferring the semiconductor substrate from the first processing chamber to the second processing chamber, and the transfer may be performed without breaking the vacuum. The method can be performed without a reactive ion etching operation. The etch may be performed with a selectivity of the first silicon-containing material relative to the second silicon-containing material greater than or about 10:1. The deposition may be performed with a selectivity of the first silicon-containing material relative to the second silicon-containing material greater than or about 2:1.

這樣的技術可以提供優於習知系統及技術的許多益處。舉例而言，處理可以藉由利用不包括活性離子蝕刻的技術來保護關鍵尺寸，並提供改善的選擇性。此外，藉由執行選擇性操作，可以執行更少的屏蔽及移除操作，這可以顯著減少製造佇列時間。結合以下描述及隨附圖式，更詳細地描述這些及其他實施例以及其許多優點及特徵。Such techniques may provide many benefits over conventional systems and techniques. For example, processing can protect critical dimensions and provide improved selectivity by utilizing techniques that do not include reactive ion etching. Furthermore, by performing selective operations, fewer masking and removal operations can be performed, which can significantly reduce manufacturing queue time. These and other embodiments, along with their many advantages and features, are described in more detail in conjunction with the following description and accompanying drawings.

本發明的技術包括用於小節距特徵的半導體處理的系統及部件。在傳統閘極四周及其他電晶體結構中，可以在具有待維護的相似或不同材料的結構旁邊形成並蝕刻基板上的材料。舉例而言，因為蓋層與間隔物可以由類似的材料形成（例如，氮化矽），所以用於移除這些層的蝕刻處理可能無法提供相對於其他關鍵特徵的足夠的選擇性。在各種凹陷處理期間，多個臨界尺寸的大小可能造成負載效應，而蝕刻超過材料的預計可用性。舉例而言，傳統處理可以包括遮罩層，隨後是允許打開間隙填充層的結構的活性離子蝕刻（「RIE」）處理。儘管RIE蝕刻係為相對各向異性處理，但是RIE蝕刻仍可能具有造成側壁損失的選擇性。儘管可能考慮對於形成期間的此損失進行預算（例如，利用材料的過度形成），但是因為所蝕刻的結構內的區域具有不同的尺寸，因此針對一個區域的損失量的計算可能並不適合針對更大區域的損失量。因此，儘管在預算的一個區段中可能出現5nm的損失，但是仍可能出現6-7nm的較大區段的損失，而造成可能在後續操作期間延長的製造期間的不匹配。The techniques of the present invention include systems and components for semiconductor processing of fine pitch features. In conventional gate perimeter and other transistor structures, the material on the substrate can be formed and etched next to the structure with similar or different materials to be maintained. For example, because cap layers and spacers can be formed of similar materials (eg, silicon nitride), the etch process used to remove these layers may not provide sufficient selectivity with respect to other critical features. During various recessing processes, multiple critical dimension sizes can cause loading effects that etch beyond the expected availability of the material. For example, a conventional process may include a mask layer followed by a reactive ion etching ("RIE") process that allows the structure of the gapfill layer to be opened. Although RIE etch is a relatively anisotropic process, RIE etch may still have selectivity that causes sidewall loss. While it may be possible to consider budgeting for this loss during formation (eg, with over-formation of material), since the regions within the etched structure are of different sizes, the calculation of the amount of loss for one region may not be appropriate for larger area losses. Thus, while a 5nm loss may occur in one segment of the budget, a larger segment loss of 6-7nm may still occur, creating a mismatch during fabrication that may be extended during subsequent operations.

此外，RIE處理產生蝕刻副產物或聚合物殘留物（通常利用灰化及濕式蝕刻處理移除）。灰化處理會影響含碳材料，因此若利用RIE凹陷的材料本身包括碳，則灰化處理可能清除所維護的材料中的碳。此外，濕式蝕刻經常將側壁保護層過度蝕刻而超過臨界尺寸（這會造成相鄰電晶體層的形成及間隔問題），並進一步蝕刻低k氮化物間隔物以及層間介電氧化物。通常利用各向異性蝕刻進行金屬材料與介電質的移除，除非形成附加屏蔽或保護層，否則可能進一步減少其他區域中的蓋材料與間隔物材料的暴露區域。由於這種RIE移除的選擇性可能在10：1的範圍內，因此所需的屏蔽量可能很大。Additionally, the RIE process produces etch by-products or polymer residues (usually removed using ashing and wet etch processes). The ashing process affects the carbonaceous material, so if the material indented with the RIE itself includes carbon, the ashing process may remove carbon from the material being maintained. In addition, wet etching often overetches the sidewall protection layer beyond the critical dimension (which can cause formation and spacing problems for adjacent transistor layers), and further etches low-k nitride spacers and interlayer dielectric oxides. The removal of metallic materials and dielectrics is typically performed using anisotropic etching, which may further reduce the exposed areas of cap and spacer materials in other areas unless additional shielding or protective layers are formed. Since the selectivity of such RIE removal may be in the range of 10:1, the amount of shielding required may be large.

在利用跨越半導體基板上的所有暴露區域的材料的毯覆塗層或材料的共形發展的習知技術中，可以進行遮罩材料與其他材料層二者的沉積。這些類型的沉積可能需要進一步的圖案化與移除操作，這會顯著增加裝置製造的佇列時間。在RIE移除的附加操作及缺陷與習知沉積中使用的多種操作之間，單獨裝置層的佇列時間可能增加幾小時。Deposition of both mask material and other material layers can be performed in conventional techniques utilizing blanket coatings of material or conformal development of material across all exposed areas on a semiconductor substrate. These types of depositions may require further patterning and removal operations, which can significantly increase the queue time for device fabrication. Between the additional operations and defects of RIE removal and the various operations used in conventional depositions, the queue time of individual device layers may increase by several hours.

本技術藉由修改用於移除及形成的處理而克服這些問題。藉由利用在特定裝備中執行的選擇性蝕刻處理，可以使用該等處理，以利用比習知RIE更高的選擇性來蝕刻，這可允許先前可能無法的附加圖案化操作，並且可以為關鍵特徵尺寸提供額外的保護。此外，藉由在特定裝備中執行選擇性沉積操作，可以在結構形成中利用減少的屏蔽、圖案化、及移除操作。相較於利用RIE與標準沉積的習知處理，這些處理可以節省數小時，並且可以保護沉積材料免於RIE清除，以產生改善的結構。The present technology overcomes these problems by modifying the process for removal and formation. By utilizing selective etch processes performed in specific equipment, these processes can be used to etch with higher selectivity than conventional RIE, which can allow for additional patterning operations that may not have been possible previously, and can be critical Feature size provides additional protection. Furthermore, by performing selective deposition operations in specific equipment, reduced masking, patterning, and removal operations can be utilized in structure formation. These processes can save hours compared to conventional processes utilizing RIE and standard deposition, and can protect the deposited material from RIE removal, resulting in improved structures.

儘管其餘的揭示將常規地識別利用所揭示的技術的特定的蝕刻及沉積處理，但應理解，系統及方法同樣適用於所描述的腔室中可能發生的各種其他的蝕刻、沉積、及清潔處理。因此，該技術不應視為受限於僅能用於所述的蝕刻及沉積處理。本揭示將論述可以與本技術一起使用的一個可能的系統及腔室，以在根據本技術的示例性處理序列的所描述操作之前執行某些移除及沉積操作。While the remainder of the disclosure will routinely identify specific etching and deposition processes utilizing the disclosed techniques, it should be understood that the systems and methods are equally applicable to various other etching, deposition, and cleaning processes that may occur in the described chambers . Therefore, this technique should not be considered limited to only the etch and deposition processes described. This disclosure will discuss one possible system and chamber that may be used with the present technology to perform certain removal and deposition operations prior to the described operations of an exemplary processing sequence in accordance with the present technology.

第1圖圖示根據實施例的沉積、蝕刻、烘焙、及固化腔室的處理系統100的一個實施例的頂視平面圖。在圖式中，一對前開式聯合晶圓盒（FOUP）102供應各種尺寸的基板，各種尺寸的基板係由機器臂104接收，並在放置到位於串聯區段109a-c中的基板處理腔室108a-f中之一者之前，放置到低壓托持區域106中。第二機器臂110可用於將基板晶圓從托持區域106運輸到基板處理腔室108a-f並返回。除了循環層沉積（CLD）、原子層沉積（ALD）、化學氣相沉積（CVD）、物理氣相沉積（PVD）、濕式蝕刻、預清潔、脫氣、定向、及其他基板處理之外，可以配備每一基板處理腔室108a-f，以執行包括本文所述的乾式蝕刻處理及選擇性沉積的大量基板處理操作。FIG. 1 illustrates a top plan view of one embodiment of a processing system 100 for deposition, etch, bake, and cure chambers in accordance with an embodiment. In the figure, a pair of front-opening union pods (FOUPs) 102 supply substrates of various sizes, which are received by robotic arms 104 and placed into substrate processing chambers located in inline sections 109a-c One of the chambers 108a-f is placed into the low pressure holding area 106. The second robotic arm 110 may be used to transport substrate wafers from the holding area 106 to the substrate processing chambers 108a-f and back. In addition to cyclic layer deposition (CLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), wet etching, pre-cleaning, degassing, orientation, and other substrate treatments, Each substrate processing chamber 108a-f may be equipped to perform a number of substrate processing operations including the dry etch processes and selective deposition described herein.

基板處理腔室108a-f可包括用於沉積、退火、固化、及/或蝕刻基板晶圓上的介電膜的一或更多個系統部件。在一個配置中，可以使用兩對處理腔室（例如，108c-d與108e-f），以在基板上沉積介電材料或含金屬材料，而第三對處理腔室（例如108a-b）可以用於蝕刻所沉積的介電質。在另一配置中，所有三對腔室（例如，108a-f）可經配置以蝕刻基板上的介電膜。可以在與不同實施例中所示的製造系統分離的腔室中執行所述的任何一或更多個處理。The substrate processing chambers 108a-f may include one or more system components for depositing, annealing, curing, and/or etching dielectric films on substrate wafers. In one configuration, two pairs of processing chambers (eg, 108c-d and 108e-f) may be used to deposit dielectric or metal-containing materials on the substrate, while a third pair of processing chambers (eg, 108a-b) Can be used to etch deposited dielectrics. In another configuration, all three pairs of chambers (eg, 108a-f) may be configured to etch the dielectric film on the substrate. Any one or more of the processes described may be performed in a separate chamber from the manufacturing system shown in the various embodiments.

在一些實施例中，腔室具體包括如下所述的至少一個蝕刻腔室以及如下所述的至少一個沉積腔室。藉由包括這些腔室並組合工廠介面的處理側，可以在受控環境中執行以下所述的所有蝕刻及沉積處理。舉例而言，在托持區域106的處理側可以維持真空環境，而使得在實施例中的所有腔室及轉移均維持在真空下。此舉亦可限制水蒸氣及其他空氣成分接觸處理中的基板。應理解，系統100可以考慮用於介電膜的沉積、蝕刻、退火、及固化腔室的附加配置。In some embodiments, the chamber specifically includes at least one etching chamber as described below and at least one deposition chamber as described below. By including these chambers and combining the process side of the factory interface, all etch and deposition processes described below can be performed in a controlled environment. For example, a vacuum environment may be maintained on the processing side of the holding region 106 such that all chambers and transfers in embodiments are maintained under vacuum. This also limits the contact of water vapor and other air components with the substrate being processed. It should be appreciated that system 100 may contemplate additional configurations of chambers for deposition, etching, annealing, and curing of dielectric films.

第2A圖圖示在處理腔室內具有分隔的電漿產生區域的示例性處理腔室系統200的橫截面圖。在膜蝕刻期間（例如，氮化鈦、氮化鉭、鎢、鈷、氧化鋁、氧化鎢、矽、多晶矽、氧化矽、氮化矽、氮氧化矽、碳氧化矽等），處理氣體可以通過氣體入口組件205流入第一電漿區域215。遠端電漿系統（RPS）201可以可選擇地包括在系統中，並且可以處理隨後行進通過氣體入口組件205的第一氣體。入口組件205可以包括二或更多個不同的氣體供應通道，其中若包括第二通道（未圖示），則第二通道可以繞過RPS 201。2A illustrates a cross-sectional view of an exemplary processing chamber system 200 having separate plasma generating regions within the processing chamber. During film etching (eg, titanium nitride, tantalum nitride, tungsten, cobalt, aluminum oxide, tungsten oxide, silicon, polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, etc.), the process gas can pass through The gas inlet assembly 205 flows into the first plasma region 215 . A remote plasma system (RPS) 201 may optionally be included in the system and may process the first gas that then travels through the gas inlet assembly 205 . The inlet assembly 205 may include two or more distinct gas supply channels, where a second channel (not shown), if included, may bypass the RPS 201 .

圖示冷卻板203、面板217、離子抑制器223、噴淋頭225、及具有基板255設置其上的基板支撐件265，且每一者可以根據實施例而被包括。台座265可以具有熱交換通道，熱交換流體流經熱交換通道以控制基板的溫度，可在處理操作期間操作基板的溫度，以加熱及/或冷卻基板或晶圓。亦可以使用嵌入式電阻加熱器元件而電阻加熱可以包含鋁、陶瓷、或其組合的台座265的晶圓支撐盤，以實現相對高的溫度，例如從高達或約100℃至高於或約1100℃的溫度。Cooling plate 203, faceplate 217, ion suppressor 223, showerhead 225, and substrate support 265 with substrate 255 disposed thereon are shown, and each may be included according to embodiments. The pedestal 265 may have heat exchange channels through which a heat exchange fluid flows to control the temperature of the substrate, which may be manipulated during processing operations to heat and/or cool the substrate or wafer. Embedded resistive heater elements may also be used to resistively heat the wafer support tray, which may include a pedestal 265 of aluminum, ceramic, or a combination thereof, to achieve relatively high temperatures, such as from up to or about 100°C to above or about 1100°C temperature.

面板217可以是金字塔形、圓錐形、或具有窄的頂部部分擴展到寬的底部部分的其他類似結構。如圖所示，附加地，面板217可以是平坦的，並包括用於分配處理氣體的複數個貫通通道。取決於RPS 201的使用，電漿產生氣體及/或電漿激發物質可以穿過面板217中如第2B圖所示的複數個孔洞，以更均勻地遞送到第一電漿區域215中。The panels 217 may be pyramidal, conical, or other similar structures with a narrow top portion extending to a wide bottom portion. As shown, the panel 217 may additionally be flat and include a plurality of through channels for distributing process gases. Depending on the use of RPS 201 , plasma generating gas and/or plasma excitation species may pass through a plurality of holes in panel 217 as shown in FIG. 2B for more uniform delivery into first plasma region 215 .

示例性配置可以包括使氣體入口組件205通入藉由面板217從第一電漿區域215分隔的氣體供應區域258，而使得氣體/物質流經面板217中的孔洞而進入第一電漿區域215。可以選擇結構及操作特徵，以防止來自第一電漿區域215的電漿大量回流到供應區域258、氣體入口組件205、及流體供應系統210中。圖示面板217或者腔室的導電頂部部分以及噴淋頭225具有位於特徵之間的絕緣環220，其允許相對於噴淋頭225及/或離子抑制器223而將AC電位施加到面板217。絕緣環220可以定位於面板217與噴淋頭225及/或離子抑制器223之間，以讓電容耦合電漿（CCP）能夠在第一電漿區域中形成。附加地，擋板（未圖示）可以位於第一電漿區域215中，或者另外與氣體入口組件205耦接，以影響流體通過氣體入口組件205進入區域的流動。Exemplary configurations may include passing the gas inlet assembly 205 into the gas supply region 258 separated from the first plasma region 215 by the faceplate 217 , while allowing the gas/substance to flow through holes in the faceplate 217 into the first plasma region 215 . The structural and operating characteristics may be selected to prevent substantial backflow of plasma from the first plasma region 215 into the supply region 258 , the gas inlet assembly 205 , and the fluid supply system 210 . The panel 217 or the conductive top portion of the chamber and the showerhead 225 are shown with insulating rings 220 between the features that allow an AC potential to be applied to the panel 217 relative to the showerhead 225 and/or the ion suppressor 223 . Insulation ring 220 may be positioned between panel 217 and showerhead 225 and/or ion suppressor 223 to allow capacitively coupled plasma (CCP) to form in the first plasma region. Additionally, a baffle (not shown) may be located in the first plasma region 215 or otherwise coupled to the gas inlet assembly 205 to affect the flow of fluids through the gas inlet assembly 205 into the region.

離子抑制器223可以包含限定貫穿結構的複數個孔隙的板狀或其他幾何形狀，複數個孔隙經配置以抑制離開第一電漿區域215的離子帶電物質的遷移，同時允許不帶電荷的中性或自由基物質穿過離子抑制器223進入抑制器與噴淋頭之間的活性氣體遞送區域。在實施例中，離子抑制器223可以包含具有各種孔隙配置的多孔板。這些不帶電荷的物質可以包括利用較少的活性載氣運輸通過孔隙的高活性物質。如上所述，離子物質通過孔洞的遷移可能減少，並在一些情況下完全抑制。控制穿過離子抑制器223的離子物質的量可以有利地提供對於與底下的晶圓基板接觸的氣體混合物的增加控制，這又可以增加對氣體混合物的沉積及/或蝕刻特性的控制。舉例而言，氣體混合物的離子濃度的調整可以顯著改變其蝕刻選擇性，例如，SiNx：SiOx蝕刻率、Si：SiOx蝕刻率等。在執行沉積的可替代實施例中，亦可以平移介電材料的共形流動式沉積的平衡。The ion suppressor 223 may comprise a plate or other geometry defining a plurality of apertures throughout the structure, the plurality of apertures being configured to inhibit migration of ionically charged species leaving the first plasmonic region 215 while allowing uncharged neutrality Or free radical species pass through ion suppressor 223 into the reactive gas delivery area between the suppressor and the showerhead. In an embodiment, the ion suppressor 223 may comprise a porous plate with various pore configurations. These uncharged species may include highly reactive species transported through the pores with less active carrier gas. As mentioned above, the migration of ionic species through the pores may be reduced, and in some cases completely suppressed. Controlling the amount of ionic species passing through ion suppressor 223 may advantageously provide increased control over the gas mixture in contact with the underlying wafer substrate, which in turn may increase control over the deposition and/or etch characteristics of the gas mixture. For example, adjustment of the ion concentration of a gas mixture can significantly alter its etch selectivity, eg, SiNx:SiOx etch rate, Si:SiOx etch rate, and the like. In an alternative embodiment where deposition is performed, the balance of conformal flow deposition of dielectric material may also be shifted.

離子抑制器223中的複數個孔隙可經配置以控制活性氣體（亦即，離子、自由基、及/或中性物質）通過離子抑制器223。舉例而言，可以控制孔洞的高寬比、或孔洞直徑對長度的比、及/或孔洞的幾何形狀，而使得穿過離子抑制器223的活性氣體中的離子帶電物質的流動減少。離子抑制器223中的孔洞可以包括面對電漿激發區域215的錐形部分以及面對噴淋頭225的圓柱形部分。圓柱形部分可以成形及定尺寸，以控制傳到噴淋頭225的離子物質的流動。作為控制離子物質通過抑制器的流動的附加手段，亦可以將可調整的電偏壓施加到離子抑制器223。The plurality of apertures in the ion suppressor 223 may be configured to control the passage of reactive gases (ie, ions, radicals, and/or neutral species) through the ion suppressor 223 . For example, the aspect ratio of the holes, or the ratio of hole diameter to length, and/or the geometry of the holes can be controlled such that the flow of ionically charged species in the reactive gas through the ion suppressor 223 is reduced. The holes in the ion suppressor 223 may include a tapered portion facing the plasma excitation region 215 and a cylindrical portion facing the showerhead 225 . The cylindrical portion may be shaped and dimensioned to control the flow of ionic species to showerhead 225. As an additional means of controlling the flow of ionic species through the suppressor, an adjustable electrical bias may also be applied to the ion suppressor 223.

離子抑制器223可以用於減少或消除從電漿產生區域行進到基板的離子帶電物質的量。不帶電的中性及自由基物質仍然可以穿過離子抑制器中的開口而與基板反應。應注意，在實施例中，可以不執行在環繞基板的反應區域中的離子帶電物質的完全消除。在某些情況下，離子物質意欲到達基板，以執行蝕刻及/或沉積處理。在這些情況下，離子抑制器可以幫助將反應區域中的離子物質濃度控制在有助於處理的層級處。The ion suppressor 223 can be used to reduce or eliminate the amount of ionically charged species traveling from the plasma generating region to the substrate. Uncharged neutral and free radical species can still pass through openings in the ion suppressor to react with the substrate. It should be noted that in embodiments, complete elimination of ionically charged species in the reaction region surrounding the substrate may not be performed. In some cases, ionic species are intended to reach the substrate to perform etching and/or deposition processes. In these cases, an ion suppressor can help control the concentration of ionic species in the reaction zone at levels that facilitate processing.

與離子抑制器223組合的噴淋頭225可以允許電漿存在於第一電漿區域215中，以避免在基板處理區域233中直接激發氣體，同時仍允許激發物質從腔室電漿區域215行進到基板處理區域233。以此方式，腔室可經配置以防止電漿接觸蝕刻中的基板255。此舉可以有利地保護基板上圖案化的各種複雜結構及膜，若直接與所產生的電漿接觸，則各種複雜結構及膜可能損傷、移位、或以其他方式彎曲。此外，當允許電漿接觸基板或接近基板層級時，可能增加氧化物物質蝕刻的速率。因此，若材料的暴露區域為氧化物，則可以藉由遠離基板維持電漿來進一步保護此材料。Showerhead 225 in combination with ion suppressor 223 can allow plasma to exist in first plasma region 215 to avoid direct excitation of gases in substrate processing region 233 while still allowing excitation species to travel from chamber plasma region 215 to the substrate processing area 233. In this manner, the chamber can be configured to prevent the plasma from contacting the substrate 255 under etching. This can advantageously protect various complex structures and films patterned on the substrate, which may be damaged, displaced, or otherwise bent if in direct contact with the generated plasma. In addition, when the plasma is allowed to contact the substrate or near the substrate level, it is possible to increase the rate of oxide species etching. Thus, if the exposed areas of the material are oxides, the material can be further protected by maintaining the plasma away from the substrate.

處理系統可以進一步包括與處理腔室電耦接的功率供應器240，以提供電功率到面板217、離子抑制器223、噴淋頭225、及/或台座265，以在第一電漿區域215或處理區域233中產生電漿。取決於所執行的處理，功率供應器可經配置以向腔室遞送可調整量的功率。這種配置可以允許可調諧電漿用於執行中的處理。與通常呈現為具有開啟或關閉功能的遠端電漿單元不同，可調諧電漿可經配置以向電漿區域215遞送特定量的功率。此舉又可以允許形成特定的電漿特性，而使得前驅物可以利用特定方式解離，以增強由這些前驅物產生的蝕刻輪廓。The processing system may further include a power supply 240 electrically coupled to the processing chamber to provide electrical power to the panel 217, the ion suppressor 223, the showerhead 225, and/or the pedestal 265 for use in the first plasma region 215 or Plasma is generated in the processing region 233 . Depending on the processing performed, the power supply can be configured to deliver an adjustable amount of power to the chamber. This configuration may allow tunable plasma to be used for ongoing processing. Unlike remote plasma cells, which are typically presented with an on or off function, the tunable plasma can be configured to deliver a specific amount of power to the plasma region 215. This in turn may allow for the formation of specific plasmonic properties that allow precursors to dissociate in specific ways to enhance the etch profile produced by these precursors.

可以在噴淋頭225上方的腔室電漿區域215或噴淋頭225下方的基板處理區域233中激發電漿。在實施例中，形成於基板處理區域233中的電漿可以是利用作為電極的台座形成的DC偏壓電漿。電漿可以存在於腔室電漿區域215中，以從例如含氟前驅物或其他前驅物的流入產生自由基前驅物。典型地，在射頻（RF）範圍中的AC電壓可以施加於處理腔室的導電頂部部分（例如，面板217）與噴淋頭225及/或離子抑制器223之間，以在沉積期間激發腔室電漿區域215中的電漿。RF功率供應器可以產生13.56MHz的高RF頻率，但亦可以單獨產生其他頻率或與13.56MHz頻率組合產生其他頻率。Plasma may be excited in the chamber plasma region 215 above the showerhead 225 or in the substrate processing region 233 below the showerhead 225 . In an embodiment, the plasma formed in the substrate processing region 233 may be a DC biased plasma formed using a pedestal as an electrode. Plasma may be present in the chamber plasma region 215 to generate radical precursors from the influx of, for example, fluorine-containing precursors or other precursors. Typically, an AC voltage in the radio frequency (RF) range can be applied between the conductive top portion of the processing chamber (eg, panel 217 ) and the showerhead 225 and/or ion suppressor 223 to excite the chamber during deposition Plasma in chamber plasma region 215 . The RF power supply can generate a high RF frequency of 13.56MHz, but can also generate other frequencies alone or in combination with the 13.56MHz frequency.

第2B圖圖示影響通過面板217的處理氣體分佈的特徵的詳細視圖253。如第2A圖及第2B圖所示，面板217、冷卻板203、及氣體入口組件205相交，以限定氣體供應區域258，其中處理氣體可以從氣體入口205遞送進入氣體供應區域258。氣體可以填充氣體供應區域258，並通過面板217中的孔隙259流到第一電漿區域215。孔隙259可經配置以基本上單向的方式引導流動，而使得處理氣體可以流入處理區域233中，但是在穿過面板217之後可以被部分或完全防止回流到氣體供應區域258中。FIG. 2B illustrates a detailed view 253 of features affecting process gas distribution through panel 217 . As shown in Figures 2A and 2B, the panel 217, the cooling plate 203, and the gas inlet assembly 205 intersect to define a gas supply region 258 into which process gas can be delivered from the gas inlet 205. Gas may fill gas supply region 258 and flow to first plasma region 215 through apertures 259 in panel 217 . Apertures 259 may be configured to direct flow in a substantially unidirectional manner such that process gas may flow into process region 233 , but may be partially or completely prevented from flowing back into gas supply region 258 after passing through panel 217 .

氣體分配組件（例如，用於處理腔室區段200中的噴淋頭225）可以指稱為雙通道噴淋頭（DCSH），並附加地在第3圖所述的實施例中詳細說明。雙通道噴淋頭可以提供蝕刻處理，以允許在處理區域233之外分離蝕刻劑，以在遞送到處理區域之前提供與腔室部件及彼此間的受限的相互作用。The gas distribution assembly (eg, showerhead 225 used in process chamber section 200 ) may be referred to as a dual channel showerhead (DCSH) and is additionally detailed in the embodiment depicted in FIG. 3 . A dual channel showerhead may provide an etch process to allow for etchant separation outside the process area 233 to provide limited interaction with chamber components and each other prior to delivery to the process area.

噴淋頭225可以包含上板214及下板216。這些板可以彼此耦接，以限定這些板之間的容積218。板的耦接可以提供通過上及下板的第一流體通道219以及通過下板216的第二流體通道221。所形成的通道可經配置以提供從容積218單獨經由第二流體通道221通過下板216的流體出入口，而第一流體通道219可以流體隔離於板與第二流體通道221之間的容積218。容積218可以通過氣體分配組件225的一側流體出入。The showerhead 225 may include an upper plate 214 and a lower plate 216 . The plates may be coupled to each other to define the volume 218 between the plates. Coupling of the plates may provide a first fluid channel 219 through the upper and lower plates and a second fluid channel 221 through the lower plate 216 . The channels formed can be configured to provide fluid access from the volume 218 through the lower plate 216 via the second fluid channel 221 alone, while the first fluid channel 219 can be fluidly isolated from the volume 218 between the plate and the second fluid channel 221 . Volume 218 can be fluidly accessed through one side of gas distribution assembly 225 .

第3圖係為根據實施例的與處理腔室一起使用的噴淋頭325的底視圖。噴淋頭325可以對應於第2A圖所示的噴淋頭225。通孔365（圖示第一流體通道219的視圖）可以具有複數種形狀及配置，以控制及影響前驅物通過噴淋頭225的流動。小孔洞375（圖示第二流體通道221的視圖）可以基本均勻地分佈在噴淋頭的表面上（即使在通孔365中），並且可以有助於前驅物在離開噴淋頭時提供比其他配置更均勻的混合。FIG. 3 is a bottom view of a showerhead 325 for use with a processing chamber, according to an embodiment. The showerhead 325 may correspond to the showerhead 225 shown in FIG. 2A. The through-holes 365 (illustrating the view of the first fluid channel 219 ) may have a variety of shapes and configurations to control and influence the flow of the precursor through the showerhead 225 . The small holes 375 (showing the view of the second fluid channel 221 ) can be substantially evenly distributed over the surface of the showerhead (even in the through holes 365 ) and can help the precursors provide a specific ratio as they exit the showerhead. Other configurations are more evenly mixed.

轉到第4圖，圖示根據本技術的一或更多個實施例的原子層沉積系統400或反應器的示意性橫截面圖。系統400可以包括裝載閘腔室10與處理腔室20。處理腔室20通常可以是可密封的外殼，其可以在真空或至少低壓下操作。處理腔室20可以藉由隔離閥15與裝載閘腔室10隔離。隔離閥15可以將處理腔室20與裝載閘腔室10密封於關閉位置，並可允許在打開位置時將基板60從裝載閘腔室10通過閥轉移至處理腔室20，反之亦然。Turning to Figure 4, illustrated is a schematic cross-sectional view of an atomic layer deposition system 400 or reactor in accordance with one or more embodiments of the present technology. System 400 may include load lock chamber 10 and process chamber 20 . The processing chamber 20 can generally be a sealable enclosure that can operate under vacuum or at least low pressure. Process chamber 20 may be isolated from load lock chamber 10 by isolation valve 15 . The isolation valve 15 can seal the process chamber 20 from the load gate chamber 10 in the closed position and can allow the substrate 60 to be valved from the load gate chamber 10 to the process chamber 20 and vice versa when in the open position.

系統400可包括氣體分配板30，氣體分配板30能夠跨越基板60分配一或更多種氣體。氣體分配板30可以是該領域具有通常知識者已知的任何合適的分配板，且所述之特定氣體分配板不應視為限制本技術之範疇。氣體分配板30之輸出面可以面向基板60的第一表面61。System 400 may include gas distribution plate 30 capable of distributing one or more gases across substrate 60 . The gas distribution plate 30 may be any suitable distribution plate known to those of ordinary skill in the art, and the particular gas distribution plate described should not be construed as limiting the scope of the present technology. The output surface of the gas distribution plate 30 may face the first surface 61 of the substrate 60 .

氣體分配板30可以包括複數個氣體埠與複數個真空埠，複數個氣體埠經配置以傳送一或更多個氣體流到基板60，而複數個真空埠係設置於每一氣體埠之間，並經配置以傳送氣體流到處理腔室20之外。如第4圖所示，氣體分配板30可以包括第一前驅物注射器420、第二前驅物注射器430、及吹掃氣體注射器440。注射器420、430、440可藉由系統電腦（未圖示）（例如，主機）控制，或藉由腔室特定控制器（例如，可程式化邏輯控制器）控制。前驅物注射器420可經配置以將化合物A的活性前驅物之連續或脈衝流通過複數個氣體埠425注射進入處理腔室20。前驅物注射器430可經配置以將化合物B的活性前驅物之連續或脈衝流通過複數個氣體埠435注射進入處理腔室20。吹掃氣體注射器440可經配置以將無活性或吹掃氣體之連續或脈衝流通過複數個氣體埠445注射進入處理腔室20。吹掃氣體可經配置以從處理腔室20移除活性材料及活性副產物。吹掃氣體典型係為惰性氣體，例如，氮氣、氬氣、及氦氣。氣體埠445可設置於氣體埠425及氣體埠435之間，以從化合物B之前軀物分離化合物A之前驅物，藉此避免前驅物之間的交叉汙染。The gas distribution plate 30 may include a plurality of gas ports and a plurality of vacuum ports, the plurality of gas ports are configured to transmit one or more gas flows to the substrate 60, and the plurality of vacuum ports are disposed between each gas port, and is configured to deliver the gas flow out of the processing chamber 20 . As shown in FIG. 4 , the gas distribution plate 30 may include a first precursor injector 420 , a second precursor injector 430 , and a purge gas injector 440 . The injectors 420, 430, 440 may be controlled by a system computer (not shown) (eg, a host computer), or by a chamber-specific controller (eg, a programmable logic controller). The precursor injector 420 may be configured to inject a continuous or pulsed flow of the active precursor of Compound A through the plurality of gas ports 425 into the processing chamber 20 . Precursor injector 430 may be configured to inject a continuous or pulsed flow of the active precursor of Compound B into process chamber 20 through a plurality of gas ports 435 . The purge gas injector 440 may be configured to inject a continuous or pulsed flow of inert or purge gas into the process chamber 20 through the plurality of gas ports 445 . The purge gas may be configured to remove active materials and active by-products from the processing chamber 20 . Purge gases are typically inert gases such as nitrogen, argon, and helium. The gas port 445 can be disposed between the gas port 425 and the gas port 435 to separate the compound A precursor from the compound B precursor, thereby avoiding cross-contamination between the precursors.

在另一態樣中，在將前驅物注射進入處理腔室20之前，遠端電漿源（未圖示）可連接至前驅物注射器420及前驅物注射器430。可以藉由將電場施加到遠端電漿源內的化合物來產生活性物質之電漿。可以使用能夠活化所意欲化合物的任何功率源。舉例而言，使用DC、射頻、及微波型放電技術的功率源可以使用。若使用RF功率源，則可以電容性或電感性耦接。亦可以藉由熱基礎技術、氣體解離技術、高強度光源（例如，紫外光源）、或暴露於x射線源來產生活化。In another aspect, a remote plasma source (not shown) may be connected to precursor injector 420 and precursor injector 430 prior to injecting the precursor into processing chamber 20 . Plasma of active species can be generated by applying an electric field to a compound within a remote plasma source. Any power source capable of activating the desired compound can be used. For example, power sources using DC, radio frequency, and microwave type discharge techniques can be used. If an RF power source is used, it can be capacitively or inductively coupled. Activation can also be produced by thermal based techniques, gas dissociation techniques, high intensity light sources (eg, UV light sources), or exposure to x-ray sources.

系統400可以進一步包括連接至處理腔室20的泵送系統450。泵送系統450大致上可經配置以通過一或更多個真空埠455將氣體流抽空到處理腔室20之外。真空埠455可設置於每一氣體埠之間，以在氣體流與基板表面反應之後將氣體流抽空到處理腔室20之外，並進一步限制前驅物之間的交叉汙染。System 400 may further include a pumping system 450 coupled to process chamber 20 . The pumping system 450 may generally be configured to evacuate the gas flow out of the processing chamber 20 through one or more vacuum ports 455 . A vacuum port 455 may be provided between each gas port to evacuate the gas flow out of the processing chamber 20 after the gas flow reacts with the substrate surface and further limit cross-contamination between precursors.

系統400可包括設置於處理腔室20上並在每一埠之間的複數個分區460。每一分區的下部可以延伸靠近基板60的第一表面61（例如，距離第一表面61約0.5mm或更多）。以此方式，分區460的下部可以從基板表面分離一距離，該距離足以允許氣體流在氣體流與基板表面反應之後，流動環繞下部而朝向真空埠455。箭頭498指示氣體流的方向。由於分區460可操作而作為對於氣體流的物理阻隔，所以分區460亦可限制前驅物之間的交叉汙染。所示之配置僅為說明性，且不應視為限制本技術之範疇。該領域具有通常知識者將理解，所示之氣體分配系統僅為一種可能的分配系統，並且可以採用其他類型的噴淋頭。System 400 may include a plurality of partitions 460 disposed on processing chamber 20 and between each port. The lower portion of each partition may extend close to the first surface 61 of the substrate 60 (eg, about 0.5 mm or more from the first surface 61 ). In this manner, the lower portion of the partition 460 may be separated from the substrate surface by a distance sufficient to allow the gas flow to flow around the lower portion toward the vacuum port 455 after the gas flow reacts with the substrate surface. Arrow 498 indicates the direction of gas flow. Since the partitions 460 can operate as physical barriers to gas flow, the partitions 460 can also limit cross-contamination between precursors. The configuration shown is illustrative only and should not be considered as limiting the scope of the present technology. Those of ordinary skill in the art will understand that the gas distribution system shown is only one possible distribution system and that other types of showerheads may be employed.

在操作中，可以將基板60（例如，藉由機器人）遞送到裝載閘腔室10，並可放置於梭子65上。在隔離閥15打開之後，梭子65可以沿著軌道70移動。一旦梭子65進入處理腔室20，隔離閥15就可以關閉，以將處理腔室20密封。然後，梭子65可以移動通過處理腔室20，以進行處理。在一個實施例中，梭子65可以在線性路徑中移動通過腔室。In operation, substrate 60 may be delivered (eg, by a robot) to load lock chamber 10 and may be placed on shuttle 65 . After the isolation valve 15 is opened, the shuttle 65 can move along the track 70 . Once the shuttle 65 enters the processing chamber 20 , the isolation valve 15 can be closed to seal the processing chamber 20 . The shuttle 65 can then be moved through the processing chamber 20 for processing. In one embodiment, the shuttle 65 can move through the chamber in a linear path.

隨著基板60移動通過處理腔室20，基板60的第一表面61可以重複暴露於來自氣體埠425的化合物A的前驅物及來自氣體埠435的化合物B的前驅物，其間具有來自氣體埠445的吹掃氣體。吹掃氣體的注入可經設計以在將基板表面61暴露至下一個前驅物之前，移除來自先前前驅物的未反應材料。在對各種氣體流的每一次暴露之後，氣體流可以藉由泵送系統450通過真空埠455抽空。由於在每一氣體埠的兩側可以設置真空埠，所以氣體流可以通過在兩側的真空埠455抽空。因此，氣體流可以從各別氣體埠垂直向下朝向基板60的第一表面61流動，跨越第一表面410且環繞分區460之下部，而最後向上朝向真空埠455流動。以此方式，每一氣體可以跨越基板表面61均勻地分佈。亦可在暴露至各種氣體流時旋轉基板60。基板的旋轉可以對於防止在所形成的層中形成條帶是有用的。基板的旋轉可以是連續或是分開的步驟。As the substrate 60 moves through the processing chamber 20, the first surface 61 of the substrate 60 may be repeatedly exposed to the compound A precursor from the gas port 425 and the compound B precursor from the gas port 435, with the gas port 445 therebetween of purge gas. The injection of the purge gas can be designed to remove unreacted material from the previous precursor before exposing the substrate surface 61 to the next precursor. After each exposure to the various gas streams, the gas streams can be evacuated through vacuum port 455 by pumping system 450 . Since vacuum ports can be provided on both sides of each gas port, the gas flow can be evacuated through the vacuum ports 455 on both sides. Thus, the gas flow can flow vertically downward from the respective gas ports toward the first surface 61 of the substrate 60 , across the first surface 410 and around the lower portion of the partition 460 , and finally upward toward the vacuum port 455 . In this way, each gas can be distributed uniformly across the substrate surface 61 . The substrate 60 may also be rotated while exposed to various gas streams. Rotation of the substrate can be useful to prevent banding in the formed layers. The rotation of the substrate can be a continuous or separate step.

可以藉由例如從氣體埠出來的每一氣體的流動速率及基板60的移動速率來決定基板表面61暴露至每一氣體的程度。在一個實施例中，每一氣體的流動速率可經配置，而不會從基板表面61移除所吸收的前驅物。每一分區之間的寬度、設置於處理腔室20上的氣體埠之數量、及基板可能來回傳遞的次數亦可決定基板表面61暴露至各種氣體的程度。因此，沉積膜的數量與品質可藉由變化上述因子來最佳化。The extent to which the substrate surface 61 is exposed to each gas can be determined by, for example, the flow rate of each gas from the gas ports and the rate of movement of the substrate 60 . In one embodiment, the flow rate of each gas can be configured without removing the absorbed precursor from the substrate surface 61 . The width between each partition, the number of gas ports disposed on the processing chamber 20, and the number of times the substrate may be passed back and forth may also determine the extent to which the substrate surface 61 is exposed to the various gases. Therefore, the quantity and quality of deposited films can be optimized by varying the above factors.

在另一實施例中，系統400可以包括前驅物注入器420與前驅物注入器430，而沒有吹掃氣體注入器440。因此，隨著基板60移動通過處理腔室20，基板表面61可以交替地暴露於化合物A的前驅物與化合物B的前驅物，而不會暴露於其間的吹掃氣體。In another embodiment, system 400 may include precursor injector 420 and precursor injector 430 without purge gas injector 440 . Thus, as the substrate 60 moves through the processing chamber 20, the substrate surface 61 may be alternately exposed to the compound A precursor and the compound B precursor without being exposed to the purge gas therebetween.

第4圖所示的實施例具有在基板上方的氣體分配板30。儘管已經針對此直立定向描述及圖示實施例，但應理解，相反的定向亦是可能的。在那種情況下，基板60的第一表面61可以面朝下，而朝向基板流動的氣體可以引導朝上。在一或更多個實施例中，至少一個輻射熱源90可以定位成加熱基板的第二側。The embodiment shown in Figure 4 has a gas distribution plate 30 above the substrate. Although the embodiment has been described and illustrated for this upright orientation, it should be understood that the opposite orientation is also possible. In that case, the first surface 61 of the substrate 60 may face downward, while the gas flowing towards the substrate may be directed upward. In one or more embodiments, at least one radiant heat source 90 may be positioned to heat the second side of the substrate.

在一些實施例中，梭子65可以是用於承載基板60的基座66。通常，基座66可以是有助於跨越基板形成均勻溫度的載體。基座66可以相對於第4圖的佈置在裝載閘腔室10與處理腔室20之間在左到右及右到左的兩個方向上移動。基座66可以具有用於承載基板60的頂表面67。基座66可以是經加熱的基座，而使得基板60可以加熱以用於處理。作為實例，可以藉由設置在基座66下方的輻射熱源90、加熱板、電阻線圈、或其他加熱裝置來加熱基座66。儘管圖示為橫向轉換，但系統400的實施例亦可用於旋轉式系統，其中輪狀物可以順時針或逆時針旋轉，以連續加工位於所示氣體分配系統下方的一或更多個基板。應類似地理解，附加修改係包括在本技術中。In some embodiments, the shuttle 65 may be a base 66 for carrying the substrate 60 . In general, the susceptor 66 may be a carrier that helps to create a uniform temperature across the substrate. The susceptor 66 is movable between the load lock chamber 10 and the process chamber 20 in both directions, left to right and right to left, relative to the arrangement of FIG. 4 . The base 66 may have a top surface 67 for carrying the substrate 60 . The susceptor 66 may be a heated susceptor such that the substrate 60 may be heated for processing. As an example, the susceptor 66 may be heated by a radiant heat source 90 disposed below the susceptor 66, a heating plate, a resistive coil, or other heating device. Although illustrated as a lateral transformation, embodiments of system 400 may also be used in rotary systems, where the wheel may be rotated clockwise or counterclockwise to continuously process one or more substrates positioned below the illustrated gas distribution system. It should be similarly understood that additional modifications are included in the present technology.

第5圖圖示形成半導體結構的方法500，其中許多操作可以執行於例如前述腔室200及400中。方法500可以包括在開始該方法之前的一或更多個操作，其包括前端處理、沉積、蝕刻、研磨、清潔、或可以在所述操作之前執行的任何其他操作。該方法可以包括圖式中所示的多個可選擇操作，其可以或可以不特別與根據本技術的方法相關聯。舉例而言，為了提供更廣泛的結構形成範圍而描述許多操作，但是對於該技術而言並非關鍵，或者可以藉由替代方法來執行，這將在下面進一步論述。方法500描述第6A圖至第6C圖中示意性圖示的操作，將結合方法500的操作而描述其說明。應理解，第6圖僅圖示局部示意圖，而基板可以包含任何數量的具有如圖式中所示的態樣的電晶體區段。FIG. 5 illustrates a method 500 of forming a semiconductor structure, many of which may be performed in, for example, chambers 200 and 400 previously described. Method 500 may include one or more operations prior to beginning the method, including front-end processing, deposition, etching, grinding, cleaning, or any other operations that may be performed prior to the operations. The method may include a number of optional operations shown in the figures, which may or may not be specifically associated with methods in accordance with the present technology. For example, many operations are described in order to provide a broader scope of structure formation, but are not critical to the technique, or may be performed by alternative methods, as discussed further below. Method 500 describes the operations schematically illustrated in FIGS. 6A-6C , the description of which will be described in conjunction with the operations of method 500 . It should be understood that Figure 6 shows only a partial schematic view, and that the substrate may contain any number of transistor segments having the aspect shown in the figures.

方法500可以涉及可選擇的操作，以將半導體結構發展到特定製造操作。如第6A圖所示，半導體結構可以表示發生某些電晶體形成操作之後的裝置。這些材料可能已經在先前操作中形成，並且可能已經拋光到特定高度，而暴露基板的頂部與側表面上的材料中之每一者。可以執行方法500的操作，以限制或消除屏蔽操作，限制或消除包括灰化及清潔的RIE處理，以及可以減少用於形成奈米線結構的處理佇列時間。The method 500 may involve selectable operations to develop a semiconductor structure to a particular fabrication operation. As shown in FIG. 6A, the semiconductor structure may represent the device after certain transistor forming operations have occurred. These materials may have been formed in previous operations, and may have been polished to a certain height, exposing each of the materials on the top and side surfaces of the substrate. The operations of method 500 can be performed to limit or eliminate masking operations, to limit or eliminate RIE processing including ashing and cleaning, and to reduce processing queue times for forming nanowire structures.

如圖所示，結構600可以包括由矽或一些其他半導體基板材料製成或含有矽或一些其他半導體基板材料的基板601。結構600可以具有形成為覆蓋基板601的多個電晶體結構。舉例而言，可以在基板601上形成虛閘極材料605，虛閘極材料605可以稍後在處理中移除，以產生金屬閘極。虛閘極605可以具有形成為覆蓋虛閘極605的蓋材料607。此外，介電材料609可以形成於虛閘極605周圍。介電材料609可以毯覆在結構上，然後圖案化成所圖示的結構，或者介電材料609可以選擇性沉積在蓋材料607與虛閘極605周圍。As shown, structure 600 may include a substrate 601 made of or containing silicon or some other semiconductor substrate material. Structure 600 may have a plurality of transistor structures formed overlying substrate 601 . For example, dummy gate material 605 can be formed on substrate 601, which can be removed later in processing to create a metal gate. The dummy gate 605 may have a cap material 607 formed to cover the dummy gate 605 . Additionally, a dielectric material 609 may be formed around the dummy gate 605 . Dielectric material 609 may be blanketed on the structure and then patterned into the structure as shown, or dielectric material 609 may be selectively deposited around capping material 607 and dummy gate 605 .

在一些實施例中，虛閘極可以是多晶矽或含矽材料。蓋材料607可以是介電材料，以及例如可以是氮化矽。介電材料609亦可以是氮化矽，或者可以是氧化物（例如，氧化矽）。如圖所示，結構600可以是N-MOS區域，而儘管未圖示，類似的P-MOS區域亦可以與結構相關聯。下面論述的幾個操作可以在結構的一側上執行，而另一側保持被屏蔽，或者可以選擇性執行而不需要屏蔽。若在二個區域上使用屏蔽，則可以利用移除及重新形成來切換屏蔽，然後可以在其他結構上執行類似的操作，其他結構可以在暴露區域內具有選擇性。這些選項將在下面進一步描述，但應理解，可以在其他區域之前處理任一區域，而這些方法不受所描述的實例的限制。In some embodiments, the dummy gate may be polysilicon or a silicon-containing material. The cap material 607 can be a dielectric material, and can be silicon nitride, for example. The dielectric material 609 can also be silicon nitride, or can be an oxide (eg, silicon oxide). As shown, the structure 600 may be an N-MOS region, and although not shown, a similar P-MOS region may also be associated with the structure. Several of the operations discussed below can be performed on one side of the structure while the other side remains shielded, or can be selectively performed without shielding. If a mask is used on two areas, the mask can be switched using removal and reformation, and then a similar operation can be performed on other structures, which can be selective in the exposed areas. These options will be described further below, but it should be understood that any region may be processed before other regions, and the methods are not limited by the described examples.

可以在基板601的源極/汲極區域上垂直形成多層材料，以用於發展根據本技術的奈米線。層可以包括至少一層第一含矽材料611以及至少一層第二含矽材料613，並且可以包括材料的交替層。如第6A圖所示，在源極及汲極上存在每一部分的三個層，但應理解，可以存在少於三個（例如，每一者的二個或一個層），以及多於三個（例如，每一者的4個、5個、6個、7個、10個、或更多個層）。如圖所示，在實施例中，層613可以是與基板材料601相同的材料，或者包括與基板材料601相同的材料。Multiple layers of material may be formed vertically on the source/drain regions of substrate 601 for use in developing nanowires according to the present technology. The layers may include at least one layer of a first silicon-containing material 611 and at least one layer of a second silicon-containing material 613, and may include alternating layers of materials. As shown in Figure 6A, there are three layers of each portion on the source and drain, but it should be understood that there may be less than three (eg, two or one layer of each), and more than three (eg, 4, 5, 6, 7, 10, or more layers of each). As shown, in embodiments, layer 613 may be the same material as substrate material 601 , or include the same material as substrate material 601 .

取決於所描述的操作包括在N-MOS區域還是P-MOS區域中，第一含矽材料與第二含矽材料可以取決於所形成的特定奈米線結構而不同。舉例而言，在所示結構的N-MOS側，奈米線可以由矽形成，而因此第二含矽材料613可以是矽或者可以包括矽，而第一含矽材料611可以是例如具有第一鍺含量的鍺化矽。然而，在結構的P-MOS側上（未圖示但可為類似的），奈米線可以由例如鍺化矽形成或包括鍺化矽，而因此第二含矽材料可以是具有高於第一鍺含量的第二鍺含量的鍺化矽，而第一含矽材料可以是例如矽。Depending on whether the described operations are included in the N-MOS region or the P-MOS region, the first silicon-containing material and the second silicon-containing material may differ depending on the particular nanowire structure being formed. For example, on the N-MOS side of the structure shown, the nanowires may be formed of silicon, and thus the second silicon-containing material 613 may be or may include silicon, and the first silicon-containing material 611 may be, for example, having a A germanium content of silicon germanium. However, on the P-MOS side of the structure (not shown but may be similar), the nanowires may be formed of or include silicon germanium, for example, and thus the second silicon-containing material may be higher than the second silicon-containing material. A germanium content and a second germanium content silicon germanium, and the first silicon-containing material may be, for example, silicon.

如第6B圖所示，可以在第一含矽材料上執行橫向蝕刻操作。可以等向性執行橫向蝕刻，以從閘極結構的兩側（例如，在虛閘極605的兩側上）移除第一含矽材料，並且可以不完全移除第一含矽材料。橫向蝕刻可以如前所述在腔室200中執行，或者在能夠執行類似蝕刻操作的不同腔室中執行。一旦定位於半導體處理腔室的處理區域內，該方法可以包括在操作505處在處理腔室的遠端電漿區域中形成含氟前驅物的電漿。遠端電漿區域可以與處理區域流體耦合，但是可以物理分隔，以將電漿限制在基板層級處，這可能損傷暴露的結構或材料。電漿的流出物可以流入處理區域，在處理區域中可以在操作510處與半導體基板接觸。As shown in FIG. 6B, a lateral etch operation may be performed on the first silicon-containing material. The lateral etch may be performed isotropically to remove the first silicon-containing material from both sides of the gate structure (eg, on both sides of the dummy gate 605), and may not completely remove the first silicon-containing material. Lateral etching can be performed in chamber 200 as previously described, or in a different chamber capable of performing similar etching operations. Once positioned within the processing region of the semiconductor processing chamber, the method may include forming a plasma of the fluorine-containing precursor in a distal plasma region of the processing chamber at operation 505 . The distal plasma region may be fluidly coupled to the processing region, but may be physically separated to confine the plasma at the substrate level, which may damage exposed structures or materials. The effluent of the plasma may flow into a processing region where it may contact the semiconductor substrate at operation 510 .

隨後，橫向蝕刻可以在操作515處執行，以形成限定於材料的各層之間的凹部617。舉例而言，凹部617可以形成於第二含矽材料613的每一層之間以及基板601上方。凹部617亦可以形成於閘極結構的每一側上或是第一含矽材料611的殘留部分的每一側上。凹部的長度在實施例中可以小於或約10nm，而在實施例中可以小於或約8nm、小於或約6nm、小於或約4nm、在約3nm與約8nm之間、或者在約5nm與約7nm之間。處理可以維持一定量的第一含矽材料，第一含矽材料可以位於與虛閘極材料垂直對準，且可以由尺寸的特徵可以與虛閘極材料類似或稍大。Subsequently, a lateral etch may be performed at operation 515 to form recesses 617 defined between the layers of material. For example, recesses 617 may be formed between each layer of the second silicon-containing material 613 and over the substrate 601 . Recesses 617 may also be formed on each side of the gate structure or on each side of the remaining portion of the first silicon-containing material 611 . The length of the recess may be less than or about 10 nm in embodiments, and may be less than or about 8 nm, less than or about 6 nm, less than or about 4 nm, between about 3 nm and about 8 nm, or between about 5 nm and about 7 nm in embodiments between. The process may maintain an amount of the first silicon-containing material, which may be located in vertical alignment with the dummy gate material, and may be similar or slightly larger than the dummy gate material by features.

舉例而言，第一含矽材料可以維持與虛閘極相等的寬度，該寬度可以大於或約10nm、大於或約20nm、大於或約30nm、大於或約40nm、大於或約50nm、大於或約60nm、大於或約70nm、大於或約80nm、大於或約90nm、或更大。此外，第一含矽材料的寬度可以稍微大於虛閘極的寬度，並且可以在虛閘極的每一側上多出多達0.5nm或約0.5nm，並且可以在每一側上多出多達1nm或約1nm、在每一側上多出多達2nm或約2nm，在每一側上多出多達3nm或約3nm，在每一側上多出多達4nm或約4nm，在每一側上多出多達5nm或約5nm，在每一側上多出多達6nm或約6nm，在每一側上多出多達7nm或約7nm、或更多。For example, the first silicon-containing material may maintain a width equal to that of the dummy gate, which may be greater than or about 10 nm, greater than or about 20 nm, greater than or about 30 nm, greater than or about 40 nm, greater than or about 50 nm, greater than or about 60 nm, greater than or about 70 nm, greater than or about 80 nm, greater than or about 90 nm, or greater. Additionally, the width of the first silicon-containing material may be slightly larger than the width of the dummy gate, and may be as much as 0.5 nm or about more on each side of the dummy gate, and may be much more on each side up to 1 nm or about 1 nm, up to 2 nm or about 2 nm more on each side, up to 3 nm or about 3 nm more on each side, up to 4 nm or about 4 nm more on each side, on each side Up to 5 nm or about extra on one side, up to 6 nm or about extra on each side, up to 7 nm or about 7 nm extra on each side, or more.

橫向蝕刻處理可以相對於第二含矽材料613（可以是矽）而選擇性移除第一含矽材料611（可以是鍺化矽）。在實施例中，操作可以具有大於或約50：1的相對於第二含矽材料的第一含矽材料的選擇性，這可以允許第一含矽材料凹陷，而基本上維持或大致上維持第二含矽材料。在一些實施例中，第二含矽材料可以在橫向蝕刻操作515期間蝕刻少於或約1nm，並且可以蝕刻少於或約0.8nm、少於或約0.6nm、少於或約0.4nm、少於或約0.2nm、少於或約0.1nm、或更少。The lateral etch process may selectively remove the first silicon-containing material 611 (which may be silicon germanium) relative to the second silicon-containing material 613 (which may be silicon). In embodiments, the operation may have a selectivity of the first silicon-containing material relative to the second silicon-containing material of greater than or about 50:1, which may allow recessing of the first silicon-containing material while substantially maintaining or substantially maintaining The second silicon-containing material. In some embodiments, the second silicon-containing material may be etched less than or about 1 nm during lateral etch operation 515, and may be etched less than or about 0.8 nm, less than or about 0.6 nm, less than or about 0.4 nm, less than At or about 0.2 nm, less than or about 0.1 nm, or less.

在可選擇的操作520處，可以將基板從蝕刻腔室轉移到沉積腔室。轉移可以在真空下進行，而兩個腔室可以都駐留在相同集群工具上，以允許轉移發生在受控環境中。舉例而言，可以在轉移期間維持真空條件，並且可以在不破壞真空的情況下進行轉移。一旦在沉積腔室中（例如，上述腔室400），則在操作525處，可以相鄰於凹陷的含矽材料611而形成或沉積間隔物材料。如第6C圖所示，間隔物材料620可以直接形成在凹陷的含矽材料611上或與凹陷的含矽材料611接觸。此橫向沉積可以是定時沉積，以在凹部617內形成間隔物材料620，同時限制在其他暴露表面上的形成。間隔物材料620可以形成於含矽材料周圍，以及形成於先前形成的凹部617內。間隔物材料620可以層疊於第二含矽材料的區域之間，並且可以完全填充凹部617，以接觸限定於第二含矽材料的各層之間的第一含矽材料的其餘部分。At optional operation 520, the substrate can be transferred from the etch chamber to the deposition chamber. The transfer can be performed under vacuum, while both chambers can reside on the same cluster tool to allow the transfer to take place in a controlled environment. For example, vacuum conditions can be maintained during the transfer, and the transfer can be performed without breaking the vacuum. Once in a deposition chamber (eg, chamber 400 described above), at operation 525 , spacer material may be formed or deposited adjacent to recessed silicon-containing material 611 . As shown in FIG. 6C , the spacer material 620 may be formed directly on or in contact with the recessed silicon-containing material 611 . This lateral deposition may be a timed deposition to form spacer material 620 within recess 617 while limiting formation on other exposed surfaces. Spacer material 620 may be formed around the silicon-containing material, as well as within previously formed recesses 617 . Spacer material 620 can be stacked between regions of the second silicon-containing material and can completely fill the recesses 617 to contact the remainder of the first silicon-containing material defined between the layers of the second silicon-containing material.

在實施例中，間隔物材料620可以是含矽材料，並且可以是或包括氮化矽、碳化矽、碳氧化矽、或包括摻碳氧化矽、多孔材料、或具有低介電常數的特徵的其他材料的低k材料。沉積操作可以是選擇性沉積，其中間隔物材料相對於暴露的第二含矽材料613、蓋材料607、及介電材料609而優先形成於含矽材料611上。相對於可以包括附加屏蔽操作的習知技術，操作525可以直接執行後續蝕刻操作515。In an embodiment, the spacer material 620 may be a silicon-containing material, and may be or include silicon nitride, silicon carbide, silicon oxycarbide, or include carbon doped silicon oxycarbide, a porous material, or feature a low dielectric constant. Low-k materials for other materials. The deposition operation may be a selective deposition in which spacer material is preferentially formed on silicon-containing material 611 relative to exposed second silicon-containing material 613 , cap material 607 , and dielectric material 609 . Operation 525 may directly perform subsequent etch operation 515 relative to conventional techniques that may include additional masking operations.

儘管可以進行基板的轉移，但是在選擇性蝕刻與選擇性沉積之間可以不執行其他基板處理。如將在下面進一步詳細解釋，選擇性沉積可以包括多個操作，儘管在實施例中可以執行操作之間的基板轉移，但是可以直接在一組蝕刻操作之後執行整個沉積處理。由於毯覆沉積或間隔物材料620的形成可能需要額外的屏蔽及移除技術，藉由根據方法500執行選擇性蝕刻及選擇性沉積，佇列時間可以比習知技術顯著降低。方法500可以不利用任何RIE操作，這可減少聚合物堆積以及與RIE相關聯的必要的灰化及清潔操作。此外，如下面進一步解釋，可以利用比RIE更高或高得多的選擇性執行蝕刻，這可以減少閘極間隔物上的關鍵尺寸損失，並且可以減少或消除閘極間隔物與接觸介電質的屏蔽。Although transfer of the substrates may occur, no other substrate processing may be performed between selective etching and selective deposition. As will be explained in further detail below, selective deposition may include multiple operations, although in embodiments substrate transfer between operations may be performed, the entire deposition process may be performed directly after a set of etching operations. Since blanket deposition or formation of spacer material 620 may require additional masking and removal techniques, by performing selective etching and selective deposition according to method 500, queue times can be significantly reduced over conventional techniques. Method 500 may not utilize any RIE operations, which may reduce polymer buildup and the necessary ashing and cleaning operations associated with RIE. Furthermore, as explained further below, the etch can be performed with a higher or much higher selectivity than the RIE, which can reduce critical dimension loss on the gate spacer, and can reduce or eliminate the gate spacer and contact dielectric shielding.

儘管習知技術可以毯覆間隔物材料，然後執行RIE操作，但是具有相對低的選擇性的這樣的處理可能蝕刻側壁、底下的基板、及所沉積的材料。此外，當在間隔物材料內使用含碳材料時，利用RIE執行的灰化可能從所形成的介電質中清除碳，這將增加材料的介電常數，而破壞形成之目的。藉由不執行間隔物材料的RIE後續沉積，間隔物材料的碳含量可以保留，這可以維持材料的較低的介電常數。在一些實施例中，可以在沉積之後藉由將基板轉移回到蝕刻腔室來執行輕微的回蝕操作。後續的乾式蝕刻可以清潔間隔物的側壁，以確保在操作530處的足夠的分隔，而蝕刻的選擇性可以是其他處所描述的任一者，以確保基本上維持所有其他暴露的材料。While conventional techniques can blanket the spacer material and then perform the RIE operation, such a process with relatively low selectivity may etch the sidewalls, the underlying substrate, and the deposited material. Furthermore, when carbon-containing materials are used within the spacer material, ashing performed with RIE may remove carbon from the formed dielectric, which would increase the dielectric constant of the material, defeating the purpose of formation. By not performing RIE subsequent deposition of the spacer material, the carbon content of the spacer material can be preserved, which can maintain the lower dielectric constant of the material. In some embodiments, a slight etch-back operation may be performed after deposition by transferring the substrate back to the etch chamber. A subsequent dry etch can clean the sidewalls of the spacers to ensure adequate separation at operation 530, while the selectivity of the etch can be any of those described elsewhere to ensure that substantially all other exposed materials are maintained.

可以在處理中利用各種材料，而蝕刻及沉積可以對於多個部件具有選擇性。因此，本技術可以不限於單組材料。舉例而言，第一含矽材料611可以是如上所述的幾種物質，而在實施例中可以包括含碳材料。介電材料609可以包括絕緣材料，並且可以包括含矽材料、含氧材料、含碳材料、或這些材料的一些組合（例如，氧化矽或氮化矽）。蓋材料607亦可以包括絕緣材料，並且也可以包括含矽材料、含氧材料、含碳材料、或這些材料的一些組合（例如，氧化矽或氮化矽）。Various materials can be utilized in processing, and etching and deposition can be selective for multiple components. Thus, the present technology may not be limited to a single set of materials. For example, the first silicon-containing material 611 may be several substances as described above, and may include carbon-containing materials in embodiments. Dielectric material 609 may include insulating materials, and may include silicon-containing materials, oxygen-containing materials, carbon-containing materials, or some combination of these materials (eg, silicon oxide or silicon nitride). The cap material 607 may also include insulating materials, and may also include silicon-containing materials, oxygen-containing materials, carbon-containing materials, or some combination of these materials (eg, silicon oxide or silicon nitride).

類似地，儘管可以取決相對於所形成或移除的其他材料而使用的材料來調整選擇性蝕刻與沉積操作，但是可以在其他實施例中類似地使用其他的絕緣材料。在實施例中，蓋材料607與介電材料609可以是相同的材料，或者可以是不同的材料。舉例而言，在一個實施例中，介電材料可為氧化矽或可以包括氧化矽，而蓋材料可為氮化矽或可以包括氮化矽。Similarly, other insulating materials may similarly be used in other embodiments, although selective etch and deposition operations may be tuned depending on the materials used relative to other materials formed or removed. In embodiments, lid material 607 and dielectric material 609 may be the same material, or may be different materials. For example, in one embodiment, the dielectric material may be or may include silicon oxide, and the cap material may be or may include silicon nitride.

蝕刻操作可以涉及與特定含氟前驅物一起的附加前驅物。在一些實施例中，可以使用三氟化氮來產生電漿流出物。亦可以利用附加或可替代的含氟前驅物。舉例而言，含氟前驅物可以流入遠端電漿區域，而含氟前驅物可以包括選自原子氟、雙原子氟、四氟化碳、三氟化溴、三氟化氯、三氟化氮、氟化氫、六氟化硫、及二氟化氙的群組的至少一個前驅物。遠端電漿區域可以在與處理腔室不同的模組內或在處理腔室內的隔間內。如第2圖所示，RPS單元201與第一電漿區域215二者可以作為遠端電漿區域。RPS可以允許電漿流出物解離而不會損傷其他腔室部件，而第一電漿區域215可以提供到基板的較短路徑長度，在此期間可能發生重組。附加前驅物亦可以遞送到遠端電漿區域，以增強含氟前驅物（例如，其他含碳前驅物、含氫前驅物、或含氧前驅物）。Etching operations may involve additional precursors along with specific fluorine-containing precursors. In some embodiments, nitrogen trifluoride can be used to generate the plasma effluent. Additional or alternative fluorine-containing precursors may also be utilized. For example, a fluorine-containing precursor can flow into the remote plasma region, and the fluorine-containing precursor can include a fluorine-containing precursor selected from the group consisting of atomic fluorine, diatomic fluorine, carbon tetrafluoride, bromine trifluoride, chlorine trifluoride, trifluoride At least one precursor of the group of nitrogen, hydrogen fluoride, sulfur hexafluoride, and xenon difluoride. The distal plasma region may be in a separate module from the processing chamber or in a compartment within the processing chamber. As shown in FIG. 2, both the RPS cell 201 and the first plasmonic region 215 may serve as a remote plasmonic region. The RPS can allow the plasmonic effluent to dissociate without damaging other chamber components, while the first plasmonic region 215 can provide a shorter path length to the substrate during which recombination may occur. Additional precursors can also be delivered to the distal plasmonic region to enhance fluorine-containing precursors (eg, other carbon-containing precursors, hydrogen-containing precursors, or oxygen-containing precursors).

在實施例中，蝕刻操作可以在低於約10Torr的情況下執行，以及在實施例中可以在低於或約5Torr的情況下執行。在實施例中，處理亦可以在低於約100℃的溫度下執行，並且可以在低於約50℃的情況下執行。隨著在腔室200或此腔室的變體中執行，或者在能夠執行類似操作的不同腔室中執行，處理可以移除對於第二含矽材料613、蓋材料607、及介電材料609具有選擇性的第一含矽材料611的部分。In embodiments, etching operations may be performed below about 10 Torr, and in embodiments below or about 5 Torr. In embodiments, processing may also be performed at temperatures below about 100°C, and may be performed at temperatures below about 50°C. As performed in chamber 200 or a variation of this chamber, or in a different chamber capable of performing similar operations, processing may remove material for second silicon-containing material 613 , cap material 607 , and dielectric material 609 Portions of the first silicon-containing material 611 with selectivity.

當執行本方法時，相對於暴露於基板的表面上的其他部件的第一含矽材料的蝕刻選擇性可以是大於或約10：1、大於或約20：1、大於或約50：1、或是大於或約100:1、或更大，以用於形成於基板上的各種材料，並可以暴露於電漿流出物。因此，取決於特徵尺寸，可以從基板的表面移除第一含矽材料，同時其他暴露材料可以減少小於1nm。舉例而言，從一個閘極區段到第二閘極區段的特徵寬度可以在約50nm與約70nm之間，並且可以向下延伸到約20nm與約30nm之間。在如上所述的實施例中，用於第一含矽材料611的橫向凹陷的深度可以小於或約50nm，並且可以小於或約40nm、小於或約30nm、小於或約20nm、小於或約10nm、或更少。由於此蝕刻深度，可以移除最小量的其他暴露材料，該最小量可以小於或約3nm、小於或約1nm、小於或約0.5nm，或者材料可以基本上或大致上維持不變。因此，相對於其他暴露材料的第一含矽材料蝕刻的特徵可以是用於每一結構的材料的上述選擇性中之任一者。When performing the method, the etch selectivity of the first silicon-containing material relative to other components exposed on the surface of the substrate may be greater than or about 10:1, greater than or about 20:1, greater than or about 50:1, Or greater than or about 100:1, or greater, for various materials formed on the substrate and can be exposed to plasma effluents. Thus, depending on the feature size, the first silicon-containing material may be removed from the surface of the substrate, while the other exposed material may be reduced by less than 1 nm. For example, the feature width from one gate segment to the second gate segment may be between about 50 nm and about 70 nm, and may extend down to between about 20 nm and about 30 nm. In the embodiments described above, the depth of the lateral recess for the first silicon-containing material 611 may be less than or about 50 nm, and may be less than or about 40 nm, less than or about 30 nm, less than or about 20 nm, less than or about 10 nm, or less. Due to this etch depth, a minimum amount of other exposed material may be removed, which may be less than or about 3 nm, less than or about 1 nm, less than or about 0.5 nm, or the material may remain substantially or substantially unchanged. Thus, the features etched of the first silicon-containing material relative to the other exposed materials can be any of the above-described selectivities for the material of each structure.

可以在能夠沉積且能夠原子層沉積的腔室（包括上述的腔室400）中執行選擇性沉積。沉積可以預設為在相對於另一絕緣材料或另一半導體材料的半導體材料上選擇性沉積絕緣材料。舉例而言，間隔物材料620可以基本上形成於第一含矽材料611上，同時最小限度地形成於或限制於第二含矽材料613上或是暴露的蓋材料607或介電材料609上。可以藉由多種操作來執行選擇性沉積，該多種操作可以包括形成自組裝單層以促進選擇性沉積，或者可以包括主動抑制在其他介電材料上形成介電質。Selective deposition may be performed in a chamber capable of deposition and atomic layer deposition, including chamber 400 described above. The deposition may be preset to selectively deposit an insulating material on a semiconductor material relative to another insulating material or another semiconductor material. For example, the spacer material 620 may be formed substantially on the first silicon-containing material 611 while being minimally formed or limited on the second silicon-containing material 613 or on the exposed cap material 607 or dielectric material 609 . Selective deposition may be performed by operations that may include forming a self-assembled monolayer to facilitate selective deposition, or may include actively inhibiting dielectric formation on other dielectric materials.

可以在結構的區域上形成自組裝單層，以調諧沉積。舉例而言，可以在結構上形成第一自組裝單層，然後從第一含矽材料611移除第一自組裝單層。單層可以維持於第二含矽材料613與暴露的頂表面上。單層可以具有可能排斥或無法與後來遞送的前驅物相互作用的封端部分。舉例而言，在實施例中，封端部分可以是疏水性，並且可以利用含氫部分（例如，甲基）封端，含氫部分可以不與附加前驅物相互作用。第二自組裝單層可以形成在第一含矽材料611上，第一含矽材料611可以是親水性或與用於產生間隔物材料620的一或更多個前驅物反應。因為材料可以與第一自組裝單層排斥，或者可以選擇性拉伸到材料，所以可以在第一含矽材料611上選擇性形成第二自組裝單層。第二自組裝單層可以利用氫氧基或其他親水部分封端，或是利用特別與用於形成間隔物材料620的附加前驅物相互作用的部分封端。Self-assembled monolayers can be formed over regions of the structure to tune the deposition. For example, a first self-assembled monolayer can be formed on the structure and then removed from the first silicon-containing material 611 . A single layer can be maintained on the second silicon-containing material 613 and the exposed top surface. The monolayer may have capping moieties that may repel or be unable to interact with the precursors that are delivered later. For example, in an embodiment, the capping moiety can be hydrophobic and can be capped with a hydrogen-containing moiety (eg, methyl), which may not interact with additional precursors. The second self-assembled monolayer can be formed on the first silicon-containing material 611 , which can be hydrophilic or reactive with one or more precursors used to create the spacer material 620 . A second self-assembled monolayer can be selectively formed on the first silicon-containing material 611 because the material can be repelled from the first self-assembled monolayer, or can be selectively stretched to the material. The second self-assembled monolayer can be terminated with hydroxyl groups or other hydrophilic moieties, or with moieties that specifically interact with additional precursors used to form spacer material 620.

然後，可以利用二或更多個前驅物執行原子層沉積，以開發間隔物材料620。沉積的前驅物可以包括多個前驅物，多個前驅物包括含矽前驅物與經配置以與封端第二自組裝單層（而非第一自組裝單層）的部分相互作用的前驅物。舉例而言，當使用親水性及疏水性封端單層時，原子層沉積前驅物中之一者可以包括水。以此方式，沉積可能不會形成於可以是疏水性的第一自組裝單層上。若間隔物材料包括氧化物（例如，氧化矽或碳氧化矽），則用於原子層沉積的前驅物可以包括含矽前驅物以及水。然後，在與水的半反應期間，水可能無法與形成在第二含矽材料與介電材料上的第一自組裝單層相互作用，而因此沉積將不在第一自組裝單層上形成。以此方式， 可以在第一含矽材料611上選擇性形成間隔物材料620，而不會形成可以化學蝕刻的遮罩層。Atomic layer deposition can then be performed using two or more precursors to develop spacer material 620 . The deposited precursor may include a plurality of precursors including a silicon-containing precursor and a precursor configured to interact with a portion of the capped second self-assembled monolayer rather than the first self-assembled monolayer . For example, when hydrophilic and hydrophobic terminated monolayers are used, one of the atomic layer deposition precursors may include water. In this way, deposition may not form on the first self-assembled monolayer, which may be hydrophobic. If the spacer material includes an oxide (eg, silicon oxide or silicon oxycarbide), the precursor for atomic layer deposition may include a silicon-containing precursor and water. Then, during the half-reaction with water, the water may not be able to interact with the first self-assembled monolayer formed on the second silicon-containing material and the dielectric material, and thus the deposition will not form on the first self-assembled monolayer. In this way, the spacer material 620 can be selectively formed on the first silicon-containing material 611 without forming a mask layer that can be chemically etched.

在間隔物材料620已經形成合適的厚度之後，可以將第一自組裝單層暴露到UV光，並從基板移除第一自組裝單層。因此，第一自組裝單層可以直接在含矽的選擇性蝕刻之後形成，或者在轉移到附加腔室之後但在附加處理操作之前形成，而在結構上可以不利用需要化學移除或蝕刻的附加屏蔽層。類似地，在選擇性沉積之後，可以不需要蝕刻間隔物材料620（亦可能需要附加屏蔽），以確保在含矽材料上選擇性形成間隔物材料620。以此方式，可以排除習知形成中使用的多個操作，這可以顯著減少佇列時間（例如，幾個小時）。After the spacer material 620 has been formed to a suitable thickness, the first self-assembled monolayer can be exposed to UV light and removed from the substrate. Thus, the first self-assembled monolayer can be formed directly after the selective etch of silicon, or after transfer to additional chambers but before additional processing operations, without the use of chemical removal or etching on the structure. Additional shielding. Similarly, after selective deposition, spacer material 620 may not need to be etched (and possibly additional masking) to ensure selective formation of spacer material 620 over the silicon-containing material. In this way, multiple operations used in conventional formations can be eliminated, which can significantly reduce queue time (eg, hours).

實施例亦可以利用抑制劑，以在第一含矽材料611上選擇性形成間隔物材料620，而不在蓋材料607與介電材料609上形成間隔物材料620。舉例而言，可以跨越基板的表面施加所噴塗的抑制劑，其可以沿著基板的頂表面施加，且可以不穿透到基板的凹陷部分內。抑制劑可以是任何數量的材料，材料的特徵可以是矽氧烷主鏈（例如，矽氧烷）或四氟乙烯主鏈（例如，PTFE），以及其他油性或表面活性劑材料。可以跨越基板的表面施加材料，以覆蓋蓋材料607與介電材料609的暴露部分。藉由使用噴塗或塗覆應用，可以不將材料施加於基板的凹陷部分內，並且可以不接觸第一含矽材料611。然後，可以例如藉由原子層沉積或其他氣相沉積或物理沉積機制來形成間隔物材料620。Embodiments may also utilize inhibitors to selectively form spacer material 620 on first silicon-containing material 611 without forming spacer material 620 on cap material 607 and dielectric material 609 . For example, the sprayed inhibitor may be applied across the surface of the substrate, it may be applied along the top surface of the substrate, and may not penetrate into recessed portions of the substrate. The inhibitor can be any number of materials that can be characterized by a siloxane backbone (eg, siloxane) or a tetrafluoroethylene backbone (eg, PTFE), as well as other oily or surfactant materials. Material may be applied across the surface of the substrate to cover the exposed portions of the capping material 607 and the dielectric material 609 . By using a spray or coating application, the material may not be applied within the recessed portion of the substrate, and may not contact the first silicon-containing material 611 . Spacer material 620 may then be formed, eg, by atomic layer deposition or other vapor deposition or physical deposition mechanisms.

抑制劑材料可以防止在第一含矽材料611可以正常形成或沉積的材料的黏附或吸附。隨後形成間隔物材料620，並可以將移除劑施加到基板上，以移除抑制劑材料。移除劑可以是濕式蝕刻劑、反應物、或表面活性劑清潔劑，其可以移除讓底下的閘極結構暴露的殘留抑制劑材料。因此，抑制劑可以直接在選擇性蝕刻之後施加，或者在基板轉移之後，但在影響基板的其他處理操作之前施加。利用抑制劑可以允許在限定區域中形成間隔物材料，而不需要經由隨後的毯覆膜的圖案化及/或蝕刻限定。藉由移除先前及後續的圖案化操作，處理可以進一步減少習知處理的佇列時間。The inhibitor material may prevent adhesion or adsorption of materials that may normally be formed or deposited in the first silicon-containing material 611 . The spacer material 620 is then formed, and a remover can be applied to the substrate to remove the inhibitor material. The remover can be a wet etchant, reactant, or surfactant cleaner, which can remove residual inhibitor material that exposes the underlying gate structure. Thus, the inhibitor can be applied directly after the selective etch, or after transfer of the substrate, but before other processing operations affecting the substrate. Utilizing an inhibitor may allow the spacer material to be formed in defined areas without the need to define via subsequent patterning and/or etching of the blanket film. By removing previous and subsequent patterning operations, the process can further reduce the queue time of conventional processes.

抑制劑亦可以是可以中和基板的表面或使基板的表面呈現惰性的電漿應用的產物。舉例而言，改性電漿可以由一或更多個前驅物形成，該前驅物可以包括惰性前驅物。可以將電漿施加到基板的表面，該電漿可以改變基板的頂表面，且可以不穿透到基板的凹陷部分內。舉例而言，含氮前驅物（可以是氮）可以遞送到產生電漿的處理腔室的電漿處理區域。電漿流出物（可以包括含氮電漿流出物）可以遞送到基板，並且可以沿著頂表面而沿著基板的暴露部分形成氮化表面（可以包括蓋材料607與介電材料609）。The inhibitor can also be the product of a plasma application that can neutralize or render the surface of the substrate inert. For example, the modified plasma can be formed from one or more precursors, which can include inert precursors. Plasma may be applied to the surface of the substrate, which may alter the top surface of the substrate, and may not penetrate into recessed portions of the substrate. For example, a nitrogen-containing precursor, which may be nitrogen, can be delivered to a plasma processing region of a plasma-generating processing chamber. Plasma effluents (which may include nitrogen-containing plasma effluents) may be delivered to the substrate and a nitrided surface (which may include capping material 607 and dielectric material 609 ) may be formed along the exposed portion of the substrate along the top surface.

電漿流出物在基板的凹陷部分內可能不遞送或者可能不流動，而可以維持第一含矽材料611的純的或未反應的表面。然後，可以利用一或更多種沉積技術形成間隔物材料620，沉積技術可以包括原子層沉積或其他氣相或物理沉積。舉例而言，可以利用原子層沉積技術，而隨後利用電漿流出物處理。在沉積的每一循環之後，含氮電漿可以重新施加到基板的表面區域上（例如，在蓋材料607與介電材料609上）。以此方式，蓋材料607與介電材料609的表面可以鈍化，以防止或限制那些區域上的間隔物材料620的形成。利用在基板的非凹陷部分上的這些電漿流出物可以允許在限定區域中形成間隔物材料，而不需要經由後續的毯覆膜的圖案化及/或蝕刻限定。藉由移除先前及後續的圖案化操作，處理可以進一步減少習知處理的佇列時間。此外，沉積可以發生在第一與第二含矽材料兩者上，但是可以在第一含矽材料上以更快的速率發生，這可以允許類似於先前描述的後續蝕刻，然後從第二含矽材料的外部移除過量的間隔物材料。Plasma effluent may not be delivered or may not flow within the recessed portion of the substrate, while a pure or unreacted surface of the first silicon-containing material 611 may be maintained. Spacer material 620 may then be formed using one or more deposition techniques, which may include atomic layer deposition or other vapor or physical deposition. For example, atomic layer deposition techniques may be utilized followed by plasma effluent processing. After each cycle of deposition, the nitrogen-containing plasma can be reapplied onto the surface area of the substrate (eg, on the capping material 607 and the dielectric material 609). In this manner, the surfaces of cap material 607 and dielectric material 609 may be passivated to prevent or limit the formation of spacer material 620 on those areas. Utilizing these plasma effluents on non-recessed portions of the substrate may allow spacer material to be formed in defined areas without the need to define through subsequent patterning and/or etching of the blanket film. By removing previous and subsequent patterning operations, the process can further reduce the queue time of conventional processes. Additionally, deposition may occur on both the first and second silicon-containing materials, but may occur at a faster rate on the first silicon-containing material, which may allow subsequent etching similar to the The exterior of the silicon material removes excess spacer material.

相對於一或更多個其他半導體、介電質、或絕緣區域，這些技術中之任一者可以在含半導體區域上選擇性沉積或形成介電或絕緣材料。選擇性可以是完整的，亦即，間隔物材料僅在第一含矽材料611或中間層上形成，而間隔物材料可以完全不在蓋材料607及介電材料609上形成。在其他實施例中，選擇性可能不是完整的，而含半導體材料上的沉積相對於介電或絕緣材料的比率可以是大於約2：1。選擇性亦可以大於或約5：1、大於或約10：1、大於或約15：1、大於或約20：1、大於或約25：1、大於或約30：1、大於或約35：1、大於或約40：1、大於或約45：1、大於或約50：1、大於或約75：1、大於或約100：1、大於或約200：1、或更多。間隔物材料可以形成為前述的厚度，厚度可以小於或約50nm，並且可以小於或約40nm、小於或約30nm、小於或約20nm、小於或約10nm、小於或約5nm、或更少。因此，低於50：1的選擇性可以是可接受的，以完全沉積間隔物材料620，同時在蓋材料607與介電材料609上形成有限量的材料或基本上沒有形成材料。Any of these techniques can selectively deposit or form a dielectric or insulating material on a semiconductor-containing region relative to one or more other semiconductor, dielectric, or insulating regions. The selectivity may be complete, that is, the spacer material is formed only on the first silicon-containing material 611 or the intermediate layer, while the spacer material may not be formed on the cap material 607 and the dielectric material 609 at all. In other embodiments, the selectivity may not be complete, and the ratio of deposition on semiconductor-containing material to dielectric or insulating material may be greater than about 2:1. The selectivity can also be greater than or about 5:1, greater than or about 10:1, greater than or about 15:1, greater than or about 20:1, greater than or about 25:1, greater than or about 30:1, greater than or about 35 : 1, greater than or about 40:1, greater than or about 45:1, greater than or about 50:1, greater than or about 75:1, greater than or about 100:1, greater than or about 200:1, or more. The spacer material may be formed to the aforementioned thicknesses, the thickness may be less than or about 50 nm, and may be less than or about 40 nm, less than or about 30 nm, less than or about 20 nm, less than or about 10 nm, less than or about 5 nm, or less. Therefore, selectivities below 50:1 may be acceptable to fully deposit spacer material 620 while forming limited or substantially no material on lid material 607 and dielectric material 609 .

沉積操作可以在前述的任何溫度或壓力下執行，並可以在大於或約50℃的溫度下執行，且可以在大於或約100℃、大於或約150℃、大於或約200℃、大於或約200℃、大於或約250℃、大於或約300℃、大於或約350℃、大於或約400℃、大於或約450℃、大於或約500℃、大於或約600℃、大於或約700℃、大於或約800℃、或更高的溫度下執行。舉例而言，在原子層沉積操作期間，可以使用大於或約400℃的溫度，以活化前驅物，以在材料層形成時彼此相互作用。The deposition operation may be performed at any of the aforementioned temperatures or pressures, and may be performed at temperatures greater than or about 50°C, and may be performed at greater than or about 100°C, greater than or about 150°C, greater than or about 200°C, greater than or about 200°C, greater than or about 250°C, greater than or about 300°C, greater than or about 350°C, greater than or about 400°C, greater than or about 450°C, greater than or about 500°C, greater than or about 600°C, greater than or about 700°C , at a temperature greater than or about 800°C, or higher. For example, during atomic layer deposition operations, temperatures greater than or about 400° C. may be used to activate the precursors to interact with each other as material layers are formed.

可以在沒有任何RIE處理或相關聯處理的情況下執行方法500，這可以更好地維持間隔物材料的組分，並保持間隔物材料的低k值。類似地，該方法藉由移除可以在習知處理中的形成之前、期間、或之後所執行的許多圖案化及移除操作而可以減少佇列時間。相較於習知技術，藉由利用本技術，可以利用更多的選擇性形成及移除來執行製造，這可以保護所形成的材料，並且可以比習知處理減少數小時的佇列時間。Method 500 may be performed without any RIE processing or associated processing, which may better maintain the composition of the spacer material and maintain a low-k value of the spacer material. Similarly, the method can reduce queue time by removing many of the patterning and removal operations that may be performed before, during, or after formation in conventional processes. By utilizing the present technology, fabrication can be performed with more selective formation and removal than conventional techniques, which preserves the material formed and reduces queue time by hours over conventional processes.

在先前描述中，為了解釋之目的，已經闡述許多細節，以提供對於本技術的各種實施例的理解。然而，對於該領域具有通常知識者顯而易見的是，可以在沒有這些細節中之一些或在具有附加細節的情況下實施某些實施例。In the foregoing description, for purposes of explanation, numerous details have been set forth in order to provide an understanding of various embodiments of the present technology. However, it will be apparent to one of ordinary skill in the art that certain embodiments may be practiced without some of these details or with additional details.

已揭示幾個實施例，但應理解，該領域具有通常知識者可以在不悖離實施例的精神的情況下使用各種修改、替代構造、及等同物。此外，為了避免不必要地模糊本技術，並未描述許多已知的處理及元件。因此，上面的描述不應視為限制本技術之範疇。Several embodiments have been disclosed, but it should be understood that various modifications, alternative constructions, and equivalents may be employed by those of ordinary skill in the art without departing from the spirit of the embodiments. Furthermore, many well-known processes and elements have not been described in order to avoid unnecessarily obscuring the technology. Accordingly, the above description should not be construed as limiting the scope of the present technology.

當提供值的範圍時，應理解，除非上下文另有明確說明，亦具體揭示該範圍的上限與下限之間的每一中間值到下限單位的最小部分。包括在所述範圍中的任何所述值或未敘述的中間值之間的任何較窄範圍以及所述範圍中的任何其他所述或中間值。除非所述範圍具有任何具體排除限制，這些較小範圍的上限與下限可以獨立地包括在範圍中或排除在外，而上限與下限中之任一者或二者都包括或都不包括在較小範圍中的每一範圍亦包括在本技術內。在所述範圍包括一或二個限制的情況下，則亦包括排除這些所包括限制中的一或二者的範圍。When a range of values is provided, it is to be understood that, unless the context clearly dictates otherwise, each intervening value between the upper and lower limit of the range to the smallest part of the unit of the lower limit is also specifically disclosed. Included are any narrower ranges between any stated or unrecited intervening value in a stated range and any other stated or intervening value in that stated range. Unless the stated range is subject to any specifically excluded limit, the upper and lower limits of these smaller ranges may independently be included in or excluded from the range, and either or both of the upper and lower limits may or may not be included in the smaller range. Each of the ranges is also encompassed within the present technology. Where the stated range includes one or both of the limitations, ranges excluding either or both of those included limitations are also included.

如本文及隨附專利申請範圍中所使用，除非上下文另有明確說明，否則單數形式「一」、「一個」、及「該」包括複數指稱。因此，舉例而言，指稱「一層」包括複數個這樣的層，而指稱「前驅物」包括指稱該領域具有通常知識者已知的一或更多個前驅物及其等同物等等。As used herein and in the scope of the appended patent application, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, by way of example, reference to "a layer" includes a plurality of such layers, and reference to a "precursor" includes reference to one or more precursors and equivalents thereof known to those of ordinary skill in the art, and the like.

此外，在本說明書及以下請求項中使用詞語「包含」、「所包含」、「含有」、「所含有」、「包括」、及「所包括」時，意欲在指定所述特徵、整體、部件、或操作的存在，但是不排除一或更多個其他特徵、整體、部件、操作、動作、或群組的存在或附加。Furthermore, when the words "comprises," "includes," "includes," "includes," "includes," and "includes" are used in this specification and the following claims, they are intended to The presence of a component, or operation, does not preclude the presence or addition of one or more other features, integers, components, operations, acts, or groups.

10‧‧‧裝載閘腔室15‧‧‧隔離閥20‧‧‧處理腔室30‧‧‧氣體分配板60‧‧‧基板61‧‧‧第一表面65‧‧‧梭子70‧‧‧軌道90‧‧‧輻射熱源100‧‧‧處理系統102‧‧‧前開式聯合晶圓盒104‧‧‧機器臂106‧‧‧托持區域108a‧‧‧處理腔室108b‧‧‧處理腔室108c‧‧‧處理腔室108d‧‧‧處理腔室108e‧‧‧處理腔室108f‧‧‧處理腔室109a‧‧‧串聯區段109b‧‧‧串聯區段109c‧‧‧串聯區段110‧‧‧第二機器臂200‧‧‧腔室201‧‧‧RPS單元203‧‧‧冷卻板205‧‧‧氣體入口組件210‧‧‧流體供應系統214‧‧‧上板215‧‧‧第一電漿區域216‧‧‧下板217‧‧‧面板218‧‧‧容積219‧‧‧第一流體通道220‧‧‧絕緣環221‧‧‧第二流體通道223‧‧‧離子抑制器225‧‧‧噴淋頭233‧‧‧基板處理區域240‧‧‧功率供應器253‧‧‧詳細視圖255‧‧‧基板258‧‧‧氣體供應區域259‧‧‧孔隙265‧‧‧台座325‧‧‧噴淋頭365‧‧‧通孔375‧‧‧小孔洞400‧‧‧腔室420‧‧‧注射器425‧‧‧氣體埠430‧‧‧注射器435‧‧‧氣體埠440‧‧‧注射器445‧‧‧氣體埠450‧‧‧泵送系統455‧‧‧真空埠460‧‧‧分區498‧‧‧箭頭500‧‧‧方法505‧‧‧操作510‧‧‧操作515‧‧‧操作520‧‧‧操作525‧‧‧操作530‧‧‧操作600‧‧‧結構601‧‧‧基板605‧‧‧虛閘極材料607‧‧‧蓋材料609‧‧‧介電材料611‧‧‧第一含矽材料613‧‧‧第二含矽材料617‧‧‧凹部620‧‧‧間隔物材料10‧‧‧Load Lock Chamber 15‧‧‧Isolation Valve 20‧‧‧Processing Chamber 30‧‧‧Gas Distribution Plate 60‧‧‧Substrate 61‧‧‧First Surface 65‧‧‧Shuttle 70‧‧‧Rail 90‧‧‧Radiant Heat Source 100‧‧‧Processing System 102‧‧‧Front Opening Combined Wafer Cassette 104‧‧‧Robot Arm 106‧‧‧Holding Area 108a‧‧‧Processing Chamber 108b‧‧‧Processing Chamber 108c ‧‧‧Processing chamber 108d‧‧‧Processing chamber 108e‧‧‧Processing chamber 108f‧‧‧Processing chamber 109a‧‧‧Series section 109b‧‧‧Series section 109c‧‧‧Series section 110‧ ‧‧Second Robot Arm 200‧‧‧Chamber 201‧‧‧RPS Unit 203‧‧‧Cooling Plate 205‧‧‧Gas Inlet Assembly 210‧‧‧Fluid Supply System 214‧‧‧Top Plate 215‧‧‧First Plasma area 216‧‧‧Lower plate 217‧‧‧Panel 218‧‧‧Volume 219‧‧‧First fluid channel 220‧‧‧Insulating ring 221‧‧‧Second fluid channel 223‧‧‧Ion suppressor 225‧ ‧‧Shower head 233‧‧‧Substrate processing area 240‧‧‧Power supply 253‧‧‧Detailed view 255‧‧‧Substrate 258‧‧‧Gas supply area 259‧‧‧Aperture 265‧‧‧Pedestal 325‧‧ ‧Sprinkler head 365‧‧‧Through hole 375‧‧‧Small hole 400‧‧‧Chamber 420‧‧‧Injector 425‧‧‧Gas port 430‧‧‧Injector 435‧‧‧Gas port 440‧‧‧Injector 445 ‧‧‧Gas Port 450‧‧‧Pumping System 455‧‧‧Vacuum Port 460‧‧‧Zone 498‧‧‧Arrow 500‧‧‧Method 505‧‧‧Operation 510‧‧‧Operation 515‧‧‧Operation 520‧ ‧‧Operation 525‧‧‧Operation 530‧‧‧Operation 600‧‧‧Structure 601‧‧‧Substrate 605‧‧‧Virtual Gate Material 607‧‧‧Cover Material 609‧‧‧Dielectric Material 611‧‧‧First Silicon-containing material 613‧‧‧Second silicon-containing material 617‧‧‧Recess 620‧‧‧Spacer material

可以藉由參照說明書及圖式的其餘部分來實現所揭示的技術的本質及優點的進一步理解。A further understanding of the nature and advantages of the disclosed technology can be realized by reference to the remainder of the specification and drawings.

第1圖圖示根據本技術的實施例的示例性處理系統的頂視平面圖。1 illustrates a top plan view of an exemplary processing system in accordance with an embodiment of the present technology.

第2A圖圖示根據本技術的實施例的示例性處理腔室的示意性橫截面圖。2A illustrates a schematic cross-sectional view of an exemplary processing chamber in accordance with embodiments of the present technology.

第2B圖圖示根據本技術的實施例的示例性噴淋頭的詳細視圖。2B illustrates a detailed view of an exemplary showerhead in accordance with embodiments of the present technology.

第3圖圖示根據本技術的實施例的示例性噴淋頭的底視平面圖。3 illustrates a bottom plan view of an exemplary showerhead in accordance with embodiments of the present technology.

第4圖圖示根據本技術的實施例的示例性處理腔室的示意性橫截面圖。4 illustrates a schematic cross-sectional view of an exemplary processing chamber in accordance with an embodiment of the present technology.

第5圖圖示根據本技術的實施例的形成半導體結構的方法中的所選擇操作。5 illustrates selected operations in a method of forming a semiconductor structure in accordance with an embodiment of the present technology.

第6A圖至第6C圖圖示根據本技術的實施例的示例性基板的示意性橫截面圖。6A-6C illustrate schematic cross-sectional views of exemplary substrates in accordance with embodiments of the present technology.

圖式中的幾個係包括作為示意圖。應理解，圖式僅用於說明目的，而除非特別聲明具有標度，否則不應視為比例。此外，作為示意圖，圖式係提供為幫助理解，並且可能不包括相較於實際表示的所有態樣或資訊，並且可能包括用於說明目的之誇大材料。Several lines in the drawings are included as schematic diagrams. It should be understood that the drawings are for illustrative purposes only and should not be considered to scale unless specifically stated to be to a scale. Furthermore, the drawings are provided as schematic illustrations to aid understanding, and may not include all aspects or information as compared to actual representations, and may include exaggerated material for illustrative purposes.

在隨附圖式中，類似的部件及/或特徵可以具有相同的元件符號。此外，相同類型的各種部件可以藉由在元件符號後利用字母來區分，以區分類似部件。若在說明書中僅使用最前面的元件符號，則該描述係適用於具有相同最前面的元件符號的任何一個類似部件，而與字母無關。In the accompanying drawings, similar components and/or features may have the same reference numerals. In addition, various components of the same type may be distinguished by using a letter after the reference symbol to distinguish similar components. If only the leading reference number is used in the specification, the description applies to any one similar component having the same leading reference symbol, regardless of the letter.

國內寄存資訊 (請依寄存機構、日期、號碼順序註記) 無Domestic storage information (please note in the order of storage institution, date and number) None

國外寄存資訊 (請依寄存國家、機構、日期、號碼順序註記) 無Foreign deposit information (please note in the order of deposit country, institution, date and number) None

611‧‧‧第一含矽材料 611‧‧‧First silicon-containing material

613‧‧‧第二含矽材料 613‧‧‧Second silicon-containing material

620‧‧‧間隔物材料 620‧‧‧Spacer material

Claims (17)

一種形成一半導體結構的方法，該方法包含以下步驟：在一處理腔室的一遠端電漿區域中形成一含氟前驅物的一電漿；使一半導體基板與該電漿的流出物接觸，其中該半導體基板係容納在該處理腔室的一處理區域中；從該半導體基板選擇性橫向凹陷一含矽材料；以及隨後相鄰於該含矽材料而沉積一間隔物材料，其中該間隔物材料相對於一閘極形成物與一奈米線材料的暴露區域而選擇性沉積在該含矽材料上，其中該方法係在並未進行一活性離子蝕刻操作的情況下執行。 A method of forming a semiconductor structure, the method comprising the steps of: forming a plasma containing a fluorine precursor in a remote plasma region of a processing chamber; contacting a semiconductor substrate with the effluent of the plasma , wherein the semiconductor substrate is contained in a processing region of the processing chamber; selectively laterally recesses a silicon-containing material from the semiconductor substrate; and then deposits a spacer material adjacent to the silicon-containing material, wherein the spacer Material is selectively deposited on the silicon-containing material relative to exposed regions of a gate former and a nanowire material, wherein the method is performed without a reactive ion etching operation. 如請求項1所述之形成一半導體結構的方法，其中該蝕刻步驟係在一第一處理腔室中執行，以及該沉積步驟係在一第二處理腔室中執行。 The method of forming a semiconductor structure of claim 1, wherein the etching step is performed in a first processing chamber, and the deposition step is performed in a second processing chamber. 如請求項2所述之形成一半導體結構的方法，進一步包含以下步驟：將該半導體基板從該第一處理腔室轉移到該第二處理腔室，且其中該轉移步驟係以在不破壞真空的情況下執行。 The method of forming a semiconductor structure of claim 2, further comprising the step of: transferring the semiconductor substrate from the first processing chamber to the second processing chamber, and wherein the transferring step is performed without breaking vacuum Executed in the case. 如請求項1所述之形成一半導體結構的方法，其中該含矽材料包含鍺化矽。 The method of forming a semiconductor structure of claim 1, wherein the silicon-containing material comprises silicon germanium. 如請求項1所述之形成一半導體結構的方法，其中該閘極形成物包含一暴露的介電材料，且其中該奈米線材料包含矽。 The method of forming a semiconductor structure of claim 1, wherein the gate formation comprises an exposed dielectric material, and wherein the nanowire material comprises silicon. 如請求項1所述之形成一半導體結構的方法，其中該間隔物材料包含一金屬氮化物或一金屬氧化物。 The method of forming a semiconductor structure of claim 1, wherein the spacer material comprises a metal nitride or a metal oxide. 如請求項1所述之形成一半導體結構的方法，其中利用該含矽材料相對於該閘極形成物與該奈米線材料大於或約10：1的一選擇性而執行該蝕刻步驟。 The method of forming a semiconductor structure of claim 1, wherein the etching step is performed with a selectivity of the silicon-containing material relative to the gate formation and the nanowire material of greater than or about 10:1. 如請求項1所述之形成一半導體結構的方法，其中利用該含矽材料相對於該閘極形成物與該奈米線材料大於或約2：1的一選擇性而執行該沉積。 The method of forming a semiconductor structure of claim 1, wherein the depositing is performed with a selectivity of the silicon-containing material relative to the gate formation and the nanowire material of greater than or about 2:1. 如請求項1所述之形成一半導體結構的方法，其中選擇性沉積該間隔物材料之步驟包含以下步驟：在該含矽材料上形成一自組裝單層，其中該自組裝單層與用於形成該間隔物材料的一或更多個前驅物相互作用。 The method of forming a semiconductor structure of claim 1, wherein the step of selectively depositing the spacer material comprises the steps of: forming a self-assembled monolayer on the silicon-containing material, wherein the self-assembled monolayer is combined with a One or more precursors that form the spacer material interact. 一種形成一半導體結構的方法，該方法包含以下步驟：相對於一第二含矽材料橫向蝕刻一第一含矽材料，其中該第一含矽材料與該第二含矽材料彼此垂直設置，且其中該第一含矽材料係垂直定位於該第二含矽材料 的二個區域之間；在藉由該第二含矽材料的該二個區域之間的該橫向蝕刻而限定的一凹部內形成一間隔物材料；以及選擇性使該間隔物材料凹陷，以分離單獨的間隔物，其中該蝕刻步驟係在一第一處理腔室中執行，以及該沉積步驟係在一第二處理腔室中執行，其中將該半導體基板從該第一處理腔室轉移到該第二處理腔室，且其中該轉移步驟係以在不破壞真空的情況下執行。 A method of forming a semiconductor structure, the method comprising the steps of laterally etching a first silicon-containing material relative to a second silicon-containing material, wherein the first silicon-containing material and the second silicon-containing material are disposed perpendicular to each other, and wherein the first silicon-containing material is positioned vertically to the second silicon-containing material between two regions of the second silicon-containing material; forming a spacer material within a recess defined by the lateral etching between the two regions of the second silicon-containing material; and selectively recessing the spacer material to separate spacers, wherein the etching step is performed in a first processing chamber, and the deposition step is performed in a second processing chamber, wherein the semiconductor substrate is transferred from the first processing chamber to The second processing chamber, and wherein the transferring step is performed without breaking the vacuum. 如請求項10所述之形成一半導體結構的方法，其中該第二含矽材料包含矽。 The method of forming a semiconductor structure of claim 10, wherein the second silicon-containing material comprises silicon. 如請求項11所述之形成一半導體結構的方法，其中該間隔物材料係選自一含碳材料、一含氮材料、及一含氧材料所組成的群組。 The method of forming a semiconductor structure of claim 11, wherein the spacer material is selected from the group consisting of a carbon-containing material, a nitrogen-containing material, and an oxygen-containing material. 如請求項10所述之形成一半導體結構的方法，其中該第一含矽材料係從一閘極形成物的兩側而部分凹陷。 The method of forming a semiconductor structure of claim 10, wherein the first silicon-containing material is partially recessed from both sides of a gate formation. 如請求項10所述之形成一半導體結構的方法，其中該第一含矽材料包含鍺化矽。 The method of forming a semiconductor structure of claim 10, wherein the first silicon-containing material comprises silicon germanium. 如請求項10所述之形成一半導體結構的方法，其中該方法係在並未進行一活性離子蝕刻操作 的情況下執行。 The method of forming a semiconductor structure of claim 10, wherein the method is performed without performing a reactive ion etching operation Executed in the case. 如請求項10所述之形成一半導體結構的方法，其中利用該第一含矽材料相對於該第二含矽材料大於或約10：1的一選擇性而執行該蝕刻步驟。 The method of forming a semiconductor structure of claim 10, wherein the etching step is performed with a selectivity of the first silicon-containing material relative to the second silicon-containing material of greater than or about 10:1. 如請求項10所述之形成一半導體結構的方法，其中利用該第一含矽材料相對於該第二含矽材料大於或約2：1的一選擇性而執行該沉積步骤。 The method of forming a semiconductor structure of claim 10, wherein the depositing step is performed with a selectivity of the first silicon-containing material relative to the second silicon-containing material of greater than or about 2:1.
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