WO2018184431A1 - 链路阻抗检测芯片及方法 - Google Patents

链路阻抗检测芯片及方法 Download PDF

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WO2018184431A1
WO2018184431A1 PCT/CN2018/077163 CN2018077163W WO2018184431A1 WO 2018184431 A1 WO2018184431 A1 WO 2018184431A1 CN 2018077163 W CN2018077163 W CN 2018077163W WO 2018184431 A1 WO2018184431 A1 WO 2018184431A1
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impedance
chip
hardware link
signal
sampling
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PCT/CN2018/077163
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English (en)
French (fr)
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葛明
罗飞
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华为技术有限公司
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/08—Locating faults in cables, transmission lines, or networks
    • G01R31/11—Locating faults in cables, transmission lines, or networks using pulse reflection methods

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  • the present invention relates to the field of link impedance testing, and in particular to a link impedance detection chip and method.
  • a large hardware system (such as a cabinet in a data center base station) is typically composed of multiple modules (for example, a Field Replace Unit (FRU)). Each module needs to work together. When the modules work together, signals need to be transmitted. The carrier of these signals is the hardware link. However, when this hardware link is abnormal, it is difficult to pinpoint exactly where the abnormality is. As shown in FIG. 1, when the hardware link of the chip B of the FRU A chip A to the FRU B is abnormal, the problem may occur in 10 positions (the numbers 1 to 10 in FIG. 1), where the positions 1-5 are located. The transmit link of chip A, location 6-10, is located on the receive link of chip B.
  • FRU Field Replace Unit
  • the existing method is to replace the modules on the hardware link of the chip A to the chip B one by one, for example, to replace the FRU A firstly. If the abnormality disappears, the FRU A is considered to be an abnormal module; if the abnormality does not disappear, the problem is on the backboard or On the FRU B, replace the FRU B. After replacing the FRU B, if the abnormality disappears, the FRU B is considered to be an abnormal module. If the abnormality does not disappear, the problem is on the backplane, and the backplane is replaced.
  • the above method has the following problems: the modules can only be replaced one by one, it is difficult to ensure that one replacement is in place, the positioning efficiency is low, and the customer feels poor. In addition, some abnormalities occur intermittently. When FRU A is replaced, it disappears abnormally. In fact, FRU A is not necessarily an abnormal cause. The root cause of the problem may be on FRU B, but it is not exposed for the time being. Therefore, after replacing FRU A, after a while, the problem will be exposed again.
  • Embodiments of the present invention provide a link impedance detecting chip and method for testing impedance at each position of a hardware link connecting two chips to determine whether an impedance at each position of the hardware link is abnormal.
  • a first aspect of the embodiments of the present invention provides a chip that is connected to another chip through a hardware link.
  • the chip is modified to detect the impedance of each position of the hardware link by the chip.
  • the chip includes a processing circuit and a transmitting circuit.
  • the embodiment of the present invention also adds an edge controller and an impedance test circuit to the chip.
  • the edge controller is connected in series with a signal generator in the transmitting circuit for adjusting a pulse signal generated by the signal generator to a step signal.
  • the impedance test circuit is coupled between the hardware link and the processing circuit.
  • the processing circuit controls the signal generator to generate a pulse signal, and controls the edge controller to adjust a pulse signal generated by the signal generator to a step signal, where the step signal is transmitted in two ways, one way to the direction
  • the hardware link transmission is transmitted all the way through the impedance test circuit, and the step signal is reflected when passing through different line impedances in the hardware link, and the reflected signal is transmitted to the impedance test circuit.
  • the processing circuit controls the impedance test circuit to periodically sample the signal voltage value passing through the impedance test circuit, and determine the different positions in the hardware link according to the sampling time and the sampling voltage sampled at each sampling time. Line impedance.
  • the impedance test circuit is connected to the hardware link by a first switch, and when the chip is working normally, the first switch cuts off the connection between the impedance test circuit and the hardware link, when When it is desired to diagnose an abnormality of the hardware link, the first switch turns on the connection of the impedance test circuit to the hardware link.
  • the chip can be freely switched between the normal working state and the test state, and the hardware link can be tested by switching the chip to the impedance test circuit through the first switch.
  • a second switch is further connected between the first switch and the hardware link, and a hardware link of the second switch is further connected with a corrective impedance, and the impedance test on the hardware link is performed.
  • the abnormality diagnosis circuit is connected to the correction impedance by the first switch and the second switch, and the corrected impedance is used as the hardware link to test the impedance value of the corrected impedance, and The corrected impedance value is compared with the actual impedance value of the corrected impedance, an impedance adjustment coefficient is obtained, and the measured line impedance is adjusted according to the adjustment coefficient.
  • the hardware link is a receiving link, and the receiving link is connected to a receiving circuit of the chip through an input end of the chip, the chip further includes a third switch, and the sending circuit passes the second switch And the third switch is connected to the receiving link.
  • the hardware link includes a transmit link and a receive link.
  • the solution in the foregoing implementation manner may be directly used for testing, but when testing the receive link, it is required.
  • the processing circuit determines the line impedance at different positions in the hardware link according to the sampling time and the sampling voltage sampled at each sampling time, specifically:
  • Vreflected Vsample-Vincent, Vsample and Vincent are known, then Vreflected can be calculated, where Vsample is the sampling voltage, Vincent is the voltage of the step signal, and Vreflected is the reflected voltage;
  • T2 is the sampling time of the impedance test circuit sampling to the reflected voltage
  • T1 is the first sampling step signal of the impedance test circuit.
  • the impedance of the line at each position in the hardware link can be accurately calculated.
  • a second aspect of the invention provides an impedance testing method.
  • the method is applied to a chip.
  • the chip is connected to another chip through a hardware link.
  • the chip includes a signal generator and an edge controller, and the pulse signal generated by the signal generator is adjusted to a step signal by the edge controller, and the chip is further connected to an impedance test circuit.
  • the method includes:
  • the impedance test circuit is controlled to periodically sample the signal voltage value passing through the impedance test circuit, and determine the line impedance at different positions in the hardware link according to the sampling time and the sampled voltage sampled at each sampling time.
  • the method when determining the line impedance at different locations in the hardware link according to the sampling time and the sampling voltage sampled by each sampling time, the method includes:
  • Vreflected Vsample-Vincent, Vsample and Vincent are known, then Vreflected can be calculated, where Vsample is the sampling voltage, Vincent is the voltage of the step signal, and Vreflected is the reflected voltage;
  • T2 is the sampling time of the impedance test circuit sampling to the reflected voltage
  • T0 is the sampling of the step signal sampled by the impedance test circuit for the first time. time;
  • the impedance of the line at each position in the hardware link can be accurately calculated.
  • an edge controller and an impedance test circuit By adding an edge controller and an impedance test circuit to the chip, it is possible to detect the impedance of the line connecting the chip and other chips in the hardware link through the chip, so that the impedance in the hardware link can be accurately and quickly located. An abnormal line to determine the module in which the abnormal line is located to replace the module.
  • Figure 1 is a schematic diagram of a hardware link between two chips.
  • FIG. 2 is a schematic structural diagram of a circuit of a chip according to a first embodiment of the present invention.
  • FIG. 3 is a flowchart of a method for detecting an abnormality of a hardware link according to an embodiment of the present invention.
  • FIG. 4 is a diagram showing relationship between sampling time and sampling voltage obtained by sampling a signal of a hardware link according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of a step signal reflected in a hardware link according to an embodiment of the present invention.
  • FIG. 6 is a diagram showing relationship between line impedance and line position in a hardware link determined in an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of determining whether a hardware link is faulty according to the tested line impedance according to an embodiment of the present invention.
  • FIG. 8 is a schematic structural diagram of a circuit of a chip according to a second embodiment of the present invention.
  • Embodiments of the present invention provide a method for detecting an abnormality of a hardware link between two chips, such as a hardware link between chip A and chip B described in the background, and the link abnormality may be a link disconnection. Open, link short circuit, line impedance is too large.
  • An abnormality diagnostic module may be added to two chips or any one of the chips that can communicate with each other in the hardware link. When the abnormality of the hardware link needs to be diagnosed, the chip A or the chip B uses the abnormality diagnosis module.
  • the impedance at multiple locations on the hardware link is tested and the measured impedance is compared to the design impedance (the impedance met by the hardware link set during circuit design), if the impedance and design impedance are tested If the difference exceeds the threshold, the position corresponding to the test impedance is the position where the abnormality occurs, and the device to be replaced is determined according to the determined position. For example, in FIG. 1, if the abnormal position is position 2, position 3 Or position 8, it is considered that the backplane is abnormal, and the backboard is replaced. In this way, the location of an abnormality in the hardware link can be accurately and quickly located.
  • an abnormality diagnosis module is added to the chip A of the FRUA, and then the chip A is diagnosed by the chip A. A location where a link abnormality occurs in the transmission link or the reception link of the chip B.
  • the circuit structure 20 of the chip A in the first embodiment of the present invention includes a processing circuit 21, a transmitting circuit 22, and a receiving circuit 23.
  • the processing circuit 21 is for processing a signal received by a received signal (for example, the receiving circuit 23), and outputs the processed signal to the chip B connected thereto through a transmission link via the transmitting circuit 22.
  • the hardware link includes a transmit link formed by locations 1, 2, 3, 4, 5 and a receive link formed by locations 6, 7, 8, 9, 10.
  • the transmitting circuit 22 includes a transmitting buffer (FIFO) 221, an encoder (Encoder) 222, a signal generator 223, a first switch (for example, a selector MUX1) 224, and the like.
  • FIFO transmitting buffer
  • Encoder encoder
  • Signal generator 223 a first switch (for example, a selector MUX1) 224, and the like.
  • a first switch for example, a selector MUX1
  • the signal generated by the processing circuit 21 is first buffered to the transmission buffer 221, and after being encoded by the encoder 222, passes through other components in the circuit, such as a polarity inversion unit.
  • the components of the serial-to-parallel converter (PISO), the transmit equalizer (Pre/emp), and the amplifier are processed and output via the output terminal 225.
  • the output 225 is connected to the chip B via a transmit link as shown in FIG.
  • the first switch 224 selectively turns on the encoder 222 or the signal generator 223 according to a command of the processing circuit 21, and when the chip A operates normally, the first switch 224 selects to turn on the encoder. 222. When the chip A needs to be tested, the first switch selects to turn on the signal generator 223.
  • an edge controller 226 is added between the first switch 224 and the signal generator 223, and the edge controller 226 It is used to adjust the pulse signal generated by the signal generator 223 to a step signal.
  • an impedance test circuit is connected between the output terminal 225 and the processing circuit 21, and the impedance is a circuit including a second switch (for example, a selector MUX2) 24 and an analog-to-digital converter (ADC) 25, wherein The second switch 24 has one end connected to the output terminal 225 and the other end connected to the analog to digital converter 25, and the analog to digital converter 25 is connected to the processing circuit 21.
  • the first switch 224 turns on the encoder 222, and the second switch 24 disconnects the analog-to-digital converter 25 from the output terminal 225, and the processing circuit
  • the signal generated by 21 is transmitted directly to the chip B through the output 225 and the transmit link.
  • An abnormality diagnostic program is programmed in the processing circuit 21, and when it is necessary to detect an abnormality of the hardware link, the processing circuit 21 executes the abnormality diagnostic program to perform abnormality detection on the hardware link, and the processing circuit The method shown in FIG. 3 is executed by running the abnormality diagnostic program:
  • Step S301 the processing circuit 21 sends a control command to the first switch 224, the second switch 24, the signal generator 223, and the edge controller 226 to control the first switch 224 to turn on the signal generator.
  • the second switch 24 turns on the ADC 25 and the output terminal 225, controls the signal generator 223 to generate a pulse signal, and controls the edge controller 226 to adjust the signal output by the signal generator to an edge signal.
  • the edge signal is transmitted in two ways, one way is transmitted to the processing circuit 21 through the second switch and the ADC, and one way is transmitted to the chip B through the output end and the hardware link.
  • Step S302 the processing circuit 21 periodically controls the ADC 25 to sample the received signal voltage, and records the relationship between the sampled voltage and the sampling time.
  • the relationship between the sampling voltage and the sampling time may be as shown in the schematic diagram of FIG. Wherein, when the voltage does not reflect, that is, when the impedance of the line in the hardware link does not change, the sampled voltage is the initial voltage (Vincent) of the transmitted signal (ie, the edge signal), when the voltage is generated, When the line impedance in the hardware link changes, the sampled voltage will be higher or lower than the initial voltage, as shown in the sampled times t1, t2, t3, and t4 in Figure 4.
  • Step S303 calculating a line impedance corresponding to the sampling time according to the corresponding relationship between the recorded sampling voltage and the sampling time.
  • the method for calculating the impedance corresponding to the sampling moment is specifically as follows:
  • Z is the impedance corresponding to the sampling instant T
  • Z0 is the impedance designed for the hardware link during circuit design, typically 50 ohms.
  • Step S304 after calculating the impedance corresponding to the sampling time, calculating the position L of the sampled line impedance in the hardware link according to the sampling time.
  • the graph shown in Figure 6 After calculating the impedance corresponding to each position, the graph shown in Figure 6 can be obtained.
  • the impedance of each position in the hardware link can be clearly seen from the figure, and the impedance of each position is compared with the design impedance.
  • Z can be determined to be in a normal state, as shown by B in Figure 7, if the impedance Close to infinity, that is, the case of A in Fig. 7, it means that it is an open circuit.
  • the impedance is close to 0hm, it means that the circuit is short-circuited, that is, the case of C in Fig. 7, both of which are abnormal cases, and the impedance is larger than the design.
  • the +10% of the impedance is not infinite, less than -10% of the design impedance, but not close to 0hm, indicating that the line impedance is outside the normal range, then the module in which the line is located needs to be replaced.
  • the calculated impedance corresponding to each location may be stored in the memory of the IC.
  • the data in the memory may be called to display the data to the user, and the user may display based on the displayed The data determines the location of the fault in the hardware link.
  • the location of the fault in the hardware link can be accurately and quickly determined.
  • the transmitting circuit further includes a third switch 26 (for example, MUX3), and the third switch 26 is connected between the second switch 24 and the output terminal 225.
  • a fourth switch is connected between the receiving circuit 23 and the input end, and an output end of the third switch is connected to an input end of the fourth switch to form a fourth line, and other circuits are connected to the first implementation. The same in the example.
  • the fourth switch 27 turns on the receiving circuit 23 and the input terminal 226, so that the signal input by the input terminal 226 is transmitted to the processing circuit 21 via the receiving circuit 23. .
  • the third switch 26 turns on the transmitting circuit 22 and the output terminal 225 when it is necessary to diagnose an abnormality of an output link between the chip A and the chip B.
  • the second switch turns on the ADC 25 and the transmitting circuit 22, so that the abnormality of the output link can be diagnosed.
  • the third opening 26 and the fourth switch 27 turn on the transmitting circuit 22 and the input terminal 226, and thus, The line anomaly in the input link to which the input 226 of the chip A is connected can be detected.
  • the method of abnormality detection is the same as that in the first embodiment, and details are not described herein again.
  • a correcting resistor 28 can be further connected to the output terminal 225, and the transmitting circuit 22 and the correcting resistor can be turned on by the third switch 26 before the hardware link diagnosis is performed. 28, then calculating the test impedance of the correction resistor 28 in the circuit by the method shown in FIG. 3, and dividing the test impedance by the actual impedance of the correction resistor, a correction coefficient ⁇ can be obtained, and thus, When the test impedance in the hardware link is calculated, the correction coefficient can be divided to correct the test impedance, and the corrected impedance is used to determine whether the impedance of the corresponding position is abnormal, thereby increasing the accuracy of the judgment.

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Abstract

一种芯片（A）及链路阻抗测试方法，所述芯片（A）通过硬件链路连接至另外一个芯片（B）。所述芯片（A）通过信号产生器（223）及边沿控制器（226）产生阶跃信号，所述阶跃信号向与所述芯片（A）的发送电路（22）连接硬件链路及连接于所述芯片（A）的处理电路（21）与所述硬件链路之间的阻抗测试电路传输，所述阶跃信号在经过所述硬件链路中阻值不同的线路阻抗时发生反射，反射后的信号传输至所述阻抗测试电路，所处理电路（21）控制所述阻抗测试电路周期性的采样经过所述阻抗测试电路的信号电压值，并根据采样时间及每个采样时间所采样的采样电压确定所述硬件链路中的不同位置处的线路阻抗。

Description

链路阻抗检测芯片及方法 技术领域
本发明涉及链路阻抗测试领域，特别涉及一种链路阻抗检测芯片及方法。
背景技术
一个大型的硬件***(比如说某数据中心基站中的机柜)一般会由多个模块(例如，现场可更换单元(Field Replace Unit,FRU))组成。每个模块需要协同工作，模块之间协同工作时，需要有信号的传递，这些信号传递的载体就是硬件链路。但当这条硬件链路出现异常时，难以精确定位出异常出在哪里。如图1所示，当FRU A芯片A到FRU B的芯片B的硬件链路出现异常后，问题可能出现在10个位置(图1中的数字1到10处),其中位置1-5位于芯片A的发送链路，位置6-10位于芯片B的接收链路。现有的做法为对芯片A到芯片B的硬件链路上的模块逐一更换，例如先更换FRU A，如果异常消失，认为FRU A是异常模块；如果异常不消失，说明问题出在背板或FRU B上，紧接着更换FRU B，更换FRU B后，如果异常消失，认为FRU B是异常模块；如果异常不消失，说明问题出在背板上，则继续更换背板。
上述方法存在如下问题：模块只能逐一更换，难以保障一次更换到位，定位效率低，客户感受差。另外有些异常是间歇性发生的，当更换FRU A后异常消失，实际上FRU A不一定是异常根因，问题根因可能是在FRU B上，只是暂时没有暴露。因此在更换FRU A后，过一段时间后，问题会再次暴露。
发明内容
本发明实施例提供一种链路阻抗检测芯片及方法，用于对连接两个芯片的硬件链路的各位置处的阻抗进行测试，以判断所述硬件链路各位置处的阻抗是否异常。
本发明实施例第一方面提供一种芯片，所述芯片与另外一个芯片通过硬件链路连接。本发明实施例通过对芯片进行改进，以通过芯片对所述硬件链路各位置的阻抗进行检测。所述芯片包括处理电路、发送电路。为了对所述硬件链路各位置的阻抗进行测试，本发明实施例还在所述芯片中加入了边沿控制器及阻抗测试电路。所述边沿控制器串联与所述发送电路中的信号产生器之后，用于将所述信号产生器产生的脉冲信号调整为阶跃信号。所述阻抗测试电路连接于所述硬件链路与所述处理电路之间。所述处理电路控制所述信号产生器产生脉冲信号，控制所述边沿控制器将所述信号产生器所产生的脉冲信号调整为阶跃信号，所述阶跃信号分两路传输，一路向所述硬件链路传输，一路经由所述阻抗测试电路传输，所述阶跃信号在经过所述硬件链路中阻值不同的线路阻抗时发生反射，反射后的信号传输至所述阻抗测试电路。所处理电路控制所述阻抗测试电路周期性的采样经过所述阻抗测试电路的信号电压值，并根据采样时间及每个采样时间所采样的采样电压确定所述硬件链路中的不同位置处的线路阻抗。
通过在芯片中加入边沿控制器及阻抗测试电路，可以通过芯片检测连接所述芯片与其他芯片的硬件链路中不同位置的线路的阻抗，这样可以准确且快速地定位出出现阻抗异常的线路，从而确定所述异常线路所在的模块，以对所述模块进行替换。
可选地，所述阻抗测试电路通过第一开关连接至所述硬件链路，当所述芯片正常工作时，所述第一开关切断所述阻抗测试电路与所述硬件链路的连接，当需要诊断所述硬件链路的异常时，所述第一开关接通所述阻抗测试电路与所述硬件链路的连接。
这样，可以使所述芯片在正常工作状态与测试状态之间随意切换，只要通过所述第一开关将所述芯片切换至所述阻抗测试电路即可对所述硬件链路进行测试。
可选地，所述第一开关与所述硬件链路之间还连接有第二开关，所述第二开关的一个硬件链路还连接有一矫正阻抗，在对所述硬件链路的阻抗测试之前，通过所述第一开关和第二开关将所述异常诊断电路与所述矫正阻抗接通，将所述矫正阻抗作为所述硬件链路，对所述矫正阻抗的阻抗值进行测试，将所测试的所述矫正阻抗值与所述矫正阻抗的实际阻抗值相比，获取阻抗调整系数，根据所述调整系数对所测试的线路阻抗进行调整。
电路中一般都存在损耗，且不同芯片的损耗也不相同，所以，在测试之前，先通过所述矫正阻抗提前测试出一个矫正系数，对所测试的硬件链路中的线路阻抗进行矫正，以提高所测试的线路阻抗的准确性。
所述硬件链路为接收链路，所述接收链路通过所述芯片的输入端连接至所述芯片的接收电路，所述芯片还包括第三开关，所述发送电路通过所述第二开关及所述第三开关连接至所述接收链路。
所述硬件链路包括发送链路和接收链路，在对发送链路中的线路阻抗进行测试时，可以直接采用上述实现方式中的方案进行测试，但在对接收链路进行测试时，需要将所述发接收链路连接至所述发送电路，这样就需要通过第二开关及第三开关将所述发接收链路连接至所述发送电路，这样可以分别对所述硬件链路中俄发送链路和接收链路中的线路阻抗进行测试。
可选地，所述处理电路根据采样时间及每个采样时间所采样的采样电压确定所述硬件链路中的不同位置处的线路阻抗时，具体为：
计算发射电压，Vreflected＝Vsample-Vincent,Vsample和Vincent已知，则可以计算出Vreflected，其中，Vsample为采样电压，Vincent为阶跃信号的电压，Vreflected为反射电压；
根据反射系数公式ρ＝Vreflected/Vincident，计算出反射系数ρ，再根据反射系数公式ρ＝Vreflected/Vincident＝(Z-Z0)/(Z+Z0)，得到Z＝Z0((1+ρ)/(1-ρ))，其中Z为所测试的线路阻抗，Z0为线路设计阻抗；
阶跃信号到达硬件链路一线路阻抗所在位置的时间T＝(T2-T1)/2，T2为阻抗测试电路采样到反射电压的采样时刻，T1为阻抗测试电路第一次采样到阶跃信号的采样时刻，
在采样时刻T2采样到的采样电压所对应的线路阻抗在硬件链路中的物理位置：L＝(v*T),其中v为信号在***介质中的传播速率。
根据上述计算公式，可以准确地计算出所述硬件链路中各位置的线路的阻抗。
本发明第二方面提供一种阻抗测试方法。所述方法应用于一芯片。所述芯片通过硬件链路连接至另外一个芯片。所述芯片包括信号产生器及边沿控制器，所述信号产生器产生的脉冲信号经过所述边沿控制器调整为阶跃信号，所述芯片还连接一阻抗测试电路。所述方法包括：
控制所述信号产生器产生脉冲信号，控制所述边沿控制器将所述信号产生器所产生的脉冲信号调整为阶跃信号，所述阶跃信号分两路传输，一路向所述硬件链路传输，一 路经由所述阻抗测试电路传输，所述阶跃信号在经过所述硬件链路中阻值不同的线路阻抗时发生反射，反射后的信号传输至所述阻抗测试电路；
控制所述阻抗测试电路周期性的采样经过所述阻抗测试电路的信号电压值，并根据采样时间及每个采样时间所采样的采样电压确定所述硬件链路中的不同位置处的线路阻抗。
通过在芯片中加入边沿控制器及阻抗测试电路，可以通过芯片检测连接所述芯片与其他芯片的硬件链路中不同位置的线路的阻抗，这样可以准确且快速地定位出出现阻抗异常的线路，从而确定所述异常线路所在的模块，以对所述模块进行替换。
可选地，所述根据采样时间及每个采样时间所采样的采样电压确定所述硬件链路中的不同位置处的线路阻抗时，包括：
计算发射电压，Vreflected＝Vsample-Vincent,Vsample和Vincent已知，则可以计算出Vreflected，其中，Vsample为采样电压，Vincent为阶跃信号的电压，Vreflected为反射电压；
根据反射系数公式ρ＝Vreflected/Vincident，计算出反射系数ρ，再根据反射系数公式ρ＝Vreflected/Vincident＝(Z-Z0)/(Z+Z0)，得到Z＝Z0((1+ρ)/(1-ρ))，其中Z为所测试的线路阻抗，Z0为线路设计阻抗；
阶跃信号到达硬件链路一线路阻抗的时间T＝(T2-T0)/2，T2为阻抗测试电路采样到反射电压的采样时刻，T0为阻抗测试电路第一次采样到阶跃信号的采样时刻；
在采样时刻T2采样到的采样电压所对应的线路阻抗在硬件链路中的物理位置：L＝(v*T),其中v为信号在***介质中的传播速率。
根据上述计算公式，可以准确地计算出所述硬件链路中各位置的线路的阻抗。
通过在芯片中加入边沿控制器及阻抗测试电路，可以通过芯片检测连接所述芯片与其他芯片的硬件链路中不同位置的线路的阻抗，这样可以准确且快速地定位出硬件链路中出现阻抗异常的线路，从而确定所述异常线路所在的模块，以对所述模块进行替换。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍。
图1为两个芯片之间的硬件链路的示意图。
图2为本发明第一实施例提供的芯片的电路结构示意图。
图3为本发明实施例提供的进行硬件链路异常检测方法的流程图。
图4为本发明实施例中对硬件链路的信号进行采样所得的采样时间与采样电压的关系图。
图5为本发明实施例中的阶跃信号在硬件链路中反射的示意图。
图6为本发明实施例中确定的硬件链路中的线路阻抗与线路位置的关系图。
图7为本发明实施例中根据所测试的线路阻抗判断硬件链路是否故障的示意图。
图8为本发明第二实施例提供的芯片的电路结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整 地描述。
本发明实施例提供一种检测两个芯片之间的硬件链路(例如背景技术中所描述的芯片A到芯片B之间的硬件链路)的异常的方法，链路异常可以为链路断开、链路短路、线路阻抗过大等。可在硬件链路中互相通信的两个芯片或者任一芯片内部增加一个异常诊断模块，在需要对所述硬件链路的异常进行诊断时，所述芯片A或芯片B使用所述异常诊断模块测试出所述硬件链路上多个位置处的阻抗，并将测试出的阻抗与设计阻抗(在电路设计时所设定的硬件链路所满足的阻抗)进行比较，若测试阻抗与设计阻抗的差值超过阈值，则所述测试阻抗对应的位置即为出现异常的位置，并根据所确定的位置确定需要更换的设备，例如，图1中，若出现异常的位置为位置2、位置3或者位置8，则认为背板异常，更换背板。如此，可准确并且快速的定位出硬件链路中出现异常的位置。
下面将仍以图1中的硬件链路说明本发明实施例所提供的硬件链路异常检测方法，本发明实施例通过在FRUA的芯片A中增加异常诊断模块，然后通过芯片A诊断连接芯片A与芯片B的发送链路或者接收链路中出现链路异常的位置。
如图2所示，为本发明第一实施例中芯片A的电路结构20。该芯片A包括处理电路21、发送电路22、及接收电路23。该处理电路21用于对接收的信号(例如接收电路23)接收的信号进行处理，并将处理过的信号经过发送电路22输出至与其通过发送链路连接的芯片B。所述硬件链路包括位置1、2、3、4、5形成的发送链路以及位置6、7、8、9、10形成的接收链路。
所述发送电路22包括发送缓冲器(FIFO)221、编码器(Encoder)222、信号产生器(Pattern Generator)223、第一开关(例如选择器MUX1)224等元件。在芯片A正常工作时，处理电路21产生的信号先缓存至所述发送缓冲器221，并经由所述编码器222编码后，经过电路中的其他元件，如极性反转单元(polarity)、串并转换器(PISO)、发送均衡器(Pre/emp)、放大器等元件的处理后，经输出端225输出。所述输出端225通过图1中所示的发送链路连接至所述芯片B。
所述第一开关224根据所述处理电路21的命令选择接通所述编码器222或者所述信号产生器223，当芯片A正常工作时，所述第一开关224选择接通所述编码器222，当芯片A需要测试时，所述第一开关选择接通所述信号产生器223。
本发明实施例为了检测芯片A与芯片B之间的硬件链路的异常，在所述第一开关224与所述信号产生器223之间加入了一个边沿控制器226，所述边沿控制器226用于将所述信号产生器223产生的脉冲信号调整为一个阶跃信号。另外，在所述输出端225及所述处理电路21之间连接一个阻抗测试电路，所述阻抗则是电路包括第二开关(例如选择器MUX2)24及模数转换器(ADC)25，其中，所述第二开关24一端连接至所述输出端225，另外一端连接至所述模数转换器25，所述模数转换器25连接至所述处理电路21。
当所述芯片A正常工作时，所述第一开关224接通所述编码器222，所述第二开关24断开所述模数转换器25与所述输出端225的连接，则处理电路21产生的信号直接通过所述输出端225及所述发送链路传输至所述芯片B。
在所述处理电路21中烧录有异常诊断程序，当需要对硬件链路的异常进行检测时，所述处理电路21执行所述异常诊断程序，对硬件链路进行异常检测，所述处理电路通过运行所述异常诊断程序，执行图3所示的方法：
步骤S301，所述处理电路21发送控制命令至第一开关224、第二开关24、信号产 生器223及边沿控制器226，以控制所述第一开关224接通所述信号产生器，控制所述第二开关24接通所述ADC25与所述输出端225,控制所述信号产生器223产生脉冲信号，控制所述边沿控制器226将所述信号产生器输出的信号调整为一个边沿信号。
所述边沿信号会分两路传输，一路经过所述第二开关及所述ADC传输至所述处理电路21，一路经过所述输出端及所述硬件链路传输至所述芯片B。
在所述边沿信号传输至所述芯片B的过程中，如果硬件链路中存在不同阻值的线路时，则信号在传输至阻值不同的线路的临界位置时会发生信号反射，例如，若硬件链路的位置2处为阻值不同的线路的临界位置，则信号在传输至位置2处时即会发生信号反射，反射的信号通过第二开关及所述ADC传输至所述处理电路21，继续传输的信号在传输到位置3处时，由于位置3也是阻值不同的线路的临界位置，则也同样会发生反射。
步骤S302，所述处理电路21周期性的控制所述ADC25采样接收到的信号电压，并记录所采样的电压与采样时间的关系，采样电压与采样时间的关系可以如图3的示意图所示。其中，当电压没有发生反射时，即硬件链路中线路的阻抗没有变化时，则采样的电压即为发送信号(即所述边沿信号)的初始电压(Vincent)，当电压发生发射时，即硬件链路中的线路阻抗发生变化时，则采样到的电压会高于或者低于初始电压，如图4中采样时刻t1、t2、t3、t4所采样到的电压。
步骤S303，根据所记录的采样电压与采样时间的对应关系，计算采样时刻对应的线路阻抗。
由于在信号传输的过程中，只有阻抗不同的位置处会发生信号反射，所以在计算采样时刻对应的线路阻抗时，也可只计算高于或者低于初始电压的采样电压对应的采样时刻的阻抗。
计算采样时刻对应的阻抗的方法具体为：
获取采样时刻对应的采样电压，采样电压(Vsample)＝初始电压(Vincent)+反射电压(Vreflected)。则Vreflected＝Vsample-Vincent,Vsample和Vincent已知，则可以计算出Vreflected。
得到反射电压Vreflected后，根据反射系数公式ρ＝Vreflected/Vincident，可计算出反射系数ρ。再根据反射系数公式ρ＝Vreflected/Vincident＝(Z-Z0)/(Z+Z0)，可得到Z＝Z0((1+ρ)/(1-ρ))。其中Z为采样时刻T对应的阻抗，Z0为在电路设计时，为硬件链路设计的阻抗，一般为50欧姆。
步骤S304，当计算出采样时刻对应的阻抗后，根据采样时刻计算出采样的线路阻抗在硬件链路中的位置L。
如图5所示，假设处理电路20在T0时刻第一次采样到电压，在T2时刻采样到硬件链路某一线路阻抗的反射电压，由于在T2时刻采样到的反射信号是发送信号到达线路阻抗所处物理位置L后再返回到ADC25被采集到的，则可推算出发送信号到达硬件链路位置3的时间T＝(T2-T0)/2。
如此，根据时间T计算出发生信号反射的线路阻抗在硬件链路中的位置L的方法如下：
根据距离与时间和速度的关系：l＝v*t。可得出ADC25在采样时刻T2采样到的电压所对应的线路阻抗的物理位置：L＝(v*T),其中v为信号在***介质中的传播速率，它与光速C存在一定关系：v＝C/((ε))，其中ε为***已知介质质电常数，即L＝(C*T)/(ε)1/2。
在计算出每个位置对应的阻抗之后，即可得到图6所示的图，从图中可以清楚的看出硬件链路中每个位置的阻抗，将每个位置的阻抗与设计阻抗相比，当某位置的阻抗在设计阻抗+/-10％范围内，如一般50ohm的***，阻抗在45ohm～55ohm之间，则Z可确定为正常状态，如图7中的B所示，如果阻抗接近无穷大，即图7中的A的情况，则说明是开路，如果阻抗接近0hm，则说明电路短路，即图7中的C的情况，这两种情况都为异常情况，另外在阻抗大于设计阻抗的+10％，且并非无穷大，小于设计阻抗的-10％，但又不是接近0hm时，则说明线路阻抗超出正常范围，则需要对该线路所在的模块进行替换。
需要说明的是，所计算的每个位置对应的阻抗可以存储在IC的存储器中，在管理该IC的管理设备启动时，可调用存储器中的数据，将数据显示给用户，用户可基于所显示的数据判断硬件链路中出故障的位置。
通过上述方法，可以准确且快速的判断出硬件链路中出现故障的位置。
在本发明的第二实施例中，所述发送电路还包括第三开关26(例如MUX3)，所述第三开关26连接于所述第二开关24与所述输出端225之间，在所述接收电路23与所述输入端之间连接有第四开关，所述第三开关的一个输出端与所述第四开关的输入端连接，形成第四条线路，其他电路连接于第一实施例中的相同。
在芯片A正常工作时，所述第四开关27接通所述接收电路23和所述输入端226，使由所述输入端226输入的信号经过所述接收电路23传输至所述处理电路21。
在需要对芯片A与芯片B之间的输出链路的异常进行诊断时，所述第三开关26接通所述发送电路22与所述输出端225。所述第二开关接通所述ADC25与所述发送电路22，如此即可对输出链路的异常进行诊断。
在需要对芯片A与芯片B之间的输入链路的异常进行诊断时，所述第三开及26与所述第四开关27接通所述发送电路22与所述输入端226，如此，即可对所述芯片A的输入端226所连接的输入链路中的线路异常进行检测了。异常检测的方法与第一实施例中的相同，在此不再赘述。
由于电路在传输的过程中存在损耗，可以进一步在输出端225连接一个矫正电阻28，在进行硬件链路诊断之前，可以通过所述第三开关26接通所述发送电路22与所述矫正电阻28，然后通过图3所示的方法计算出所述矫正电阻28在电路中的测试阻抗，用所述测试阻抗除以所述矫正电阻的实际阻抗，则可得到一个矫正系数Δ，如此，在计算出硬件链路中的测试阻抗时，则可除以该矫正系数，以对测试阻抗进行矫正，用矫正后的阻抗再去判断对应位置的阻抗是否异常，增加了判断的准确率。
以上对本发明实施例所提供的数据备份装置及方法进行了详细介绍，本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的方法及其核心思想；同时，对于本领域的一般技术人员，依据本发明的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本发明的限制。

Claims (7)

  1. 一种芯片，通过硬件链路连接至另外一个芯片，包括处理电路、发送电路，所述发送电路连接于所述处理电路与所述硬件链路之间，所述发送电路包括信号产生器，用于产生脉冲信号，其特征在于，所述芯片还包括：
    边沿控制器，与所述信号产生器连接；
    阻抗测试电路，连接于所述硬件链路与所述处理电路之间；
    所述处理电路控制所述信号产生器产生脉冲信号，控制所述边沿控制器将所述信号产生器所产生的脉冲信号调整为阶跃信号，所述阶跃信号分两路传输，一路向所述硬件链路传输，一路向所述阻抗测试电路传输，所述阶跃信号在经过所述硬件链路中阻值不同的线路时发生反射，反射后的信号传输至所述阻抗测试电路；
    所处理电路控制所述阻抗测试电路周期性的采样经过所述阻抗测试电路的信号电压值，并根据采样时间及每个采样时间所采样的采样电压确定所述硬件链路中的不同位置处的线路的阻抗。
  2. 如权利要求1所述的芯片，其特征在于，所述阻抗测试电路通过第一开关连接至所述硬件链路，当所述芯片正常工作时，所述第一开关切断所述阻抗测试电路与所述硬件链路的连接，当需要诊断所述硬件链路的异常时，所述第一开关接通所述阻抗测试电路与所述硬件链路的连接。
  3. 如权利要求2所述的芯片，其特征在于，所述第一开关与所述硬件链路之间还连接有第二开关，所述第二开关的一个硬件链路还连接有一矫正阻抗，在对所述硬件链路的阻抗测试之前，通过所述第一开关和第二开关将所述异常诊断电路与所述矫正阻抗接通，将所述矫正阻抗作为所述硬件链路，对所述矫正阻抗的阻抗值进行测试，将所测试的所述矫正阻抗值与所述矫正阻抗的实际阻抗值相比，获取阻抗调整系数，根据所述调整系数对所测试的线路阻抗进行调整。
  4. 如权利要求2所述的芯片，其特征在于，所述硬件链路为接收链路，所述接收链路通过所述芯片的输入端连接至所述芯片的接收电路，所述芯片还包括第三开关，所述发送电路通过所述第二开关及所述第三开关连接至所述接收链路。
  5. 如权利要求任意一项所述的芯片，其特征在于，所述处理电路根据采样时间及每个采样时间所采样的采样电压确定所述硬件链路中的不同位置处的线路阻抗时，具体为：
    计算发射电压，Vreflected＝Vsample-Vincent,Vsample和Vincent已知，则可以计算出Vreflected，其中，Vsample为采样电压，Vincent为阶跃信号的电压，Vreflected为反射电压；
    根据反射系数公式ρ＝Vreflected/Vincident，计算出反射系数ρ，再根据反射系数公式ρ＝Vreflected/Vincident＝(Z-Z0)/(Z+Z0)，得到Z＝Z0((1+ρ)/(1-ρ))，其中Z为所测试的线路阻抗，Z0为线路设计阻抗；
    阶跃信号到达硬件链路一线路阻抗所在位置的时间T＝(T2-T1)/2，T2为阻抗测试电路采样到反射电压的采样时刻，T1为阻抗测试电路第一次采样到阶跃信号的采样时刻，
    在采样时刻T2采样到的采样电压所对应的线路阻抗在硬件链路中的物理位置：L＝ (v*T),其中v为信号在***介质中的传播速率。
  6. 一种阻抗测试方法，应用于一芯片，所述芯片通过硬件链路连接至另外一个芯片，包括信号产生器及边沿控制器，所述信号产生器产生的脉冲信号经过所述边沿控制器调整为阶跃信号，所述芯片还连接一阻抗测试电路，所述方法包括：
    控制所述信号产生器产生脉冲信号，控制所述边沿控制器将所述信号产生器所产生的脉冲信号调整为阶跃信号，所述阶跃信号分两路传输，一路向所述硬件链路传输，一路向所述阻抗测试电路传输，所述阶跃信号在经过所述硬件链路中阻值不同的线路时发生反射，反射后的信号传输至所述阻抗测试电路；
    控制所述阻抗测试电路周期性的采样经过所述阻抗测试电路的信号电压值，并根据采样时间及每个采样时间所采样的采样电压确定所述硬件链路中的不同位置处的线路的阻抗。
  7. 如权利要求6所述的阻抗测试方法，其特征在于，所述根据采样时间及每个采样时间所采样的采样电压确定所述硬件链路中的不同位置处的线路的阻抗时，包括：
    计算发射电压，Vreflected＝Vsample-Vincent,Vsample和Vincent已知，则可以计算出Vreflected，其中，Vsample为采样电压，Vincent为阶跃信号的电压，Vreflected为反射电压；
    根据反射系数公式ρ＝Vreflected/Vincident，计算出反射系数ρ，再根据反射系数公式ρ＝Vreflected/Vincident＝(Z-Z0)/(Z+Z0)，得到Z＝Z0((1+ρ)/(1-ρ))，其中Z为所测试的线路阻抗，Z0为线路设计阻抗；
    阶跃信号到达硬件链路一线路阻抗的时间T＝(T2-T0)/2，T2为阻抗测试电路采样到反射电压的采样时刻，T0为阻抗测试电路第一次采样到阶跃信号的采样时刻；
    在采样时刻T2采样到的采样电压所对应的线路阻抗在硬件链路中的物理位置：L＝(v*T),其中v为信号在***介质中的传播速率。
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