WO2018182698A1

WO2018182698A1 - Perpendicular spin transfer torque memory (psttm) devices with enhanced thermal stability and methods to form the same

Info

Publication number: WO2018182698A1
Application number: PCT/US2017/025438
Authority: WO
Inventors: Tofizur RAHMAN; Christopher J. WIEGAND; Daniel G. OUELLETTE; Angeline K. SMITH; Justin S. BROCKMAN; Kaan OGUZ; Kevin P. O'brien; Mark L. Doczy; Brian S. Doyle; Oleg Golonzka; Tahir Ghani
Original assignee: Intel Corporation
Priority date: 2017-03-31
Filing date: 2017-03-31
Publication date: 2018-10-04

Abstract

A material layer stack for a pSTTM device includes a magnetic tunnel junction (MTJ) having a fixed magnetic layer, a tunnel barrier disposed above the fixed magnetic layer and a free magnetic layer disposed on the tunnel barrier. An oxide layer is disposed on the free magnetic layer and a follower magnetic layer is disposed on the oxide layer, wherein the magnetic layer is magnetically coupled to the free magnetic layer.

Description

PERPENDICULAR SPIN TRANSFER TORQUE MEMORY (PSTTM) DEVICES WITH ENHANCED THERMAL STABILITY AND METHODS TO FORM THE SAME

TECHNICAL FIELD

Embodiments of the invention are in the field of integrated circuit fabrication and, in particular, perpendicular spin transfer torque memory (pSTTM) devices with enhanced thermal stability and methods to form same.

BACKGROUND

For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of

semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased functionality. The drive for ever-more functionality, however, is not without issue. It has become increasingly significant to rely heavily on innovative fabrication techniques to meet the exceedingly tight tolerance requirements imposed by scaling.

Non-volatile embedded memory with pSTTM devices, e.g., on-chip embedded memory with non-volatility can enable energy and computational efficiency. However, the technical challenges of assembling a pSTTM stack to form functional devices present formidable roadblocks to commercialization of this technology today. Specifically, increasing thermal stability of pSTTM devices is one of the challenges in assembling a viable pSTTM stack.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 A illustrates a cross-sectional view of a material layer stack for a perpendicular

STTM device, in accordance with an embodiment of the present invention.

Figure IB illustrates a cross-sectional view of the material layer stack including a follower magnetic layer for a perpendicular STTM device, in an accordance with an embodiment of the present invention.

Figure 2A illustrates a cross-sectional view of a material layer stack for a perpendicular

STTM device, where a storage layer includes a first free magnetic layer, a coupling layer and a second free magnetic layer in an accordance with an embodiment of the present invention.

Figure 2B illustrates a cross-sectional view of the material layer stack with a synthetic anti-ferromagnetic layer disposed below a fixed magnetic layer in accordance with an

embodiment of the present invention. Figure 2C illustrates a cross-sectional view of a material layer stack for a perpendicular STTM device, where a storage layer includes a first free magnetic layer, a coupling layer and a second free magnetic layer, and where a synthetic anti-ferromagnetic layer is disposed below a fixed magnetic layer in an accordance with an embodiment of the present invention.

Figures 3 illustrates a cross-sectional view of individual layers of the synthetic antiferromagnetic layer.

Figure 4A-4E illustrate cross-sectional views representing various operations in a method of fabricating a pSTTM material layer stack in accordance with embodiments of the present invention.

Figure 4A illustrates a cross-sectional view of the formation of a bottom electrode on a conductive interconnect structure formed above a substrate.

Figure 4B illustrates a cross-sectional view of the structure in Figure 4A following the formation of various layers for a magnetic tunnel junction device including a synthetic anti- ferromagnetic layer formed on the bottom electrode layer.

Figure 4C illustrates a cross-sectional view of the structure in Figure 4B following the formation of an oxide layer and the formation of the follower magnetic layer on the oxide layer.

Figure 4D illustrates a cross-sectional view of the structure in Figure 4C following the formation of a capping layer on the follower layer and the formation of a top electrode on the capping layer.

Figure 4E illustrates a cross-sectional view of the structure in Figure 4D following the process of patterning and etching to form a pSTTM device followed by the formation of a spacer layer surrounding the pSTTM device.

Figure 5 illustrates a cross-sectional view of a pSTTM device on a conductive interconnect coupled to a transistor.

Figure 6 illustrates a computing device in accordance with embodiments of the present invention.

DESCRIPTION OF THE EMBODIMENTS

Perpendicular-spin transfer torque memory (pSTTM) devices with enhanced stability and methods of fabrication are described. In the following description, numerous specific details are set forth, such as novel structural schemes and detailed fabrication methods in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that embodiments of the present invention may be practiced without these specific details. In other instances, well-known features, such as transistor operations and switching operations associated with embedded memory, are described in lesser detail in order to not unnecessarily obscure embodiments of the present invention. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.

A pSTTM device functions as a variable resistor where the resistance of the device may switch between a high resistance state and a low resistance state. The resistance state of a pSTTM device is defined by the relative orientation of magnetization of two magnetic layers (fixed and free) that are separated by a tunnel barrier. When the magnetization of the two magnetic layers have orientations that are in the same direction the pSTTM device is said to be in a low resistance state. Conversely, when the magnetization of the two magnetic layers have orientations that are in opposite directions the pSTTM device is said to be in a high resistance state. In an embodiment, resistance switching is brought about by passing a critical amount of spin polarized current or switching current through the pSTTM device so as to influence the orientation of the magnetization of the free magnetic layer to align with the magnetization of the fixed magnetic layer. By changing the direction of the current, the magnetization in the free magnetic layer may be reversed relative to that of the fixed magnetic layer. Since the free magnetic layer does not need power to retain relative orientation of magnetization, the resistance state of the pSTTM device is retained even when there is no power applied to the pSTTM device. For this reason, pSTTM belongs to a class of memory known as non-volatile memory.

Integrating a non-volatile memory device such as a STTM device onto an access transistor enables the formation of embedded memory for system on chip or for other

applications. However, approaches to integrate an STTM device onto an access transistor presents challenges that have become far more formidable with scaling. Examples of such challenges range from improving thermal stability of STTM devices against perturbing forces, reducing switching current and enabling patterning of STTM devices at less than 40nm feature sizes. As scaling continues, the need for smaller memory devices to fit into a scaled cell size has driven the industry in the direction of "perpendicular" STTM or pSTTM. Fortunately, while pSTTM devices have higher stability for small memory device sizes, maintaining stability along with improving other device parameters such as switching current continues to be a challenge.

As the pSTTM device typically includes a multilayer stack of magnetic and non-magnetic materials, the stack is engineered to exhibit thermal stability that allows the device to function as a memory device. To an extent, thermal stability of a pSTTM device depends on the strength of the perpendicular anisotropy of the free magnetic layers in the pSTTM material layer stack. Strength of perpendicular anisotropy depends on the quality and size of the free magnets and to an extent on the number and quality of interfaces between magnetic and non-magnetic layers in the free magnetic layers. Hence, controlling the degree of thermal stability in such pSTTM devices is partly dictated by the increasing the number of magnetic layers and controlling the desired interfacial properties which give rise to perpendicular anisotropy in the first place.

An embodiment of a pSTTM device includes a fixed (reference magnetic layer), a tunnel barrier disposed on the fixed magnetic layer and a free magnetic layer (a switching magnetic layer) including iron disposed on the tunnel barrier. In an embodiment, a thin oxide layer is disposed on the free magnetic layer. A follower magnetic layer including iron is disposed above the oxide layer. The follower magnetic layer is magnetically coupled to the free magnetic layer below the oxide layer to form a coupled system of switching magnetic layers. In an

embodiment, a follower magnetic layer has a weaker magnetic field strength than the magnetic field strength of the free magnetic layer. A magnet having a weaker magnetic field undergoes current induced magnetization switching more easily than a magnet with a stronger magnetic field. The presence of the follower magnetic layer with a weaker magnetic field does not increase the switching current requirements of a pSTTM device. The switching current of a pSTTM device with a weaker magnetic follower layer is dictated by the magnetic strength of the stronger free magnetic layer.

However, by adding a follower magnetic layer, the coupled system of switching magnetic layers has an increased overall thickness. An increase in the total effective thickness (volume) of the switching magnetic layers of the above the tunnel barrier partially results in an increase in thermal stability of the pSTTM device. An increase in thermal stability also results from an increase in the overall interfacial perpendicular anisotropy of the magnetic and non-magnetic layers. In an embodiment, the addition of the oxide layer above the free magnetic layer also further adds interfacial perpendicular anisotropy at the interface between the oxide layer and the free magnetic layer as well at the interface at the between the oxide layer and the follower magnetic layer.

In accordance with embodiments of the present invention, a material layer stack for a pSTTM memory device includes a magnetic tunnel junction (MTJ) stack, an oxide layer, and a follower magnetic layer. In an embodiment, the MTJ includes a fixed magnetic layer, a tunnel barrier disposed above the fixed magnetic layer and a free magnetic layer disposed on the tunnel barrier. The oxide layer is disposed on the free magnetic layer and enables an increase in perpendicular anisotropy of the pSTTM material layer stack. The follower magnetic layer is disposed on the oxide and provides an additional interface for increasing perpendicular anisotropy. The follower magnetic layer is magnetically coupled to the free magnetic layer. The follower magnetic layer also has a material composition and a thickness that enables it to retain magnetic properties. In an embodiment, the follower magnetic layer has a magnetic field strength that is less than the magnetic field strength of the free magnetic layer and also a current switching threshold that is less that than a current switching threshold of the free magnetic layer.

In an embodiment, the follower magnetic layer may include an upper magnetic layer and a lower magnetic layer separated by a non-magnetic conductive layer. In one such embodiment, the upper and lower magnetic layers are also magnetically coupled with each other and with the free magnetic layer below. The presence of extra magnetic layers will also help to increase the perpendicular magnetic anisotropy and increase thermal stability.

Figure 1A illustrates a cross-sectional illustration of a material layer stack 100 for a pSTTM device in accordance with an embodiment of the present invention. The material layer stack 100 for a pSTTM memory device includes a magnetic tunnel junction (MTJ) stack 102 disposed on a bottom electrode layer 104. The MTJ stack 102 has a free magnetic layer 106 which includes iron. The material layer stack 100 further includes an oxide layer 108 disposed on the free magnetic layer 106 of the MTJ stack 102. In an embodiment, the oxide layer 108 includes an MgO. The oxide layer 108 provides a source of oxygen that enables oxygen-iron hybridization at an interface 105 located between an uppermost surface of the free magnetic layer 106 and a lowermost surface of the oxide layer 108. The oxide layer 108 enables an increase in interfacial perpendicular anisotropy of the material layer stack 100. The MTJ stack 102 further includes a follower magnetic layer 110 disposed on the oxide layer 108. The interface 107 formed between the follower magnetic layer 110 and the oxide layer 108 increases the interfacial perpendicular anisotropy. The follower magnetic layer 110 is magnetically coupled to the free magnetic layer 106. In an embodiment, the follower magnetic layer 110 has a magnetic field strength that is less than a magnetic field strength of the free magnetic layer 106. In an embodiment, the follower magnetic layer 110 has a current switching threshold that is less than a current switching threshold of the free magnetic layer 106. In an embodiment, the follower magnetic layer 110 has a thin uppermost portion that can be non-magnetic. In such an embodiment, the follower magnetic layer 110 has a material composition and thickness such that the follower magnetic layer 110 is sufficiently magnetic and is sufficiently magnetically coupled to the free magnetic layer 106.

In an embodiment, the follower magnetic layer 110 includes an alloy such as but not limited to CoFe or CoFeB. In an embodiment the follower magnetic layer 110 is CoFeB. In an embodiment, the follower magnetic layer 110 has a thickness between 0.6nm-2.0 nm. In an embodiment, a CoFeB follower magnetic layer 110 has a thickness of at least 0.6nm to possess sufficient perpendicular anisotropy. Moreover, the interfacial perpendicular anisotropy arising from iron-oxygen hybridization at the interface 107 aids in maintaining the overall

perpendicularity of the follower magnetic layer 110.

In an embodiment, the follower magnetic layer 110 may include multiple magnetic layers separated by a non-magnetic material. Figure IB illustrates a follower magnetic layer 110' which includes a first magnetic layer 111 and a second magnetic layer 113 separated by a conductive layer 112 that is non-magnetic. In one such embodiment, the first and the second magnetic layers 111 and 113, respectively, are also magnetically coupled with each other and with the free magnetic layer 106 below. The presence of the conductive layer 112 introduces two interfaces: (a) interface 115 between the first magnetic layer 111 and the conductive layer 112 and (b) interface 117 between the second magnetic layer 113 and the conductive layer 112. Interfaces 115 and 117 increase the interfacial perpendicular magnetic anisotropy of the pSTTM material layer stack 100.

Referring again to Figure IB, in an embodiment, the first magnetic layer 11 1 and the second magnetic layer 113 are compositionally similar to the follower magnetic layer 110. In an embodiment, the first magnetic layer 111 includes an alloy such as but not limited to CoFe or CoFeB. In an embodiment, the second magnetic layer 113 includes an alloy such as but not limited to CoFe or CoFeB. In an embodiment, the first magnetic layer 111 and the second magnetic layer 113 are CoFeB. In an embodiment, the first magnetic layer 111 has a thickness that is between 0.6nm-1.3 nm and the second magnetic layer 113 has a thickness between O. lnm- 0.9nm. In an embodiment, the first and second magnetic layers 111 and 113 respectively, in the follower magnetic layer 110' has a total thickness between 0.6nm - 2.0 nm. In an embodiment, the follower magnetic layer 110' has a thickness that is between 1-2 times less than the thickness of the free magnetic layer 106.

In an embodiment, the conductive layer 112 is a transition metal layer selected from the group consisting of tungsten, tantalum, molybdenum and ruthenium. In an embodiment, the conductive layer has a thickness that is between 0.3nm-lnm.

Referring again to Figure 1 A, in an embodiment, a capping layer 114 is disposed on the follower magnetic layer 110. In an embodiment, the capping layer 114 includes a metal having a low oxygen affinity. Because atoms from the capping layer 114 can diffuse through the follower magnetic layer 110 and scavenge the oxygen (oxidation) from the oxide layer 108 at the interface 107, a metal with a low oxygen affinity is utilized to form a capping layer 114. The iron-oxygen hybridization in interface 107 is not appreciably altered by the presence of diffused atoms from a low oxygen affinity metal. Thus, by maintaining the iron-oxygen hybridization, interfacial anisotropy can be preserved. In an embodiment, the capping layer 114 includes a metal such as, but not limited to, osmium, rhodium, molybdenum, ruthenium, tungsten, iridium, gold, palladium or platinum. In an embodiment, the capping layer 114 is molybdenum. In an embodiment the capping layer 114 includes a metal that has an oxygen affinity less than the oxygen affinity of tantalum. In an embodiment, the capping layer 114 has a thickness that is between 1.5nm - 6nm. A capping layer 114 having a thickness of 1.5nm-6nm does not appreciably increase the resistivity of the material layer stack 100.

In an embodiment, the MTJ stack 102 further includes a fixed magnetic layer 116 that is disposed on the bottom electrode layer 104. A tunnel barrier 118 is disposed on the fixed magnetic layer 116 and the free magnetic layer 106 is disposed on the tunnel barrier 118. The fixed magnetic layer 116 and the free magnetic layer 106 have perpendicular magnetic anisotropy. The MTJ stack 102 is in a high resistance state when direction of magnetization in the free magnetic layer 106 is opposite (anti-parallel) to the direction of magnetization in the fixed magnetic layer 116. Conversely, the MTJ stack 102 is in a low resistance state when the direction of magnetization in the free magnetic layer 106 is parallel to the direction of magnetization in the fixed magnetic layer 116. A change in resistance (high to low or low to high) in the MTJ stack 102 results when a spin polarized electron current passing from the fixed magnetic layer 116 through the tunnel barrier 118 brings about a change in the direction of the magnetization in the free magnetic layer 106.

In an embodiment, the free magnetic layer 106 of the MTJ stack 102 includes an alloy such as CoFe and CoFeB. In another embodiment, the free magnetic layer 106 includes a layer CoFeB-M, where M is nonmagnetic metal such as but not limited to Mo, W, Ta. In an embodiment, the free magnetic layer 106 is FeB, where the concentration of Boron is between 10-40%. In another embodiment, the free magnetic layer 106 includes a layer of FeB-M, where M is nonmagnetic metal such as but not limited to Mo, W, Ta. In an embodiment the free magnetic layer 106 is CoFeB.

In an embodiment, the free magnetic layer 106 has a thickness between 0.9 nm - 3 nm. In an embodiment, a CoFeB free magnetic layer 106 having a thickness less than 3 nm exhibits a perpendicular anisotropy. Moreover, the interfacial perpendicular anisotropy arising from iron- oxygen hybridization in the interface 105 aids in maintaining the perpendicularity of the free magnetic layer 106.

In an embodiment, the tunnel barrier 118 is composed of a material suitable for allowing electron current having a majority spin to pass through the tunnel barrier 118, while impeding at least to some extent electron current having a minority spin from passing through the tunnel barrier 118. Thus, the tunnel barrier 118 (or spin filter layer) may also be referred to as a tunneling layer for electron current of a particular spin orientation. In one embodiment, the tunnel barrier 118 includes a material such as, but not limited to, magnesium oxide (MgO) or aluminum oxide (AI2O3). In one embodiment, the tunnel barrier 118 is MgO and has a thickness of approximately lnm to 2 nm. In an embodiment, the tunnel barrier 118 and the oxide layer 108 are MgO. In an embodiment, tunnel barrier 118 has a thickness that is greater than the thickness of the oxide layer 108. In an embodiment, the tunnel barrier 118 has a material and thickness that at least 1000 times less conductive than the oxide layer 108.

In an embodiment, the fixed magnetic layer 116 is composed of materials and has a thickness suitable for maintaining a fixed magnetization. In one embodiment, the fixed magnetic layer 116 is composed of a single layer of cobalt iron boron (CoFeB). In an embodiment the fixed magnetic layer 116 has a thickness that is between 2- 3nm. In an embodiment, the fixed magnetic layer 116 has a thickness that is greater than the thickness of the free magnetic layer 106.

In an embodiment, the bottom electrode layer 104 is composed of a material or stack of materials suitable for electrically contacting the fixed magnetic layer 116 side of the material layer stack 100. In an embodiment, the bottom electrode includes an amorphous conductive layer. In an embodiment, the bottom electrode layer 104 is a topographically smooth electrode. In a specific embodiment, the bottom electrode layer 104 is composed of Ru layers interleaved with Ta layers. In another embodiment, the bottom electrode layer 104 is TiN. In an

embodiment, the bottom electrode layer 104 has a thickness between 20nm-50nm.

A top electrode layer 120 is disposed above the MTJ stack 102. In an embodiment, the top electrode layer 120 is disposed on the capping layer 114 as illustrated in Figure 1 A. In an embodiment, the top electrode layer 120 includes a material such as Ta or TiN. In an

embodiment, the top electrode layer 120 has a thickness between 30-70nm. In an embodiment, the top electrode and the bottom electrode include a same metal such as Ta or TiN.

In an embodiment, the free magnetic layer 106 includes multiple free magnetic layers in order increase perpendicular anisotropy of the MTJ stack 102. Figure 2A illustrates a cross sectional view of the material layer stack 200 A, in which the storage layer 201 includes (a) a coupling layer 202 disposed on the free magnetic layer 106 and (b) a second free magnetic layer 204 disposed on the coupling layer 202. Insertion of the coupling layer 202 and the second free magnetic layer 204 increases the number of interfaces between an uppermost surface of the tunnel barrier 118 and a lower most surface of the oxide 108 from 1 to 4. The increase in the number of interfaces increases the overall interfacial perpendicular anisotropy in the MTJ stack 203.

In an embodiment, the free magnetic layer 106 and the second free magnetic layer 204 are a same material. In an embodiment, the free magnetic layer 106 and the second free magnetic layer 204 include different materials each selected independently from the group of consisting of but not limited to CoFeB or FeB, where the concentration of boron is between 10- 40%, or CoFeB-M or FeB-M, where M is nonmagnetic metal such as but not limited to Mo, W, Ta. In an embodiment, the free magnetic layer 106 and the second free magnetic layer 204 include a CoFeB layer. In an embodiment, the free magnetic layer 106 is CoFeB and the second free magnetic layer 204 is FeB, where the concentration of Boron is 20%.

In an embodiment, when the free magnetic layer 106 and the second free magnetic layer 204 include a CoFeB layer, the first free magnetic layer 106 has a thickness greater than the thickness of the second free magnetic layer 204. In an embodiment the CoFeB free magnetic layer 106 has a thickness between 0.5nm - 2.5 nm and the second CoFeB free magnetic layer 204 has a thickness between 0.3nm - 1.5nm. In an embodiment, the CoFeB free magnetic layer 106 and the second CoFeB free magnetic layer 204 have a combined thickness that is between 0.9nm-3.0nm.

In an embodiment, the coupling layer 202 includes a non-magnetic transition metal such as, but not limited to, tungsten, molybdenum, vanadium, niobium iridium. In an embodiment, the coupling layer 202 has a thickness between 0. lnm-lnm. In an embodiment coupling layer 202, is a same metal as the conductive layer 112. In an embodiment, the coupling layer 202 and the conductive layer 112 are both tungsten. In an embodiment, the coupling layer 202 is tantalum and the conductive layer 112 is tungsten.

Depending on embodiments, the follower magnetic layer may be a single magnetic follower layer 110 or a magnetic follower layer 110' as illustrated in Figure 2A. Each follower magnetic layer 110 or 110' is magnetically coupled to the storage layer 201. In an embodiment, the follower magnetic layer 110' has a magnetic field strength and a current switching threshold that is less than a magnetic field strength and a current switching threshold of the storage layer 201. In an embodiment, the follower magnetic layer 110 has a magnetic field strength and a current switching threshold that is less than a magnetic field strength and a current switching threshold of the storage layer 201.

Figure 2B illustrates a cross-sectional illustration of a material layer stack 200B in which a synthetic antiferromagnetic (SAF) structure 220 is disposed between the bottom electrode layer 104 and the fixed magnetic layer 116 in accordance with an embodiment of the present invention. In an embodiment, the free magnetic layer 106 and the fixed magnetic layer 116 can have similar thicknesses and an injected electron spin current which changes the orientation of the magnetization in the free magnetic layer 106 can also affect the magnetization of the fixed magnetic layer 116. In an embodiment, to make the fixed magnetic layer 1 16 more resistant to accidental flipping a synthetic antiferromagnetic (SAF) structure 220 is disposed between the bottom electrode 104 and the fixed magnetic layer 116. In an embodiment, when the fixed magnetic layer 116 has a thickness that is less than 1.5nm, a synthetic antiferromagnetic (SAF) structure 150 is disposed on the bottom electrode layer 104 and below the fixed magnet 106 in order to prevent accidental flipping of the fixed magnetic layer 116. The SAF structure 150 is ferromagnetically coupled with the fixed magnetic layer 116 and pins the direction of the magnetization in the fixed magnetic layer 116.

Figure 3 illustrates cross-sectional view of the synthetic antiferromagnetic (SAF) structure 220 in an accordance of an embodiment of the present invention. In an embodiment, the SAF structure 220 includes a non-magnetic layer 220B sandwiched between a first ferromagnetic layer 220A and a second ferromagnetic layer 220C as depicted in Figure 3. The first ferromagnetic layer 220A and the second ferromagnetic layer 220C are anti- ferromagnetically coupled to each other. In an embodiment, the first ferromagnetic layer 220A includes a layer of a magnetic metal such as Co, Ni, Fe, alloys such as CoFe, CoFeB, or alloys of magnetic metals such as Co, Ni, Fe or a bilayer of a magnetic/non-magnetic metals such but not limited to Co/Pd or a Co/Pt. In an embodiment, the non-magnetic layer 220B includes a ruthenium or an iridium layer. In an embodiment, the second ferromagnetic layer 220C includes a layer of a magnetic metal such as Co, Ni, Fe, alloys such as CoFe, CoFeB, or alloys of magnetic metals such as Co, Ni, Fe or a bilayer of a magnetic/non-magnetic metals such but not limited to Co/Pd or a Co/Pt. In an embodiment, a ruthenium based non-magnetic layer 220B is limited to a thickness between 4-9 Angstroms to ensure that the coupling between the first ferromagnetic layer 220A and the second ferromagnetic layer 220C is anti-ferromagnetic in nature.

It is to be appreciated that an additional layer of non-magnetic spacer material (not shown in Figure 2B) may be disposed on the SAF structure 220, below the fixed magnetic layer 116. The non-magnetic spacer layer enables coupling between the SAF structure 220 and the fixed magnetic layer 116. In an embodiment, a non-magnetic spacer layer may include metals such as Ta, Ru or Ir.

Figure 2C illustrates a cross-sectional view of a material layer stack 200C which includes (a) the coupling layer 202 and the second free magnetic layer 204 to improve perpendicular anisotropy in the material layer stack 200C and (b) the SAF structure 220 to improve stability in the fixed magnetic layer 116. Depending on embodiments, the follower magnetic layer may be a single magnetic follower layer 110 or a magnetic follower layer 110' as illustrated in Figure 2C. Each follower magnetic layer 110 or 110' is magnetically coupled to the storage layer 201. In an embodiment, the follower magnetic layer 110' has a magnetic field strength and a current switching threshold that is less than a magnetic field strength and a current switching threshold of the storage layer 201. In an embodiment, the follower magnetic layer 110 has a magnetic field strength and a current switching threshold that is less than a magnetic field strength and a current switching threshold of the storage layer 201.

It is to be appreciated that an additional layer of non-magnetic spacer material (not shown in Figure 2C) may be disposed on the SAF structure 220, below the fixed magnetic layer 116. The non-magnetic spacer layer enables coupling between the SAF structure 220 and the fixed magnetic layer 116. In an embodiment, a non-magnetic spacer layer may include metals such as Ta, Ru or Ir.

Figure 4A-4D illustrate cross-sectional views representing various operations in a method of fabricating the pSTTM material layer stack 200C depicted in Figure 2C.

Figure 4 A illustrates a cross-sectional view of the formation of the bottom electrode 104 on a conductive interconnect structure 400 formed above a substrate 410. In an embodiment, the conductive interconnect structure 400 includes a conductive interconnect 401 formed in a dielectric layer 402 by a dual damascene process that is well known in the art. In an

embodiment, the conductive interconnect includes a material such as tungsten, tantalum or ruthenium and the dielectric layer 402 includes a material such as but not limited to silicon dioxide, silicon nitride, silicon carbide, or carbon doped silicon oxide. In an embodiment, the bottom electrode layer 104 includes an alloy such as TiN or TaN. In an embodiment, the bottom electrode layer 104 is deposited using a physical vapor deposition process or a plasma enhanced chemical vapor deposition process. In an embodiment the bottom electrode 104 is first blanket deposited and subsequently planarized to form a topographically smooth uppermost surface having a surface roughness that is less than 2nm.

Figure 4B illustrates a cross-sectional view of the formation of the SAF structure 220 above the conductive bottom electrode 104, the formation of the MTJ stack 203 above the SAF structure 220. In an embodiment, the SAF structure 220, the fixed magnetic layer 116, the tunnel barrier 118, the free magnetic layer 106, the coupling layer 202 and the second free magnetic layer 204 are sequentially blanket deposited onto the bottom electrode 104 by deposition methods that are well known in the art. It is to be appreciated that an additional layer of non- magnetic spacer material (not shown in Figure 4B) may be deposited on the SAF structure 220 before deposition of the fixed magnetic layer 116. In an embodiment, a non-magnetic spacer layer may include metals such as, but not limited to, Ta, Ru or Ir.

The free magnetic layer 106, the coupling layer 202 and the second free magnetic layer 204 are collectively referred to as the storage layer 201. In an embodiment, the deposition process includes a (PVD) process. In an embodiment, an RF or a DC sputtering process is utilized to form the various layer in the MTJ stack 203, as is well known in the art. In an embodiment, the bottom electrode layer 104, the SAF structure 220, the non-magnetic spacer material, and the MTJ stack 203 are deposited sequentially without an air break. In an embodiment, The SAF structure 220 is blanket deposited onto the bottom electrode 104 that has been planarized. Figure 4C illustrates a cross-sectional view of the structure in Figure 4B following the formation of the oxide layer 108 on the MTJ stack 203 and the formation of the follower magnetic layer 110' on the oxide layer 108. In an embodiment, the oxide layer 108 is deposited using a reactive sputter deposition technique and includes a material such as MgO. In an embodiment, the oxide layer 108 is deposited to a thickness between 0.3nm - 1.5nm. In an embodiment, the oxide layer 108 and the tunnel barrier 118 are MgO. In one such embodiment, the oxide layer 108 has a thickness that is less than the thickness of the tunnel barrier 118.

In an embodiment, the follower magnetic layer 110' is blanket deposited on the uppermost surface of the oxide layer 108 using a co-sputter and reactive sputtering process. In an embodiment, the deposition process includes a physical vapor deposition (PVD) process. In an embodiment, an RF or a DC sputtering process is utilized to form the various layers in the magnetic layer 110'. In an embodiment, the magnetic follower layer is a single magnetic layer

110 and is also deposited using an RF or a DC sputtering process.

In an embodiment, the first magnetic layer 111 is Coi-x-yFe_xBy, where X and Y each represent atomic percent, further where X is between 0.5-0.8 and Y is between 0.1-0.4, and further where the sum of X and Y is less than 1. In an embodiment the first magnetic layer 111 is deposited on the oxide layer 108 to a thickness of 0.6nm-1.5nm.

The conductive layer 112 is deposited on the first magnetic layer 111. In an embodiment, the deposition process includes a process such as but not limited to PVD or a reactive sputter deposition process. The conductive layer 112 includes a transition metal layer selected from the group consisting of tungsten, tantalum, molybdenum and ruthenium. In an embodiment, the conductive layer 112 is deposited to a thickness of 0.1-lnm.

In an embodiment, the process of depositing the conductive layer 112 causes in a small uppermost fraction of the first magnetic layer 111 to become magnetically dead. In an embodiment, the free magnetic layer 111 has magnetically dead portion that is less than 5% of the total thickness of the first magnetic layer 111. In an embodiment, the free magnetic layer

111 has magnetically dead portion that is at least 50% of the total thickness of the first magnetic layer 111. In an embodiment, the magnetically dead portion is not continuous throughout the structure of the first magnetic layer 111. By depositing the first magnetic layer 111 to a thickness of at least 0.6nm, the first magnetic layer 111 functions as a magnetic layer even if portions of it are magnetically dead.

In an embodiment, the second magnetic layer 113 is deposited on the surface of the conductive layer 112 by a process similar to the process utilized to deposit the first magnetic layer 111. In an embodiment, the iron composition of the second magnetic layer 113 is less than compared to the iron composition of the first magnetic layer. In an embodiment, the second magnetic layer 113 is deposited to a thickness that is less than the thickness of the first magnetic layer. In an embodiment, the second magnetic layer 113 is deposited to a thickness that is similar to the thickness of the first magnetic layer, but its effective perpendicular anisotropy becomes weaker when the capping layer 114 is subsequently deposited, as will be discussed below. In an embodiment, the process of depositing the second magnetic layer 113 can lead to intermixing with the underlying conductive layer 112.

In an embodiment, the Coi-x-yFe_xBy, in each of the first and the second magnetic layers 111 and 113, respectively are deposited to a total thickness of 0.9nm to 1.6nm to ensure that the follower magnetic layer 110' has a resulting magnetic field strength that is less than the magnetic field strength of the storage layer 201 in the MTJ stack 203.

Figure 4D illustrates a cross-sectional view of the structure in Figure 4C formation of a capping layer 114 on the follower layer 110' and the formation of a top electrode 120 on the capping layer 114. In an embodiment, the capping layer 114 includes a metal such as molybdenum or ruthenium. Metals with a lack of oxygen affinity such as molybdenum and ruthenium provide protection against oxygen scavenging from the interface 105 and 107.

Protection against oxygen scavenging from interface 105 and 107 helps to maintain interfacial perpendicular anisotropy in the follower layer. In an embodiment, the capping layer 114 is blanket deposited onto the surface of the protective layer 110, using a low energy physical vapor deposition (PVD) process. In an embodiment, the capping layer 114 is deposited to a thickness of 1.5nm-5nm. A capping layer 114 having a thickness of 1.5-5nm provides a barrier against out-diffusion of oxygen from the oxide layer 108.

In an embodiment, the process of depositing the capping layer 114 can lead to intermixing with the underlying second magnetic layer 113. In another embodiment, the process of depositing the capping layer 114 can render portions of the second magnetic layer 113 magnetically dead. However, the magnetically dead portions may not be continuous throughout the structure of the second magnetic layer 113. In an embodiment, the second magnetic layer 113 is deposited to a thickness of at least 0.6nm to remain magnetic after the deposition of the capping layer 114.

In an embodiment, the top electrode layer 120 is blanket deposited on the surface of the capping layer 114. In an embodiment, the top electrode layer 120 includes a material suitable to provide a hardmask for etching the material layer stack 100 to form pSTTM devices. In an embodiment, the top electrode layer includes a material such as Ta. In an embodiment, the thickness of the top electrode layer ranges from 30-70nm. The thickness is chosen to

accommodate the various sizes of the pSTTM devices that will subsequently be fabricated as well as to provide etch resistivity during etching of the MTJ stack 102 or 203. In an embodiment, after all the layers in the pSTTM material layer stack 200C are deposited, an anneal is performed under conditions well known in the art to promote solid phase epitaxy of the free magnetic layer 106 following a template of a crystalline layer of the tunnel barrier layer 118. A post-deposition anneal of the pSTTM material layer stack 200C is carried out in a furnace at a temperature between 300-400 degrees C. In an embodiment, the anneal is performed immediately post deposition but before patterning of the pSTTM material layer stack 200C to enable crystalline MgO to be formed in the tunnel barrier layer 118.

In an embodiment, the annealing process is also performed in the presence of a magnetic field which sets the magnetization direction of the fixed magnetic layer 116 and the free magnetic layer 106, the second free magnetic layer 204 and the follower magnetic layer 110' . An applied magnetic field that is directed parallel to the vertical axis of the pSTTM material layer stack 200C, during the annealing process, enables a perpendicular anisotropy to be set in the fixed magnetic layer 116, in the free magnetic layer 106, in the second free magnetic layer 204 and in the follower magnetic layer 110' . The annealing process initially aligns the magnetization of the fixed magnetic layer 116, the free magnetic layer 106, the second free magnetic layer 204 and the follower magnetic layer 110' to be parallel to each other.

Figure 4E illustrates the structure of Figure 4E following the formation of a pSTTM device 450 and the formation of a dielectric spacer liner 404 surrounding the pSTTM device 450. In an embodiment, a layer of resist is formed (not shown) on the pSTTM material layer stack 200C. The is lithographically patterned and etched. In an embodiment, the pSTTM material layer stack 200C is etched by a plasma etch process. The plasma etch process etches the entire pSTTM material layer stack 200C to form the pSTTM device 450. In an embodiment, the plasma etch process consumes between 50-80% of the top electrode layer 120. In an

embodiment, the pSTTM device 450 has a sidewall angle that is tapered.

In an embodiment, a dielectric spacer layer 404 is deposited on the pSTTM device 450 and on an uppermost surface of the dielectric layer 402. In an embodiment, the dielectric spacer layer 404 is deposited without a break following the plasma etch process. In an embodiment, the dielectric spacer layer 404 includes a material such as silicon nitride or carbon doped silicon nitride and does not contain a material that includes oxygen.

In an embodiment, a second anneal process can be performed after formation of the pSTTM device 450 and deposition of the dielectric spacer layer 404. In an embodiment, the second anneal process is carried out at a process temperature of at least 300 degrees Celsius but less than 500 degrees Celsius. In an embodiment, the post patterning and spacer deposition anneal process can help to recrystallize sidewalls of the tunnel barrier 118 that may have become potentially damaged during the etching process utilized to form the pSTTM device 450. Magnetic measurements of thermal stability and tunneling magneto-resistance ratio (TMR) and resistance area (RA) product may be measured after the pSTTM material layer stack 200C has been formed. In an embodiment, thermal stability measurements of pSTTM devices having a device size of 40nm, fabricated with the pSTTM material layer stack 200C, exhibit mean thermal stability that is 30% higher than a stack without a follower magnetic layer 110' . In one such embodiment, measurements of the TMR ratio and RA product of the pSTTM material layer stack 200C exhibit similar mean TMR and mean RA product values as a material layer stack without the follower magnetic layer 110' .

Figure 5 illustrates a pSTTM memory device 500, formed on a conductive interconnect 502. In an embodiment, the conductive interconnect is disposed on a contact structure 504 above a drain region 506 of an access transistor 508 disposed above a substrate 510. In an

embodiment, a material layer stack such as the material layer stack 200C described in association with Figure 4D, is blanket deposited on a conductive interconnect 502. The MTJ material layer stack 200C is lithographically patterned and then etched to form a pSTTM memory device 500 as is illustrated in Figure 5. In an embodiment, the pSTTM memory device 500 includes a pSTTM memory device such as pSTTM memory device 100A described in association with Figure 1 A. In an embodiment, the pSTTM memory device 500 includes a bottom electrode layer 104, a fixed magnetic layer 116 disposed on the bottom electrode layer 104, a tunnel barrier 118, a free magnetic layer 106, an oxide layer 108, a follower magnetic layer 110', a capping layer 114 and a top electrode layer 120. In an embodiment, the pSTTM memory device 500 is surrounded by a dielectric spacer layer 501 as illustrated in Figure 5. In an embodiment, the pSTTM memory device 500 has a width that is greater than the width of the conductive interconnect 502. In one such embodiment, a portion of the bottom electrode 104 of pSTTM memory device 500 is also disposed on a dielectric layer 503. In an embodiment, the pSTTM memory device 500 has a width smaller than the width of the conductive interconnect 502. In an embodiment, the pSTTM memory device 500 has a width equal to the width of the conductive interconnect 502.

In an embodiment, the underlying substrate 510 represents a surface used to manufacture integrated circuits. Suitable substrate 510 includes a material such as single crystal silicon, polycrystalline silicon and silicon on insulator (SOI), as well as similar substrates formed of other semiconductor materials. The substrate 510 may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates.

In an embodiment, the access transistor 508 associated with substrate 510 are metal- oxide- semi conductor field-effect transistors (MOSFET or simply MOS transistors), fabricated on the substrate 510. In various implementations of the invention, the access transistor 508 may be planar transistors, nonplanar transistors, or a combination of both. Nonplanar transistors include

FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors.

In an embodiment, the access transistor 508 of substrate 510 includes a gate stack formed of at least two layers, a gate dielectric layer 514 and a gate electrode layer 512. The gate dielectric layer 514 may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide (S1O2) and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer 514 to improve its quality when a high-k material is used.

The gate electrode layer 512 of the access transistor 508 of substrate 510 is formed on the gate dielectric layer 514 and may consist of at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an MOS transistor. In some implementations, the gate electrode layer 512 may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a conductive fill layer.

For a PMOS transistor, metals that may be used for the gate electrode layer 512 include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV.

In some implementations, the gate electrode may consist of a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode 512 may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the invention, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode 512 may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

In some implementations of the invention, a pair of sidewall spacers 516 may be formed on opposing sides of the gate stack that bracket the gate stack. The sidewall spacers 516 may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process operations. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

As is well known in the art, source region 518 and drain region 506 are formed within the substrate adjacent to the gate stack of each MOS transistor. The source region 518 and drain region 506 are generally formed using either an implantation/diffusion process or an

etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source region 518 and drain region 506. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source region 518 and drain region 506. In some implementations, the source region 518 and drain region 506 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the source region 518 and drain region 506 may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the source region 518 and drain region 506.

In an embodiment, a gate contact 520 and a source contact 522 are formed in a second dielectric layer 524 and in the dielectric layer 503 above the gate electrode 512 and source region 518, respectively.

Figure 6 illustrates a computing device 600 in accordance with one embodiment of the invention. The computing device 600 houses a motherboard 602. The motherboard 602 may include a number of components, including but not limited to a processor 604 and at least one communication chip 606. The processor 604 is physically and electrically coupled to the motherboard 602. In some implementations the at least one communication chip 606 is also physically and electrically coupled to the motherboard 602. In further implementations, the communication chip 606 is part of the processsor 604.

Depending on its applications, computing device 600 may include other components that may or may not be physically and electrically coupled to the motherboard 602. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

The communication chip 606 enables wireless communications for the transfer of data to and from the computing device 600. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 606 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 600 may include a plurality of communication chips 606. For instance, a first communication chip 606 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 606 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 604 of the computing device 600 includes an integrated circuit die packaged within the processor 604. In some implementations of embodiments of the invention, the integrated circuit die of the processor includes one or more memory devices, such as a pSTTM memory device 500, built with a pSTTM material layer stack 200C in accordance with embodiments of the present invention. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 606 also includes an integrated circuit die packaged within the communication chip 606. In accordance with another implementation of an embodiment of the invention, the integrated circuit die of the communication chip includes pSTTM memory elements integrated with access transistors, built in accordance with embodiments of the present invention.

In further implementations, another component housed within the computing device 600 may contain a stand-alone integrated circuit memory die that includes one or more memory elements, built in accordance with embodiments of the present invention.

In various implementations, the computing device 600 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra- mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set- top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 600 may be any other electronic device that processes data.

Accordingly, one or more embodiments of the present invention relate generally to the fabrication of embedded microelectronic memory. The microelectronic memory may be nonvolatile, wherein the memory can retain stored information even when not powered. One or more embodiments of the present invention relate to the fabrication of a pSTTM material layer stack 200C. Such pSTTM material layer stack 200C may be used in an embedded non-volatile memory application.

Thus, embodiments of the present invention include perpendicular-STTM (pSTTM) devices with enhanced stability and methods to form same.

Specific embodiments are described herein with respect to pSTTM devices. It is to be appreciated that embodiments described herein may also be applicable to other non-volatile memory devices. Such non-volatile memory devices may include, but are not limited to, magnetic random access memory (MRAM) devices, spin torque transfer memory (STTM) devices and spin orbit torque (SOT) memory devices.

Example 1 : A material layer stack for a pSTTM device includes a magnetic tunnel junction (MTJ) having a fixed magnetic layer, a tunnel barrier disposed above the fixed magnetic layer and a free magnetic layer disposed on the tunnel barrier. An oxide layer is disposed on the free magnetic layer and a follower magnetic layer is disposed on the oxide layer, wherein the magnetic layer is magnetically coupled to the free magnetic layer.

Example 2: The material layer stack of example 1, wherein the follower magnetic layer has a magnetic field strength that is less than a magnetic field strength of the free magnetic layer.

Example 3 : The material layer stack of example 1 or 2, wherein the follower magnetic layer has a current switching threshold that is less than a current switching threshold of the free magnetic layer.

Example 4: The material layer stack of example 1, 2, or 3, wherein the follower magnetic layer and the free magnetic layer include cobalt and iron.

Example 5: The material layer stack of example 1, 2, 3 or 4, wherein the follower magnetic layer and the free magnetic layer further include boron.

Example 6: The material layer stack of example 1, 2, 3, 4 or 5, wherein the free magnetic layer has a thickness that is between 1-2 times thicker than the follower magnetic layer.

Example 7: The material layer stack of example 1, wherein the follower layer includes a first magnetic layer and a second magnetic layer separated by a conductive layer in between.

Example 8: The material layer stack of example 7, wherein the first magnetic layer has thickness that is between 1.5-2 times thicker than the second magnetic layer.

Example 9: The material layer stack of example 7, wherein the conductive layer is a transition metal layer.

Example 10: The material layer stack of example 9, wherein the transition metal is selected from the group consisting of tungsten, tantalum, molybdenum and ruthenium.

Example 11 : A material layer stack for a pSTTM device includes a magnetic tunnel junction (MTJ). The MTJ incudes a fixed magnetic layer, a tunnel barrier disposed above the fixed magnetic layer, a storage layer including a first free magnetic layer disposed on the tunnel barrier, a coupling layer disposed above the first free magnetic layer and a second free magnetic layer disposed on the coupling layer. An oxide layer is disposed on the storage layer. A follower magnetic layer is disposed on the oxide layer and the follower magnetic layer incudes a conductive layer sandwiched between a first magnetic layer and a second magnetic layer. The first magnetic layer is disposed on the oxide layer and the follower magnetic layer is

magnetically coupled to the storage layer. A capping layer is disposed directly on the follower magnetic layer. A top electrode layer disposed above the capping layer. A bottom electrode layer is disposed below the MTJ.

Example 12: The material layer stack of example 11, wherein the follower magnetic layer has a current switching threshold that is less than a current switching threshold of the storage layer.

Example 13 : The material layer stack of example 11 or 12, wherein the follower magnetic layer has a magnetic field strength that is less than a magnetic field strength of the storage layer.

Example 14: The material layer stack of example 11, wherein the first free magnetic layer, the second free magnetic layer, the first magnetic layer and the second magnetic layer include cobalt and iron. Example 15: The material layer stack of example 11 or 14, wherein the first free magnetic layer, the second free magnetic layer, the first magnetic layer and the second magnetic layer further include boron.

Example 16: The material layer stack of example 1 lor 12, wherein the first magnetic layer has a thickness between 0.6nm-l .5nm and wherein the second magnetic layer has a thickness between 0.1nm-0.6nm.

Example 17: The material layer stack of example 11, wherein the first magnetic layer and the second magnetic layer have a combined total thickness that is approximately less than a combined total thickness of first free magnetic layer and the second free magnetic layer.

Example 18: The material layer stack of example 11, wherein the conductive layer is a transition metal layer selected from the group consisting of tungsten, tantalum, molybdenum and ruthenium.

Example 19: The material layer stack of example 11 or 18, wherein the conductive layer has a thickness that ranges from 0.1-0.6nm.

Example 20: The material layer stack of example 11, 18 or 19, wherein the conductive layer is a same metal as the coupling layer.

Example 21 : The material layer stack of example 11, wherein a synthetic

antiferromagnetic layer is disposed between the fixed layer and the bottom electrode layer.

Example 22: A method of fabricating a material layer stack for a non-volatile memory device includes forming a bottom electrode layer and forming a magnetic tunnel junction (MTJ) above the bottom electrode. The method of forming the MTJ includes forming a fixed magnetic layer above the bottom electrode, forming a tunnel barrier on fixed magnetic layer, and forming a storage layer above the tunnel barrier. The method of fabricating the material layer stack further includes forming an oxide layer on the coupling layer, forming a follower magnetic layer on the oxide layer, forming a capping layer on the follower magnetic layer and forming a top electrode layer on the capping layer.

Example 23 : The method of example 22, wherein forming the follower magnetic layer includes depositing a first magnetic layer on the oxide layer, depositing a conductive layer on the first magnetic layer and depositing a second magnetic layer on the conductive layer.

Example 24: The method of example 23, wherein depositing the conductive layer on the second magnetic layer causes intermixing between materials including the second magnetic layer and materials including the conductive layer, and wherein the process of depositing the conductive layer on the first magnetic layer damages an uppermost magnetic portion of the first magnetic layer.

Claims

CLAIMS What is claimed is:

1. A material layer stack for a pSTTM device, the material layer stack comprising:

a magnetic tunnel junction (MTJ) including a fixed magnetic layer, a tunnel barrier above the fixed magnetic layer and a free magnetic layer on the tunnel barrier; an oxide layer on the free magnetic layer; and

a follower magnetic layer on the oxide layer, wherein the magnetic layer is magnetically coupled to the free magnetic layer.

2. The material layer stack of claim 1, wherein the follower magnetic layer has a magnetic field strength that is less than a magnetic field strength of the free magnetic layer.

3. The material layer stack of claim 2, wherein the follower magnetic layer has a current switching threshold that is less than a current switching threshold of the free magnetic layer.

4. The material layer stack of claim 1, wherein the follower magnetic layer and the free magnetic layer comprise cobalt and iron.

5. The material layer stack of claim 4, wherein the follower magnetic layer and the free magnetic layer further comprise boron.

6. The material layer stack of claim 1, wherein the free magnetic layer has a thickness that is between 1-2 times thicker than the follower magnetic layer.

7. The material layer stack of claim 1, wherein the follower layer includes a first magnetic layer and a second magnetic layer separated by a conductive layer in between.

8. The material layer stack of claim 7, wherein the first magnetic layer has thickness that is between 1.5-2 times thicker than the second magnetic layer.

9. The material layer stack of claim 7, wherein the conductive layer is a transition metal layer.

10. The material layer stack of claim 9, wherein the transition metal is selected from the group consisting of tungsten, tantalum, molybdenum and ruthenium.

11. A material layer stack for a pSTTM device, the material layer stack comprising:

a magnetic tunnel junction (MTJ), the MTJ comprising:

a fixed magnetic layer;

a tunnel barrier above the fixed magnetic layer;

a storage layer, the storage layer including a first free magnetic layer on the tunnel barrier, a coupling layer above the first free magnetic layer and a second free magnetic layer on the coupling layer;

an oxide layer on the storage layer;

a follower magnetic layer on the oxide layer, the follower magnetic layer comprising a conductive layer sandwiched between a first magnetic layer and a second magnetic layer, wherein the first magnetic layer is on the oxide layer and wherein the follower magnetic layer is magnetically coupled to the storage layer;

a capping layer directly on the follower magnetic layer;

a top electrode layer above the capping layer; and

a bottom electrode layer below the MTJ.

12. The material layer stack of claim 11, wherein the follower magnetic layer has a current switching threshold that is less than a current switching threshold of the storage layer.

13. The material layer stack of claim 11, wherein the follower magnetic layer has a magnetic field strength that is less than a magnetic field strength of the storage layer.

14. The material layer stack of claim 11, wherein the first free magnetic layer, the second free magnetic layer, the first magnetic layer and the second magnetic layer comprise cobalt and iron.

15. The material layer stack of claim 14, wherein the first free magnetic layer, the second free magnetic layer, the first magnetic layer and the second magnetic layer further comprise boron.

16. The material layer stack of claim 11, wherein the first magnetic layer has a thickness between 0.6nm-1.5nm and wherein the second magnetic layer has a thickness between O. lnm- 0.6nm.

The material layer stack of claim 11, wherein the first magnetic layer and the second magnetic layer have a combined total thickness that is approximately less than a combined total thickness of first free magnetic layer and the second free magnetic layer.

18. The material layer stack of claim 11, wherein the conductive layer is a transition metal layer selected from the group consisting of tungsten, tantalum, molybdenum and ruthenium.

19. The material layer stack of claim 11, wherein the conductive layer has a thickness that ranges from 0.1-0.6nm.

20. The material layer stack of claim 11, wherein the conductive layer is a same metal as the coupling layer.

21. The material layer stack of claim 11, wherein a synthetic antiferromagnetic layer is between the fixed layer and the bottom electrode layer.

22. A method comprising, fabricating a material layer stack for a non-volatile memory device, the method comprising:

forming a bottom electrode layer;

forming a magnetic tunnel junction (MTJ) above the bottom electrode, the forming

comprising:

forming a fixed magnetic layer;

forming a tunnel barrier on fixed magnetic layer;

forming a storage layer above the tunnel barrier;

forming an oxide layer on the coupling layer;

forming a follower magnetic layer on the oxide layer;

forming a capping layer on the follower magnetic layer; and

forming a top electrode layer on the capping layer.

23. The method of claim 22, wherein forming the follower magnetic layer includes depositing a first magnetic layer on the oxide layer, depositing a conductive layer on the first magnetic layer and depositing a second magnetic layer on the conductive layer.

24. The method of claim 23, wherein depositing the conductive layer on the second magnetic layer causes intermixing between materials comprising the second magnetic layer and materials comprising the conductive layer, and wherein the process of depositing the conductive layer on the first magnetic layer damages an uppermost magnetic portion of the first magnetic layer.