WO2019005158A1

WO2019005158A1 - Spin orbit torque (sot) memory devices with enhanced thermal stability and methods to form same

Info

Publication number: WO2019005158A1
Application number: PCT/US2017/040497
Authority: WO
Inventors: Kaan OGUZ; Kevin P. O'brien; Brian S. Doyle; Charles C. Kuo; Mark L. Doczy
Original assignee: Intel Corporation
Priority date: 2017-06-30
Filing date: 2017-06-30
Publication date: 2019-01-03

Abstract

A spin orbit torque (SOT) memory device includes a spin orbit torque electrode disposed in a dielectric layer above a substrate and a magnetic tunnel junction (MTJ) device disposed on a portion of the spin orbit torque electrode. The spin orbit torque electrode has a uppermost surface area that is 10-20 times larger than a lowermost surface area of the MTJ memory device. The MTJ memory device includes a storage layer disposed on the spin orbit torque electrode, a tunnel barrier such as an MgO disposed on the storage layer and a fixed magnetic layer disposed on the tunnel barrier.

Description

SPIN ORBIT TORQUE (SOT) MEMORY DEVICES WITH ENHANCED THERMAL STABILITY AND

METHODS TO FORM SAME

TECHNICAL FIELD

Embodiments of the disclosure are in the field of integrated circuit fabrication and, in particular, related to spin orbit torque (SOT) memory devices with enhanced thermal stability and methods to form the same.

BACKGROUND

For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased functionality. The drive for ever-more functionality, however, is not without issue. It has become increasingly significant to rely on innovative devices such as spin orbit torque (SOT) memory devices replete with complicated material layer stacks to overcome the requirements imposed by scaling.

Non-volatile embedded memory with SOT memory devices, e.g., on-chip embedded memory with non-volatility can enable energy and computational efficiency. However, the technical challenges of assembling a material layer stack to form functional devices present formidable roadblocks to commercialization of this technology today. Specifically, increasing thermal stability and reducing retention loss of SOT memory devices are some important areas of process development.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 A illustrates a cross-sectional view of a spin orbit torque (SOT) memory device, in accordance with an embodiment of the present disclosure.

Figure IB illustrates a plan view of a magnetic tunnel junction device disposed on a spin orbit torque electrode, in accordance with an embodiment of the present disclosure.

Figure 1C illustrates a cross-sectional view depicting the direction of magnetization in a free magnetic layer relative to the direction of magnetization in a fixed magnetic layer, in accordance with an embodiment of the present disclosure.

Figure ID illustrates a cross-sectional view depicting the direction of magnetization in a free magnetic layer relative to the direction of magnetization in a fixed magnetic layer, in accordance with an embodiment of the present disclosure.

Figure IE illustrates a cross-sectional view of individual layers of a synthetic antiferromagnetic layer.

Figure 2 illustrates a cross-sectional view of a spin orbit torque (SOT) memory device, in accordance with an embodiment of the present disclosure.

Figure 3 A illustrates a spin orbit torque (SOT) memory device in a low resistance state.

Figure 3B illustrates a spin orbit torque (SOT) memory device switched to a high resistance state after the application of a spin hall current and a spin torque transfer current and/or an external magnetic field.

Figure 3C illustrates a spin orbit torque (SOT) memory device switched to a low resistance state after the application of a spin hall current and a spin torque transfer current and/or an external magnetic field.

Figures 4A- 4H illustrate cross-sectional views representing various operations in a method of fabricating spin orbit torque (SOT) memory device in accordance with embodiments of the present disclosure.

Figure 4A illustrates a cross-sectional view of the formation of a spin orbit torque layer on an insulator formed above a substrate, in accordance with embodiments of the present disclosure.

Figure 4B illustrates a cross-sectional view of the structure in Figure 4A following the formation of a lithographically patterned resist layer to subsequently pattern the spin orbit torque layer.

Figure 4C illustrates a cross-sectional view of the structure in Figure 4B following patterning of the spin orbit torque layer to form a spin orbit torque electrode.

Figure 4D illustrate cross-sectional and plan views of the structure in Figure 4C following the deposition of a dielectric layer on the spin orbit torque electrode and planarization of the dielectric layer and an uppermost portion of the spin orbit torque electrode.

Figure 4E illustrates a cross-sectional view of the structure in Figure 4D following the formation of a storage layer on the spin orbit torque electrode and on the dielectric layer.

Figure 4F illustrates a cross-sectional view of the structure in Figure 4E following the formation of a tunnel barrier layer, a fixed magnetic layer, a top electrode and dielectric hardmask layer to form a material layer stack for magnetic tunnel junction device.

Figure 4G illustrates a cross-sectional view of the structure in Figure 4F following the process of etching the material layer stack to form a magnetic tunnel junction device on the spin orbit torque electrode. Figure 4H illustrates a cross-sectional view of the structure in Figure 4G following the formation of a dielectric spacer adjacent to the magnetic tunnel junction device.

Figure 5 illustrates a cross-sectional view of a SOT memory device coupled to a first transistor, a second transistor and a bit line.

Figure 6 illustrates a computing device in accordance with embodiments of the present disclosure.

Figure 7 illustrates an integrated circuit (IC) structure that includes one or more embodiments of the present disclosure.

DESCRIPTION OF THE EMBODIMENTS

Spin orbit torque (SOT) memory devices with enhanced stability and methods of fabrication are described. In the following description, numerous specific details are set forth, such as novel structural schemes and detailed fabrication methods in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as transistor operations and switching operations associated with embedded memory, are described in lesser detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.

Certain terminology may also be used in the following description for the purpose of reference only, and thus are not intended to be limiting. For example, terms such as "upper", "lower", "above", and "below" refer to directions in the drawings to which reference is made. Terms such as "front", "back", "rear", and "side" describe the orientation and/or location of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.

A SOT memory device includes a magnetic tunnel junction (MTJ) memory device formed on a spin orbit torque electrode. The MTJ memory device functions as a memory device where the resistance of the MTJ memory device switches between a high resistance state and a low resistance state. The resistance state of a MTJ memory device is defined by the relative orientation of magnetization of two magnetic layers (fixed and free) that are separated by a tunnel barrier. When the magnetization of the two magnetic layers have orientations that are in the same direction the MTJ memory device is said to be in a low resistance state. Conversely, when the magnetization of the two magnetic layers have orientations that are in opposite directions the MTJ memory device is said to be in a high resistance state.

In an embodiment, in an absence of a spin orbit torque electrode, resistance switching in an MTJ memory device is brought about by passing a critical amount of spin polarized current through the MTJ memory device so as to influence the orientation of the

magnetization of the free magnetic layer to align with the magnetization of the fixed magnetic layer. The act of influencing the magnetization is brought about by a phenomenon known as spin torque transfer, where the torque from the spin current is imparted to the magnetization of the free magnetic layer. By changing the direction of the current, the magnetization in the free magnetic layer may be reversed relative to that of the fixed magnetic layer. Since the free magnetic layer does not need a constant source of spin polarized current to maintain a magnetization direction, the resistance state of the MTJ memory device is retained even when there is no current flowing through the MTJ memory device. For this reason, the MTJ memory device belongs to a class of memory known as non-volatile memory.

As an MTJ memory device is scaled down in size, the amount of critical spin current density required to switch the device increases. It then becomes advantageous to have an additional source of switching torque to avoid simply increasing the spin current. By implementing an MTJ memory device on a spin orbit torque electrode, the magnetization in the free magnetic layer gets an additional switching torque from a different source. The additional torque comes from a spin diffusion current, induced by passing an electrical current in a transverse direction, through the spin orbit torque electrode. The spin diffusion current arises from spin dependent scattering of electrons due to a phenomenon of spin orbit interaction. Electrons of one spin polarity are directed towards an upper portion of the spin orbit torque electrode and electrons with an opposite spin polarity are directed toward a bottom portion of the spin orbit torque electrode. Electrons of a particular spin polarity are directed toward the MTJ memory device and impart a spin orbit torque on the magnetization of the free magnetic layer. The torque assistance from the spin diffusion current aids the torque from the spin torque transfer current to enable a change in magnetization of the free magnetic layer. In addition to providing switching assistance in the form of a spin orbit torque, the spin hall current can also help the MTJ memory device to switch faster. It is to be appreciated that, in an embodiment, the spin hall current can fully switch the magnetization of a free magnetic layer that is oriented in an in-plane direction, even in the absence of a spin polarized current passing through the MTJ memory device. An in-plane direction is defined as a direction that is parallel to an uppermost surface of the spin orbit torque electrode.

Integrating a non-volatile memory device such as an SOT memory device onto access transistors enables the formation of embedded memory for system on chip (SOC) applications. However, approaches to integrate an SOT memory device onto access transistors presents challenges that have become far more formidable with scaling. One such challenge is the need to improve stability of the SOT memory device against thermal fluctuations during the lifetime of a device. Thermal fluctuations can cause unwanted reversal of magnetization of the free magnetic layer, the fixed magnetic layer or both, leading to loss of information stored in an SOT memory device. As the MTJ memory device in the SOT memory device typically includes a multilayer stack of magnetic and non-magnetic materials, the stack is engineered to possess thermal stability. The thermal stability of the multilayer stack depends on the strength of the magnetic anisotropy of the free magnetic layer or layers in the MTJ memory device and the thickness of the free magnetic layer.

Strength of magnetic anisotropy depends on the quality of the free magnetic layer. If there are more than one free magnetic layer, the strength of the magnetic anisotropy depends to an extent on the number and quality of interfaces between magnetic and non-magnetic layers in the free magnetic layers. Hence, controlling the degree of thermal stability in such SOT memory devices is partly dictated by the increasing the number of magnetic layers and choosing appropriate layers of magnetic anisotropy in the first place. The magnetism arising from the interfacial properties of the free magnetic layer and the adjacent non-magnetic layer is called interfacial magnetic anisotropy.

As MTJ memory devices are scaled, the need for smaller memory elements to fit into a scaled cell size has driven the industry in the direction of perpendicular MTJs.

Perpendicular MTJs are memory devices where the fixed magnetic layer and the free magnetic layer have magnetic anisotropy that is perpendicular with respect to a plane defining an uppermost surface of the spin orbit torque electrode. While it is to be appreciated that the spin hall current induced in the spin orbit torque electrode can assist or even fully switch in-plane MTJ memory devices, the spin hall current cannot fully reverse the magnetization direction of the free magnetic layer in a perpendicular MTJ (pMTJ). Complete reversal of magnetization in the free magnetic layer requires either a spin polarized current through the pMTJ or an application of an external magnetic field.

In accordance with embodiments of the present disclosure, a spin orbit torque (SOT) memory device includes a spin orbit torque electrode disposed in a dielectric layer above a substrate and a magnetic tunnel junction (MTJ) device disposed on a portion of the spin orbit torque electrode. In an embodiment, the spin orbit torque electrode has uppermost surface area that is 10-20 times larger than a lowermost surface area of the MTJ memory device. For SOT functionality, the spin orbit torque electrode has a width that is similar or approximately similar to a width of an MTJ memory device. In an embodiment, the MTJ memory device includes a free magnetic layer disposed on the spin orbit torque electrode, a tunnel barrier such as an MgO or AI2O3 disposed on the free magnetic layer and a fixed magnetic layer disposed on the tunnel barrier. In an embodiment, the free magnetic layer includes a magnetic stability enhancement layer disposed on the spin orbit torque electrode, a magnetic coupling layer disposed on the stability enhancement layer, and a free magnet disposed on the magnetic coupling layer. In an embodiment, the magnetic stability enhancement layer includes a multilayer stack of alternating layers of magnetic and non-magnetic materials and increases the stability of the free magnetic layer in the MTJ memory device.

The stability of the free magnetic layer is given by the following equation:

Stability = K_eff*Vol, where Keff is an effective magnetic anisotropy and Vol is an effective magnet volume.

One form of magnetic anisotropy is interfacial magnetic anisotropy. Interfacial refers to a property arising from an interface between two layers. Thus, in order to increase the stability of the free magnetic layer, the Keff, can be increased by creating a multilayer stack of alternating layers of magnetic and non-magnetic materials. A multilayer stack provides an increase in the overall effective magnetic anisotropy by increasing the "interfacial" magnetic anisotropy between each magnetic and non-magnetic layer.

While a multilayer stack can enable higher stability, the formation of the free magnet directly on the magnetic stability enhancement layer can lead to potential mismatch between lattices of the free magnet and the multilayer stack. In an embodiment, the magnetic coupling layer is disposed between the magnetic stability enhancement layer and the free magnet to address any potential issues arising from lattice mismatch. In an embodiment, when a magnetic coupling layer including molybdenum is disposed between the magnetic stability enhancement layer and the free magnet, the free magnet can be textured to have an orientation that matches the crystal orientation of the tunnel barrier disposed above rather than be mismatched with the lattice of the multilayer stack disposed below. Closely matching the crystal structure of the free magnet with the tunnel barrier enables a higher tunneling magnetoresi stance ratio (TMR) in the MTJ memory device. The TMR of a MTJ memory device is the ratio of the difference between a high resistance value and a low resistance value divided by the low resistance value of the MTJ memory device.

Figure 1 A is an illustration of a cross-sectional view of a SOT device 100 in accordance with an embodiment of the present disclosure. The SOT device 100 includes a spin orbit torque electrode 101 disposed in a dielectric layer 102 and a magnetic tunnel junction (MTJ) device 104, such as a perpendicular MTJ, disposed on the spin orbit torque electrode 101. In an embodiment, the MTJ memory device 104 is disposed approximately in the center of the spin orbit torque electrode 101 as shown in the plan view illustration of Figure IB.

Referring again to Figure 1A, the MTJ memory device includes a storage layer 106. The storage layer 106 includes a magnetic stability enhancement layer 108 disposed on the spin orbit torque electrode 101, a conductive coupling layer 1 10 disposed on the magnetic stability enhancement layer 108 and a free magnet 112 disposed on the conductive coupling layer 110. The combination of the magnetic stability enhancement layer 108, conductive coupling layer 110 and the free magnet 112 improves the stability of the storage layer 106 and TMR of the MTJ memory device 104. The MTJ memory device 104 further includes a tunnel barrier 1 14 such as an MgO, disposed on the free magnet 112 and a fixed magnet 116 disposed on the tunnel barrier 1 14.

The spin orbit torque electrode 101 includes a metal with high spin orbit coupling and/or metals that exhibit spin dependent scattering. In an embodiment, the spin orbit torque electrode 101 includes a metal or metals such as but not limited to tantalum, tungsten, platinum or gadolinium. In an embodiment, spin orbit torque electrode 101 includes beta phase tantalum or beta phase tungsten. In an embodiment, the spin orbit torque electrode 101 includes a multilayer stack including one or more layers of metals such as but not limited to tantalum, tungsten, platinum or gadolinium. In an embodiment, when the spin orbit torque electrode 101 includes a multilayer stack, the layer with the greatest spin-orbit coupling coefficient or the greatest spin dependent scattering strength is disposed directly adjacent to the MTJ memory device 104.

Figure IB illustrates a plan view of the MTJ memory device 104 disposed on the spin orbit torque electrode, in accordance with an embodiment of the present disclosure. In an embodiment, the spin orbit torque electrode 101 has a rectangular plan view profile and the MTJ memory device 104 has a circular plan view profile as illustrated in Figure IB. In another embodiment, an MTJ memory device 104, such as an in-plane MTJ, has a plan view profile that is elliptical. In another embodiment, the MTJ memory device 104 has a plan view profile that is rectangular In an embodiment, the spin orbit torque electrode 101 has a length, LSOT, between 100nm-500nm. In an embodiment, the spin orbit torque electrode 101 has a thickness between 2nm-10nm. In an embodiment, the spin orbit torque electrode 101 has a width, WSOT, between 10nm-50nm. In an embodiment, the MTJ memory device 104 has a broadest cross sectional width, WMTJ, that is similar or substantially similar to the width, WSOT. In an embodiment, the MTJ memory device 104 has a broadest cross sectional width, WMTJ, that is between 10nm-50nm.

In an embodiment, the MTJ memory device 104 has a center, CMTJ and the spin orbit torque electrode 101 has a center, CSOT. In an embodiment, CMTJ is aligned CSOT in both x and y directions, as illustrated in Figure IB. In another embodiment, CMTJ is misaligned from the CSOT in the y-direction. The electrical resistivity of the spin orbit torque electrode 101 may play a role in positioning of the MTJ memory device 104 on the spin orbit torque electrode 101 along the y-direction in Figure IB.

In an embodiment, the magnetic stability enhancement layer 108 includes a multilayer stack of alternating layers of magnetic material 108 A and a non-magnetic material 108B. In an embodiment, the non-magnetic material 108B is on the spin orbit torque electrode 101. In an embodiment, the magnetic material 108 A includes Co, Ni or Fe. In an embodiment, the non-magnetic material 108B includes a metal such as but not limited to Pt, Pd or Ir. In an embodiment, the multilayer stack of alternating layers of magnetic material 108 A and a nonmagnetic material 108B includes a Co magnetic layer and Pt NM. In an embodiment, the number of alternating layers of magnetic material 108 A and non-magnetic material 108B ranges from 4-10. In an embodiment, the magnetic material 108A has a thickness between O. lnm-1.0 nm and the non-magnetic material 108B has a thickness between 0.2nm-2.0nm. In an embodiment, the stability enhancement layer has a total combined thickness between 0.8- 3.0nm. In an exemplary embodiment, the magnetic stability enhancement layer 108 includes a Co/Pt multilayer stack, where the magnetic material 108A is Co and the non-magnetic material 108B is Pt. In an embodiment, the magnetic material 108A is Co and has a thickness of 0.5nm and the non-magnetic material is Pt and has a thickness of lnm. In an embodiment, the Co/Pt multilayer stack has a stability that increases by 300% when the number of alternating layers of magnetic material 108 A and non-magnetic material 108B increases from 2 layers to 4 layers.

Referring again to Figure 1A, in an embodiment, the conductive coupling layer 1 10 includes a non-magnetic material such as but not limited to molybdenum, iridium, tungsten and tantalum. In an embodiment, the conductive coupling layer 110 is molybdenum. In an embodiment, the coupling layer has a thickness between 0.3nm-l Onm. In an embodiment, the coupling layer is molybdenum and has a thickness of 0.4nm-0.6nm.

Referring again to Figure 1, in an embodiment, the free magnet 112 includes cobalt, boron and iron. In an embodiment, the free magnet 1 12 includes cobalt, boron and iron. In an embodiment, the free magnet 112 of the MTJ device 104 includes an alloy such as CoFe or CoFeB. In an embodiment, the free magnet 1 12 includes a layer of Coioo-x-_yFe_xB_y, where X and Y each represent atomic percent, further where X is between 50-80 and Y is between 10-40, and further where the sum of X and Y is less than 100. In one specific embodiment, X is 60 and Y is 20. In an embodiment, the free magnet 1 12 is FeB, where the concentration of boron is between 10-40 atomic percent of the total composition of the FeB alloy. In an embodiment the free magnet 1 12 has a thickness that is between lnm- 2.5nm. In an embodiment, free magnet 1 12 having a thickness between l .Onm and 2.5nm results in the free magnet 112 having a perpendicular magnetic anisotropy. When the free magnet 1 12 including a Co, Fe and B is disposed between a conductive coupling layer 110 including a molybdenum and a tunnel barrier 114 including an MgO, the presence of molybdenum helps the free magnet 1 12 to be textured in desired orientation matching the crystal orientation of the tunnel barrier 114. In an embodiment, the crystal orientation of the tunnel barrier 114 is (001). Closely matching the crystal structure of the free magnet 112 with the tunnel barrier 114 enables a higher tunneling magnetoresi stance ratio (TMR) in the MTJ memory device 104.

In an embodiment, the tunnel barrier 114 is composed of a material suitable for allowing electron current having a majority spin to pass through the tunnel barrier 114, while impeding at least to some extent electron current having a minority spin from passing through the tunnel barrier 114. Thus, the tunnel barrier 114 (or spin filter layer) may also be referred to as a tunneling layer for electron current of a particular spin orientation. In one

embodiment, the tunnel barrier 114 includes a material such as, but not limited to, magnesium oxide (MgO) or aluminum oxide (AI2O3). In one embodiment, the tunnel barrier 114 is MgO and has a thickness between lnm to 2nm.

Referring again to Figure 1A, in an embodiment, the fixed magnet 116 is composed of materials and has a thickness sufficient for maintaining a fixed magnetization. In an embodiment, the fixed magnet 1 16 is composed of a single layer of an alloy of cobalt, iron and boron. In an embodiment, the fixed magnet 116 of the MTJ memory device 104 includes an alloy such as CoFe and CoFeB. In an embodiment, the fixed magnet 1 16 comprises a layer of Coioo-x-yFe_xB_y, where X and Y each represent atomic percent, further where X is between 50-80 and Y is between 10-40, and further where the sum of X and Y is less than 100. In one specific embodiment, X is 60 and Y is 20. In an embodiment, the fixed magnet 116 is FeB, where the concentration of boron is between 10-40 atomic percent of the total composition of the FeB alloy. In an embodiment the fixed magnet 1 16 has a thickness that is between lnm- 3nm. In an embodiment, the fixed magnet 116 has a thin uppermost portion that is insufficient to maintain magnetization and is said to be magnetically dead. In an embodiment, the magnetically dead uppermost portion of the fixed magnet 116 has a thickness between 0.2nm-0.5nm. In one such embodiment, in spite of having a magnetically dead uppermost portion, the fixed magnet 1 16 has a remaining magnetic portion with a thickness that is sufficient for maintaining a fixed magnetization.

Referring again to Figure 1 A, the MTJ memory device 104 further includes a top electrode 120 disposed on the fixed magnet 116. In an embodiment, the top electrode layer 120 includes a material such as Ta or TiN. In an embodiment, the top electrode layer 120 has a thickness between 20nm-70nm.

As illustrated in Figure 1C, the MTI memory device 104 is in a high resistance state when direction of magnetization 154 (denoted by the direction of the arrow) in the free magnet 112 is opposite (anti-parallel) to the direction of magnetization 156 in the fixed magnet 116. Conversely, the MTJ memory device 104 is in a low resistance state when the magnetization 154 in the free magnet 112 is parallel to the magnetization 156 in the fixed magnet 116 as illustrated in Figure ID. A change in resistance (high to low or low to high) in the material layer stack 100 results when a spin polarized electron current passing into the free magnet 112 through the tunnel barrier 1 14 brings about a change in the direction of the magnetization 154 in the free magnet 112.

In an embodiment, the free magnet 1 12 and the fixed magnet 1 16 can have similar thicknesses and an injected electron spin current which changes the direction of the magnetization 154 in the free magnet 112 can also affect the magnetization 156 of the fixed magnet 116. In an embodiment, to make the fixed magnet 1 16 more resistant to accidental flipping the fixed magnet 116 has higher perpendicular magnetic anisotropy than the storage layer 106. In another embodiment, a synthetic antiferromagnetic (SAF) structure is disposed between the top electrode 120 and the fixed magnet 1 16 in order to prevent accidental flipping of the magnetization 156 in the fixed magnet 1 16. The SAF structure 1 18 is ferromagnetically coupled with the fixed magnet 1 16.

Figure IE illustrates cross-sectional view of the synthetic antiferromagnetic (SAF) structure 1 18, in accordance of an embodiment of the present disclosure. In an embodiment, the SAF structure 1 18 includes a non-magnetic layer 1 18B disposed between a first ferromagnetic layer 1 18A and a second ferromagnetic layer 1 18C as depicted in Figure IE. The first ferromagnetic layer 1 18A and the second ferromagnetic layer 1 18C are anti- ferromagnetically coupled to each other.

In an embodiment, the SAF structure 1 18 includes a non-magnetic layer 1 18B between a first ferromagnetic layer 118A and a second ferromagnetic layer 118C as depicted in Figure IE. The first ferromagnetic layer 118A and the second ferromagnetic layer 118C are antiferromagnetically coupled to each other. In an embodiment, the first ferromagnetic layer 118A includes a layer of a magnetic metal such as Co, Ni or Fe. In an embodiment, the first ferromagnetic layer 118A includes an alloy such as CoFe, CoFeB, CoFe, FeB. In an embodiment, the second ferromagnetic layer 1 18C includes a layer of a magnetic metal such as Co, Ni or Fe. In an embodiment, the second ferromagnetic layer 118C includes an alloy such as CoFe, CoFeB, CoFe, FeB. In an embodiment, the non-magnetic layer 118B includes a ruthenium or an iridium layer. In an embodiment, a ruthenium based non-magnetic layer 118B has a thickness between 4-9 Angstroms to ensure that the coupling between the first ferromagnetic layer 1 18A and the second ferromagnetic layer 1 18C is anti-ferromagnetic in nature.

In an embodiment, the SAF structure 1 18 includes a bilayer having a magnetic metal disposed on a non-magnetic metal such as a bilayer of Co/Pd or a bilayer of Co/Pt. In an embodiment, the SAF structure 118 includes a stack of bilayers, where each bilayer includes a magnetic metal disposed on a non-magnetic metal, where the total number of bilayers can range from 2-10.

In an embodiment, an additional layer of non-magnetic spacer material may be disposed on the fixed magnet 116 and below the SAF structure 118. A non-magnetic spacer layer enables magnetic coupling between the first ferromagnetic layer 118A and the fixed magnet 116. In an embodiment, a non-magnetic spacer layer may include metals such as Ta, Ru or Ir.

Figure 2 illustrates a cross sectional view of an SOT device 200 having an MTJ memory device 202 disposed on a spin orbit torque electrode 101, in an accordance with an embodiment of the present disclosure. In an embodiment, MTJ memory device 202 has a storage layer 204 which includes a spacer structure 208 disposed between the magnetic stability enhancement layer 108 and the free magnet 112. In an embodiment, the spacer structure 208 includes a first conductive coupling layer 210 disposed on the magnetic stability enhancement layer 108, a magnetic coupler 212 disposed on the first conductive coupling layer 210 and a second conductive coupling layer 214 disposed on the magnetic coupler 212. Insertion of the spacer structure 208 in the MTJ memory device 202 of Figure 2 enables an effective increase in the thermal stability of the storage layer 204.

In an embodiment, the first conductive coupling layer 210 includes a metal selected from the group consisting of Ta, Ru, Mo and Ir. In an embodiment, the second conductive coupling layer 214 includes a metal selected from the group consisting of Ta, Ru, Mo and Ir. In an embodiment, the first conductive coupling layer 210 and second conductive coupling layer 214 each include Ta. In an embodiment, the first conductive coupling layer 210 and second conductive coupling layer 214 have thickness between 0. lnm-0.5nm. In an embodiment, the first conductive coupling layer 210 and the second conductive coupling layer 214 each include Ta and have a thickness of 0.2nm and 0.3nm, respectively.

In an embodiment, the magnetic coupler 212 has a material composition and a thickness similar to the material composition of the free magnet 1 12. In an embodiment, the magnetic coupler 212 is a layer of Coioo-x-yFe_xB_y, where X and Y each represent atomic percent, further where X is between 50-80 and Y is between 10-40, and further where the sum of X and Y is less than 100. In one specific embodiment, X is 60 and Y is 20. In an embodiment, the magnetic coupler 212 has a thickness that is between 0.6nm-0.9nm.

In an embodiment, the spacer structure 208 has a combined total thickness that is between l . lnm - 1.5nm. In an embodiment, a spacer structure 208 having a combined total thickness of less than 1.5nm enables the free magnet 1 12 and the magnetic stability enhancement layer 108 to be anti-ferromagnetically coupled.

Figures 3A-3C illustrate a mechanism for switching an MTJ memory device 104 formed on a spin orbit torque electrode 101.

Figure 3 A illustrates an MTJ memory device, such as an MTJ memory device 104 disposed on a spin orbit torque electrode 101, where a magnetization 154 of the storage layer 106 is in the same direction as a magnetization 156 of the fixed magnet 116. In an embodiment, the direction of magnetization 154 of the storage layer 106 and the direction of magnetization 156 of the fixed magnet 1 16 are both in the negative z-direction as illustrated in Figure 3 A. As discussed above, when the magnetization 154 of the storage layer 106 is in the same direction as a magnetization 156 of the fixed magnet 116, MTJ memory device 104 is in a low resistance state.

Figure 3B illustrates a spin orbit torque (SOT) memory device switched to a high resistance state. In an embodiment, a reversal in the direction of magnetization 154 of the storage layer 106 in Figure 3B compared to the direction of magnetization 154 of the storage layer 106 in Figure 3 A is brought about by (a) inducing a spin hall current 168 in the spin orbit torque electrode 101 in the y-direction and (b) by applying a spin torque transfer current 170, isTTM, (by applying a positive voltage at terminal B with respect to ground C), and/or (c) by applying an external magnetic field, H_y, in the y-direction.

In an embodiment, a charge current 160 is passed through the spin orbit torque electrode 101 in the negative y-direction (by applying a positive voltage at terminal A with respect to ground C). In response to the charge current 160, an electron current 162 flows in the positive y-direction. The electron current 160 includes electrons with two opposite spin orientations and experience a spin dependent scattering phenomenon in the spin orbit torque electrode 101. The spin dependent scattering phenomenon causes electrons with a spin angular moment 164 (directed in the negative x direction) to be deflected upwards towards an uppermost portion of the spin orbit torque electrode 101 and electrons with a spin angular moment 166 (directed in the positive x direction) to be deflected downwards towards a lowermost portion of the spin orbit torque electrode 101. The separation between the electrons with the spin angular moment 164 and the electrons with the spin angular moment 166 induces a spin diffusion current 168 in the spin orbit torque electrode 101. This spin diffusion current 168 is directed upwards toward the storage layer 106 of the MTJ memory device 104. The spin diffusion current 168 induces a spin orbit torque on the magnetization 154 of the storage layer 106 causing the magnetization to change from the negative z direction in Figure 3A to an intermediate magnetization state (negative x direction). The Z^'STTM current 170 flowing through the MTJ memory device 104 exerts an additional torque on the magnetization 154 of the storage layer 106. The combination of spin hall torque and spin transfer torque causes flipping of magnetization 154 in the storage layer 106 from the intermediate magnetization state (negative x-direction) to a positive z-direction illustrated in Figure 3B. In an embodiment, an additional torque can be exerted on the storage layer 106 by applying an external magnetic field, H_y, in the y-direction, as illustrated in Figure 3B, instead of applying an ISTTM current 170.

Figure 3C illustrates a spin orbit torque (SOT) memory device switched to a low resistance state. In an embodiment, a reversal in the direction of magnetization 154 of the storage layer 106 in Figure 3C compared to the direction of magnetization 154 of the storage layer 106 in Figure 3B is brought about by (a) reversing the direction of the spin hall current 168 in the spin orbit torque electrode 101 and (b) by reversing the direction of the iSTTM current 170, and/or (c) by reversing the direction of the external magnetic field, H_y.

Figures 4A-4H illustrate cross-sectional views representing various operations in a method of fabricating spin orbit torque (SOT) memory device in accordance with embodiments of the present disclosure.

Figure 4A illustrates a cross-sectional view of the formation of a spin orbit torque layer 401 on a dielectric layer 404 formed above a substrate 406. In an embodiment, the spin orbit torque layer 401 is a material that is substantially similar to the spin orbit torque electrode 101. In an embodiment, the spin orbit torque electrode 401 includes a metal such as Pt, beta-tungsten and beta-tantalum. In an embodiment, the spin orbit torque layer 401 is deposited using a physical vapor deposition process or a plasma enhanced chemical vapor deposition (PECVD) process. In an embodiment, the spin orbit torque layer 401 has a thickness that is between 20nm-100nm.

In an embodiment, the spin orbit torque layer 401includes a multilayer stack of metals consisting of two or more layers of metals that can induce spin hall currents. In one such embodiment, the multilayer stack of metals includes a layer of platinum deposited on the dielectric layer 404, a layer of beta-tungsten deposited on the layer of platinum and a layer of beta-tantalum deposited on the layer of beta-tungsten. In an embodiment, the combined total thickness of the multilayer stack of metals is between 20nm-100nm.

In an embodiment, the dielectric layer 404 includes a material such as but not limited to silicon dioxide, silicon nitride, silicon carbide, or carbon doped silicon oxide.

In an embodiment, the substrate 406 includes a suitable semiconductor material such as but not limited to, single crystal silicon, polycrystalline silicon and silicon on insulator (SOI), as well as similar substrates formed of other semiconductor materials such as germanium, silicon germanium or a suitable group III-V or a group III-N compound.

Figure 4B illustrates a cross-sectional view of the structure in Figure 4A following the formation of a photoresist mask 407 on the spin orbit torque layer 401. The photoresist mask 407 defines a size of a spin orbit torque electrode that will subsequently be formed. In an embodiment, the photoresist mask 407 has a rectangular shape as is depicted in the plan view illustration of Figure IB. In another embodiment, the photoresist mask 407 has a square shape.

Figure 4C illustrates a cross-sectional view of the structure in Figure 4B following the patterning of the spin orbit torque layer 401 to form a spin orbit torque electrode 402. In an embodiment, the spin orbit torque electrode is patterned by a plasma etch process. Upon completion of the etch process, any remaining photoresist mask 407 is subsequently removed.

Figure 4D illustrates a cross-sectional view of the structure in Figure 4C following the deposition of a second dielectric layer 408 and a planarization process. In an embodiment, the second dielectric layer 408 is deposited on the spin orbit torque electrode 402 and on the dielectric layer 404. A planarization process is carried out to remove the second dielectric layer 408 above the spin orbit torque electrode 402 and an upper portion of the spin orbit torque electrode 402. In an embodiment, the spin orbit torque electrode 402 and the second dielectric layer 408 surrounding the spin orbit torque electrode 402 have uppermost surfaces that are substantially co-planar following the planarization process. In an embodiment, the planarization process is a chemical mechanical polish process. In an embodiment the planarization process forms a spin orbit torque electrode 402 having a topographically smooth uppermost surface having a surface roughness that is less than lnm.

The plan view Figure 4D (Α-Α'), illustrates the size and shape of the spin orbit torque electrode 402. The spin orbit torque electrode 402 has a length LSOT and a width WSOT. In an embodiment, the spin orbit torque electrode 402 has a length, LSOT, that is between 50nm to 500nm and a width, WSOT, that is between 20nm to 200nm.

Figure 4E illustrates a cross-sectional view of the structure in 4D following the formation of a storage layer 410 on the spin orbit torque electrode 402 and on the second dielectric layer 408. In an embodiment, formation of the storage layer 410 includes formation of a magnetic stability enhancement layer 411, a conductive coupling layer 414 on the magnetic stability enhancement layer 411 and a free magnetic layer 416 on the conductive coupling layer 414, in accordance with an embodiment of the present disclosure.

In an embodiment, forming the magnetic stability enhancement layer 41 1 includes depositing a multilayer stack of alternating layers of magnetic material 411 A and nonmagnetic material 41 IB on the magnetic material 41 1 A. In an embodiment, each of the alternating layers of magnetic material 41 1A and non-magnetic material 41 IB are sequentially deposited without an air break by a physical vapor deposition (PVD) process. In a different embodiment, the magnetic material 41 1 A is deposited first and non-magnetic material 41 IB is deposited on the magnetic material 411 A.

In an embodiment, the magnetic material 411 A includes Co, Ni or Fe. In an embodiment, the non-magnetic material 41 IB includes a metal such as but not limited to Pt, Pd or Ir. In an embodiment, the magnetic stability enhancement layer 411 includes a Co/Pt multilayer. In an embodiment, the total number of alternating layers of magnetic material 41 1 A and non-magnetic material 41 IB ranges from 1-10 layers. In an embodiment, the magnetic material 411A is deposited to a thickness between 0. lnm-l .Onm and the nonmagnetic material 41 IB is deposited to a thickness between 0.2nm-2.0nm. In an

embodiment, the stability enhancement layer is deposited to a total combined thickness between 0.8nm-3.0nm. In an exemplary embodiment, the magnetic stability enhancement layer 411 includes a Co/Pt multilayer stack, where each layer of Co is deposited to a thickness of 0.2nm and where each of the layer of Pt is deposited to a thickness of 0.4nm and where the total number of each layer is 4. In an embodiment, the Co Pt layers have a (111) crystal structure.

The conductive coupling layer 413 is deposited on the magnetic stability enhancement layer 411 to separate the magnetic stability enhancement layer 41 1 from a subsequent free magnet layer that will be formed. In an embodiment, the conductive coupling layer 413 is deposited using a PVD process. In an embodiment, the conductive coupling layer 413 includes a non-magnetic material such as but not limited to molybdenum, iridium, tungsten and tantalum. In an embodiment, the conductive coupling layer 413 includes molybdenum. In an embodiment, the conductive coupling layer 413 is deposited to a thickness between 0.3nm-1.0nm. In an embodiment, the conductive coupling layer 413 is molybdenum and deposited to a thickness of 0.5nm. In an embodiment, the conductive coupling layer 413 has an amorphous or partially body-center-cubic (BCC) crystal structure.

Referring again to Figure 4E, a free magnetic layer 415 is deposited on the conductive coupling layer 414. In an embodiment, the free magnetic layer 415 is deposited using a PVD process. In an embodiment, the free magnetic layer 415 includes a material similar to the material of the free magnet 112. In an embodiment, the free magnetic layer 415 includes a CoFeB. In an embodiment, the free magnetic layer 415 includes a CoFeB and is amorphous as deposited. In an embodiment, the free magnetic layer 415 has a thickness between 0.9nm- 2.5nm.

Figure 4F illustrates a cross-sectional view of the structure in Figure 4E following the formation of a tunnel barrier layer 417, a fixed magnetic layer 419 on the tunnel barrier layer 417 and a top electrode layer 421.

In an embodiment, the tunnel barrier layer 417 is deposited using a reactive sputter deposition technique and includes a material such as MgO. In an embodiment, the tunnel barrier layer 417 is deposited to a thickness between 0.9nm-1.9nm.

A tunnel barrier layer 417 is then blanket deposited on the free magnetic layer 415. In an embodiment, the tunnel barrier layer 417 includes a material such as MgO or AI2O3. In an embodiment, the tunnel barrier layer 417 is an MgO and is deposited using a reactive sputter process. In an embodiment, the reactive sputter process is carried out at room temperature. In an embodiment, the tunnel barrier layer 417 is deposited to a thickness between 0.8nm to lnm. In an embodiment, the deposition process is carried out in a manner that yields a tunnel barrier layer 417 having an amorphous structure. In an embodiment, the amorphous tunnel barrier layer 417 becomes crystalline after a high temperature anneal process to be described further below. In an embodiment, the tunnel barrier layer 417 is crystalline as deposited.

In an embodiment, the fixed magnetic layer 419 is blanket deposited on the uppermost surface of the tunnel barrier layer 417. In an embodiment, the deposition process includes a physical vapor deposition (PVD) or a plasma enhanced chemical vapor deposition process. In an embodiment, the PVD deposition process includes an RF or a DC process.

In an embodiment, the fixed magnetic layer 419 is a layer of Coioo-x-_yFe_xB_y, where X and Y each represent atomic percent, further where X is between 50-80 and Y is between 10- 40, and further where the sum of X and Y is less than 100. In one specific embodiment, X is 60 and Y is 20. In an embodiment, the fixed magnetic layer 419 is similar to the fixed magnetic layer 116 described above. In an embodiment the fixed magnetic layer 419 is deposited to a thickness between 1.5nm-2.5nm.

In an embodiment, a top electrode layer 421 is blanket deposited on the surface of the fixed magnetic layer 419. In an embodiment, the top electrode layer 421 includes a material that is suitable to act as a hardmask during a subsequent etching of the material layer stack 450 to form an MTI memory device. In an embodiment, the top electrode layer 421 includes a material such as Ta or TaN. In an embodiment, the thickness of the top electrode layer ranges from 30-70nm. The thickness of the top electrode layer 421 is chosen to

accommodate patterning requirements of the various sizes of MTJ devices that will subsequently be fabricated.

In an embodiment, the process of sputter depositing the top electrode layer 421 causes a small uppermost portion of the fixed magnetic layer 419 to become magnetically dead. In an embodiment, the fixed magnetic layer 419 has magnetically dead portion that is less than 5% of the total thickness of the fixed magnetic layer 419. In an embodiment, the fixed magnetic layer 419 has magnetically dead portion that is at least 50% of the total thickness of the fixed magnetic layer 419. In an embodiment, the magnetically dead portion is not continuous throughout the structure of the fixed magnetic layer 419. By depositing a fixed magnetic layer 419 to a thickness of at least 2nm, the fixed magnetic layer 419 functions as a pinned magnetic layer even if portions of it are magnetically dead.

In an embodiment, after all the layers in the MTJ material layer stack 450 are deposited, an anneal is performed to enable crystalline MgO to be formed in the tunnel barrier layer 417. In an embodiment, the anneal is performed immediately post deposition but before patterning of the MTJ material layer stack 450. A post-deposition anneal of the MTI material layer stack 450 is carried out in a furnace at a temperature between 300-350 degrees Celsius in a forming gas environment. In an embodiment, the forming gas includes a mixture of Fh and N2 gas. In an embodiment, the annealing process promotes solid phase epitaxy of the free magnetic layer 415 to follow a crystalline template of the tunnel barrier layer 417 (e.g., MgO) formed above. The presence of the conductive coupling layer 414 between the free magnetic layer 415 and the stability enhancement layer 412 prevents stability enhancement layer 412 from affecting the crystallinity of the free magnetic layer 415 during the anneal process. Lattice matching between the tunnel barrier layer 417 and the free magnetic layer 415 enables a higher TMR to be obtained in the MTJ material layer stack 450.

In an embodiment, the anneal also promotes solid phase epitaxy of the fixed magnetic layer 419 to follow a crystalline template of the tunnel barrier layer 417 (e.g., MgO).

In an embodiment, when the free magnetic layer 415 includes boron, the annealing process enables boron to diffuse away from an interface 430 between the free magnetic layer 415 and the tunnel barrier layer 417. The process of diffusing boron away from the interface 430 enables lattice matching between the free magnetic layer 415 and the tunnel barrier layer 417. In an embodiment, when the fixed magnetic layer 419 includes boron, the annealing process enables boron to diffuse away from an interface 432 between the fixed magnetic layer 419 and the tunnel barrier layer 417.

In an embodiment, the annealing process is also performed in the presence of a magnetic field which sets the magnetization direction of the fixed magnetic layer 419, the free magnetic layer 415 and the magnetic material 411A in the stability enhancement layer 41 1. In an embodiment, an applied magnetic field that is directed parallel to a vertical axis of the MTJ material layer stack 450, during the annealing process, enables a perpendicular anisotropy to be set in the fixed magnetic layer 419, in the free magnetic layer 415 and in the magnetic material 412A in the stability enhancement layer 412. In an embodiment, the annealing process initially aligns the magnetization of the fixed magnetic layer 419, of the free magnetic layer 415 and of the magnetic material 412A in the stability enhancement layer 412 to be parallel to each other.

While one MTJ material layer stack 450 has been described above, a material layer stack for forming the MTJ memory device 202 illustrated in Figure 2 can also be fabricated by the deposition techniques described above. Furthermore, in an embodiment, when an MTJ memory device 202 includes tantalum in both the first conductive coupling layer 210 and in the second conductive coupling layer 214, the material layer stack for forming the MTJ memory device 202 can be annealed at temperatures of up to 400 degrees Celsius without destroying the magnetism of the storage layer 410. Figure 4G illustrates a cross-sectional view of the structure in Figure 4F following patterning and etching of the MTJ material layer stack 450. In an embodiment, the patterning process includes lithographically patterning a layer of resist formed (not shown) over the MTJ material layer stack 450. The lithography process defines the shape and size of a MTJ memory device and a location where the MTJ memory device is to be subsequently formed with respect the spin orbit torque electrode 402. In an embodiment, the patterning process includes etching the top electrode layer 421 by a plasma etch process to form a top electrode 422. In an embodiment, plasma etch process possesses sufficient ion energy and chemical reactivity to render vertical etched profiles of the top electrode layer 422. In an embodiment, the remaining layer of resist above the top electrode 422 is then removed by a plasma ash process.

In an embodiment, the plasma etch process is then continued to pattern the remaining layers of the MTJ material layer stack 450 to form a MTJ memory device 470. The MTJ memory device 470 has a fixed magnet 420, a tunnel barrier 418, a fixed magnet 416, a patterned conductive coupling layer 414 and a stability enhancement structure 412. The plasma etch process also exposes the spin orbit torque electrode 402 and the underlying second dielectric layer 408. In an embodiment, when the plasma etch does not have a high etch selectivity between the stability enhancement structure 412 and spin orbit torque electrode 402, uppermost portions of the spin orbit torque electrode 402 can be etched as indicated by dashed lines 424. In an embodiment, 5nm-10nm of the uppermost portion of the spin orbit torque electrode 402 can be removed.

Figure 4H illustrates a cross-sectional view of the structure in Figure 4G following the formation of a dielectric spacer 426 adjacent to the magnetic tunnel junction device. In an embodiment, a dielectric spacer layer is deposited on the MTJ memory device 470 and on the uppermost surface of the spin orbit torque electrode 402 and on the second dielectric layer 408. In an embodiment, the dielectric spacer layer is deposited without a vacuum break following the plasma etch process. In an embodiment, the dielectric spacer layer includes a material such as but not limited silicon nitride, carbon doped silicon nitride or silicon carbide. In an embodiment, the dielectric spacer layer includes an insulator layer that does not have any oxygen content to prevent oxidation of magnetic layers. In an embodiment, the dielectric spacer layer is etched by a plasma etch process forming dielectric spacer 426 on sidewalls of the MTJ memory device 104. In an embodiment, the etch process may cause an uppermost portion of the dielectric layer 408 to become partially recessed leading to partial exposure of sidewalls of the spin orbit torque electrode 402. The MTJ memory device 470 formed over the spin orbit torque electrode 402, thus constitutes a spin orbit torque memory device 480.

Figure 5 illustrates a spin orbit torque (SOT) memory device, such as the spin orbit torque memory device 480 coupled with a first transistor 500 and a second transistor 520 and a bit line. In an embodiment, the first transistor 500 and second transistor 520 are disposed on a substrate 501.

In an embodiment, the first transistor 500 and second transistor 520 associated with substrate 510 are metal-oxide-semiconductor field-effect transistors (MOSFET or simply MOS transistors), fabricated on the substrate 501. In various implementations of the present disclosure, the transistor 508 may be planar transistors, nonplanar transistors, or a combination of both. Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors. In an embodiment, the first transistor 500 and second transistor 520 are tri-gate transistors that are horizontally disposed on a same plane as illustrated in Figure 5. The first transistor 500 and second transistor 520 are electrically isolated by a dielectric layer 545 although they are formed on a common substrate 501.

In an embodiment, the first transistor 500 has a source region 502, a drain region 504 and a gate 506. The first transistor 500 further includes a gate contact 514 disposed above and electrically coupled to the gate 506, a source contact 516 disposed above and electrically coupled to the source region 502, and a drain contact 518 disposed above and electrically coupled to the drain region 504 as is illustrated in Figure 5. In an embodiment, the second transistor 520 has a source region 524, a drain region 522 and a gate 526. The second transistor 520 further includes a gate contact 534 disposed above and electrically coupled to the gate 526, a source contact 536 disposed above and electrically coupled to the source region 524, and a drain contact 538 disposed above and electrically coupled to the drain region 522 as is illustrated in Figure 5. In an embodiment, the source contact 516 of the first transistor 500 and the source contact of the second transistor 520 are electrically connected (as indicated by dashed line 582).

In an embodiment, the spin orbit torque memory device 480 includes an MTJ memory device such as an MTJ memory device 470, described in association with Figure 4H, disposed on a spin orbit torque electrode such as a spin orbit torque electrode 402, described in association with Figure 4D. In an embodiment, the spin orbit torque electrode 402 is disposed above a dielectric layer 550 and is surrounded by a second dielectric layer 555. A portion of the spin orbit torque electrode 402 is disposed on and in electrical contact with the drain contact 538 of the second transistor 520. An MTJ contact 528 is disposed on and electrically coupled with the MTJ memory device 470. A spin orbit torque contact 540 is disposed on and electrically coupled with the spin orbit torque electrode 402.

In an embodiment, the spin orbit contact 540 is connected to a bit line (BL) 542 of a memory array. In an embodiment, the BL 542 is connected to a spin orbit torque contact of a second spin orbit torque memory device (not shown). In an embodiment, the MTJ contact 528 is electrically connected to a drain contact 518 of the first transistor 500 (indicated by the dashed line 580). In an embodiment, The MTJ contact 528, connected to the drain contact 518, of the first transistor 500, enables flow of an STTM current through the MTJ memory device 470. In an embodiment, the source contact 516 of the first transistor and the source contact 536 of the second transistor 520 are electrically connected to a shared source line (SL) 582. In an embodiment, the gate contact 514 of the first transistor 500 is electrically connected to a first wordline (WLi) 541 and the gate contact 534 of the second transistor 520 is electrically connected to a second wordline (WL2) 543, where WLi 541 and WL2 543 are independently programmable.

In an embodiment, when the second transistor 520 is energized in a manner that causes charge current to flow through the spin orbit torque electrode 402, a spin hall current is generated in the spin orbit torque electrode 402. The spin hall current will exert a torque on the magnetization of a storage layer 410 of the MTJ memory device 470. By energizing the first transistor 500 a charge current can flow from the drain contact 518, into the MTJ memory device 470 through the MTJ contact 528. The charge current is a source of a polarized STTM current, ISTIM, that will exert a torque on the magnetization of the storage layer 410. In an embodiment, the torque transfer from the spin hall current and from the spin torque transfer current will change the direction of magnetization in the storage layer 410. In an embodiment, by appropriately biasing the first transistor 500 and the second transistor 520, write and erase operations may be enabled in the MTJ memory device. A read operation of the MTJ memory device 470 may be enabled by applying a biasing voltage between 0. IV- 0.2V between the SL 582 and the BL 542 and by applying an appropriate voltage bias on WLi 541, to energize the first transistor 520.

Referring again to Figure 5, in an embodiment, the underlying substrate 501 represents a surface used to manufacture integrated circuits. In an embodiment, the substrate 501 includes a suitable semiconductor material such as but not limited to, single crystal silicon, polycrystalline silicon and silicon on insulator (SOI). In another embodiment, the substrate 501 includes other semiconductor materials such as germanium, silicon germanium, or a suitable group III-V or group III-N compound. The substrate 501 may also include semiconductor materials, metals, dopants, and other materials commonly found in semiconductor substrates.

In an embodiment, the first transistor 500 includes a gate stack formed of at least two layers, a gate dielectric layer 510 and a gate electrode layer 512. The gate dielectric layer 510 may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide (Si0₂) and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer 510 to improve its quality when a high-k material is used.

The gate electrode layer 512 of the first transistor 500 is formed on the gate dielectric layer 510 and may consist of at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer 512 may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a conductive fill layer.

For a PMOS transistor, metals that may be used for the gate electrode layer 512 include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode layer 512 with a workfunction that is between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode layer 512 include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode layer 512 with a workfunction that is between about 3.9 eV and about 4.2 eV.

In some implementations, the gate electrode layer 512 may consist of a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode layer 512 may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the present disclosure, the gate electrode layer 512 may consist of a combination of U-shaped structures and planar, non-U- shaped structures. For example, the gate electrode layer 512 may consist of one or more U- shaped metal layers formed atop one or more planar, non-U-shaped layers.

In some implementations of the present disclosure, a pair of gate dielectric layer 508 may be formed on opposing sides of the gate stack that bracket the gate stack. The gate dielectric layer 508 may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process operations. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

As is well known in the art, source region 502 and drain region 504 are formed within the substrate adjacent to the gate stack of the first transistor 500. The source region 502 and drain region 504 are generally formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source region 502 and drain region 504. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source region 502 and drain region 504. In some implementations, the source region 502 and drain region 504 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the source region 502 and drain region 504 may be formed using one or more alternate semiconductor materials such as germanium or a suitable group III-V compound. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the source region 502 and drain region 504.

In an embodiment, the second transistor 520 also includes a gate stack formed of at least two layers, a gate dielectric layer 530 and a gate electrode layer 512 layer 532. In an embodiment, the second transistor 520 is similar or substantially similar to the first transistor 500. In an embodiment, the gate dielectric layer 530 and a gate electrode layer 512 layer 532 of the second transistor 520 are substantially similar to the gate dielectric layer 510 and a gate electrode layer 512 of the first transistor 500.

In an embodiment, the gate contact 514, source contact 516 and drain contact 518 of the first transistor 500 are partially formed in the dielectric layer 550 and partially formed in the second dielectric layer 555. Similarly, the gate contact 534, source contact 536 and drain contact 538 of the second transistor 520 are partially formed in the dielectric layer 550 and partially formed in the second dielectric layer 555.

Figure 6 illustrates a computing device 600 in accordance with one embodiment of the disclosure. The computing device 600 houses a motherboard 602. The motherboard 602 may include a number of components, including but not limited to a processor 604 and at least one communication chip 606. The processor 604 is physically and electrically coupled to the motherboard 602. In some implementations the at least one communication chip 606 is also physically and electrically coupled to the motherboard 602. In further implementations, the communication chip 606 is part of the processsor 604.

Depending on its applications, computing device 600 may include other components that may or may not be physically and electrically coupled to the motherboard 602. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

The communication chip 606 enables wireless communications for the transfer of data to and from the computing device 600. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 606 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 600 may include a plurality of communication chips 606. For instance, a first communication chip 606 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second

communication chip 606 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others

The processor 604 of the computing device 600 includes an integrated circuit die packaged within the processor 604. In some implementations of embodiments of the disclosure, the integrated circuit die of the processor includes one or more memory devices, such as a spin orbit torque memory device 480, built with a MTJ material layer stack 450 in accordance with embodiments of the present disclosure. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 606 also includes an integrated circuit die packaged within the communication chip 606. In accordance with another implementation of an embodiment of the disclosure, the integrated circuit die of the communication chip includes spin orbit torque memory device 480 integrated with access transistors, built in accordance with embodiments of the present disclosure.

In further implementations, another component housed within the computing device

600 may contain a stand-alone integrated circuit memory die that includes one or more memory elements, built in accordance with embodiments of the present disclosure.

In various implementations, the computing device 600 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra- mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 600 may be any other electronic device that processes data.

Figure 7 illustrates an integrated circuit (IC) structure 700 that includes one or more embodiments of the disclosure. The integrated circuit (IC) structure 700 is an intervening substrate used to bridge a first substrate 702 to a second substrate 704. The first substrate 702 may be, for instance, an integrated circuit die. The second substrate 704 may be, for instance, a memory module, a computer mother, or another integrated circuit die. Generally, the purpose of an integrated circuit (IC) structure 700 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an integrated circuit (IC) structure 700 may couple an integrated circuit die to a ball grid array (BGA) 706 that can subsequently be coupled to the second substrate 704. In some embodiments, the first and second substrates 702/704 are attached to opposing sides of the integrated circuit (IC) structure 700. In other embodiments, the first and second substrates 702/704 are attached to the same side of the integrated circuit (IC) structure 700. And in further embodiments, three or more substrates are interconnected by way of the integrated circuit (IC) structure 700.

The integrated circuit (IC) structure 700 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the integrated circuit (IC) structure may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.

The integrated circuit (IC) structure may include metal interconnects 708 and vias 710, including but not limited to through-silicon vias (TSVs) 710. The integrated circuit (IC) structure 700 may further include embedded devices 714, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, transistors, spin orbit torque memory devices, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio- frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the integrated circuit (IC) structure 700. In accordance with embodiments of the disclosure, apparatuses or processes disclosed herein may be used in the fabrication of integrated circuit (IC) structure 700.

Accordingly, one or more embodiments of the present disclosure relate generally to the fabrication of embedded microelectronic memory. The microelectronic memory may be non-volatile, wherein the memory can retain stored information even when not powered. One or more embodiments of the present disclosure relate to the fabrication of a spin orbit torque memory device such as the spin orbit torque memory device 480. The spin orbit torque memory device 480 may be used in an embedded non-volatile memory application.

Thus, embodiments of the present disclosure include spin orbit torque memory devices with enhanced stability and methods to form same.

Specific embodiments are described herein with respect to pSOT devices. It is to be appreciated that embodiments described herein may also be applicable to other non-volatile memory devices. Such non-volatile memory devices may include, but are not limited to, magnetic random access memory (MRAM) devices, spin torque transfer memory (STTM) devices such as in-plane STTM or perpendicular STTM devices

Example 1 : A spin orbit torque (SOT) device includes a spin orbit torque electrode and a memory device disposed above a portion of the spin orbit torque electrode. The memory device has a storage layer, wherein the storage layer includes, a magnetic stability enhancement layer, a conductive coupling layer disposed on the stability enhancement layer, a free magnet disposed on the conductive coupling layer. The conductive coupling layer ferromagnetically couples the magnetic stability enhancement layer and the free magnet. A tunnel barrier is disposed on the storage layer, a fixed magnet is disposed on the tunnel barrier, and a top electrode is disposed on the fixed magnet.

Example 2: The SOT device of example 1, wherein the spin orbit torque electrode comprises a metal selected from the group consisting of tantalum, tungsten and platinum.

Example 3 : The SOT device of example 1, wherein the magnetic stability enhancement layer includes a multilayer stack of alternating layers of magnetic and non- magnetic materials, wherein the number of alternating layers of magnetic and non-magnetic materials ranges from 4-10.

Example 4: The SOT device of example 3, wherein the non-magnetic layers comprise a metal selected from the group consisting of platinum, palladium and iridium.

Example 5 : The SOT device of example 3, wherein the magnetic material comprises cobalt.

Example 6: The SOT device of example 3, 4 or 5, wherein the magnetic stability enhancement layer has a total combined thickness between 0.8nm-3.0nm.

Example 7: The SOT device of example 1, wherein the coupling layer comprises a metal selected from the group consisting of molybdenum, iridium, tungsten and tantalum.

Example 8: The SOT device of example 1 or 7, wherein the coupling layer is molybdenum.

Example 9: The SOT device of example 1, 7 or 8, wherein the coupling layer has a thickness between 0.3nm-1.0nm.

Example 10: The SOT device of example 1, wherein the free magnet comprises cobalt, boron and iron.

Example 11 : A spin orbit torque (SOT) memory device includes a spin orbit torque electrode and a memory device disposed above a portion of the spin orbit torque electrode A magnetic stability enhancement layer is disposed on the spin orbit torque electrode. A spacer is disposed above the magnetic stability enhancement layer, wherein the spacer includes a first coupling layer disposed on the stability enhancement layer, a magnetic coupler disposed on the first coupling layer, a second coupling layer disposed on the magnetic coupler. A free magnet is disposed on the complex spacer, a tunnel barrier is disposed on the free magnet, a fixed magnet is disposed on the tunnel barrier, and a top electrode is disposed on the fixed magnet.

Example 12: The SOT memory device of example 1 1, wherein the spin orbit torque electrode comprises a metal selected from the group consisting of tantalum, tungsten and platinum.

Example 13 : The SOT memory device of example 1 1, wherein the stability enhancement layer includes a multilayer stack of alternating layers of magnetic and nonmagnetic materials, wherein the number of alternating layers of magnetic and non-magnetic materials ranges from 4-10.

Example 14: The SOT memory device of example 13, wherein the non-magnetic material in the stability enhancement layer comprises a metal selected from the group consisting of platinum, nickel, palladium and iridium.

Example 15 : The SOT memory device of example 13, wherein the magnetic material comprises cobalt.

Example 16: The SOT memory device of example 1 1, wherein the first coupling layer and the second coupling layer comprise a metal selected from the group consisting of molybdenum, iridium, tungsten and tantalum.

Example 17: The SOT memory device of example 1 1, wherein the magnetic coupler comprises cobalt, boron and iron.

Example 18: The SOT memory device of example 1 1, wherein the free magnet comprises cobalt, boron and iron.

Example 19: A method of fabricating a spin orbit torque (SOT) device includes depositing a spin orbit toque electrode layer above a substrate and patterning the spin orbit torque electrode layer to form a spin orbit torque electrode having an uppermost surface. The method further includes forming a material layer stack for a magnetic tunnel junction (MTJ) memory device on the uppermost surface of the spin orbit torque electrode. The method further includes depositing a magnetic stability enhancement layer on the spin orbit torque electrode, forming a spacer layer above the magnetic stability enhancement layer, depositing a free magnetic layer on the spacer layer, depositing a tunnel barrier layer on the free magnetic layer, depositing a fixed magnetic layer on the tunnel barrier layer and depositing a top electrode layer on the fixed magnetic layer. The method further includes etching the material layer stack to form an MTJ memory device over a portion of the spin orbit torque electrode, wherein the etching forms a top electrode, a fixed magnet, a tunnel barrier, a free magnet, a spacer and a magnetic stability enhancement structure.

Example 20: The method of example 19, wherein forming the spacer layer includes depositing a metallic coupling layer between the magnetic stability enhancement layer and the free magnetic layer.

Example 21 : The method of example 20, wherein the metallic layer is deposited using a physical vapor deposition technique to form an amorphous metallic layer.

Example 22: The method of example 20 or 21, wherein depositing the spacer layer includes depositing to a thickness of less than lnm to enable magnetic coupling between the magnetic stability enhancement layer and the free magnetic layer.

Example 23 : The method of example 19, wherein the process further includes performing a high temperature anneal to enable <001> lattice matching of the free magnetic layer to the tunnel barrier layer.

Example 24: The method of example 19, wherein forming the spacer layer includes, depositing a first metallic coupling layer on the magnetic stability enhancement structure, depositing a coupling magnetic layer on the first metallic coupling layer, and depositing a second metallic coupling layer on the coupling magnetic layer.

Claims

CLAIMS What is claimed is:

1. A spin orbit torque (SOT) device, comprising:

a spin orbit torque electrode;

a memory device disposed above a portion of the spin orbit torque electrode comprising:

a storage layer, wherein the storage layer includes:

a magnetic stability enhancement layer;

a conductive coupling layer disposed on the stability enhancement layer; a free magnet disposed on the conductive coupling layer, the conductive coupling layer ferromagnetically coupling the magnetic stability enhancement layer and the free magnet;

a tunnel barrier disposed on the storage layer;

a fixed magnet disposed on the tunnel barrier; and

a top electrode disposed on the fixed magnet.

2. The SOT device of claim 1, wherein the spin orbit torque electrode comprises a selected from the group consisting of tantalum, tungsten and platinum.

3. The SOT device of claim 1, wherein the magnetic stability enhancement layer includes a multilayer stack of alternating layers of magnetic and non-magnetic materials, wherein the number of alternating layers of magnetic and non-magnetic materials ranges from 4-10.

4. The SOT device of claim 3, wherein the non-magnetic layers comprise a metal selected from the group consisting of platinum, palladium and iridium.

5. The SOT device of claim 3, wherein the magnetic material comprises cobalt.

6. The SOT device of claim 3, wherein the magnetic stability enhancement layer has a total combined thickness between 0.8nm-3.0nm.

7. The SOT device of claim 1, wherein the coupling layer comprises a metal selected from the group consisting of molybdenum, iridium, tungsten and tantalum.

8. The SOT device of claim 1, wherein the coupling layer is molybdenum.

9. The SOT device of claim 1, wherein the coupling layer has a thickness between 0.3nm- l .Onm.

10. The SOT device of claim 1, wherein the free magnet comprises cobalt, boron and iron.

11. A spin orbit torque (SOT) memory device, comprising:

a spin orbit torque electrode;

a magnetic stability enhancement layer disposed on the spin orbit torque electrode;

a spacer disposed above the magnetic stability enhancement layer, wherein the spacer includes:

a first coupling layer disposed on the stability enhancement layer; a magnetic coupler disposed on the first coupling layer;

a second coupling layer disposed on the magnetic coupler;

a free magnet disposed on the complex spacer;

a tunnel barrier disposed on the free magnet;

a fixed magnet disposed on the tunnel barrier; and

a top electrode disposed on the fixed magnet.

12. The SOT device of claim 1 1, wherein the spin orbit torque electrode comprises a metal selected from the group consisting of tantalum, tungsten and platinum.

13. The SOT device of claim 1 1, wherein the stability enhancement layer includes a multilayer stack of alternating layers of magnetic and non-magnetic materials, wherein the number of alternating layers of magnetic and non-magnetic materials ranges from 4-10.

14. The SOT device of claim 13, wherein the non-magnetic material in the stability enhancement layer comprises a metal selected from the group consisting of platinum, nickel, palladium and iridium.

15. The SOT device of claim 13, wherein the magnetic material comprises cobalt.

16. The SOT device of claim 1 1, wherein the first coupling layer and the second coupling layer comprise a metal selected from the group consisting of molybdenum, iridium, tungsten and tantalum.

17. The SOT device of claim 1 1, wherein the magnetic coupler comprises cobalt, boron and iron.

18. The SOT device of claim 1 1, wherein the free magnet comprises cobalt, boron and iron.

19. A method of fabricating a spin orbit torque (SOT) device, the method comprising:

depositing a spin orbit toque electrode layer above a substrate;

patterning the spin orbit torque electrode layer to form a spin orbit torque electrode having an uppermost surface;

forming a material layer stack for a magnetic tunnel junction (MTJ) memory device on the uppermost surface of the spin orbit torque electrode, the forming comprising:

depositing a magnetic stability enhancement layer on the spin orbit torque electrode; forming a spacer layer above the magnetic stability enhancement layer;

depositing a free magnetic layer on the spacer layer;

depositing a tunnel barrier layer on the free magnetic layer;

depositing a fixed magnetic layer on the tunnel barrier layer;

depositing a top electrode layer on the fixed magnetic layer;

etching the material layer stack to form an MTJ memory device over a portion of the spin orbit torque electrode; wherein the etching forms a top electrode, a fixed magnet, a tunnel barrier, a free magnet, a spacer and a magnetic stability enhancement structure.

20. The method of claim 19, wherein forming the spacer layer includes depositing a metallic coupling layer between the magnetic stability enhancement layer and the free magnetic layer.

21. The method of claim 20, wherein the metallic layer is deposited using a physical vapor deposition technique to form an amorphous metallic layer.

22. The method of claim 20, wherein depositing the spacer layer includes depositing to a thickness of less than lnm to enable magnetic coupling between the magnetic stability enhancement layer and the free magnetic layer.

23. The method of claim 19, wherein the process further includes performing a high temperature anneal to enable <001> lattice matching of the free magnetic layer to the tunnel barrier layer.

24. The method of claim 19, wherein forming the spacer layer includes:

depositing a first metallic coupling layer on the magnetic stability enhancement structure;

depositing a coupling magnetic layer on the first metallic coupling layer; and depositing a second metallic coupling layer on the coupling magnetic layer.