WO2018179265A1 - Display device, method for manufacturing display device, and apparatus for manufacturing display device - Google Patents

Display device, method for manufacturing display device, and apparatus for manufacturing display device Download PDF

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Publication number
WO2018179265A1
WO2018179265A1 PCT/JP2017/013355 JP2017013355W WO2018179265A1 WO 2018179265 A1 WO2018179265 A1 WO 2018179265A1 JP 2017013355 W JP2017013355 W JP 2017013355W WO 2018179265 A1 WO2018179265 A1 WO 2018179265A1
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WO
WIPO (PCT)
Prior art keywords
display device
layer
terminal
conduction hole
manufacturing
Prior art date
Application number
PCT/JP2017/013355
Other languages
French (fr)
Japanese (ja)
Inventor
薫 安部
山渕　浩二
伸一 川戸
Original Assignee
シャープ株式会社
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Application filed by シャープ株式会社 filed Critical シャープ株式会社
Priority to PCT/JP2017/013355 priority Critical patent/WO2018179265A1/en
Publication of WO2018179265A1 publication Critical patent/WO2018179265A1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/02—Details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/02—Details
    • H05B33/04—Sealing arrangements, e.g. against humidity
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/02—Details
    • H05B33/06—Electrode terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H10K59/8731—Encapsulations multilayered coatings having a repetitive structure, e.g. having multiple organic-inorganic bilayers

Definitions

  • the present invention relates to a display device.
  • Patent Document 1 describes a configuration in which a flexible printed circuit board (FPC) is mounted on a device including an organic EL element.
  • FPC flexible printed circuit board
  • a display device includes a lower layer portion and a light emitting element layer formed in an upper layer than the lower layer portion, and the lower layer portion includes a terminal portion including a terminal electrode and the terminal portion.
  • the lower layer portion includes a terminal portion including a terminal electrode and the terminal portion.
  • the frame portion surrounding the display area can be reduced.
  • FIG. 3 is a cross-sectional view illustrating a configuration example of a display device (non-display area) according to Embodiment 1.
  • FIG. 4 is a flowchart showing a film forming process and a mounting process in the first embodiment.
  • 6 is a plan view showing a film forming process and a mounting process in Embodiment 1.
  • FIG. 5 is a cross-sectional view illustrating a film forming process and a mounting process in Embodiment 1.
  • FIG. FIG. 10 is a plan view showing a modification of the first embodiment.
  • FIG. 6 is a cross-sectional view showing a modification of the first embodiment. It is a block diagram which shows the structure of the display device manufacturing apparatus of this embodiment. 10 is a flowchart illustrating a film forming process and a mounting process in the second embodiment. 6 is a plan view showing a film forming process and a mounting process in Embodiment 2.
  • FIG. 10 is a cross-sectional view showing a film forming process and a mounting process in Embodiment 2.
  • FIG. 6 is a plan view illustrating a configuration of a display device according to Embodiment 3.
  • FIG. 10 is a cross-sectional view showing a modification of the third embodiment. 10 is a plan view showing another configuration of the display device of Embodiment 3.
  • FIG. 10 is a plan view illustrating another configuration of the display device of Embodiment 3.
  • FIG. 1 is a flowchart illustrating an example of a method for manufacturing a display device
  • FIG. 2A is a cross-sectional view illustrating a configuration example of a display device (display region) according to Embodiment 1
  • FIG. 3 is a cross-sectional view illustrating a configuration example of a display device (non-display area) according to Embodiment 1.
  • FIG. FIG. 3 is a cross-sectional view illustrating a configuration example of the display device (non-display area) according to the first embodiment.
  • a resin layer 12 is formed on a translucent support 50 (for example, a glass substrate) (step S1).
  • the barrier layer 3 is formed (step S2).
  • the TFT layer 4 including the semiconductor film 15, the gate electrode G, the source electrode S, the drain electrode D, and the inorganic insulating films 16, 18, and 20 is formed (step S3).
  • a light emitting element layer (for example, OLED element layer) 5 is formed (step S4).
  • the sealing layer 6 including the inorganic sealing films 26 and 28 and the organic sealing film 27 is formed (step S5).
  • the top film 9 is pasted on the sealing layer 6 via the adhesive layer 8 (step S6).
  • the lower surface of the resin layer 12 is irradiated with laser light through the support 50 (step S7).
  • the resin layer 12 absorbs the laser beam irradiated to the lower surface of the support 50 and transmitted through the support 50, whereby the lower surface of the resin layer 12 (interface with the support 50) is altered by ablation, and the resin The bonding force between the layer 12 and the support 50 is reduced.
  • the support 50 is peeled from the resin layer 12 (step S8).
  • the lower film 10 for example, PET
  • the laminated body with the bottom film is divided and separated into pieces (step S10).
  • step S11 the functional film 39 is pasted through the adhesive layer 38 (step S11).
  • an electronic circuit board 60 (for example, FPC) is mounted on the back surface of the terminal portion of the TFT layer 4 to obtain the singulated display device 2 shown in FIGS. 2B and 3 (step S12).
  • Each step is performed by a display device manufacturing apparatus.
  • Examples of the material of the lower film 10 include polyethylene terephthalate (PET).
  • Examples of the material of the resin layer 12 include polyimide, epoxy, polyamide, and acrylic.
  • the barrier layer 3 is a layer that prevents moisture and impurities from reaching the TFT layer 4 and the light emitting element layer 5 when the display device is used.
  • the barrier layer 3 is formed by CVD, such as a silicon oxide film, a silicon nitride film, Alternatively, a silicon oxynitride film or a laminated film thereof can be used.
  • the thickness of the inorganic barrier layer 3 is, for example, 50 nm to 1500 nm.
  • the TFT layer 4 includes a semiconductor film 15, an inorganic insulating film 16 (gate insulating film) formed on the upper side of the semiconductor film 15, a gate electrode G formed on the upper side of the gate insulating film 16, and an upper side of the gate electrode G. Formed on the inorganic insulating film 18, the capacitive electrode C formed on the upper side of the inorganic insulating film 18, the inorganic insulating film 20 formed on the upper side of the capacitive electrode C, and the upper side of the inorganic insulating film 20. A source electrode S, a drain electrode D, and a terminal electrode TM, and an organic interlayer film 21 formed above the source electrode S and the drain electrode D.
  • the semiconductor film 15, the inorganic insulating film 16, the gate electrode G, the inorganic insulating films 18 and 20, the source electrode S, and the drain electrode D constitute a thin layer transistor (TFT).
  • TFT thin layer transistor
  • the plurality of terminal electrodes TM formed at the end (non-display area NA) of the TFT layer 4 are used for connection to an electronic circuit board such as an IC chip or FPC.
  • the end surface of the terminal electrode TM is covered with the organic interlayer film 21.
  • the semiconductor film 15 is made of, for example, low temperature polysilicon (LPTS) or an oxide semiconductor.
  • the gate insulating film 16 can be constituted by, for example, a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a stacked film thereof formed by a CVD method.
  • the gate electrode G, the source electrode S, the drain electrode D, and the terminal are, for example, aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), copper ( It is comprised by the metal single layer film or laminated film containing at least 1 of Cu).
  • the TFT having the semiconductor film 15 as a channel is shown as a top gate structure, but a bottom gate structure may be used (for example, when the TFT channel is an oxide semiconductor).
  • the inorganic insulating films 16, 18, and 20 can be formed of, for example, a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a stacked film thereof formed by a CVD method.
  • SiOx silicon oxide
  • SiNx silicon nitride
  • the organic interlayer film 21 can be made of a photosensitive organic material that can be applied, such as polyimide or acrylic.
  • the organic interlayer film 21 functions as a base (planarization film) for the light emitting element layer 5.
  • the organic interlayer film 21 and the lower portion 21y of the convex structure TK in the non-display area are formed in the same process.
  • the anode electrode 22 is composed of, for example, a laminate of ITO (Indium Tin Oxide) and an alloy containing Ag or Al, and has light reflectivity.
  • ITO Indium Tin Oxide
  • the light emitting element layer 5 (for example, OLED layer) includes an anode electrode 22 formed above the organic interlayer film 21, a bank 23 defining subpixels in the display area DA, and an EL formed above the anode electrode 22.
  • An (electroluminescence) layer 24 and a cathode electrode 25 formed on the upper side of the EL layer 24 are included.
  • the bank 23 in the display area and the upper portion 23y of the convex structure TK in the non-display area can be formed using a photosensitive organic material such as polyimide, epoxy, acrylic, or the like, for example, in the same process.
  • the convex structure TK is formed in an upper layer than the inorganic insulating film 20 and defines the edge of the organic sealing film 27.
  • the EL layer 24 is formed in a region (subpixel region) defined by the bank 23 by a vapor deposition method or an ink jet method.
  • the light emitting element layer 5 is an OLED (organic light emitting diode) layer
  • the EL layer 24 includes a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer in order from the lower layer side. It is composed by doing.
  • the cathode electrode 25 can be made of a transparent metal such as ITO (Indium Tin Oxide), IZO (Indium Zincum Oxide), or MgAg alloy.
  • the light emitting element layer 5 is an OLED layer
  • holes and electrons are recombined in the EL layer 24 by the driving current between the anode electrode 22 and the cathode electrode 25, and the exciton generated thereby falls to the ground state. Light is emitted.
  • the light emitting element layer 5 is not limited to the OLED layer, but may be an inorganic light emitting diode layer or a quantum dot light emitting diode layer.
  • the sealing layer 6 includes a first inorganic sealing film 26 that covers the partition wall 23 c and the cathode electrode 25, an organic sealing film 27 that covers the first inorganic sealing film 26, and a second inorganic sealing film that covers the organic sealing film 27. And a stop film 28.
  • the first inorganic sealing film 26 and the second inorganic sealing film 28 are each formed of, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a stacked film thereof formed by CVD using a mask. Can be configured.
  • the organic sealing film 27 is a light-transmitting organic insulating film that is thicker than the first inorganic sealing film 26 and the second inorganic sealing film 28, and is made of a photosensitive organic material that can be applied, such as polyimide or acrylic. can do. For example, an ink containing such an organic material is applied onto the first inorganic sealing film 26 by inkjet and then cured by UV irradiation.
  • the sealing layer 6 covers the light emitting element layer 5 and prevents penetration of foreign matters such as water and oxygen into the light emitting element layer 5.
  • the sealing layer 6 can also be comprised only with an inorganic film
  • the upper surface film 9 is affixed on the sealing layer 6 through the adhesive 8 and functions as a support material when the support 50 is peeled off.
  • the material for the top film 9 include PET (polyethylene terephthalate).
  • the lower film 10 is for manufacturing a display device having excellent flexibility by being attached to the lower surface of the resin layer 12 after the support 50 is peeled off.
  • Examples of the material include PET.
  • the functional film 39 has, for example, an optical compensation function, a touch sensor function, a protection function, and the like.
  • the electronic circuit board 60 disposed on the back surface of the terminal portion 44 is, for example, an IC chip or a flexible printed board.
  • the lower layer portion 7 including the resin layer 12, the barrier layer 3, and the TFT layer 4 is provided with a terminal portion 44 located on the inorganic insulating film 20 of the TFT layer 4, and an inorganic insulation from the terminal portion 44.
  • a conduction hole DH that penetrates the film 20, the inorganic insulating film 18, the inorganic insulating film 16, the barrier layer 3, and the resin layer 12 and reaches the back surface 49 (the lower surface of the resin layer 12) of the terminal portion 44 is formed.
  • the terminal portion 44 includes a plurality of terminal electrodes TM, and the terminal electrodes TM are formed on the inner wall of the conduction hole DH (inner walls of the inorganic insulating films 16, 18, 20, the barrier layer 3 and the resin layer 12 through holes).
  • the conduction part DC is included.
  • a conductor 55 is disposed inside the conduction hole DH, and the conductor 55 is disposed on the back surface 49 of the terminal portion 44 (the lower end portion of the resin layer 12) and the conduction portion DC of the terminal electrode TM.
  • the terminal electrode TM and the electronic circuit board 60 are electrically connected by contacting each of them.
  • the inorganic insulating films 16, 18, 20 and the resin layer 12 can be formed by dry etching using, for example, photolithography. Holes can be formed in the resin layer 12 by laser irradiation.
  • FIG. 4 is a flowchart showing a film forming process and a mounting process in the first embodiment.
  • FIG. 5 is a plan view showing a film forming process and a mounting process in the first embodiment.
  • FIG. 6 is a cross-sectional view showing a film forming process and a mounting process in the first embodiment.
  • a conduction hole DH is formed at the terminal portion formation position (step S4a).
  • the conduction hole DH is provided for each position where the terminal electrode is formed.
  • the conduction hole DH has a forward tapered shape (thinning toward the bottom) and penetrates the inorganic insulating film 20, the inorganic insulating film 18, the inorganic insulating film 16, the barrier layer 3, and the resin layer 12.
  • the taper angle of the conduction hole DH is desirably 30 ° to 80 °.
  • a terminal electrode TM that passes through the inner wall of the conduction hole DH is formed in the terminal portion 44 (step S4b). That is, the terminal electrode TM includes a conduction part DC formed on the inner wall of the conduction hole DH.
  • the support 50 is peeled off (from the resin layer 12) (step S8).
  • the support 50 is peeled off (from the resin layer 12) (step S8).
  • the portion located on the bottom surface of the conduction hole of the terminal electrode TM is removed.
  • step S9 the lower surface film 10 is attached (step S9).
  • separation is performed by dividing (step S10).
  • the lower film 10 corresponding to the back side of the terminal portion 44 is cut.
  • the lower surface film corresponding to the back side of the terminal portion is peeled off (step S12a).
  • the display device 2 is placed on the stage ST1 having an opening (provided at a position corresponding to the terminal portion), and the electronic circuit board 60 is placed on the stage ST2.
  • the conductor 55 conductive binder
  • the stage ST2 is disposed on the back side of the terminal portion 44 so that the conductor 55 and the bottom surface of the conduction hole face each other (step S12b).
  • the crimping head AH is arranged on the conductive hole upper surface (opening surface) side, the stage ST2 is raised, and the electric conductor 55 is formed by the electronic circuit board 60 and the crimping head AH. Is applied to fill the conductive hole DH in the conduction hole DH (step S12c).
  • the conductor 55 filled in the conduction hole DH is cured by heat from the pressure bonding head AH (step S12d).
  • the electronic circuit board 60 is made of resin in a state in which the conductor 55 that is a conductive binder is in contact with the conduction portion DC and the electronic circuit board 60. Bonded to the lower surface of layer 12. That is, the terminal electrode TM and the electronic circuit board 60 are electrically connected, and the electronic circuit board 60 is mounted on the back surface of the terminal portion 44.
  • FIG. 7 is a cross-sectional view showing a modification of the display device of the first embodiment.
  • FIG. 7 shows a terminal part configuration in the case where the conduction part DC is formed by the same process as the terminal electrode TM (formed in the same source layer and made of the same material).
  • the conduction hole DH is surrounded by the edge Te of the terminal electrode TM.
  • one end is connected to the terminal electrode TM, and a terminal wiring TW made of the same material as the terminal electrode TM is provided.
  • the wiring width w1 of the terminal wiring TW is the wiring width w1. Is smaller than the size w2 of the conduction hole DH in the same direction.
  • the terminal electrode TM is connected to the source layer (for example, the source electrode) of the TFT layer 4, but the present invention is not limited to this.
  • the terminal electrode TM can also be connected to the gate layer (same layer as the gate electrode) of the TFT layer 4.
  • the openings of the barrier layer 3 and the resin layer 12 are made smaller than the openings of the inorganic insulating films 16, 18, and 20.
  • Conductive portions DC are formed on the inner walls of the through holes of the inorganic insulating films 16, 18, and 20 and the barrier layer 3.
  • the electronic circuit board 60 is disposed under the bottom surface of the conduction hole DH, and the conductor 55 (conductive binder) applied to the holding plate PZ is disposed on the opening of the conduction hole DH. Then, the pressure bonding head AH may be lowered to apply pressure to the conductor 55 between the pressing plate PZ and the electronic circuit board 60 to fill the conductor 55 in the conduction hole DH.
  • the display device manufacturing apparatus 70 includes a film forming apparatus 76, a cutting apparatus 74, a mounting apparatus 80 including a thermocompression bonding tool and the like, and a controller 72 that controls these apparatuses.
  • the film forming apparatus 76 controlled by the controller 72 performs steps S4a to S4b of FIG. 4, and the mounting apparatus 80 controlled by the controller 72 performs steps S12a to S12d of FIG.
  • the frame portion is compared with a configuration in which an electronic circuit board (FPC or the like) mounted on the terminal portion is bent on the back surface. Can be reduced. Further, since it is not necessary to bend the electronic circuit board, the mounting reliability can be improved.
  • FPC electronic circuit board
  • FIG. 10 is a flowchart showing a film forming process and a mounting process in the second embodiment.
  • FIG. 11 is a plan view showing a film forming process and a mounting process in the second embodiment.
  • FIG. 12 is a cross-sectional view illustrating a mounting process in the second embodiment.
  • a conduction hole DH is formed at the terminal portion formation position (step S4a).
  • the conduction hole DH has a forward tapered shape (thinning toward the bottom) and penetrates the inorganic insulating film 20, the inorganic insulating film 18, the inorganic insulating film 16, the barrier layer 3, and the resin layer 12.
  • the terminal electrode TM (source layer) is formed on the terminal portion 44 (step S4b).
  • step S8 the support 50 is peeled (from the resin layer 12) (step S8), and the lower surface film is attached (step S9).
  • separation is performed by dividing (step S10).
  • the lower film corresponding to the back side of the terminal portion 44 is cut.
  • the lower surface film corresponding to the back side of the terminal portion is peeled off (step S12a).
  • the electronic circuit board 60 is adhered to the back side of the terminal portion 44 with an adhesive 59 (step S12b).
  • the conductor 56 is applied in the terminal electrode TM and the conduction hole DH by the ink jet method (step S12e).
  • the conductor 56 is made of, for example, an ink-jetable conductive material including silver nanoparticles, and contacts the terminal electrode TM and the electronic circuit board 60.
  • terminal electrode TM and the electronic circuit board 60 are electrically connected via the conductor 56, and the electronic circuit board 60 is mounted on the back surface of the terminal portion 44.
  • the terminal electrode TM is configured to include the conduction part DC formed on the inner wall of the conduction hole DH, and the inside of the conduction hole DH.
  • the conductor 56 may be brought into contact with the terminal electrode TM and the electronic circuit board 60 by driving the conductor 56 into the ink jet system.
  • the conduction hole DH is provided for each terminal electrode TM.
  • one (common) conduction hole DH is provided for a plurality of terminal electrodes.
  • one (common) conduction hole DH may be provided for all terminal electrodes.
  • the conduction hole DH corresponding to the plurality of terminal electrodes TM includes a resin hole 12k formed for each terminal electrode TM, and the terminal electrode TM is a resin hole.
  • An anisotropic conductive film 58 (including a thermosetting resin 58j and conductive particles 58c) disposed in the conduction hole DH includes a conduction part DC formed on the 12k side wall, and a conduction part DC of the terminal electrode TM.
  • a configuration in contact with the electronic circuit board 60 disposed below the resin layer 12 is also possible. As shown in FIG.
  • the terminal portion 44 and the electronic circuit board 60 are provided on the back surface corresponding to one side (one edge) of the rectangular display device in a plan view having four sides, but this is not limitative.
  • the electronic circuit board 60 can be provided on the terminal portion 44 and the back surface thereof corresponding to each of the four sides (FA, FB, FC, FD). In this way, the area of the routing wiring is reduced, and the frame portion can be reduced.
  • the terminal portion 44 corresponding to two opposite sides and the electronic circuit board 60 on the back surface thereof are connected as shown in FIG. 3 (that is, the terminal electrode TM is electrically connected to the source layer of the TFT layer 4).
  • the terminal portion 44 corresponding to the remaining two sides (two sides facing each other) and the electronic circuit board 60 on the back surface thereof are connected as shown in FIG. 15 (that is, the terminal electrode TM is electrically connected to the gate layer of the TFT layer 4).
  • the edge of the display device 2 in plan view is not limited to a rectangle, and may be a polygon, a circle, an ellipse, or the like (for example, the entire edge of the display device may be an ellipse or a circle, or a part of the edge may be an ellipse). Shape or circular shape). As shown in FIG. 16, a part of the edge of the display device 2 may be a curved portion Fa having a curvature, and a terminal portion 44 may be formed along the curved portion Fa. In this case, a part of the edge of the electronic circuit board 60 provided on the back surface of the terminal portion 44 may have a curvature.
  • the electro-optic element provided in the display device according to the present embodiment is not particularly limited.
  • a display device for example, an organic EL (Electro Luminescence) display including an OLED (Organic Light Emitting Diode) as an electro-optical element, an inorganic EL display including an inorganic light-emitting diode as an electro-optical element, Examples of the electro-optical element include a QLED display provided with a QLED (Quantum dot Light Emitting Diode).
  • Aspect 1 A lower layer, and a light emitting element layer formed in an upper layer than the lower layer, A display device in which the lower layer portion includes a terminal portion including a terminal electrode, and a conduction hole extending from the terminal portion to the lower surface of the lower layer portion, which is the back surface thereof.
  • Aspect 2 A conductor at least a part of which is located in the conduction hole is provided, and the conductor is in contact with the terminal electrode and an electronic circuit board disposed below the lower layer portion. The indicated display device.
  • Aspect 3 The display device according to Aspect 2, for example, wherein the terminal electrode includes a conduction portion formed on an inner wall of the conduction hole, and the conductor is in contact with the conduction portion and the electronic circuit board.
  • Aspect 4 The conduction hole and the terminal electrode are formed of the same material, The display device according to any one of aspects 1 to 3, for example, wherein the conduction hole is surrounded by an edge of the terminal electrode in a plan view.
  • Aspect 5 The lower layer part is provided with a terminal wiring having one end connected to the terminal electrode and formed of the same material as the terminal electrode, and the wiring width of the terminal wiring is the size of the conduction hole in the same direction as the wiring width.
  • the display device according to aspect 4 for example, smaller than the display device.
  • Aspect 6 The display device according to any one of Embodiments 1 to 5, for example, wherein the conduction hole has a forward tapered shape.
  • Aspect 7 The display device according to Aspect 2, for example, wherein the conductor is a conductive binder.
  • Aspect 8 The display device according to Aspect 2, for example, wherein the conductor includes a conductive material that can be applied by an inkjet method.
  • Aspect 9 The lower layer portion includes a TFT layer provided with the terminal portion, a barrier layer formed under the TFT layer, and a resin layer formed under the barrier layer. The display device according to claim 1.
  • Aspect 10 The display device according to Aspect 9, for example, wherein the conduction hole extends from the terminal portion to the lower surface of the lower layer portion through the barrier layer and the resin layer.
  • Aspect 11 Including a bottom film bonded to the resin layer; The display device according to, for example, the aspect 9 or 10, wherein the lower surface film is removed from the back surface of the terminal portion.
  • Aspect 12 The display device according to any one of aspects 9 to 11, for example, wherein the terminal electrode is formed in the same layer as a conduction electrode of a transistor in the TFT layer.
  • Aspect 13 Having a polygonal shape with three or more sides, The display device according to, for example, aspect 2, including the terminal portion and the electronic circuit board disposed on the back surface side corresponding to each of a plurality of sides.
  • Aspect 14 The display device according to any one of aspects 1 to 13, for example, wherein at least a part of an edge of the display device is a curved portion having a curvature, and the terminal portion is formed along the curved portion.
  • Aspect 15 A manufacturing method of a display device comprising a lower layer part and a light emitting element layer formed in an upper layer than the lower layer part, The manufacturing method of the display device which forms the terminal part containing a terminal electrode in the said lower layer part, and the conduction
  • Aspect 16 The display according to Aspect 15, for example, in which a conductor at least partially located in the conduction hole is provided, and the conductor is brought into contact with the terminal electrode and an electronic circuit board disposed below the lower layer portion.
  • Aspect 17 The manufacturing method of the display device of the aspect 14, for example which makes the said conduction
  • Aspect 18 The method for manufacturing a display device according to any one of embodiments 15 to 17, for example, wherein the conductor is a conductive binder.
  • Aspect 19 The method for manufacturing a display device according to aspect 18, for example, in which the conductor is filled in the conduction hole by pressure.
  • Aspect 20 The method for producing a display device according to any one of embodiments 15 to 17, for example, in which the conductor is applied by an inkjet method.
  • Aspect 21 21. The display device manufacturing method according to any one of embodiments 15 to 20, wherein a resin layer, a barrier layer, and a TFT layer including the terminal portion are formed on the upper side of the support.
  • Aspect 22 The manufacturing method of the display device of the aspect 21, for example, which peels the said support body from the said resin layer, and affixes a lower surface film on the said resin layer.
  • Aspect 23 The method for manufacturing a display device according to, for example, aspect 22, wherein a portion corresponding to the back surface of the terminal portion of the bottom film is removed.
  • a display device manufacturing apparatus comprising a lower layer part and a light emitting element layer formed in an upper layer than the lower layer part, An apparatus for manufacturing a display device, wherein a terminal portion including a terminal electrode and a conduction hole extending from the terminal portion to the lower surface of the lower layer portion, which is the back surface, are formed in the lower layer portion.
  • the present invention is not limited to the above-described embodiments, and embodiments obtained by appropriately combining technical means disclosed in different embodiments are also included in the technical scope of the present invention. Furthermore, a new technical feature can be formed by combining the technical means disclosed in each embodiment.

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  • Electroluminescent Light Sources (AREA)

Abstract

This display device is provided with: a light emitting element layer (5); a terminal part (44) including a plurality of terminal electrodes (TM); a conduction hole (DH) extending from the terminal part (44) to a rear surface thereof; a conductive material (55) disposed inside the conduction hole (DH); and an electronic circuit substrate (60) disposed on the rear surface of the terminal part, wherein the terminal electrodes (TM) include conduction parts (DC) formed on an inner wall of the conduction hole, and the conductive material (55) contacts the conduction parts (DC) and the electronic circuit substrate (60).

Description

表示デバイス、表示デバイスの製造方法、表示デバイスの製造装置Display device, display device manufacturing method, display device manufacturing apparatus
　本発明は、表示デバイスに関する。 The present invention relates to a display device.
　特許文献１には、有機ＥＬ素子を含むデバイスにフレキシブルプリント基板（ＦＰＣ）を実装する構成が記載されている。 Patent Document 1 describes a configuration in which a flexible printed circuit board (FPC) is mounted on a device including an organic EL element.
日本国再公表特許公報「ＷＯ２０１３－９９１３５号（２０１３年７月４日公開）」Japanese republished patent publication “WO2013-99135 (released on July 4, 2013)”
　特許文献１の手法では、ＦＰＣ等の電子回路基板の実装領域を確保するために額縁部分が大きくなるという問題がある。 In the method of Patent Document 1, there is a problem that a frame portion becomes large in order to secure a mounting area of an electronic circuit board such as an FPC.
　本発明の一態様に係る表示デバイスは、下層部と、前記下層部よりも上層に形成される発光素子層とを備え、前記下層部には、端子電極を含む端子部と、前記端子部から、その裏面である前記下層部の下面に到る導通ホールとが形成されている。 A display device according to one embodiment of the present invention includes a lower layer portion and a light emitting element layer formed in an upper layer than the lower layer portion, and the lower layer portion includes a terminal portion including a terminal electrode and the terminal portion. In addition, a conduction hole reaching the lower surface of the lower layer portion, which is the back surface, is formed.
　本発明の一態様によれば、表示領域を取り囲む額縁部分を縮小することができる。 According to one aspect of the present invention, the frame portion surrounding the display area can be reduced.
表示デバイスの製造方法の一例を示すフローチャートである。It is a flowchart which shows an example of the manufacturing method of a display device. （ａ）は、実施形態１の表示デバイス（表示領域）の製造途中の構成例を示す断面図であり、（ｂ）は、実施形態１の表示デバイス（表示領域）の構成例を示す断面図である。(A) is sectional drawing which shows the structural example in the middle of manufacture of the display device (display area) of Embodiment 1, (b) is sectional drawing which shows the structural example of the display device (display area) of Embodiment 1. It is. 実施形態１の表示デバイス（非表示領域）の構成例を示す断面図である。3 is a cross-sectional view illustrating a configuration example of a display device (non-display area) according to Embodiment 1. FIG. 実施形態１での成膜工程および実装工程を示すフローチャートである。4 is a flowchart showing a film forming process and a mounting process in the first embodiment. 実施形態１での成膜工程および実装工程を示す平面図である。6 is a plan view showing a film forming process and a mounting process in Embodiment 1. FIG. 実施形態１での成膜工程および実装工程を示す断面図である。5 is a cross-sectional view illustrating a film forming process and a mounting process in Embodiment 1. FIG. 実施形態１の変形例を示す平面図である。FIG. 10 is a plan view showing a modification of the first embodiment. 実施形態１の変形例を示す断面図である。FIG. 6 is a cross-sectional view showing a modification of the first embodiment. 本実施形態の表示デバイス製造装置の構成を示すブロック図である。It is a block diagram which shows the structure of the display device manufacturing apparatus of this embodiment. 実施形態２での成膜工程および実装工程を示すフローチャートである。10 is a flowchart illustrating a film forming process and a mounting process in the second embodiment. 実施形態２での成膜工程および実装工程を示す平面図である。6 is a plan view showing a film forming process and a mounting process in Embodiment 2. FIG. 実施形態２での成膜工程および実装工程を示す断面図である。10 is a cross-sectional view showing a film forming process and a mounting process in Embodiment 2. FIG. 実施形態２における成膜工程および実装工程の別例を示す断面図である。It is sectional drawing which shows another example of the film-forming process in Embodiment 2, and a mounting process. 実施形態３の表示デバイスの構成を示す平面図である。6 is a plan view illustrating a configuration of a display device according to Embodiment 3. FIG. 実施形態３の変形例を示す断面図である。FIG. 10 is a cross-sectional view showing a modification of the third embodiment. 実施形態３の表示デバイスの別構成を示す平面図である。10 is a plan view showing another configuration of the display device of Embodiment 3. FIG.
　図１は、表示デバイスの製造方法の一例を示すフローチャートであり、図２（ａ）は、実施形態１の表示デバイス（表示領域）の構成例を示す断面図であり、図（ｂ）は、実施形態１の表示デバイス（非表示領域）の構成例を示す断面図である。図３は、実施形態１の表示デバイス（非表示領域）の構成例を示す断面図である。 FIG. 1 is a flowchart illustrating an example of a method for manufacturing a display device, FIG. 2A is a cross-sectional view illustrating a configuration example of a display device (display region) according to Embodiment 1, and FIG. 3 is a cross-sectional view illustrating a configuration example of a display device (non-display area) according to Embodiment 1. FIG. FIG. 3 is a cross-sectional view illustrating a configuration example of the display device (non-display area) according to the first embodiment.
　図１および図２（ａ）に示すように、まず、透光性の支持体５０（例えば、ガラス基板）上に樹脂層１２を形成する（ステップＳ１）。次いで、バリア層３を形成する（ステップＳ２）。次いで、半導体膜１５、ゲート電極Ｇ、ソース電極Ｓ、ドレイン電極Ｄ、および無機絶縁膜１６・１８・２０を含むＴＦＴ層４を形成する（ステップＳ３）。次いで、発光素子層（例えば、ＯＬＥＤ素子層）５を形成する（ステップＳ４）。次いで、無機封止膜２６・２８および有機封止膜２７を含む封止層６を形成する（ステップＳ５）。次いで、封止層６上に接着層８を介して上面フィルム９を貼り付ける（ステップＳ６）。 As shown in FIGS. 1 and 2A, first, a resin layer 12 is formed on a translucent support 50 (for example, a glass substrate) (step S1). Next, the barrier layer 3 is formed (step S2). Next, the TFT layer 4 including the semiconductor film 15, the gate electrode G, the source electrode S, the drain electrode D, and the inorganic insulating films 16, 18, and 20 is formed (step S3). Next, a light emitting element layer (for example, OLED element layer) 5 is formed (step S4). Next, the sealing layer 6 including the inorganic sealing films 26 and 28 and the organic sealing film 27 is formed (step S5). Next, the top film 9 is pasted on the sealing layer 6 via the adhesive layer 8 (step S6).
　次いで、支持体５０越しに樹脂層１２の下面にレーザ光を照射する（ステップＳ７）。ここでは、支持体５０の下面に照射され、支持体５０を透過したレーザ光を樹脂層１２が吸収することで、樹脂層１２の下面（支持体５０との界面）がアブレーションによって変質し、樹脂層１２および支持体５０間の結合力が低下する。次いで、支持体５０を樹脂層１２から剥離する（ステップＳ８）。次いで、樹脂層１２の下面に、接着層１１を介して下面フィルム１０（例えば、ＰＥＴ）を貼り付ける（ステップＳ９）。次いで、下面フィルム付きの積層体を分断し、個片化する（ステップＳ１０）。次いで、接着層３８を介して機能フィルム３９を貼り付ける（ステップＳ１１）。次いで、ＴＦＴ層４の端子部の裏面に電子回路基板６０（例えば、ＦＰＣ）を実装し、図２（ｂ）および図３に示す、個片化された表示デバイス２を得る（ステップＳ１２）。なお、前記各ステップは表示デバイスの製造装置が行う。 Next, the lower surface of the resin layer 12 is irradiated with laser light through the support 50 (step S7). Here, the resin layer 12 absorbs the laser beam irradiated to the lower surface of the support 50 and transmitted through the support 50, whereby the lower surface of the resin layer 12 (interface with the support 50) is altered by ablation, and the resin The bonding force between the layer 12 and the support 50 is reduced. Next, the support 50 is peeled from the resin layer 12 (step S8). Next, the lower film 10 (for example, PET) is attached to the lower surface of the resin layer 12 via the adhesive layer 11 (step S9). Next, the laminated body with the bottom film is divided and separated into pieces (step S10). Next, the functional film 39 is pasted through the adhesive layer 38 (step S11). Next, an electronic circuit board 60 (for example, FPC) is mounted on the back surface of the terminal portion of the TFT layer 4 to obtain the singulated display device 2 shown in FIGS. 2B and 3 (step S12). Each step is performed by a display device manufacturing apparatus.
　下面フィルム１０の材料としては、例えばポリエチレンテレフタレート（ＰＥＴ）が挙げられる。樹脂層１２の材料としては、例えば、ポリイミド、エポキシ、ポリアミド、アクリル等が挙げられる。 Examples of the material of the lower film 10 include polyethylene terephthalate (PET). Examples of the material of the resin layer 12 include polyimide, epoxy, polyamide, and acrylic.
　バリア層３は、表示デバイスの使用時に、水分や不純物が、ＴＦＴ層４や発光素子層５に到達することを防ぐ層であり、例えば、ＣＶＤにより形成される、酸化シリコン膜、窒化シリコン膜、あるいは酸窒化シリコン膜、またはこれらの積層膜で構成することができる。無機バリア層３の厚さは、例えば、５０ｎｍ～１５００ｎｍである。 The barrier layer 3 is a layer that prevents moisture and impurities from reaching the TFT layer 4 and the light emitting element layer 5 when the display device is used. For example, the barrier layer 3 is formed by CVD, such as a silicon oxide film, a silicon nitride film, Alternatively, a silicon oxynitride film or a laminated film thereof can be used. The thickness of the inorganic barrier layer 3 is, for example, 50 nm to 1500 nm.
　ＴＦＴ層４は、半導体膜１５と、半導体膜１５の上側に形成される無機絶縁膜１６（ゲート絶縁膜）と、ゲート絶縁膜１６の上側に形成されるゲート電極Ｇと、ゲート電極Ｇの上側に形成される無機絶縁膜１８と、無機絶縁膜１８の上側に形成される、容量電極Ｃと、容量電極Ｃの上側に形成される無機絶縁膜２０と、無機絶縁膜２０の上側に形成される、ソース電極Ｓ、ドレイン電極Ｄおよび端子電極ＴＭと、ソース電極Ｓおよびドレイン電極Ｄの上側に形成される有機層間膜２１とを含む。半導体膜１５、無機絶縁膜１６、ゲート電極Ｇ、無機絶縁膜１８・２０、ソース電極Ｓおよびドレイン電極Ｄは、薄層トランジスタ（ＴＦＴ）を構成する。 The TFT layer 4 includes a semiconductor film 15, an inorganic insulating film 16 (gate insulating film) formed on the upper side of the semiconductor film 15, a gate electrode G formed on the upper side of the gate insulating film 16, and an upper side of the gate electrode G. Formed on the inorganic insulating film 18, the capacitive electrode C formed on the upper side of the inorganic insulating film 18, the inorganic insulating film 20 formed on the upper side of the capacitive electrode C, and the upper side of the inorganic insulating film 20. A source electrode S, a drain electrode D, and a terminal electrode TM, and an organic interlayer film 21 formed above the source electrode S and the drain electrode D. The semiconductor film 15, the inorganic insulating film 16, the gate electrode G, the inorganic insulating films 18 and 20, the source electrode S, and the drain electrode D constitute a thin layer transistor (TFT).
　ＴＦＴ層４の端部（非表示領域ＮＡ）に形成される複数の端子電極ＴＭは、ＩＣチップ、ＦＰＣ等の電子回路基板との接続に用いられる。端子電極ＴＭの端面は、有機層間膜２１によって覆われている。 The plurality of terminal electrodes TM formed at the end (non-display area NA) of the TFT layer 4 are used for connection to an electronic circuit board such as an IC chip or FPC. The end surface of the terminal electrode TM is covered with the organic interlayer film 21.
　半導体膜１５は、例えば低温ポリシリコン（ＬＰＴＳ）あるいは酸化物半導体で構成される。ゲート絶縁膜１６は、例えば、ＣＶＤ法によって形成された、酸化シリコン（ＳｉＯｘ）膜あるいは窒化シリコン（ＳｉＮｘ）膜またはこれらの積層膜によって構成することができる。ゲート電極Ｇ、ソース電極Ｓ、ドレイン電極Ｄ、および端子は、例えば、アルミニウム（Ａｌ）、タングステン（Ｗ）、モリブデン（Ｍｏ）、タンタル（Ｔａ）、クロム（Ｃｒ）、チタン（Ｔｉ）、銅（Ｃｕ）の少なくとも１つを含む金属の単層膜あるいは積層膜によって構成される。なお、図２では、半導体膜１５をチャネルとするＴＦＴがトップゲート構造で示されているが、ボトムゲート構造でもよい（例えば、ＴＦＴのチャネルが酸化物半導体の場合）。 The semiconductor film 15 is made of, for example, low temperature polysilicon (LPTS) or an oxide semiconductor. The gate insulating film 16 can be constituted by, for example, a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a stacked film thereof formed by a CVD method. The gate electrode G, the source electrode S, the drain electrode D, and the terminal are, for example, aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), copper ( It is comprised by the metal single layer film or laminated film containing at least 1 of Cu). In FIG. 2, the TFT having the semiconductor film 15 as a channel is shown as a top gate structure, but a bottom gate structure may be used (for example, when the TFT channel is an oxide semiconductor).
　無機絶縁膜１６・１８・２０は、例えば、ＣＶＤ法によって形成された、酸化シリコン（ＳｉＯｘ）膜あるいは窒化シリコン（ＳｉＮｘ）膜またはこれらの積層膜によって構成することができる。 The inorganic insulating films 16, 18, and 20 can be formed of, for example, a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a stacked film thereof formed by a CVD method.
　有機層間膜２１は、ポリイミド、アクリル等の塗布可能な感光性有機材料によって構成することができる。有機層間膜２１は、発光素子層５の下地（平坦化膜）として機能する。また、有機層間膜２１と、非表示領域の凸状構造体ＴＫの下部２１ｙは同一工程で形成される。 The organic interlayer film 21 can be made of a photosensitive organic material that can be applied, such as polyimide or acrylic. The organic interlayer film 21 functions as a base (planarization film) for the light emitting element layer 5. The organic interlayer film 21 and the lower portion 21y of the convex structure TK in the non-display area are formed in the same process.
　アノード電極２２は、例えばＩＴＯ（Indium Tin Oxide）とＡｇまたはＡｌを含む合金との積層またはによって構成され、光反射性を有する。 The anode electrode 22 is composed of, for example, a laminate of ITO (Indium Tin Oxide) and an alloy containing Ag or Al, and has light reflectivity.
　発光素子層５（例えば、ＯＬＥＤ層）は、有機層間膜２１の上側に形成されるアノード電極２２と、表示領域ＤＡのサブピクセルを規定するバンク２３と、アノード電極２２の上側に形成されるＥＬ（エレクトロルミネッセンス）層２４と、ＥＬ層２４の上側に形成されるカソード電極２５とを含む。 The light emitting element layer 5 (for example, OLED layer) includes an anode electrode 22 formed above the organic interlayer film 21, a bank 23 defining subpixels in the display area DA, and an EL formed above the anode electrode 22. An (electroluminescence) layer 24 and a cathode electrode 25 formed on the upper side of the EL layer 24 are included.
　なお、表示領域のバンク２３および非表示領域の凸状構造体ＴＫの上部２３ｙは、ポリイミド、エポキシ、アクリル等の塗布可能な感光性有機材料を用いて、例えば同一工程で形成することができる。凸状構造体ＴＫは、無機絶縁膜２０よりも上層に形成され、有機封止膜２７のエッジを規定する。 Note that the bank 23 in the display area and the upper portion 23y of the convex structure TK in the non-display area can be formed using a photosensitive organic material such as polyimide, epoxy, acrylic, or the like, for example, in the same process. The convex structure TK is formed in an upper layer than the inorganic insulating film 20 and defines the edge of the organic sealing film 27.
　ＥＬ層２４は、蒸着法あるいはインクジェット法によって、バンク２３で規定された領域（サブピクセル領域）に形成される。　発光素子層５がＯＬＥＤ（有機発光ダイオード）層である場合、ＥＬ層２４は、例えば、下層側から順に、正孔注入層、正孔輸送層、発光層、電子輸送層、電子注入層を積層することで構成される。カソード電極２５は、ＩＴＯ（Indium Tin Oxide）、ＩＺＯ（Indium Zincum Oxide）等の透明金属または、ＭｇＡｇ合金で構成することができる。 The EL layer 24 is formed in a region (subpixel region) defined by the bank 23 by a vapor deposition method or an ink jet method. When the light emitting element layer 5 is an OLED (organic light emitting diode) layer, for example, the EL layer 24 includes a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer in order from the lower layer side. It is composed by doing. The cathode electrode 25 can be made of a transparent metal such as ITO (Indium Tin Oxide), IZO (Indium Zincum Oxide), or MgAg alloy.
　発光素子層５がＯＬＥＤ層である場合、アノード電極２２およびカソード電極２５間の駆動電流によって正孔と電子がＥＬ層２４内で再結合し、これによって生じたエキシトンが基底状態に落ちることによって、光が放出される。 When the light emitting element layer 5 is an OLED layer, holes and electrons are recombined in the EL layer 24 by the driving current between the anode electrode 22 and the cathode electrode 25, and the exciton generated thereby falls to the ground state. Light is emitted.
　なお、　発光素子層５は、前記のＯＬＥＤ層に限られず、無機発光ダイード層でもよいし、量子ドット発光ダイオード層でもよい。 The light emitting element layer 5 is not limited to the OLED layer, but may be an inorganic light emitting diode layer or a quantum dot light emitting diode layer.
　封止層６は、隔壁２３ｃおよびカソード電極２５を覆う第１無機封止膜２６と、第１無機封止膜２６を覆う有機封止膜２７と、有機封止膜２７を覆う第２無機封止膜２８とを含む。 The sealing layer 6 includes a first inorganic sealing film 26 that covers the partition wall 23 c and the cathode electrode 25, an organic sealing film 27 that covers the first inorganic sealing film 26, and a second inorganic sealing film that covers the organic sealing film 27. And a stop film 28.
　第１無機封止膜２６および第２無機封止膜２８はそれぞれ、例えば、マスクを用いたＣＶＤにより形成される、酸化シリコン膜、窒化シリコン膜、あるいは酸窒化シリコン膜、またはこれらの積層膜で構成することができる。有機封止膜２７は、第１無機封止膜２６および第２無機封止膜２８よりも厚い、透光性の有機絶縁膜であり、ポリイミド、アクリル等の塗布可能な感光性有機材料によって構成することができる。例えば、このような有機材料を含むインクを第１無機封止膜２６上にインクジェット塗布した後、ＵＶ照射により硬化させる。封止層６（特に、第１無機封止膜２６および第２無機封止膜２８）は、発光素子層５を覆い、水、酸素等の異物の発光素子層５への浸透を防いでいる。なお、封止層６を無機膜だけで構成することもできる。 The first inorganic sealing film 26 and the second inorganic sealing film 28 are each formed of, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a stacked film thereof formed by CVD using a mask. Can be configured. The organic sealing film 27 is a light-transmitting organic insulating film that is thicker than the first inorganic sealing film 26 and the second inorganic sealing film 28, and is made of a photosensitive organic material that can be applied, such as polyimide or acrylic. can do. For example, an ink containing such an organic material is applied onto the first inorganic sealing film 26 by inkjet and then cured by UV irradiation. The sealing layer 6 (particularly, the first inorganic sealing film 26 and the second inorganic sealing film 28) covers the light emitting element layer 5 and prevents penetration of foreign matters such as water and oxygen into the light emitting element layer 5. . In addition, the sealing layer 6 can also be comprised only with an inorganic film | membrane.
　なお、上面フィルム９は、接着剤８を介して封止層６上に貼り付けられ、支持体５０を剥離した時の支持材として機能する。上面フィルム９の材料としては、ＰＥＴ（ポリエチレンテレフタレート）等が挙げられる。 In addition, the upper surface film 9 is affixed on the sealing layer 6 through the adhesive 8 and functions as a support material when the support 50 is peeled off. Examples of the material for the top film 9 include PET (polyethylene terephthalate).
　下面フィルム１０は、支持体５０を剥離した後に樹脂層１２の下面に貼り付けることで、柔軟性に優れた表示デバイスを製造するためのものであり、その材料としては、ＰＥＴ等が挙げられる。 The lower film 10 is for manufacturing a display device having excellent flexibility by being attached to the lower surface of the resin layer 12 after the support 50 is peeled off. Examples of the material include PET.
　機能フィルム３９は、例えば、光学補償機能、タッチセンサ機能、保護機能等を有する。端子部４４の裏面に配される電子回路基板６０は、例えば、ＩＣチップあるいはフレキシブルプリント基板である。 The functional film 39 has, for example, an optical compensation function, a touch sensor function, a protection function, and the like. The electronic circuit board 60 disposed on the back surface of the terminal portion 44 is, for example, an IC chip or a flexible printed board.
　図３に示すように、樹脂層１２、バリア層３およびＴＦＴ層４を含む下層部７には、ＴＦＴ層４の無機絶縁膜２０上に位置する端子部４４と、端子部４４から、無機絶縁膜２０、無機絶縁膜１８、無機絶縁膜１６、バリア層３、および樹脂層１２を貫通し、端子部４４の裏面４９（樹脂層１２の下面）に到る導通ホールＤＨとが形成される。 As shown in FIG. 3, the lower layer portion 7 including the resin layer 12, the barrier layer 3, and the TFT layer 4 is provided with a terminal portion 44 located on the inorganic insulating film 20 of the TFT layer 4, and an inorganic insulation from the terminal portion 44. A conduction hole DH that penetrates the film 20, the inorganic insulating film 18, the inorganic insulating film 16, the barrier layer 3, and the resin layer 12 and reaches the back surface 49 (the lower surface of the resin layer 12) of the terminal portion 44 is formed.
　端子部４４は複数の端子電極ＴＭを含み、端子電極ＴＭは、導通ホールＤＨの内側壁（無機絶縁膜１６・１８・２０、バリア層３および樹脂層１２の貫通孔の内壁）に形成された導通部ＤＣを含む。導通ホールＤＨの内部には導電体５５が配され、導電体５５が、端子部４４の裏面４９（樹脂層１２の下面端部）に配された電子回路基板６０および端子電極ＴＭの導通部ＤＣそれぞれと接触することで、端子電極ＴＭと電子回路基板６０とが電気的に接続される。 The terminal portion 44 includes a plurality of terminal electrodes TM, and the terminal electrodes TM are formed on the inner wall of the conduction hole DH (inner walls of the inorganic insulating films 16, 18, 20, the barrier layer 3 and the resin layer 12 through holes). The conduction part DC is included. A conductor 55 is disposed inside the conduction hole DH, and the conductor 55 is disposed on the back surface 49 of the terminal portion 44 (the lower end portion of the resin layer 12) and the conduction portion DC of the terminal electrode TM. The terminal electrode TM and the electronic circuit board 60 are electrically connected by contacting each of them.
　なお、導通ホールＤＨの形成手法としては、無機絶縁膜１６・１８・２０および樹脂層１２については、例えばフォトリソグラフィを用いたドライエッチングによってホール形成が可能である。樹脂層１２についてはレーザ照射によってもホール形成が可能である。 As a method for forming the conduction hole DH, the inorganic insulating films 16, 18, 20 and the resin layer 12 can be formed by dry etching using, for example, photolithography. Holes can be formed in the resin layer 12 by laser irradiation.
　〔実施形態１〕
　図４は、実施形態１での成膜工程および実装工程を示すフローチャートである。図５は、実施形態１での成膜工程および実装工程を示す平面図である。図６は、実施形態１での成膜工程および実装工程を示す断面図である。 Embodiment 1
FIG. 4 is a flowchart showing a film forming process and a mounting process in the first embodiment. FIG. 5 is a plan view showing a film forming process and a mounting process in the first embodiment. FIG. 6 is a cross-sectional view showing a film forming process and a mounting process in the first embodiment.
　まず、図４・図５（ａ）・図６（ａ）に示すように、端子部形成位置に導通ホールＤＨを形成する（ステップＳ４ａ）。導通ホールＤＨは、端子電極の形成位置ごとに設ける。導通ホールＤＨは順テーパ（底に向けて細る）形状であり、無機絶縁膜２０、無機絶縁膜１８、無機絶縁膜１６、バリア層３、および樹脂層１２を貫通する。導通ホールＤＨのテーパ角は、３０°～８０°が望ましい。 First, as shown in FIG. 4, FIG. 5 (a) and FIG. 6 (a), a conduction hole DH is formed at the terminal portion formation position (step S4a). The conduction hole DH is provided for each position where the terminal electrode is formed. The conduction hole DH has a forward tapered shape (thinning toward the bottom) and penetrates the inorganic insulating film 20, the inorganic insulating film 18, the inorganic insulating film 16, the barrier layer 3, and the resin layer 12. The taper angle of the conduction hole DH is desirably 30 ° to 80 °.
　次いで、図４・図５（ｂ）・図６（ｂ）に示すように、端子部４４に、導通ホールＤＨの内側壁を通る端子電極ＴＭを形成する（ステップＳ４ｂ）。すなわち、端子電極ＴＭは、導通ホールＤＨの内側壁に形成された導通部ＤＣを含む。 Next, as shown in FIG. 4, FIG. 5B, and FIG. 6B, a terminal electrode TM that passes through the inner wall of the conduction hole DH is formed in the terminal portion 44 (step S4b). That is, the terminal electrode TM includes a conduction part DC formed on the inner wall of the conduction hole DH.
　その後、支持体５０を（樹脂層１２から）剥離する（ステップＳ８）。これにより、図図５（ｃ）に示すように、端子電極ＴＭの導通ホール底面に位置する部分が除去される。 Thereafter, the support 50 is peeled off (from the resin layer 12) (step S8). As a result, as shown in FIG. 5C, the portion located on the bottom surface of the conduction hole of the terminal electrode TM is removed.
　次いで、図４・図６（ｃ）に示すように、下面フィルム１０を貼り付ける（ステップＳ９）。次いで、分断による個片化を行う（ステップＳ１０）。このステップでは、端子部４４の裏側にあたる下面フィルム１０を切断しておく。次いで、図４・図６（ｄ）に示すように、端子部の裏側にあたる下面フィルムを剥離する（ステップＳ１２ａ）。 Next, as shown in FIG. 4 and FIG. 6C, the lower surface film 10 is attached (step S9). Next, separation is performed by dividing (step S10). In this step, the lower film 10 corresponding to the back side of the terminal portion 44 is cut. Next, as shown in FIGS. 4 and 6D, the lower surface film corresponding to the back side of the terminal portion is peeled off (step S12a).
　次いで、図４・図６（ｅ）に示すように、表示デバイス２を、開口（端子部に対応する位置に設けられている）を有するステージＳＴ１に載せ、電子回路基板６０をステージＳＴ２に載せて電子回路基板６０上に導電体５５（導電性バインダー）を配置し、導電体５５と導通ホール底面とが向かい合うように、ステージＳＴ２を端子部４４の裏側に配置する（ステップＳ１２ｂ）。次いで、図４・図６（ｅ）に示すように、圧着ヘッドＡＨを導通ホール上面（開口面）側に配してステージＳＴ２を上昇させて、電子回路基板６０および圧着ヘッドＡＨによって導電体５５に圧力をかけ、導電体５５を導通ホールＤＨ内に充填する（ステップＳ１２ｃ）。次いで、圧着ヘッドＡＨからの熱によって導通ホールＤＨ内に充填された導電体５５を硬化させる（ステップＳ１２ｄ）。 Next, as shown in FIGS. 4 and 6E, the display device 2 is placed on the stage ST1 having an opening (provided at a position corresponding to the terminal portion), and the electronic circuit board 60 is placed on the stage ST2. Then, the conductor 55 (conductive binder) is disposed on the electronic circuit board 60, and the stage ST2 is disposed on the back side of the terminal portion 44 so that the conductor 55 and the bottom surface of the conduction hole face each other (step S12b). Next, as shown in FIG. 4 and FIG. 6E, the crimping head AH is arranged on the conductive hole upper surface (opening surface) side, the stage ST2 is raised, and the electric conductor 55 is formed by the electronic circuit board 60 and the crimping head AH. Is applied to fill the conductive hole DH in the conduction hole DH (step S12c). Next, the conductor 55 filled in the conduction hole DH is cured by heat from the pressure bonding head AH (step S12d).
　これにより、図４・図５（ｄ）・図６（ｆ）に示すように、導電性バインダーである導電体５５が導通部ＤＣおよび電子回路基板６０に接触した状態で電子回路基板６０が樹脂層１２の下面に接着される。すなわち、端子電極ＴＭおよび電子回路基板６０が電気的に接続され、電子回路基板６０が、端子部４４の裏面に実装される。 As a result, as shown in FIGS. 4, 5 (d), and 6 (f), the electronic circuit board 60 is made of resin in a state in which the conductor 55 that is a conductive binder is in contact with the conduction portion DC and the electronic circuit board 60. Bonded to the lower surface of layer 12. That is, the terminal electrode TM and the electronic circuit board 60 are electrically connected, and the electronic circuit board 60 is mounted on the back surface of the terminal portion 44.
　図７は、実施形態１の表示デバイスの変形例を示す断面図である。図７は導通部ＤＣが端子電極ＴＭと同一プロセスで形成される（同じソース層に、かつ同材料で形成される）場合の端子部構成を示している。この場合、導通ホールＤＨが端子電極ＴＭのエッジＴｅで囲まれる構成となる。また、無機絶縁膜２０上には、一端が端子電極ＴＭに繋がり、端子電極ＴＭと同一材料で形成された端子配線ＴＷが設けられており、端子配線ＴＷの配線幅ｗ１が、この配線幅ｗ１と同方向に関する導通ホールＤＨのサイズｗ２よりも小さい。 FIG. 7 is a cross-sectional view showing a modification of the display device of the first embodiment. FIG. 7 shows a terminal part configuration in the case where the conduction part DC is formed by the same process as the terminal electrode TM (formed in the same source layer and made of the same material). In this case, the conduction hole DH is surrounded by the edge Te of the terminal electrode TM. In addition, on the inorganic insulating film 20, one end is connected to the terminal electrode TM, and a terminal wiring TW made of the same material as the terminal electrode TM is provided. The wiring width w1 of the terminal wiring TW is the wiring width w1. Is smaller than the size w2 of the conduction hole DH in the same direction.
　なお、図２および図３では、端子電極ＴＭがＴＦＴ層４のソース層（例えば、ソース電極）に接続されているがこれに限定されない。端子電極ＴＭをＴＦＴ層４のゲート層（ゲート電極と同層）に接続することもできる。 In FIGS. 2 and 3, the terminal electrode TM is connected to the source layer (for example, the source electrode) of the TFT layer 4, but the present invention is not limited to this. The terminal electrode TM can also be connected to the gate layer (same layer as the gate electrode) of the TFT layer 4.
　導通ホールＤＨの形状については、図８（ａ）に示すように、段階的に先細となる構成でもよい。例えば、無機絶縁膜１６・１８・２０の開口よりもバリア層３および樹脂層１２の開口を小さくする。また、導通部ＤＣを、無機絶縁膜１６・１８・２０およびバリア層３の貫通孔の内壁に形成する。 As for the shape of the conduction hole DH, as shown in FIG. For example, the openings of the barrier layer 3 and the resin layer 12 are made smaller than the openings of the inorganic insulating films 16, 18, and 20. Conductive portions DC are formed on the inner walls of the through holes of the inorganic insulating films 16, 18, and 20 and the barrier layer 3.
　また、図８（ｂ）のように、導通ホールＤＨの底面下に電子回路基板６０を配するとともに、押さえ板ＰＺに塗布した導電体５５（導電性バインダー）を導通ホールＤＨの開口上に配し、圧着ヘッドＡＨを降下させて押さえ板ＰＺおよび電子回路基板６０間の導電体５５に圧力を加えて導電体５５を導通ホールＤＨ内に充填してもよい。 Further, as shown in FIG. 8B, the electronic circuit board 60 is disposed under the bottom surface of the conduction hole DH, and the conductor 55 (conductive binder) applied to the holding plate PZ is disposed on the opening of the conduction hole DH. Then, the pressure bonding head AH may be lowered to apply pressure to the conductor 55 between the pressing plate PZ and the electronic circuit board 60 to fill the conductor 55 in the conduction hole DH.
　なお、図９に示すように、表示デバイス製造装置７０は、成膜装置７６と、分断装置７４と、熱圧着ツール等を含む実装装置８０と、これらの装置を制御するコントローラ７２とを含んでおり、コントローラ７２の制御を受けた成膜装置７６が図４のステップＳ４ａ～ステップＳ４ｂを行い、コントローラ７２の制御を受けた実装着装置８０が図４のステップＳ１２ａ～ステップＳ１２ｄを行う。 As shown in FIG. 9, the display device manufacturing apparatus 70 includes a film forming apparatus 76, a cutting apparatus 74, a mounting apparatus 80 including a thermocompression bonding tool and the like, and a controller 72 that controls these apparatuses. The film forming apparatus 76 controlled by the controller 72 performs steps S4a to S4b of FIG. 4, and the mounting apparatus 80 controlled by the controller 72 performs steps S12a to S12d of FIG.
　実施形態１では、端子部４４の裏面に電子回路基板６０を実装することができるため、端子部上に実装した電子回路基板（ＦＰＣ等）を裏面に折り曲げるような構成と比較して額縁部分を縮小することができる。また、電子回路基板を折り曲げる必要もないため、実装の信頼性も高められる。 In the first embodiment, since the electronic circuit board 60 can be mounted on the back surface of the terminal portion 44, the frame portion is compared with a configuration in which an electronic circuit board (FPC or the like) mounted on the terminal portion is bent on the back surface. Can be reduced. Further, since it is not necessary to bend the electronic circuit board, the mounting reliability can be improved.
　〔実施形態２〕
　図１０は、実施形態２での成膜工程および実装工程を示すフローチャートである。図１１は、実施形態２での成膜工程および実装工程を示す平面図である。図１２は、実施形態２での実装工程を示す断面図である。 [Embodiment 2]
FIG. 10 is a flowchart showing a film forming process and a mounting process in the second embodiment. FIG. 11 is a plan view showing a film forming process and a mounting process in the second embodiment. FIG. 12 is a cross-sectional view illustrating a mounting process in the second embodiment.
　まず、図１０・図１１（ａ）・図１２（ａ）に示すように、端子部形成位置に導通ホールＤＨを形成する（ステップＳ４ａ）。導通ホールＤＨは順テーパ（底に向けて細る）形状であり、無機絶縁膜２０、無機絶縁膜１８、無機絶縁膜１６、バリア層３、および樹脂層１２を貫通する。 First, as shown in FIG. 10, FIG. 11 (a), and FIG. 12 (a), a conduction hole DH is formed at the terminal portion formation position (step S4a). The conduction hole DH has a forward tapered shape (thinning toward the bottom) and penetrates the inorganic insulating film 20, the inorganic insulating film 18, the inorganic insulating film 16, the barrier layer 3, and the resin layer 12.
　次いで、図１０・図１１（ｂ）に示すように、端子部４４に、端子電極ＴＭ（ソース層）を形成する（ステップＳ４ｂ）。 Next, as shown in FIGS. 10 and 11B, the terminal electrode TM (source layer) is formed on the terminal portion 44 (step S4b).
　その後、図１０に示すように、支持体５０を（樹脂層１２から）剥離し（ステップＳ８）、下面フィルムを貼り付ける（ステップＳ９）。次いで、分断による個片化を行う（ステップＳ１０）。このステップでは、端子部４４の裏側にあたる下面フィルムを切断しておく。次いで、図１０に示すように、端子部の裏側にあたる下面フィルムを剥離する（ステップＳ１２ａ）。 Thereafter, as shown in FIG. 10, the support 50 is peeled (from the resin layer 12) (step S8), and the lower surface film is attached (step S9). Next, separation is performed by dividing (step S10). In this step, the lower film corresponding to the back side of the terminal portion 44 is cut. Next, as shown in FIG. 10, the lower surface film corresponding to the back side of the terminal portion is peeled off (step S12a).
　次いで、図１０・図１２（ｂ）に示すように、電子回路基板６０を、接着剤５９によって端子部４４の裏側に接着する（ステップＳ１２ｂ）。次いで、図１０・図１１（ｃ）・図１２（ｃ）に示すように、インクジェット法により、端子電極ＴＭおよび導通ホールＤＨ内に導電体５６を塗布する（ステップＳ１２ｅ）。導電体５６は、例えば、銀ナノ粒子を含むインクジェット可能な導電材で構成され、端子電極ＴＭおよび電子回路基板６０に接触する。 Next, as shown in FIGS. 10 and 12B, the electronic circuit board 60 is adhered to the back side of the terminal portion 44 with an adhesive 59 (step S12b). Next, as shown in FIG. 10, FIG. 11 (c), and FIG. 12 (c), the conductor 56 is applied in the terminal electrode TM and the conduction hole DH by the ink jet method (step S12e). The conductor 56 is made of, for example, an ink-jetable conductive material including silver nanoparticles, and contacts the terminal electrode TM and the electronic circuit board 60.
　これにより、導電体５６を介して端子電極ＴＭおよび電子回路基板６０が電気的に接続され、電子回路基板６０が、端子部４４の裏面に実装される。 Thereby, the terminal electrode TM and the electronic circuit board 60 are electrically connected via the conductor 56, and the electronic circuit board 60 is mounted on the back surface of the terminal portion 44.
　なお、実施形態２においても、図１２（ｘ）・（ｙ）に示すように、端子電極ＴＭを導通ホールＤＨの内側壁に形成された導通部ＤＣを含むように構成し、導通ホールＤＨ内にインクジェット方式にて導電体５６を打ち込むことで、導電体５６を、端子電極ＴＭおよび電子回路基板６０に接触させる構成でもよい。 In the second embodiment as well, as shown in FIGS. 12 (x) and 12 (y), the terminal electrode TM is configured to include the conduction part DC formed on the inner wall of the conduction hole DH, and the inside of the conduction hole DH. Alternatively, the conductor 56 may be brought into contact with the terminal electrode TM and the electronic circuit board 60 by driving the conductor 56 into the ink jet system.
　図１１（ａ）～（ｃ）の例では、導通ホールＤＨを端子電極ＴＭごとに設けているが、図１１（ｄ）のように、複数の端子電極に１つの（共通の）導通ホールＤＨを設けてもよいし、すべての端子電極に対して１つの（共通の）導通ホールＤＨを設けてもよい。 In the examples of FIGS. 11A to 11C, the conduction hole DH is provided for each terminal electrode TM. However, as shown in FIG. 11D, one (common) conduction hole DH is provided for a plurality of terminal electrodes. Alternatively, one (common) conduction hole DH may be provided for all terminal electrodes.
　さらに、図１３（ａ）（ｄ）に示すように、複数の端子電極ＴＭに対応する導通ホールＤＨに、端子電極ＴＭごとに形成された樹脂ホール１２ｋが含まれ、端子電極ＴＭが、樹脂ホール１２ｋの側壁に形成された導通部ＤＣを含み、導通ホールＤＨ内に配された異方性導電フィルム５８（熱硬化樹脂５８ｊおよび導電粒子５８ｃを含む）が、端子電極ＴＭの導通部ＤＣと、樹脂層１２の下側に配された電子回路基板６０とに接触している構成も可能である。図１３（ｂ）のように、圧着ヘッドＡＨから抑え板ＰＺを介して異方性導電フィルム５８に圧力および熱を加えることで、樹脂ホール１２ｋ内に導電粒子５８ｃが押し込まれ、導通部ＤＣと電子回路基板６０とが導電粒子５８ｃを介して接続される（図１３（ｃ）参照）。なお、端子電極ＴＭの並ぶ方向（図１３（ｄ）の縦方向）には絶縁性が担保される。 Further, as shown in FIGS. 13A and 13D, the conduction hole DH corresponding to the plurality of terminal electrodes TM includes a resin hole 12k formed for each terminal electrode TM, and the terminal electrode TM is a resin hole. An anisotropic conductive film 58 (including a thermosetting resin 58j and conductive particles 58c) disposed in the conduction hole DH includes a conduction part DC formed on the 12k side wall, and a conduction part DC of the terminal electrode TM. A configuration in contact with the electronic circuit board 60 disposed below the resin layer 12 is also possible. As shown in FIG. 13B, by applying pressure and heat from the pressure bonding head AH to the anisotropic conductive film 58 via the restraining plate PZ, the conductive particles 58c are pushed into the resin hole 12k, and the conduction portion DC and The electronic circuit board 60 is connected via the conductive particles 58c (see FIG. 13C). Insulating properties are ensured in the direction in which the terminal electrodes TM are arranged (the vertical direction in FIG. 13D).
　〔実施形態３〕　
　実施形態１・２では、４辺を有する平面視において矩形の表示デバイスの１辺（１つのエッジ）に対応して端子部４４およびその裏面に電子回路基板６０を設けているが、これに限定されない。例えば、図１４のように、４辺（ＦＡ・ＦＢ・ＦＣ・ＦＤ）それぞれに対応して、端子部４４およびその裏面に電子回路基板６０を設けることもできる。こうすれば、引き回し配線の領域が削減され、額縁部分を縮小することができる。 [Embodiment 3]
In the first and second embodiments, the terminal portion 44 and the electronic circuit board 60 are provided on the back surface corresponding to one side (one edge) of the rectangular display device in a plan view having four sides, but this is not limitative. Not. For example, as shown in FIG. 14, the electronic circuit board 60 can be provided on the terminal portion 44 and the back surface thereof corresponding to each of the four sides (FA, FB, FC, FD). In this way, the area of the routing wiring is reduced, and the frame portion can be reduced.
　図１４の構成では、向かい合う２辺に対応する端子部４４およびその裏面の電子回路基板６０を図３のように接続（すなわち、端子電極ＴＭをＴＦＴ層４のソース層に電気的に接続）し、残りの２辺（向かい合う２辺）に対応する端子部４４およびその裏面の電子回路基板６０を図１５のように接続（すなわち、端子電極ＴＭをＴＦＴ層４のゲート層に電気的に接続）することもできる。 In the configuration of FIG. 14, the terminal portion 44 corresponding to two opposite sides and the electronic circuit board 60 on the back surface thereof are connected as shown in FIG. 3 (that is, the terminal electrode TM is electrically connected to the source layer of the TFT layer 4). The terminal portion 44 corresponding to the remaining two sides (two sides facing each other) and the electronic circuit board 60 on the back surface thereof are connected as shown in FIG. 15 (that is, the terminal electrode TM is electrically connected to the gate layer of the TFT layer 4). You can also
　なお、平面視における表示デバイス２のエッジは矩形に限られず、多角形、円形、楕円形等でもよい（例えば、表示デバイスのエッジ全体が楕円形状あるいは円形状でもよいし、エッジの一部が楕円形状あるいは円形状でもよい）。図１６に示すように、表示デバイス２のエッジの一部が曲率を有する湾曲部Ｆａであり、湾曲部Ｆａに沿って端子部４４が形成されている構成でもよい。この場合、端子部４４の裏面に設けられる電子回路基板６０のエッジの一部が曲率を有していてもよい。 Note that the edge of the display device 2 in plan view is not limited to a rectangle, and may be a polygon, a circle, an ellipse, or the like (for example, the entire edge of the display device may be an ellipse or a circle, or a part of the edge may be an ellipse). Shape or circular shape). As shown in FIG. 16, a part of the edge of the display device 2 may be a curved portion Fa having a curvature, and a terminal portion 44 may be formed along the curved portion Fa. In this case, a part of the edge of the electronic circuit board 60 provided on the back surface of the terminal portion 44 may have a curvature.
 本実施形態にかかる表示デバイスが備える電気光学素子は特に限定されるものではない。表示デバイスとしては、例えば、電気光学素子としてＯＬＥＤ（Organic Light Emitting Diode：有機発光ダイオード）を備えた有機ＥＬ（Electro Luminescence：エレクトロルミネッセンス）ディスプレイ、電気光学素子として無機発光ダイオードを備えた無機ＥＬディスプレイ、電気光学素子としてＱＬＥＤ（Quantum dot Light Emitting Diode：量子ドット発光ダイオード）を備えたＱＬＥＤディスプレイ等が挙げられる。 The electro-optic element provided in the display device according to the present embodiment is not particularly limited. As a display device, for example, an organic EL (Electro Luminescence) display including an OLED (Organic Light Emitting Diode) as an electro-optical element, an inorganic EL display including an inorganic light-emitting diode as an electro-optical element, Examples of the electro-optical element include a QLED display provided with a QLED (Quantum dot Light Emitting Diode).
　〔まとめ〕
態様１：
　下層部と、前記下層部よりも上層に形成される発光素子層とを備え、
　前記下層部には、端子電極を含む端子部と、前記端子部から、その裏面である前記下層部の下面に到る導通ホールとが形成されている表示デバイス。
態様２：
　少なくとも一部が前記導通ホール内に位置する導電体が設けられ、前記導電体は、前記端子電極と、前記下層部よりも下側に配された電子回路基板とに接触している例えば態様１記載の表示デバイス。
態様３：
　前記端子電極は、前記導通ホールの内側壁に形成された導通部を含み、前記導電体は、前記導通部および前記電子回路基板に接触している例えば態様２記載の表示デバイス。
態様４：
　前記導通ホールと前記端子電極とが同一材料で形成され、
　平面視において、前記導通ホールが、前記端子電極のエッジで囲まれている例えば態様１～３のいずれか１項に表示デバイス。
態様５：
　前記下層部には、一端が前記端子電極に繋がり、前記端子電極と同一材料で形成された端子配線が設けられ、前記端子配線の配線幅は、前記配線幅と同方向に関する前記導通ホールのサイズよりも小さい例えば態様４に記載の表示デバイス。
態様６：
　前記導通ホールは、順テーパ形状である例えば態様１～５のいずれか１項に記載の表示デバイス。
態様７：
　前記導電体は、導電性バインダーである例えば態様２に記載の表示デバイス。
態様８：
　前記導電体はインクジェット法で塗布可能な導電材を含む例えば態様２に記載の表示デバイス。
態様９：
　前記下層部は、前記端子部が設けられたＴＦＴ層と、前記ＴＦＴ層の下層に形成されたバリア層と、前記バリア層の下層に形成された樹脂層とを含む例えば態様１～８のいずれか１項に記載の表示デバイス。
態様１０：
　前記導通ホールは、前記端子部から、前記バリア層および前記樹脂層を貫通して前記下層部の下面に到る例えば態様９に記載の表示デバイス。
態様１１：
　前記樹脂層に接着された下面フィルムを含み、
　前記端子部の裏面においては前記下面フィルムが除去されている例えば態様９または１０に記載の表示デバイス。
態様１２：
　前記端子電極は、前記ＴＦＴ層内のトランジスタの導通電極と同層に形成されている例えば態様９～１１のいずれか１項に記載の表示デバイス。
態様１３：
　３辺以上を有する多角形状を有し、
　複数の辺それぞれに対応して、前記端子部およびその裏面側に配された前記電子回路基板を備える例えば態様２に記載の表示デバイス。
態様１４：
　前記表示デバイスのエッジの少なくとも一部が曲率を有する湾曲部であり、前記湾曲部に沿って前記端子部が形成されている例えば態様１～１３のいずれか１項に記載の表示デバイス。
態様１５：
　下層部と、前記下層部よりも上層に形成される発光素子層とを備える表示デバイスの製造方法であって、
　前記下層部に、端子電極を含む端子部と、前記端子部から、その裏面である前記下層部の下面に到る導通ホールとを形成する表示デバイスの製造方法。
態様１６：
　少なくとも一部が前記導通ホール内に位置する導電体を設け、前記導電体を、前記端子電極と、前記下層部よりも下側に配された電子回路基板とに接触させる例えば態様１５記載の表示デバイスの製造方法。
態様１７：
　前記導通ホールを、順テーパ形状とする例えば態様１４記載の表示デバイスの製造方法。
態様１８：
　前記導電体は、導電性バインダーである例えば態様１５～１７のいずれか１項に記載の表示デバイスの製造方法。
態様１９：
　圧力によって前記導電体を前記導通ホール内に充填する例えば態様１８記載の表示デバイスの製造方法。
態様２０：
　前記導電体をインクジェット法で塗布する例えば態様１５～１７のいずれか１項に記載の表示デバイスの製造方法。
態様２１：
　支持体の上側に、樹脂層と、バリア層と、前記端子部を含むＴＦＴ層とを形成する例えば態様１５～２０のいずれか１項に記載の表示デバイスの製造方法。
態様２２：
　前記支持体を前記樹脂層から剥離し、前記樹脂層に下面フィルムを貼り付ける例えば態様２１に記載の表示デバイスの製造方法。
態様２３：
　前記下面フィルムの前記端子部の裏面にあたる部分を除去する例えば態様２２に記載の表示デバイスの製造方法。
態様２４：
　下層部と、前記下層部よりも上層に形成される発光素子層とを備える表示デバイスの製造装置であって、
　前記下層部に、端子電極を含む端子部と、前記端子部から、その裏面である前記下層部の下面に到る導通ホールとを形成する表示デバイスの製造装置。 [Summary]
Aspect 1:
A lower layer, and a light emitting element layer formed in an upper layer than the lower layer,
A display device in which the lower layer portion includes a terminal portion including a terminal electrode, and a conduction hole extending from the terminal portion to the lower surface of the lower layer portion, which is the back surface thereof.
Aspect 2:
A conductor at least a part of which is located in the conduction hole is provided, and the conductor is in contact with the terminal electrode and an electronic circuit board disposed below the lower layer portion. The indicated display device.
Aspect 3:
The display device according to Aspect 2, for example, wherein the terminal electrode includes a conduction portion formed on an inner wall of the conduction hole, and the conductor is in contact with the conduction portion and the electronic circuit board.
Aspect 4:
The conduction hole and the terminal electrode are formed of the same material,
The display device according to any one of aspects 1 to 3, for example, wherein the conduction hole is surrounded by an edge of the terminal electrode in a plan view.
Aspect 5:
The lower layer part is provided with a terminal wiring having one end connected to the terminal electrode and formed of the same material as the terminal electrode, and the wiring width of the terminal wiring is the size of the conduction hole in the same direction as the wiring width. The display device according to aspect 4, for example, smaller than the display device.
Aspect 6:
The display device according to any one of Embodiments 1 to 5, for example, wherein the conduction hole has a forward tapered shape.
Aspect 7:
The display device according to Aspect 2, for example, wherein the conductor is a conductive binder.
Aspect 8:
The display device according to Aspect 2, for example, wherein the conductor includes a conductive material that can be applied by an inkjet method.
Aspect 9:
The lower layer portion includes a TFT layer provided with the terminal portion, a barrier layer formed under the TFT layer, and a resin layer formed under the barrier layer. The display device according to claim 1.
Aspect 10:
The display device according to Aspect 9, for example, wherein the conduction hole extends from the terminal portion to the lower surface of the lower layer portion through the barrier layer and the resin layer.
Aspect 11:
Including a bottom film bonded to the resin layer;
The display device according to, for example, the aspect 9 or 10, wherein the lower surface film is removed from the back surface of the terminal portion.
Aspect 12:
The display device according to any one of aspects 9 to 11, for example, wherein the terminal electrode is formed in the same layer as a conduction electrode of a transistor in the TFT layer.
Aspect 13:
Having a polygonal shape with three or more sides,
The display device according to, for example, aspect 2, including the terminal portion and the electronic circuit board disposed on the back surface side corresponding to each of a plurality of sides.
Aspect 14:
The display device according to any one of aspects 1 to 13, for example, wherein at least a part of an edge of the display device is a curved portion having a curvature, and the terminal portion is formed along the curved portion.
Aspect 15:
A manufacturing method of a display device comprising a lower layer part and a light emitting element layer formed in an upper layer than the lower layer part,
The manufacturing method of the display device which forms the terminal part containing a terminal electrode in the said lower layer part, and the conduction | electrical_connection hole from the said terminal part to the lower surface of the said lower layer part which is the back surface.
Aspect 16:
The display according to Aspect 15, for example, in which a conductor at least partially located in the conduction hole is provided, and the conductor is brought into contact with the terminal electrode and an electronic circuit board disposed below the lower layer portion. Device manufacturing method.
Aspect 17:
The manufacturing method of the display device of the aspect 14, for example which makes the said conduction | electrical_connection hole a forward taper shape.
Aspect 18:
The method for manufacturing a display device according to any one of embodiments 15 to 17, for example, wherein the conductor is a conductive binder.
Aspect 19
The method for manufacturing a display device according to aspect 18, for example, in which the conductor is filled in the conduction hole by pressure.
Aspect 20:
The method for producing a display device according to any one of embodiments 15 to 17, for example, in which the conductor is applied by an inkjet method.
Aspect 21:
21. The display device manufacturing method according to any one of embodiments 15 to 20, wherein a resin layer, a barrier layer, and a TFT layer including the terminal portion are formed on the upper side of the support.
Aspect 22:
The manufacturing method of the display device of the aspect 21, for example, which peels the said support body from the said resin layer, and affixes a lower surface film on the said resin layer.
Aspect 23:
The method for manufacturing a display device according to, for example, aspect 22, wherein a portion corresponding to the back surface of the terminal portion of the bottom film is removed.
Aspect 24:
A display device manufacturing apparatus comprising a lower layer part and a light emitting element layer formed in an upper layer than the lower layer part,
An apparatus for manufacturing a display device, wherein a terminal portion including a terminal electrode and a conduction hole extending from the terminal portion to the lower surface of the lower layer portion, which is the back surface, are formed in the lower layer portion.
　本発明は上述した実施形態に限定されるものではなく、異なる実施形態にそれぞれ開示された技術的手段を適宜組み合わせて得られる実施形態についても本発明の技術的範囲に含まれる。さらに、各実施形態にそれぞれ開示された技術的手段を組み合わせることにより、新しい技術的特徴を形成することができる。 The present invention is not limited to the above-described embodiments, and embodiments obtained by appropriately combining technical means disclosed in different embodiments are also included in the technical scope of the present invention. Furthermore, a new technical feature can be formed by combining the technical means disclosed in each embodiment.
　２　　表示デバイス
　４　　ＴＦＴ層
　５　　発光素子層
　６　　封止層
　７　　下層部
　１０　下面フィルム
　１２　樹脂層
　１６　無機絶縁膜
　１８　無機絶縁膜
　２０　無機絶縁膜
　２１　有機層間膜
　２４　ＥＬ層
　２６　第１無機封止膜
　２７　有機封止膜
　２８　第２無機封止膜
　４４　端子部
　５０　支持体
　５５　導電体
　６０　電子回路基板
　７０　表示デバイス製造装置
　８０　実装装置
　ＤＨ　導通ホール
　ＤＣ　導通部
　ＡＨ　圧着ヘッド
　ＴＭ　端子電極
 
 
 
  DESCRIPTION OF SYMBOLS 2 Display device 4 TFT layer 5 Light emitting element layer 6 Sealing layer 7 Lower layer part 10 Lower surface film 12 Resin layer 16 Inorganic insulating film 18 Inorganic insulating film 20 Inorganic insulating film 21 Organic interlayer film 24 EL layer 26 1st inorganic sealing film 27 Organic sealing film 28 Second inorganic sealing film 44 Terminal section 50 Support body 55 Conductor 60 Electronic circuit board 70 Display device manufacturing apparatus 80 Mounting apparatus DH conduction hole DC conduction section AH Pressure bonding head TM Terminal electrode


Claims (24)

  1. 　下層部と、前記下層部よりも上層に形成される発光素子層とを備え、
    　前記下層部には、端子電極を含む端子部と、前記端子部から、その裏面である前記下層部の下面に到る導通ホールとが形成されている表示デバイス。     A lower layer, and a light emitting element layer formed in an upper layer than the lower layer,
    A display device in which the lower layer portion includes a terminal portion including a terminal electrode, and a conduction hole extending from the terminal portion to the lower surface of the lower layer portion, which is the back surface thereof.
  2. 　少なくとも一部が前記導通ホール内に位置する導電体が設けられ、前記導電体は、前記端子電極と、前記下層部よりも下側に配された電子回路基板とに接触している請求項１記載の表示デバイス。 2. A conductor, at least a portion of which is located in the conduction hole, is provided, and the conductor is in contact with the terminal electrode and an electronic circuit board disposed below the lower layer portion. The indicated display device.
  3. 　前記端子電極は、前記導通ホールの内側壁に形成された導通部を含み、前記導電体は、前記導通部および前記電子回路基板に接触している請求項２記載の表示デバイス。 3. The display device according to claim 2, wherein the terminal electrode includes a conductive portion formed on an inner wall of the conductive hole, and the conductor is in contact with the conductive portion and the electronic circuit board.
  4. 　前記導通ホールと前記端子電極とが同一材料で形成され、
    　平面視において、前記導通ホールが、前記端子電極のエッジで囲まれている請求項１～３のいずれか１項に表示デバイス。     The conduction hole and the terminal electrode are formed of the same material,
    The display device according to any one of claims 1 to 3, wherein the conduction hole is surrounded by an edge of the terminal electrode in a plan view.
  5. 　前記下層部には、一端が前記端子電極に繋がり、前記端子電極と同一材料で形成された端子配線が設けられ、前記端子配線の配線幅は、前記配線幅と同方向に関する前記導通ホールのサイズよりも小さい請求項４に記載の表示デバイス。 The lower layer part is provided with a terminal wiring having one end connected to the terminal electrode and formed of the same material as the terminal electrode, and the wiring width of the terminal wiring is the size of the conduction hole in the same direction as the wiring width. The display device according to claim 4, which is smaller than the display device.
  6. 　前記導通ホールは、順テーパ形状である請求項１～５のいずれか１項に記載の表示デバイス。 The display device according to any one of claims 1 to 5, wherein the conduction hole has a forward tapered shape.
  7. 　前記導電体は、導電性バインダーである請求項２に記載の表示デバイス。 The display device according to claim 2, wherein the conductor is a conductive binder.
  8. 　前記導電体はインクジェット法で塗布可能な導電材を含む請求項２に記載の表示デバイス。 The display device according to claim 2, wherein the conductor includes a conductive material that can be applied by an inkjet method.
  9. 　前記下層部は、前記端子部が設けられたＴＦＴ層と、前記ＴＦＴ層の下層に形成されたバリア層と、前記バリア層の下層に形成された樹脂層とを含む請求項１～８のいずれか１項に記載の表示デバイス。 The lower layer portion includes a TFT layer provided with the terminal portion, a barrier layer formed under the TFT layer, and a resin layer formed under the barrier layer. The display device according to claim 1.
  10. 　前記導通ホールは、前記端子部から、前記バリア層および前記樹脂層を貫通して前記下層部の下面に到る請求項９に記載の表示デバイス。 The display device according to claim 9, wherein the conduction hole extends from the terminal portion to the lower surface of the lower layer portion through the barrier layer and the resin layer.
  11. 　前記樹脂層に接着された下面フィルムを含み、
    　前記端子部の裏面においては前記下面フィルムが除去されている請求項９または１０に記載の表示デバイス。     Including a bottom film bonded to the resin layer;
    The display device according to claim 9 or 10, wherein the bottom film is removed on a back surface of the terminal portion.
  12. 　前記端子電極は、前記ＴＦＴ層内のトランジスタの導通電極と同層に形成されている請求項９～１１のいずれか１項に記載の表示デバイス。 The display device according to any one of claims 9 to 11, wherein the terminal electrode is formed in the same layer as a conductive electrode of a transistor in the TFT layer.
  13. 　３辺以上を有する多角形状を有し、
    　複数の辺それぞれに対応して、前記端子部およびその裏面側に配された前記電子回路基板を備える請求項２に記載の表示デバイス。     Having a polygonal shape with three or more sides,
    The display device according to claim 2, further comprising the electronic circuit board disposed on the terminal portion and the back side thereof corresponding to each of a plurality of sides.
  14. 　前記表示デバイスのエッジの少なくとも一部が曲率を有する湾曲部であり、前記湾曲部に沿って前記端子部が形成されている請求項１～１３のいずれか１項に記載の表示デバイス。 The display device according to any one of claims 1 to 13, wherein at least a part of an edge of the display device is a curved portion having a curvature, and the terminal portion is formed along the curved portion.
  15. 　下層部と、前記下層部よりも上層に形成される発光素子層とを備える表示デバイスの製造方法であって、
    　前記下層部に、端子電極を含む端子部と、前記端子部から、その裏面である前記下層部の下面に到る導通ホールとを形成する表示デバイスの製造方法。     A manufacturing method of a display device comprising a lower layer part and a light emitting element layer formed in an upper layer than the lower layer part,
    The manufacturing method of the display device which forms the terminal part containing a terminal electrode in the said lower layer part, and the conduction | electrical_connection hole from the said terminal part to the lower surface of the said lower layer part which is the back surface.
  16. 　少なくとも一部が前記導通ホール内に位置する導電体を設け、前記導電体を、前記端子電極と、前記下層部よりも下側に配された電子回路基板とに接触させる請求項１５記載の表示デバイスの製造方法。 The display according to claim 15, wherein at least a part of the conductor is provided in the conduction hole, and the conductor is brought into contact with the terminal electrode and an electronic circuit board disposed below the lower layer portion. Device manufacturing method.
  17. 　前記導通ホールを、順テーパ形状とする請求項１４記載の表示デバイスの製造方法。 The display device manufacturing method according to claim 14, wherein the conduction hole has a forward tapered shape.
  18. 　前記導電体は、導電性バインダーである請求項１５～１７のいずれか１項に記載の表示デバイスの製造方法。 The method for manufacturing a display device according to any one of claims 15 to 17, wherein the conductor is a conductive binder.
  19. 　圧力によって前記導電体を前記導通ホール内に充填する請求項１８記載の表示デバイスの製造方法。 The method for manufacturing a display device according to claim 18, wherein the conductor is filled in the conduction hole by pressure.
  20. 　前記導電体をインクジェット法で塗布する請求項１５～１７のいずれか１項に記載の表示デバイスの製造方法。 The method for manufacturing a display device according to any one of claims 15 to 17, wherein the conductor is applied by an inkjet method.
  21. 　支持体の上側に、樹脂層と、バリア層と、前記端子部を含むＴＦＴ層とを形成する請求項１５～２０のいずれか１項に記載の表示デバイスの製造方法。 21. The method of manufacturing a display device according to claim 15, wherein a resin layer, a barrier layer, and a TFT layer including the terminal portion are formed on the support.
  22. 　前記支持体を前記樹脂層から剥離し、前記樹脂層に下面フィルムを貼り付ける請求項２１に記載の表示デバイスの製造方法。 The method for manufacturing a display device according to claim 21, wherein the support is peeled from the resin layer, and a bottom film is attached to the resin layer.
  23. 　前記下面フィルムの前記端子部の裏面にあたる部分を除去する請求項２２に記載の表示デバイスの製造方法。 The method for manufacturing a display device according to claim 22, wherein a portion corresponding to the back surface of the terminal portion of the bottom film is removed.
  24. 　下層部と、前記下層部よりも上層に形成される発光素子層とを備える表示デバイスの製造装置であって、
    　前記下層部に、端子電極を含む端子部と、前記端子部から、その裏面である前記下層部の下面に到る導通ホールとを形成する表示デバイスの製造装置。
     
     
     
     
     
     
     
     
     
          A display device manufacturing apparatus comprising a lower layer part and a light emitting element layer formed in an upper layer than the lower layer part,
    An apparatus for manufacturing a display device, wherein a terminal portion including a terminal electrode and a conduction hole extending from the terminal portion to the lower surface of the lower layer portion, which is the back surface, are formed in the lower layer portion.









PCT/JP2017/013355 2017-03-30 2017-03-30 Display device, method for manufacturing display device, and apparatus for manufacturing display device WO2018179265A1 (en)

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