WO2018179234A1 - Convertisseur en pont h et conditionneur d'énergie - Google Patents

Convertisseur en pont h et conditionneur d'énergie Download PDF

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Publication number
WO2018179234A1
WO2018179234A1 PCT/JP2017/013268 JP2017013268W WO2018179234A1 WO 2018179234 A1 WO2018179234 A1 WO 2018179234A1 JP 2017013268 W JP2017013268 W JP 2017013268W WO 2018179234 A1 WO2018179234 A1 WO 2018179234A1
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WIPO (PCT)
Prior art keywords
leg
phase
output
voltage
circuit
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PCT/JP2017/013268
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English (en)
Japanese (ja)
Inventor
洋一 森島
大輔 兒嶋
涼夫 齋藤
Original Assignee
株式会社 東芝
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Priority to PCT/JP2017/013268 priority Critical patent/WO2018179234A1/fr
Priority to JP2019508019A priority patent/JPWO2018179234A1/ja
Publication of WO2018179234A1 publication Critical patent/WO2018179234A1/fr

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration

Definitions

  • Embodiments of the present invention relate to an H-type bridge converter and a power conditioner using the H-type bridge converter.
  • PWM control is used to obtain an AC current waveform with a low current ripple. It is common.
  • the switching device constituting the positive arm or the negative arm cuts off the full load current at the switching frequency, the switching loss is increased and the apparatus may be increased in size.
  • one of the two legs of the H-type bridge converter is a high-frequency switching leg (hereinafter referred to as HF leg) that performs PWM control of the switching frequency f PWM , and the other is the output fundamental frequency f 0 .
  • HF leg high-frequency switching leg
  • LF leg low-frequency switching leg
  • switching devices specifically MOSFETs
  • switching devices specifically power transistors
  • the multiphase interleave method can be applied to a converter in which the input and output may be direct current or alternating current, and there is a proposal that adjusts the current balance. It is made.
  • a clear control method is not necessarily proposed for current balance control in the interleave method of the H-type bridge converter, for example, current balance control when operating the power conditioner with output voltage control.
  • An object of the present invention is to provide an H-type bridge converter and a power conditioner using the H-type bridge converter that can be easily realized as hardware.
  • the H-bridge converter includes an HF leg in which a plurality of sub-legs including a pair of switching devices connected in series between a DC positive voltage bus and a DC negative voltage bus are connected in parallel; and the DC positive voltage A pair of switching devices are connected in series between the bus and the DC negative voltage bus, and are electrically connected to the LF leg connected in parallel to the HF leg and each of the pair of switching devices.
  • the HF leg is controlled based on a multiphase interleaving method in which conduction phases of the plurality of AC output terminals and the plurality of sub-leg switching devices are shifted, and the output is switched every half cycle of the output fundamental frequency. And a control circuit for controlling the LF leg.
  • FIG. 1 is a block diagram illustrating a configuration example of an H-type bridge converter and a power conditioner according to the first embodiment.
  • FIG. 2 is a diagram showing an example of a voltage reference to be generated by the H-bridge converter shown in FIG.
  • FIG. 3 is a diagram showing a configuration example of a control circuit that performs voltage control of the H-bridge converter according to the voltage reference shown in FIG.
  • FIG. 4 is a waveform diagram for schematically explaining an example of an operation in which the HF leg of the H-type bridge converter performs PWM control to generate a gate signal in the control circuit of FIG.
  • FIG. 5 is a block diagram illustrating a configuration example of the H-type bridge converter and the power conditioner according to the second embodiment.
  • FIG. 6 is a block diagram illustrating a configuration example of the control circuit of the power conditioner according to the second embodiment.
  • FIG. 7 is a diagram illustrating a configuration example of a PCS current control circuit that performs current control in the control circuit of the power conditioner illustrated in FIG. 6.
  • FIG. 1 is a block diagram illustrating a configuration example of an H-type bridge converter and a power conditioner according to the first embodiment.
  • the power conditioner of this embodiment is a power conditioner connected between the DC power source 11 and the single-phase AC system 12, and includes an LF leg 15, an HF leg 13, reactors L1, L2, and L3, and a control. Circuit CTR.
  • the H-type bridge converter of this embodiment includes an LF leg 15, an HF leg 13, and a control circuit CTR.
  • the power conditioner of the present embodiment is configured to generate a line voltage v 0 to be supplied to the single-phase AC system 12, and the line voltage v 0 is obtained from the phase voltage v h of the HF leg 13 to the phase of the LF leg 15. is a value obtained by subtracting the voltage v L.
  • the phase voltage v h and the phase voltage v L are potentials based on the intermediate voltage point O of the DC power supply 11.
  • the HF leg 13 includes a plurality of sub-legs connected in parallel and AC output terminals H1 to H3, and includes a pair of switching devices in which each of the plurality of sub-legs is connected in series. In each of the plurality of sub-legs of the HF leg 13, the pair of switching devices and the AC output terminals H1 to H3 are electrically connected.
  • the LF leg 15 includes a pair of switching devices connected in series and an AC output terminal L0, and is connected to the HF leg 13 in parallel. The pair of switching devices of the LF leg 15 and the AC output terminal L0 are electrically connected.
  • the HF leg 13 is a K-phase interleave circuit that performs PWM control at, for example, the switching frequency f PWM .
  • the switching frequency f PWM is, for example, 13333 Hz (1/3 of 40 kHz).
  • the HF leg 13 includes a first subleg, a second subleg, and a third subleg. The first subleg, the second subleg, and the third subleg are connected in parallel to each other.
  • the first subleg includes an upper arm and a lower arm connected in series with each other.
  • the upper arm includes a switching device 131 connected between the DC positive voltage bus P and the AC output terminal H1, and an antiparallel diode 131a.
  • the lower arm includes a switching device 132 connected between the AC output terminal H1 and the DC negative voltage bus N, and an antiparallel diode 132a.
  • the second subleg has an upper arm and a lower arm connected in series with each other.
  • the upper arm includes a switching device 133 connected between the DC positive voltage bus P and the AC output terminal H2, and an antiparallel diode 133a.
  • the lower arm includes a switching device 134 connected between the AC output terminal H2 and the DC negative voltage bus N, and an antiparallel diode 134a.
  • the third subleg has an upper arm and a lower arm connected in series with each other.
  • the upper arm includes a switching device 135 connected between the DC positive voltage bus P and the AC output terminal H3, and an antiparallel diode 135a.
  • the lower arm includes a switching device 136 connected between the AC output terminal H3 and the DC negative voltage bus N, and an antiparallel diode 136a.
  • the AC output terminal H1 connected to the first subleg is electrically connected to the AC terminal H0 via the reactor L1.
  • the AC output terminal H2 connected to the second sub-leg is electrically connected to the AC terminal H0 via the reactor L2.
  • the AC output terminal H3 connected to the third subleg is electrically connected to the AC terminal H0 via the reactor L3.
  • AC terminal H ⁇ b> 0 is electrically connected to one terminal of single-phase AC system 12.
  • an alternating current output from the AC output terminals H1 and i 1 the alternating current output from the AC output terminal H2 and i 2
  • an alternating current output from the AC output terminal H3 i 3 and then, the AC current output from the AC terminal H0 to single phase AC system 12 and the i 0.
  • the alternating current i 0 is the sum of the alternating currents i 1 , i 2 , i 3 .
  • the LF leg 15 is for operating to switch the output every half cycle of the output fundamental frequency f 0, and a upper arm and the lower arm connected in series with each other.
  • the fundamental frequency f 0 is, for example, 50 Hz.
  • the upper arm includes a switching device 151 that is connected between the direct current positive voltage bus P and the alternating current output terminal L0 and incorporates an antiparallel diode.
  • the lower arm includes a switching device 152 that is connected between the AC output terminal L0 and the DC negative voltage bus N and incorporates an antiparallel diode.
  • the AC output terminal L0 is electrically connected to one terminal of the single-phase AC system 12.
  • the reactor L1, the reactor L2, and the reactor L3 are described as separate circuit elements, but the three reactors are magnetically coupled to increase the operating frequency as one reactor having three windings.
  • control method for the H-bridge converter of the power conditioner there are a method of controlling a single-phase AC voltage as an output voltage to a sine wave (voltage control method), and an AC current flowing through a single-phase AC system as an output current And a method for controlling the current to a sine wave (current control method).
  • the voltage control method of the H-bridge converter will be described with reference to the drawings. Although only the voltage control method will be described in the present embodiment, the present invention is not limited to this, and it is not excluded to control the H-bridge converter of the present embodiment by the current control method. .
  • FIG. 2 is a diagram showing an example of a voltage reference to be generated by the H-bridge converter shown in FIG.
  • the single-phase AC voltage reference v 0 * the voltage reference v H * of the HF leg 13, and the voltage reference v L * of the LF leg 15 are shown.
  • the voltage reference v H * to be generated in the HF leg 13 is a voltage obtained by viewing the AC output terminals H1, H2, and H3 of the HF leg 13 with reference to the intermediate voltage point O of the DC power supply 11, and the HF leg phase voltage and It is called voltage.
  • the voltage reference v L * to be generated in the LF leg 15 indicates a voltage when the AC output terminal L0 of the LF leg 15 is viewed with reference to the intermediate voltage point O of the DC power supply 11, and is a voltage called an LF leg phase voltage. .
  • the HF leg 13 generates the actual voltage v H corresponding to the voltage reference v H * by PWM control, and the LF leg 15 corresponds to the one-pulse actual voltage corresponding to the rectangular wave voltage reference v L *. v L and thus the may be generated.
  • FIG. 3 is a diagram showing a configuration example of a control circuit that performs voltage control of the H-bridge converter according to the voltage reference shown in FIG.
  • the control circuit CTR includes a line voltage reference generation circuit 21, an HF leg phase voltage reference generation circuit 22, an LF leg phase voltage reference generation circuit 23, a 120 ° phase difference triangular wave carrier wave generation circuit 24, and a PWM waveform generation circuit 251.
  • 252, 253, negation circuits 261, 262, 263, phase average current difference detection circuits 271, 272, current detectors 281, 282, 283 (shown in FIG. 1), subtracters 291, 292, current Control circuits 301 and 302, adders 311 and 312, and a negation circuit 32 are provided.
  • a sine wave line voltage reference v 0 * is generated.
  • the HF leg phase voltage reference generation circuit 22 receives the line voltage reference v 0 * from the line voltage reference generation circuit 21 and generates the HF leg phase voltage reference v H * .
  • the LF leg phase voltage reference generation circuit 23 receives the line voltage reference v 0 * from the line voltage reference generation circuit 21 and generates the LF leg phase voltage reference v L * .
  • the LF leg phase voltage reference v L * is output as the positive voltage bus potential (+ E / 2) or the negative voltage bus potential (-E / 2) of the DC voltage E. If the DC voltage E is determined, the actual voltage v L is determined. Therefore, in the LF leg phase voltage reference generation circuit 23, the amplitude of the LF leg phase voltage reference v L * is a waveform that is originally determined by the DC voltage E. On the other hand, the HF leg phase voltage reference generation circuit 22 calculates a waveform that changes the amplitude of the HF leg phase voltage reference v H * in accordance with the change in the amplitude of the line voltage reference v 0 * .
  • the phase voltage reference v H1 * in the first sub-leg of the HF leg 13 is equal to the HF leg phase voltage reference v H * .
  • the PWM waveform generation circuit 251 receives the phase voltage reference v H1 * in the first subleg as a modulation wave, and receives the carrier voltage v T1 in the first subleg from the 120 ° phase difference triangular wave carrier generation circuit 24.
  • the gate signals G Q11 and G Q12 to be supplied to the upper arm switching device 131 and the lower arm switching device 132 are generated.
  • the output signal of the PWM waveform generation circuit 251 is a gate signal GQ11 to be given to the switching device 131.
  • the output signal of the PWM waveform generation circuit 251 becomes a gate signal GQ12 to be supplied to the switching device 132 via the negation circuit 261. Therefore, the gate signal GQ11 and the gate signal GQ12 have waveforms inverted from each other.
  • FIG. 4 is a waveform diagram for schematically explaining an example of an operation in which the HF leg of the H-type bridge converter performs PWM control to generate a gate signal in the control circuit of FIG.
  • the 120 ° phase difference triangular wave carrier wave generation circuit 24 generates a carrier voltage v T1 in the first sub-leg, a carrier voltage v T2 in the second sub-leg, and a carrier voltage v T3 in the third sub-leg.
  • the carrier is a continuous triangular wave PWM control frequency f PWM.
  • the bold line indicates the carrier voltage v T1 in the first sub-leg
  • the thin line indicates the carrier voltage v T2 in the second sub-leg
  • the broken line indicates the carrier voltage v T3 in the third sub-leg.
  • the HF leg since the HF leg includes three sub-legs, the triangular waves (carrier wave voltages) v T1 , v T2 , and v T3 have a phase difference of 120 ° from each other, but the triangular wave (carrier wave voltage) And the phase difference thereof are appropriately changed according to the number of sub-legs.
  • FIG. 4 shows the phase voltage reference v H1 * and the carrier voltage v T1 , the gate signal G Q11 applied to the upper arm switching device 131 of the first sub-leg of the HF leg, and the gate signal applied to the lower arm switching device 132.
  • GQ12 An example with GQ12 is shown.
  • the PWM waveform generation circuit 251 compares the phase voltage reference v H1 * and the carrier voltage v T1 in the first subleg, generates a gate signal G Q11 based on the comparison result, and outputs it. That is, the gate signal GQ11 supplied to the switching device 131 is turned on during the phase voltage reference v H1 * > carrier voltage v T1 and turned off during the phase voltage reference v H1 * ⁇ carrier voltage v T1 .
  • the gate signal GQ21 given to the switching device 132 is a signal obtained by inverting the gate signal GQ11 , and is turned on in the period of the phase voltage reference v H1 * ⁇ carrier voltage v T1 and the phase voltage reference v H1 * > carrier. It turned off for a period of voltage v T1.
  • the PWM waveform generation circuit 252 receives the phase voltage reference v H2 * of the second sub-leg as a modulation wave, and has a phase of 120 ° with respect to the carrier voltage v T1 in the first sub-leg from the 120 ° phase difference triangular wave carrier generation circuit 24.
  • the second sub-leg carrier voltage v T2 is received.
  • the PWM waveform generation circuit 252 and the NOT circuit 262 generates and outputs the gate signal G Q22 when applied to the gate signal G Q12 and the switching device 134 of the lower arm to be given to switching device 133 of the upper arm of second Saburegu.
  • the PWM waveform generation circuit 253 receives the phase voltage reference v H3 * of the third sub-leg as a modulation wave, and is phased by 120 ° with respect to the carrier voltage v T2 in the second sub-leg from the 120 ° phase difference triangular wave carrier generation circuit 24.
  • the carrier voltage v T3 of the third sub-leg delayed is received.
  • the PWM waveform generation circuit 253 and the negation circuit 263 generate and output a gate signal G Q13 to be supplied to the switching device 135 of the upper arm of the third subleg and a gate signal G Q23 to be supplied to the switching device 136 of the lower arm.
  • the instantaneous alternating currents i 1 , i 2 , i 3 of the first sub-leg, the second sub-leg, and the third sub-leg are expressed as current waveforms having ripples that increase / decrease at the frequency f PWM.
  • the pulse of the gate signal applied to the switching devices of the first sub-leg, the second sub-leg, and the third sub-leg has a conduction phase of 120 ° because the carrier voltages v T1 , v T2 , and v T3 are shifted by 120 °. It's off.
  • the instantaneous alternating current i 0 obtained by adding the instantaneous alternating currents i 1 , i 2 , and i 3 becomes a current waveform having a ripple that increases and decreases at a PWM frequency (3 ⁇ f PWM ) that is three times the frequency.
  • the switching frequency can be tripled.
  • the inverter is reduced in size by balancing the average alternating currents i 1AVE , i 2AVE , and i 3AVE by control.
  • the phase average current difference detection circuits 271 and 272 receive the instantaneous alternating currents i 1 , i 2 , and i 3 , calculate the difference between the output alternating current of each phase and the three-phase current average value, and output it.
  • the average current difference detection circuit 272 receives the instantaneous alternating currents i 1 , i 2 , i 3 detected by the current detectors 281, 282, 283, and receives the average alternating current i 1AVE of the first subleg and the second subleg.
  • I mean and alternating current i 2AVE of mean and alternating current i 3AVE third Saburegu, by using the sum i 0AVE average alternating current ( i 1AVE + i 2AVE + i 3AVE), the average AC current i 2AVE second Saburegu
  • the subtractor 291 subtracts the reference value from the current difference ⁇ i 1AVE output from the average current difference detection circuit 271 and outputs the result. In this embodiment, the reference value is zero.
  • the subtractor 292 subtracts the reference value from the current difference ⁇ i 2AVE output from the average current difference detection circuit 272 and outputs the result. In this embodiment, the reference value is zero.
  • the current control circuit 301 is a control circuit including at least an integration element, and amplifies the value output from the subtractor 291 to generate and output the phase voltage reference correction signal v Had1 * in the first subleg.
  • the current control circuit 302 is a control circuit including at least an integration element, and amplifies the value output from the subtractor 292 to generate and output the phase voltage reference correction signal v Had2 * in the second subleg.
  • the current control circuits 301 and 302 perform proportional integral (PI) control.
  • the adder 311 adds the phase voltage reference correction signal v Had1 * and the HF leg phase voltage reference v H *, and outputs the result as the phase voltage reference v H1 * of the first subleg.
  • the adder 312 adds the phase voltage reference correction signal v Had2 * and the HF leg phase voltage reference v H *, and outputs the result as the phase voltage reference v H2 * of the second sub-leg.
  • the HF leg 13 of this embodiment is a three-phase interleave system
  • the current balance of the third phase can be obtained by controlling the current balance of two of the three phases. Therefore, for the third sub-leg, it is not necessary to correct the HF leg phase voltage reference v H * by the correction signal in the same way as the first leg and the second leg, and the phase voltage reference in the third sub-leg is the HF leg. Use phase voltage reference v H * .
  • the LF leg phase voltage reference generation circuit 23 receives the line voltage reference v 0 * generated by the line voltage reference generation circuit 21 and generates an LF leg phase voltage reference v L * .
  • the LF leg voltage reference v L * is output by switching the potentials of the DC positive voltage bus and the DC negative voltage bus according to the frequency f 0 of the single-phase AC system. That is, the LF leg phase voltage reference generation circuit 23 only needs to generate one pulse of the actual voltage v L , and the LF leg voltage reference v L * is a rectangular wave signal.
  • the LF leg voltage reference v L * output from the LF leg phase voltage reference generation circuit 23 is a gate signal G Q3 provided to the switching device 153.
  • the negation circuit 32 inverts the LF leg voltage reference v L * and outputs a gate signal G Q4 to be supplied to the switching device 152. That is, when the LF leg voltage reference v L * is ⁇ E / 2, the switching device 152 is turned on.
  • the LF leg 15 is switched at the same PWM frequency as the switching frequency of normal PWM control, an equivalent switching in an AC current waveform is performed.
  • the frequency is 1.5 times, and the ripple can be further reduced, leading to improvement of the waveform near the zero cross of the AC waveform, especially total harmonic distortion (THD) or electromagnetic interference (EMI). Can be reduced.
  • TDD total harmonic distortion
  • EMI electromagnetic interference
  • the HF leg 13 includes three-phase sub-legs, and an IGBT (Insulated Gate-Bipolar-Transistor) having a current capacity of 1/3 is used as the switching devices 131, 132, 133, 134, 135, 136 constituting the sub-legs. Can do.
  • IGBT Insulated Gate-Bipolar-Transistor
  • the interleaving method is applied to the HF leg 13, so that the ratio of switching loss is relatively reduced by reducing the switching frequency to 1/3 of the necessary frequency, and the characteristic of low conduction loss is achieved.
  • the IGBT that is also included. Note that the six IGBTs used in the HF leg 13 may be configured as one package.
  • the LF leg 15 has one leg including switching devices 151 and 152 connected in series.
  • the switching devices 151 and 152 are MOSFETs (Metal-Oxide-Semiconductor-Field-Effect-Transistors) or Super- Junction MOSFETs can be used.
  • the present embodiment when an alternating current waveform having the same current ripple is obtained, the power conversion efficiency is improved, the size is small, and the main circuit and the control circuit can be easily realized as hardware. It is possible to provide an H-type bridge converter and a power conditioner using the H-type bridge converter.
  • FIG. 5 is a block diagram illustrating a configuration example of an H-type bridge converter according to the second embodiment and a power conditioner using the H-type bridge converter.
  • a power conditioner including the H-bridge converter of the first embodiment will be described below with reference to the drawings.
  • the same components as those in the first embodiment described above are denoted by the same reference numerals and description thereof is omitted.
  • the power conditioner of the present embodiment is configured such that the power conditioner of the first embodiment described above is connected to the single-phase AC system 12 so that single-phase AC system interconnection operation is possible.
  • the power conditioner of the present embodiment switches the connection from the single-phase AC system 12 to the AC load 41 when a power failure occurs in the single-phase AC system 12 and supplies the AC load 41 with power.
  • the power supply operation (generally called self-sustained operation) is configured to be possible.
  • the first subleg is electrically connected to the AC terminal H0 via the reactor L1
  • the second subleg is electrically connected to the AC terminal H0 via the reactor L2
  • the third subleg is connected to the AC terminal H0 via the reactor L3. And is electrically connected.
  • the first subleg, the second subleg, and the third subleg are connected in parallel to the AC terminal H0.
  • the AC terminal H0 When performing the single-phase AC system interconnection operation, the AC terminal H0 is connected to one terminal of the single-phase AC system 12 on the a side of the switching circuit 421. At this time, when a power failure or the like occurs in the single-phase AC system 12, the switching circuit 421 is switched from the a side to the b side, and the AC terminal H0 is connected to one terminal of the AC load 41.
  • FIG. 6 is a block diagram illustrating a configuration example of the control circuit of the power conditioner according to the second embodiment.
  • the control circuit CTR switches the output current control so as to perform the output voltage control during the single-phase AC grid connection operation and performs the output voltage control during the AC load power supply operation, thereby controlling the H-type bridge converter.
  • the control circuit CTR includes a single-phase AC grid connection operation command circuit 43, a PCS current control circuit 44, a switching circuit a side input command circuit 45, an AC load power supply operation command circuit 46, and a PCS voltage control circuit 47. , A switching circuit b-side input command circuit 48, switches 431 and 432, and a switching circuit 421 (shown in FIG. 5) and 422.
  • the single-phase AC system interconnection operation command circuit 43 determines, for example, whether or not the single-phase AC system 12 is normal (or receives a signal indicating that the single-phase AC system 12 is normal) from the outside. When the AC system 12 is normal, the single-phase AC system interconnection operation signal SGC is output.
  • the AC load power supply operation command circuit 46 determines, for example, whether the single-phase AC system 12 is normal (or receives a signal indicating that the single-phase AC system 12 is normal) from the outside, and When the AC system 12 is normal, the AC load power supply operation command circuit 46 does not output the AC load power supply operation signal SLC .
  • the switch 431 is turned on by a single-phase AC grid interconnection operation signal SGC .
  • PCS current control circuit 44, the single-phase AC system interconnection operation command circuit 43 receives single-phase AC system interconnection operation signal S GC to perform output current control.
  • the PCS current control circuit 44 gives an output current command value I 0 * for commanding the magnitude of the AC current from the outside via the switch 431 input by the single-phase AC grid connection operation signal S GC . It is done. Further, the PCS current control circuit 44 includes the voltage v 0 of the single-phase AC system 12 detected by the voltage detector 53, the first subleg, the second subleg, and the third subleg detected by the current detectors 281, 282, and 283. Gate currents G Q11 , G Q12 , G Q13 , G Q21 , G Q22 , G Q23 , G Q13 , G Q3 , G Q4 of the current alternating currents i 1 , i 2 , i 3. Is generated and output.
  • gate signals G Q11 , G Q12 , G Q13 , G Q21 , G Q22 , G Q23 , G Q13 , G Q3 , G Q4 are connected to the switching devices 131, 133, 135, via the a side of the switching circuit 422. 132, 134, 136, 151, 152.
  • the operation in which the PCS current control circuit 44 performs output current control will be described in detail later with reference to FIG.
  • Switching circuit a side closing command circuit 45 the single-phase AC system interconnection operation command circuit 43 receives a single-phase AC system interconnection operation signal S GC, the switching circuit of the switching circuit 421 and the control circuit of the main circuit 422 In response to this, a command is output to switch to the a side.
  • the gate signal G Q11 output from the PCS current control circuit 44, G Q12, G Q13, G Q21, G Q22, G Q23, G Q13, G Q3, G Q4 is, the control circuit CTR Are output to the switching devices 31, 133, 135, 132, 134, 136, 151, and 152.
  • the single-phase AC system interconnection operation command circuit 43 determines, for example, whether the single-phase AC system 12 is normal (or receives a signal indicating that the single-phase AC system 12 is normal) from the outside. When an abnormality such as a power failure occurs in the single-phase AC system 12, the single-phase AC system interconnection operation command circuit 43 does not output the single-phase AC system interconnection operation signal SGC .
  • the AC load power supply operation command circuit 46 determines, for example, whether the single-phase AC system 12 is normal (or receives a signal indicating that the single-phase AC system 12 is normal) from the outside, and When an abnormality such as a power failure occurs in the AC system 12 (when it is not normal), the AC load power supply operation command circuit 46 outputs an AC load power supply operation signal SLC .
  • the switch 432 is turned on by an AC load power supply operation signal SLC .
  • PCS voltage control circuit 47 receives the AC load power supply operation signals S LC from the AC load power supply operation command circuit 46 performs output voltage control.
  • the PCS voltage control circuit 47 is given an output voltage command value V 0 * for commanding the magnitude of the AC voltage from the outside via the switch 432 input by the AC load power supply operation signal S LC . Further, the PCS voltage control circuit 47 receives the AC currents i 1 , i 2 , and i 3 of the first subleg, the second subleg, and the third subleg detected by the current detectors 281, 282, and 283, and performs voltage control. the gate signal G Q11 of the results, G Q12, G Q13, G Q21, G Q22, G Q23, G Q13, G Q3, to generate a G Q4 output.
  • gate signals G Q11 , G Q12 , G Q13 , G Q21 , G Q22 , G Q23 , G Q13 , G Q3 , G Q4 are connected to the switching devices 131, 133, 135, via the b side of the switching circuit 422. 132, 134, 136, 151, 152.
  • the operation of the PCS voltage control circuit 47 is the same as that of the control circuit CTR of the first embodiment described above, and thus the description thereof is omitted in this embodiment.
  • Switching circuit b side closing command circuit 48 receives the AC load power supply operation signals S LC from the AC load power supply operation command circuit 46 for the switching circuit 422 of the switching circuit 421 and the control circuit of the main circuit, b-side Command to switch to.
  • PCS voltage control circuit 47 a gate signal G Q11 output from, G Q12, G Q13, G Q21, G Q22, G Q23, G Q13, G Q3, G Q4 is, the control circuit CTR Are output to the switching devices 31, 133, 135, 132, 134, 136, 151, and 152.
  • FIG. 7 is a diagram illustrating a configuration example of a PCS current control circuit that performs current control in the control circuit of the power conditioner illustrated in FIG. 6.
  • the PCS current control circuit 44 includes a 1/3 multiplier 51, a multiplier 52, a line voltage peak value detection circuit 54, a divider 55, subtracters 561, 562, and 563, and current control circuits 571 and 572. 573, positive / negative polarity discrimination circuit 58, 120 ° phase difference triangular wave carrier wave generation circuit 24, PWM waveform generation circuits 251, 252, 253, and negation circuits 261, 262, 263.
  • the 1/3 multiplier 51 receives an output current command value I 0 * for commanding the magnitude of the AC current from the outside, and outputs the AC current magnitude command value I 0 * / 3.
  • the multiplier 52 receives and multiplies the AC current magnitude command value I 0 * / 3 and the output signal v 0 / V 0 of the divider 55 (power factor 1, sine wave of magnitude 1). To obtain and output current references i 1 * , i 2 * , i 3 * of each sub-leg of the three-phase interleave.
  • the line voltage peak value detection circuit 54 receives the voltage v 0 of the single-phase AC system 12 detected by the voltage detector 53 shown in FIG. 5, obtains the AC voltage peak value V 0 from the voltage v 0 and outputs it.
  • Divider 55 receives the voltages v 0 and AC voltage peak value V 0, and outputs the operation signal v 0 / V 0 to the multiplier 52 and the positive and negative determination circuit 58. That is, the signal v 0 / V 0 is a sine wave having a power factor of 1 and a magnitude of 1 input to the multiplier 52.
  • the subtractor 561 subtracts the actual current i 1 detected by the current detector 281 from the current reference i 1 * and outputs the result to the current control circuit 571.
  • the subtractor 562 subtracts the actual current i 2 detected by the current detector 282 from the current reference i 2 * and outputs the result to the current control circuit 572.
  • the subtractor 563 subtracts the actual current i 3 detected by the current detector 283 from the current reference i 3 * and outputs the result to the current control circuit 573.
  • the current control circuit 571 includes at least an integration element, performs an amplification operation so that the value input from the subtractor 561 becomes zero, and generates and outputs the phase voltage reference v H1 * in the first subleg. In the present embodiment, the current control circuit 571 performs proportional-integral control.
  • the current control circuit 572 includes at least an integration element, performs an amplification operation so that the value input from the subtractor 562 becomes zero, and generates and outputs the phase voltage reference v H2 * in the second subleg. In the present embodiment, the current control circuit 572 performs proportional-integral control.
  • the current control circuit 573 includes at least an integration element, performs an amplification operation so that the value input from the subtractor 563 becomes zero, and generates and outputs the phase voltage reference v H3 * in the third subleg. In the present embodiment, the current control circuit 573 performs proportional-integral control.
  • the 120 ° phase difference triangular wave carrier wave generation circuit 24, the PWM waveform generation circuits 251, 252, and 253, and the negation circuits 261, 262, and 263 are the same as those described in the first embodiment.
  • the 120 ° phase difference triangular wave carrier wave generation circuit 24 generates the carrier voltage v T1 in the first sub-leg, the carrier voltage v T2 in the second sub-leg, and the carrier voltage v T3 in the third sub-leg.
  • the carrier is a continuous triangular wave PWM control frequency f PWM.
  • the PWM waveform generation circuit 251 receives the phase voltage reference v H1 * as a modulation wave, and outputs a gate signal G Q11 to be supplied to the switching device 131 to the switching device 131 and the negation circuit 261.
  • NOT circuit 261 inverts the gate signal G Q11, and generates and outputs a gate signal G Q21 to be supplied to the switching device 132.
  • the PWM waveform generation circuit 252 receives the phase voltage reference v H2 * as a modulation wave, and outputs a gate signal G Q12 to be supplied to the switching device 133 to the switching device 133 and the negative circuit 262.
  • NOT circuit 262 inverts the gate signal G Q12, and generates and outputs a gate signal G Q22 to be supplied to the switching device 134.
  • the PWM waveform generation circuit 253 receives the phase voltage reference v H3 * as a modulation wave, and outputs a gate signal G Q13 to be supplied to the switching device 135 to the switching device 135 and the negation circuit 263.
  • the negation circuit 263 inverts the gate signal G Q13 to generate and output a gate signal G Q23 to be supplied to the switching device 136.
  • the phase of the output signal v 0 / V 0 of the divider 55 is an AC voltage phase, it can be used to control the LF leg 15 as in the case of output voltage control.
  • the potential of the DC positive voltage bus and the DC negative voltage bus may be switched and output in accordance with the frequency f 0 of the single-phase AC system.
  • LF leg-phase voltage reference generation circuit of the control circuit CTR shown in FIG. 3 23 is for generating and outputting a LF leg-phase voltage reference v L * and receive line voltage reference v 0 *.
  • the positive / negative polarity discrimination circuit 58 receives the signal v 0 / V 0 , generates a one-pulse rectangular wave signal (gate signal G Q4 ), and outputs it to the switching device 152 and the negative circuit 32. To do.
  • NOT circuit 32 receives the gate signal G Q4 output from a polarity discriminating circuit 58, and outputs a gate signal G Q3 obtained by inverting the value.
  • the switching device 152 is turned on by the gate signal G Q4 and the switching device 151 is turned off by the gate signal G Q3 .
  • the switching device 152 is turned off by the gate signal G Q4 and the switching device 151 is turned on by the gate signal G Q3 .
  • the types of switching devices that can be used for the H-type bridge converter are the same as those in the first embodiment.
  • the power conversion efficiency is improved, the size is small, and the main circuit and the control circuit can be easily realized as hardware.
  • An H-type bridge converter and a power conditioner can be provided.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)

Abstract

La présente invention concerne, selon un mode de réalisation, un convertisseur en pont H comprenant : un pied HF 13 ayant une pluralité de segments de pied connectés en parallèle, lesdits segments de pied comprenant chacun une paire de dispositifs de commutation connectés en série entre une ligne de bus de tension positive continue P et une ligne de bus de tension négative continue N ; un segment de pied LF 15 connecté en parallèle au pied HF 13 et ayant une paire de dispositifs de commutation connectés en série entre la ligne de bus de tension positive continue P et la ligne de bus de tension négative continue N ; une pluralité de bornes de sortie CA H1-H3, L0 connectées électriquement entre les paires de dispositifs de commutation, respectivement ; et un circuit de commande CTR commandant le pied HF 13 sur la base d'un procédé d'entrelacement multiphase dans lequel les phases conductrices des dispositifs de commutation des segments de pied décalées les uns par rapport aux autres et commandant le pied LF 15 pour commuter la sortie chaque demi-cycle d'une fréquence fondamentale de sortie f0.
PCT/JP2017/013268 2017-03-30 2017-03-30 Convertisseur en pont h et conditionneur d'énergie WO2018179234A1 (fr)

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JP2019508019A JPWO2018179234A1 (ja) 2017-03-30 2017-03-30 Ｈ型ブリッジ変換器およびパワーコンディショナ

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CN113411005A (zh) * 2020-03-16 2021-09-17 西门子交通有限公司 车辆、特别是轨道车辆

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