WO2018171790A1 - 一种数据传输方法及相关设备 - Google Patents

一种数据传输方法及相关设备 Download PDF

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WO2018171790A1
WO2018171790A1 PCT/CN2018/080394 CN2018080394W WO2018171790A1 WO 2018171790 A1 WO2018171790 A1 WO 2018171790A1 CN 2018080394 W CN2018080394 W CN 2018080394W WO 2018171790 A1 WO2018171790 A1 WO 2018171790A1
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length
sub
code length
bit sequence
segments
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PCT/CN2018/080394
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English (en)
French (fr)
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徐晨
李榕
张公正
周悦
黄凌晨
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华为技术有限公司
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Priority to EP21177059.9A priority Critical patent/EP3934138B1/en
Priority to BR112019019532-7A priority patent/BR112019019532B1/pt
Priority to EP18770517.3A priority patent/EP3598673B1/en
Priority to JP2019552518A priority patent/JP6986091B2/ja
Publication of WO2018171790A1 publication Critical patent/WO2018171790A1/zh
Priority to US16/579,867 priority patent/US10637609B2/en
Priority to US16/817,626 priority patent/US11251903B2/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H04L1/0043—Realisations of complexity reduction techniques, e.g. use of look-up tables
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/618—Shortening and extension of codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/635—Error control coding in combination with rate matching
    • H03M13/6356—Error control coding in combination with rate matching by repetition or insertion of dummy data, i.e. rate reduction
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/635—Error control coding in combination with rate matching
    • H03M13/6362—Error control coding in combination with rate matching by puncturing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0054—Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0064—Concatenated codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0067—Rate matching
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0067—Rate matching
    • H04L1/0068—Rate matching by puncturing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0067—Rate matching
    • H04L1/0068—Rate matching by puncturing
    • H04L1/0069—Puncturing patterns
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/3769—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35 using symbol combining, e.g. Chase combining of symbols received twice or more

Definitions

  • Embodiments of the present invention relate to the field of communications, and more particularly, to a Ploar encoding method and encoding apparatus, decoding method, and decoding apparatus.
  • Polar codes proposed by Turkish professor Arikan are the first good code to theoretically prove that Shannon capacity can be achieved with low coding complexity.
  • the Polar code is a linear block code whose coding matrix is G N and the encoding process is among them Is a binary line vector with a length of N (ie, the length of the mother code); G N is an N ⁇ N matrix, and Defined as the Kronecker product of log 2 N matrices F 2 .
  • the encoding process of the Polar code is equivalent to:
  • G N. (A) is a sub-matrix obtained from those rows corresponding to the index in the set A in G N.
  • G N (A C ) is obtained from the rows corresponding to the indexes in the set A C in G N .
  • the construction process of the Polar code is a collection
  • the selection process determines the performance of the Polar code.
  • the construction process of the Polar code is generally: determining that there are N polarized channels in total according to the length N of the mother code, respectively corresponding to N rows of the coding matrix, calculating the reliability of the polarized channel, and the first K polarizations with higher reliability.
  • the index of the channel is the element of set A, and the index corresponding to the remaining (NK) polarized channels is used as the index set of fixed bits.
  • Set A determines the position of the information bits, the set The position of the fixed bit is determined.
  • the original Polar code (parent code) has a code length of 2, which is an integer power of 2, and in practice, a Polar code of arbitrary code length needs to be implemented by rate matching.
  • Rate matching schemes for Polar codes, namely, Punchture Shortening and Repetition.
  • the first two schemes determining that the mother code length is greater than or equal to the integer power of 2 of the target code length M, determining the punching or shortening the position according to a preset rule, and deleting the coded bits of the corresponding position during transmission to achieve rate matching.
  • the log likelihood ratio LLR of the corresponding position is restored according to a predetermined rule to implement de-rate matching.
  • a repeated rate matching scheme may be determined in the communication system according to agreed rules.
  • the Polar code encoded with the mother code length is repeated to obtain a target code length greater than the length of the mother code, thereby realizing rate matching of the Polar code.
  • the repetition is achieved by repeatedly transmitting the encoded bit sequence encoded as the length of the mother code in a specific order until the target code length is reached.
  • the LLRs of the repeated positions are combined to achieve de-rate matching, and the decoded mother code length is decoded. Rate matching in a repetitive manner can reduce decoding complexity, reduce latency, and reduce hardware implementation area. However, in some cases, repeated performance of the Polar code will cause some loss.
  • the embodiment of the present application provides an encoding method, an encoding apparatus, a decoding method, and a decoding apparatus, which can reduce the number of times of repeated rate matching schemes and reduce performance loss caused by repetition.
  • a Polar coding method including:
  • the information bit sequence to be encoded is divided into p sub-segments, and P sub-segments
  • the segments are independently coded by Polar, and p coded bit sequences of lengths of sub-segment mother codes are obtained, where p is an integer greater than or equal to 2; rate matching is performed on p coding results respectively, and p lengths are respectively obtained.
  • the coded bit sequence of the target code length of the segment; the p code bit sequence after the rate matching is combined to obtain a coded bit sequence of length M.
  • the information bit sequence to be encoded by using the mother code length N is Polar coded. a first coded bit sequence of length N, repeating at least a part of the bits in the first coded bit sequence to obtain a coded bit sequence of length M;
  • the information bit sequence to be encoded is Polar coded by using the mother code length N to obtain a second Encoding a bit sequence, shortening or puncturing the second coded bit sequence to obtain a coded bit sequence of length M.
  • the total length of the information bit sequence to be encoded is Kc
  • the information bit length of the p sub-segments The lengths of the mother codes used for independent Polar coding for K1, K2, ..., Kp, and p sub-segments are respectively N1, N2, ..., Np
  • the corresponding target code lengths are M1, M2, ..
  • the information bit sequence to be encoded includes the information block, Kc is greater than or equal to The length K of the information block; for each Mi, if the target code length Mi of the sub-section corresponding to Mi is greater than the mother code length Ni, and the coding parameters of the sub-section corresponding to Ki satisfy the preset condition, Mi corresponds to
  • a fourth possible implementation manner of the first aspect if the target code length Mi is greater than the mother code length Ni, and the encoding parameter of the Mi corresponding sub-segment does not satisfy the foregoing
  • the preset condition is that the sub-segment corresponding to the Mi is encoded by the mother code length Ni to obtain a third coded bit sequence of length Ni, and at least a part of the bits of the third coded bit sequence are repeated to obtain a length of Mi.
  • the mother code length Ni is used to perform Polar coding on the sub-segment corresponding to Ki to obtain a fourth coded bit sequence, and the fourth coded bit sequence is shortened or punched. , to obtain a coding sequence of length Mi.
  • an encoding apparatus including:
  • An acquiring unit configured to obtain a target code length M of the information block to be sent and the Polar code
  • a coding unit which determines a mother code length N used by the Polar code, and when the target code length M is greater than N, if the coding parameter of the information block satisfies a preset condition, the information bit sequence to be encoded is divided into p sub-segments.
  • Separate Polar coding is performed on P sub-segments respectively, and p coded bit sequences whose lengths are sub-segment mother code lengths are obtained, where p is an integer greater than or equal to 2; rate matching unit is used to respectively rate the p coding results Matching, obtaining p coded bit sequences each having a length of the target code length of the sub-segment; a merging unit for combining and combining the p-coded bit sequences after the rate matching to obtain a coded bit sequence of length M.
  • the coding unit is configured to: if the coding parameter of the information block does not meet the preset condition, use the code length N to be encoded. Performing Polar coding on the bit sequence to obtain a first coded bit sequence of length N; the rate matching unit is configured to repeat at least a part of the bits in the first coded bit sequence to obtain a coded bit sequence of length M; or
  • the coding unit is configured to: if the target code length M is less than or equal to the mother code length N, use the mother code length N to the information bits to be encoded.
  • the sequence is subjected to Polar coding to obtain a second coded bit sequence; the rate matching unit is configured to shorten or punctify the second coded bit sequence to obtain a coded bit sequence of length M.
  • the coding unit is configured to: if the target code length Mi is greater than the mother code length Ni, And the encoding parameter of the sub-segment of the Mi does not satisfy the preset condition, and the sub-segment corresponding to the Mi is encoded by the mother code length Ni to obtain a third coding bit sequence of length Ni; the rate matching unit is used for Repeating at least a part of the bits in the third coded bit sequence to obtain a code sequence of length Mi; or the coding unit is configured to use a mother code length Ni to Ki if the target code length Mi is less than or equal to the mother code length Ni
  • the sub-segment performs Polar coding to obtain a fourth coded bit sequence; the rate matching unit is configured to shorten or punctify the fourth coded bit sequence to obtain a code sequence of length Mi.
  • a further encoding apparatus comprising:
  • a memory for storing a program
  • a processor configured to execute the program stored by the memory, when the program is executed, acquiring a target code length M of the information block to be transmitted and the Polar code; determining the use of the Polar code
  • the mother code length N is, when the target code length M is greater than N, if the coding parameter of the information block satisfies a preset condition, the information bit sequence to be coded is divided into p sub-segments, and P sub-segments are separately independent.
  • Polar coding obtain p coded bit sequences of length sub-segment mother code length, where p is an integer greater than or equal to 2; rate matching of p coding results respectively, to obtain p target lengths of sub-segments respectively a coded bit sequence; combining the rate-matched p coded bit sequences to obtain a coded bit sequence of length M.
  • the processor is configured to: if the coding parameter of the information block does not meet the preset condition, use the information code bit to be encoded by the mother code length N
  • the sequence is Polar-coded to obtain a first coded bit sequence of length N, and at least a part of the bits of the first coded bit sequence are repeated to obtain a coded bit sequence of length M.
  • the processor is configured to: if the target code length M is less than or equal to the mother code length N, use the mother code length N to the information bit sequence to be encoded. Polar coding is performed to obtain a second coded bit sequence, and the second coded bit sequence is shortened or punctured to obtain a coded bit sequence of length M.
  • the total length of the information bit sequence to be encoded is Kc
  • the information bit length of the p sub-segments The lengths of the mother codes used for independent Polar coding for K1, K2, ..., Kp, and p sub-segments are respectively N1, N2, ..., Np
  • the corresponding target code lengths are M1, M2, ..
  • the information bit sequence to be encoded includes the information block, Kc is greater than or equal to a length K of the information block;
  • the processor is configured to: for each Mi, if the target code length Mi of the sub-section corresponding to Mi is greater than the mother code length Ni, and the encoding parameter of the sub-section corresponding to Ki satisfies the preset
  • a coding apparatus including:
  • the at least one input terminal is configured to receive the information block; the signal processor is configured to obtain the target code length M of the information block to be sent and the Polar code; and determine the mother code length N used by the Polar code, when the target code length is M If the encoding parameter of the information block satisfies a preset condition, the information bit sequence to be encoded is divided into p sub-segments, and P sub-segments are separately subjected to independent Polar coding, and p lengths are respectively sub-segment mother codes.
  • a coded bit sequence of length where p is an integer greater than or equal to 2; rate matching is performed on p coding results respectively, to obtain p coded bit sequences each having a length of a sub-segment of the target code length; combining the rate-matched p The coded bit sequence is obtained to obtain a coded bit sequence of length M; at least one output terminal is used for outputting a coded bit sequence obtained by the signal processor.
  • the signal processor is configured to: if the encoding parameter of the information block does not meet the preset condition, use the information that the mother code length N is to be encoded.
  • the bit sequence is Polar-coded to obtain a first coded bit sequence of length N, and at least a part of the bits of the first coded bit sequence are repeated to obtain a coded bit sequence of length M.
  • the signal processor is configured to: if the target code length M is less than or equal to the mother code length N, use the mother code length N to the information bits to be encoded.
  • the sequence is Polar coded to obtain a second coded bit sequence, and the second coded bit sequence is shortened or punctured to obtain a coded bit sequence of length M.
  • the total length of the information bit sequence to be encoded is Kc
  • the information bit length of the p sub-segments The lengths of the mother codes used for independent Polar coding for K1, K2, ..., Kp, and p sub-segments are respectively N1, N2, ..., Np
  • the corresponding target code lengths are M1, M2, ..
  • the information bit sequence to be encoded includes the information block, Kc is greater than or equal to a length K of the information block;
  • the signal processor is configured to: for each Mi, if the target code length Mi of the sub-section corresponding to Mi is greater than the mother code length Ni, and the coding parameters of the sub-section corresponding to Ki satisfy the pre-
  • the fifth aspect provides a method for decoding a Polar code, including:
  • the bit length to be decoded is the target code length M at the time of encoding; determining the mother code length N at the time of encoding, when the target code length M is greater than the mother code length N If the coding parameter satisfies the preset condition, the LLR corresponding to the bit to be decoded is divided into p sub-segments, and the p sub-segments are respectively subjected to solution rate matching, where p is an integer greater than or equal to 2; The LLRs of the sub-segments are respectively subjected to independent SCL decoding to obtain decoding results of p sub-segments; the decoding results of p sub-segments are combined, and the decoding bit sequence is output.
  • the code lengths of the p sub-segments are N1, N2, ..., Np, and the target code lengths are M1, M2, ..., respectively.
  • the coding parameters satisfy the preset condition, and further divide the LLR sequence of the sub-segment corresponding to Mi into p sub-segments for de-rate matching and decoding, and obtain decoding results of corresponding p sub-segments, and merge p sub-segments
  • the LLR of the punched or shortened position is restored, and the length after the solution rate matching is N.
  • the LLR sequence is decoded and decoded to obtain a decoded bit sequence.
  • a decoding apparatus including:
  • a receiving unit configured to receive a log likelihood ratio LLR corresponding to the bit to be decoded, the bit length to be decoded is a target code length M when encoding; and a de-rate matching unit is configured to determine a mother code length N when encoding, when When the target code length M is greater than the mother code length N, if the coding parameter satisfies the preset condition, the LLR corresponding to the bit to be decoded is divided into p sub-segments, and p sub-segments are respectively subjected to solution rate matching, where p is greater than An integer equal to 2; a decoding unit configured to perform independent SCL decoding on the LLRs of the p sub-segments to obtain a decoding result of the p sub-segments; and output units, combine the decoding results of the p sub-segments, and output the decoded bit sequence .
  • the code lengths of the p sub-segments are N1, N2, ..., Np, and the target code lengths are M1, M2, ..., respectively.
  • Mp the corresponding information bit length is K1, K2, ..., Kp;
  • the position will be repeated.
  • the LLRs are superimposed to obtain a rate-matched LLR sequence of length Ni; the decoding unit is used to decode the LLR sequence of length Ni , the decoding result of the sub-section Mi is obtained.
  • the de-rate matching unit recovers the LLR of the punched or shortened position when the target code length M is smaller than the mother code length N, and obtains the rate matching.
  • the LLR sequence of length N the decoding unit is configured to decode the LLR sequence of length N to obtain a decoded bit sequence.
  • a decoding apparatus including:
  • a memory for storing a program
  • a processor configured to execute the program stored by the memory, when the program is executed, receiving a log likelihood ratio LLR corresponding to a bit to be decoded, and the bit length to be decoded is The target code length M at the time of encoding; determining the mother code length N at the time of encoding, when the target code length M is greater than the mother code length N, if the encoding parameter satisfies a preset condition, the LLR corresponding to the bit to be decoded is divided into p Sub-segment, de-rate matching is performed on p sub-segments respectively; independent SCL decoding is performed on LLRs of p sub-segments to obtain decoding results of p sub-segments; decoding results of p sub-segments are combined, and decoding bit sequences are output , where p is an integer greater than or equal to 2.
  • the code lengths of the p sub-segments are N1, N2, ..., Np, and the target code lengths are M1, M2, ..., respectively.
  • Mp the corresponding information bit length is K1, K2, ..., Kp;
  • the processor is configured to: when the target code length M is smaller than the mother code length N, recover the LLR of the punched or shortened position, and obtain the solution rate matching.
  • the LLR sequence of length N is decoded and decoded to obtain a decoded bit sequence.
  • a decoding apparatus including:
  • At least one input terminal is configured to receive a log likelihood ratio LLR corresponding to the bit to be decoded, the bit length to be decoded is a target code length M at the time of encoding, and a signal processor is configured to receive a logarithm corresponding to the bit to be decoded
  • the bit length to be decoded is the target code length M at the time of encoding
  • the mother code length N at the time of encoding is determined, and when the target code length M is greater than the mother code length N, if the encoding parameter satisfies the preset condition
  • the LLR corresponding to the bit to be decoded is divided into p sub-segments, and the p sub-segments are respectively subjected to de-rate matching; the LLRs of the p-sub-segments after the de-rate matching are separately subjected to independent SCL decoding, and the p sub-segments are decoded.
  • the code lengths of the p sub-segments are N1, N2, ..., Np, and the target code lengths are M1, M2, ..., respectively.
  • Mp the corresponding information bit length is K1, K2, ..., Kp;
  • the coding parameter of the sub-section corresponding to the Mi satisfies the preset condition, and further divides the LLR sequence of the sub-segment corresponding to Mi into p sub-segments for de-rate matching and decoding, and obtains translation of the corresponding p sub-segments.
  • the length of Ni, and the encoding parameter of the sub-segment corresponding to Mi does not satisfy the preset condition, and the LLRs of the repeated position are superimposed to obtain a LLR sequence of length Ni after de-rate matching, and decoding is performed to obtain a sub-segment Mi
  • the signal processor is configured to recover the LLR of the punched or shortened position when the target code length M is smaller than the mother code length N, to obtain a solution rate matching.
  • the LLR sequence of length N is then decoded and a decoded bit sequence is obtained.
  • the encoding parameter includes one of: an encoding bit rate R, an information bit sequence length Kc to be encoded, a length K of the information block, or a target code length M; the preset condition Including any one of the following: for a given code rate R, the information bit sequence length Kc to be encoded is greater than a preset threshold; for a given code rate R, the length K of the information block is greater than a preset Threshold; or for a given code rate R, the target code length M is greater than a preset threshold.
  • determining the length of the mother code Indicates rounding up min( ⁇ ) means taking the minimum value, and N max means the maximum mother code length supported by the system.
  • the preset condition is one of the following:
  • the information bit sequence length Kc to be encoded presets a threshold Kc1, and Kc1 belongs to an integer of the interval [330, 370];
  • the length Kc of the information bit sequence to be encoded is greater than a preset threshold Kc2, and Kc2 belongs to an integer of the interval [345, 365];
  • the length Kc of the information bit sequence to be encoded is greater than a preset threshold Kc3, and Kc3 belongs to an integer of the interval [370, 380];
  • the length Kc of the information bit sequence to be encoded is greater than a preset threshold Kc4, and Kc4 belongs to an integer of the interval [450, 460];
  • the information bit sequence length Kc to be encoded is greater than a preset threshold Kc5, and Kc5 belongs to an integer of the interval [500, 510];
  • the length K of the information block is greater than a preset threshold Kt1, and Kt1 belongs to an integer of the interval [314-354];
  • the length K of the information block is greater than a preset threshold Kt2, and Kt2 belongs to an integer of the interval [329-349];
  • the length K of the information block is greater than a preset threshold Kt3, and Kt3 belongs to an integer of the interval [354-364];
  • the length K of the information block is greater than a preset threshold Kt4, and Kt4 belongs to an integer of the interval [434-444];
  • the length K of the information block is greater than a preset threshold Kt5, and Kt5 belongs to an integer of the interval [484-494];
  • the target code length M is greater than a preset threshold Mt1, and Mt1 belongs to an integer of the interval [3768-4248];
  • the target code length M is greater than a preset threshold Mt2, and Mt2 belongs to an integer of the interval [1974-2094];
  • the target code length M is greater than a preset threshold Mt3, and Mt3 belongs to an integer of the interval [1416-1456];
  • the target code length M is greater than a preset threshold Mt4, and Mt4 belongs to an integer of the interval [1302-1332]; or
  • the target code length M is greater than a preset threshold Mt5, and Mt5 belongs to an integer of the interval [1210-1235].
  • the Polar code is CA-Polar code
  • the preset condition is one of the following:
  • the information bit sequence length Kc to be encoded presets a threshold Kc1, and Kc1 belongs to an integer of the interval [310-340];
  • the length Kc of the information bit sequence to be encoded is greater than a preset threshold Kc2, and Kc2 belongs to an integer of the interval [350-365];
  • the information bit sequence length Kc to be encoded is greater than a preset threshold Kc3, and Kc3 belongs to an integer of the interval [410-450];
  • the length Kc of the information bit sequence to be encoded is greater than a preset threshold Kc4, and Kc4 belongs to an integer of the interval [470-495];
  • the length Kc of the information bit sequence to be encoded is greater than a preset threshold Kc5, and Kc5 belongs to an integer of the interval [520-530];
  • the length K of the information block is greater than a preset threshold Kt1, and Kt1 belongs to an integer of the interval [291-321];
  • the length K of the information block is greater than a preset threshold Kt2, and Kt2 belongs to an integer of the interval [331-346];
  • the length K of the information block is greater than a preset threshold Kt3, and Kt3 belongs to an integer of the interval [391-431];
  • the length K of the information block is greater than a preset threshold Kt4, and Kt4 belongs to an integer of the interval [451-476];
  • the length K of the information block is greater than a preset threshold Kt5, and Kt5 belongs to an integer of the interval [501-511];
  • the target code length M is greater than a preset threshold Mt1, and Mt1 belongs to an integer of the interval [3492-3852];
  • the target code length M is greater than a preset threshold Mt2, and Mt2 belongs to an integer of the interval [1986-2076];
  • the target code length M is greater than a preset threshold Mt3, and Mt3 belongs to an integer of the interval [1564-1724];
  • the target code length M is greater than a preset threshold Mt4, and Mt4 belongs to an integer of the interval [1353-1428]; or
  • the target code length M is greater than a preset threshold Mt5, and Mt5 belongs to an integer of the interval [1253-1278].
  • a ninth aspect provides a communication device, including: a bus, a processor, a storage medium, a bus interface, a network adapter, a user interface, and an antenna;
  • the bus is configured to connect a processor, a storage medium, a bus interface, and a user interface;
  • the processor is configured to perform the coding method of the first aspect or any implementation thereof, or to perform the coding method of the fifth aspect or any implementation thereof.
  • the storage medium for storing an operating system and data to be sent or received
  • the bus interface is connected to a network adapter
  • the network adapter is configured to implement a signal processing function of a physical layer in a wireless communication network
  • the user interface is configured to connect to a user input device
  • the antenna is used for signal transmission and reception.
  • Yet another aspect of the present application is directed to a computer readable storage medium having instructions stored therein that, when executed on a computer, cause the computer to perform the methods described in the various aspects above.
  • Yet another aspect of the present application provides a computer program product comprising instructions which, when run on a computer, cause the computer to perform the methods described in the various aspects above.
  • Yet another aspect of the present application provides a computer program that, when run on a computer, causes the computer to perform the methods described in the various aspects above.
  • the target code length exceeds the length of the mother code determined according to the agreed rule
  • the coding parameter satisfies the preset condition
  • the information bit sequence to be coded is segmentally and independently coded, thereby reducing the repetition rate matching method.
  • the probability of use reduces the performance loss caused by repetition.
  • FIG. 1 is a schematic diagram of a basic flow of a wireless communication transmitting end and a receiving end;
  • FIG. 2 is a schematic flowchart of an encoding method provided by an embodiment of the present application.
  • FIG. 3 is a schematic flowchart of an encoding method provided by an embodiment of the present application.
  • FIG. 4 is a schematic flow chart of an encoding method and a decoding method of Arikan Polar;
  • FIG. 5 is a schematic flow chart of a coding method and a decoding method of a PC-Polar
  • FIG. 6 is a schematic flow chart of a PC-CA-SCL decoding method
  • FIG. 7 is a comparison diagram of decoding performance of a general PC-Polar encoding and a segmented PC-Poar encoding
  • FIG. 8 is a schematic flow chart of a coding method and a decoding method of CA-Polar
  • FIG. 9 is a schematic flow chart of another CA-Polar encoding method and decoding method.
  • FIG. 10 is a schematic flow chart of another CA-Polar encoding method and decoding method
  • FIG. 11 is a schematic structural diagram of an encoding apparatus 1100 according to an embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of another encoding apparatus 1200 according to an embodiment of the present disclosure.
  • FIG. 13 is a schematic structural diagram of another encoding apparatus 1300 according to an embodiment of the present disclosure.
  • FIG. 14 is a schematic structural diagram of a decoding apparatus 1400 according to an embodiment of the present disclosure.
  • FIG. 15 is a schematic structural diagram of a decoding apparatus 1500 according to an embodiment of the present disclosure.
  • FIG. 16 is a schematic structural diagram of a decoding apparatus 1600 according to an embodiment of the present disclosure.
  • FIG. 17 is a schematic structural diagram of a communication device 1700 according to an embodiment of the present application.
  • FIG. 1 is a basic flow of wireless communication.
  • the source is sequentially transmitted after source coding, channel coding, and digital modulation.
  • the destination is outputted by digital demodulation, channel decoding, and source decoding.
  • the channel codec can use a Polar code. Since the code length of the original Polar code (parent code) is an integer power of 2, in practical applications, a Polar code of arbitrary code length needs to be implemented by rate matching. As shown in FIG. 1, rate matching is performed after channel coding at the transmitting end to implement an arbitrary target code length, and at the receiving end, de-rate matching is performed before channel decoding.
  • the technical solution of the embodiment of the present application can be applied to a 5G communication system, and can also be applied to other various communication systems, for example, a Global System of Mobile communication (GSM) system, and Code Division Multiple Access (CDMA).
  • GSM Global System of Mobile communication
  • CDMA Code Division Multiple Access
  • WCDMA Wideband Code Division Multiple Access
  • GPRS General Packet Radio Service
  • LTE Long Term Evolution
  • FDD Frequency Division Duplex
  • UMTS Universal Mobile Telecommunication System
  • the length of the mother code is usually determined according to the agreed rules in the communication system.
  • the rate matching can be achieved by shortening or puncturing the rate matching scheme.
  • rate matching can be performed by a repeated rate matching scheme, and the repeated scheme brings performance loss.
  • Some communication systems also specify the maximum mother code length used by the Polar code. For example, the maximum downlink mother code length is 512 in the communication system, and the maximum uplink mother code length is 1024. Since the Polar code code has the limitation of the maximum mother code length, when the target code length is greater than Nmax, simply repeating the transmission of the Polar code with the code length of Nmax brings performance loss, and the more the repeated bits, the greater the loss.
  • Segmentation coding and re-merging of Polar codes will also bring performance loss, but under certain conditions (for example, when the mother code rate is K/N is large), the coding gain brought by segmentation coding will be to some extent. It compensates for the loss caused by segmentation coding, so under certain conditions (for example, when the code rate is greater than a certain mother code), the segmentation coding performance will be better than the repetition rate matching scheme.
  • the present invention adopts segmentation coding of the information bits to be encoded under the condition that the coding parameters satisfy the preset condition, and reduces the loss caused by the existing rate matching scheme (repetition) on the performance of the Polar code.
  • Polar coding may be performed according to the mother code length N to obtain a coded bit sequence of length N, and then punctured or shortened to obtain a coded bit sequence of length M.
  • FIG. 2 is a schematic flowchart of an encoding method provided by an embodiment of the present application, where the method includes:
  • the length of the information block is K
  • the code rate is R
  • M INT (K/R)
  • INT means rounding.
  • the information bit sequence to be encoded is divided into p sub-segments, and p sub-segments are separately coded separately to obtain p coded bit sequences, wherein p is an integer greater than or equal to 2, and the total length of the information bit sequence to be encoded is Kc,p
  • M1, M2, ..., Mp the mother code length of each sub-segment N1, N2, ..., Np, respectively, using the mother code length N1, N2, ..., Np for p sub-segments respectively Polar coding.
  • the sub-segment corresponding to Ki is Polar-coded using the mother code length Ni to obtain a coded bit of length Ni. Sequence, then use repeated rate matching.
  • the sub-segment corresponding to Ki is encoded by the mother code length Ni to obtain a coding sequence of length Ni, and a rate matching scheme of shortening or puncturing is adopted later.
  • M ⁇ Nmax adopt Coding to obtain a coded bit sequence of length N, using a shortened or punctured rate matching scheme to obtain a coded bit sequence of length M, wherein Indicates rounding up.
  • N preferentially selects a value smaller than the target code length and satisfies the mother code rate lower than or equal to the code rate threshold, otherwise selects among them Indicates rounding up.
  • N preferentially selects a value smaller than the target code length and satisfies M ⁇ N * (1 + ⁇ ), otherwise selects among them Indicates rounding up.
  • ⁇ can be a constant, for example set to 1/8, 1/4 or 3/8.
  • ⁇ is a linear function of R1
  • the larger R0 is, the smaller ⁇ is, that is, the smaller the number of repeated bits is allowed.
  • the 205 Perform corresponding rate matching on the p sub-segments respectively, and obtain p coded bit sequences each having a length of the sub-segment object code length. Specifically, if the target code length Mi of each sub-segment is greater than the mother code length Ni, at least a part of the bits of the coded bit sequence of length Ni are repeated to obtain a coded bit sequence of length Mi. If the target code length Mi of each sub-segment is less than or equal to the mother code length Ni, the punctured or shortened rate matching scheme is used to delete the punctured position or shorten the position of the coded bits to obtain a coded bit sequence of length Mi.
  • step 206 Combine the p coded bit sequences obtained in step 205 to obtain a coded bit sequence of length M.
  • the coding parameters in the p sub-segments may be further divided into p sub-segments and the independent coding and rate matching are performed separately.
  • the target code length Mi is greater than the mother code length Ni, and the coding parameters of the sub-section corresponding to Mi satisfy the preset condition.
  • the sub-segments corresponding to Mi are further divided into p sub-segments for independent coding and rate matching, and corresponding p-coded bit sequences are obtained and combined to obtain a coded bit sequence of the target code length Mi. If the target code length Mi is greater than the mother code length Ni, but the coding parameters of the sub-section corresponding to Mi do not satisfy the preset condition, the mother code length Ni is used to perform Polar coding on the sub-section corresponding to Mi to obtain a code length of Ni.
  • a bit sequence repeating at least a portion of the bits of the third coded bit sequence to obtain a code sequence of length Mi. If the target code length Mi is less than or equal to the maximum mother code length Ni, the mother code length Ni is used, and the sub-segment corresponding to Mi is subjected to Polar coding to obtain a coded bit sequence, and the coded bit sequence is shortened or punctured to obtain a length of Mi. Coding sequence
  • step 204 may be performed.
  • the Polar code obtains a coded bit sequence of length N, and repeats at least a part of the coded bit sequence of length N to obtain a coded bit sequence of length M;
  • step 202 may be performed.
  • the Polar code obtains a coded bit sequence of length N, and shortens or punctured the coded bit sequence of length N to obtain a coded bit sequence of length M.
  • FIG. 3 is a schematic flowchart of an encoding method provided by an embodiment of the present application, where the method includes:
  • the encoding parameters related to the encoding end of the receiving end can be obtained through the scheduling information of the system, for example, K, M, R, N and the like.
  • the receiving end can also determine the target code length M according to the received LLR.
  • 303 Determine a mother code length N.
  • the target code length M is greater than the mother code length N determined in step 301, if the coding parameter satisfies a preset condition (which may also be referred to as a segmentation coding condition), the information bit to be decoded is to be decoded.
  • a preset condition which may also be referred to as a segmentation coding condition
  • the LLR sequence is divided into p segments and de-rate matching is performed separately.
  • the mother code length N and the corresponding rate matching mode are determined according to the agreed rules.
  • the specific method is consistent with the encoding end.
  • the mother code lengths of each sub-section are respectively determined to be N1, N2, ..., Np.
  • the mother code lengths of each sub-section are respectively determined to be N1, N2, ..., Np.
  • An LLR sequence of length Ni When Mi ⁇ Ni, it is determined that the transmitting end adopts the method of shortening or punching for rate matching, and the LLR of the shortening or punching position is restored (set to a predetermined fixed value), and the length after the rate matching is obtained by Ni. LLR sequence.
  • the coding parameters in the p sub-segments may be further divided into p sub-segments, and then rate matching and decoding are respectively performed to obtain decoding of p sub-segments. The results are combined.
  • step 304 may be performed.
  • step 302 may be performed.
  • the LLR that is punctured or shortened is restored, and a rate-matched LLR sequence of length N is obtained and decoded.
  • the p sub-segments may be uniform sub-segments.
  • the total length of the bit sequence to be encoded is Kc
  • the length of each sub-segment is Kc/p, corresponding to each sub-segment.
  • the target code length is also M/p. If it cannot be divided, it will be slightly adjusted.
  • the coding parameters mentioned in the present application include one or more of the following: an encoding code rate R, a target code length M, a mother code length N, a length K of a information block, a CRC length Lrc, and the like.
  • the preset condition (segment coding condition) of the present application may include any one of the following:
  • the length K of the information block is greater than a preset threshold.
  • the target code length M is greater than a preset threshold.
  • the information bit sequence length Kc to be encoded is greater than a preset threshold.
  • the information block referred to in this application refers to information actually to be transmitted in the communication system.
  • the "information bit sequence to be encoded” as used in the embodiment of the present application refers to a sequence composed of information carried by information bits corresponding to a set of information bit indexes in Polar coding.
  • the "length” in this article can also be said to be "number”.
  • the Polar code in the embodiment of the present application may also be a CA-Polar code, a PC-Polar code or a PC-CA-Polar code.
  • Arikan Polar refers to the original Polar code, which is not cascaded with other codes, only information bits and frozen bits.
  • the CA-Polar code is a Polar code cascading a Cyclic Redundancy Check (CRC) Polar code
  • the PC-Polar code is a Polar code level Parity Check (PC) code, PC.
  • the -CA-Polar code is a code that concatenates both CRC and PC at the same time. PC-Polar, CA-Polar, and PC-CA-Pola improve the performance of Polar codes by cascading different codes.
  • the coding method and the decoding method in different embodiments will be introduced in combination with different types of Polar code coding methods.
  • the coding method and the decoding method will be introduced together, but those skilled in the art can understand that the coding method at the transmitting end and the decoding method at the receiving end are mutually corresponding but independent processes.
  • M ⁇ N Therefore it can be simplified as when M ⁇ Nmax or Time Perform Polar coding and use the rate matching method of shortening or puncturing to obtain the target code length. Therefore, the following embodiment replaces "M is greater than N" with " Greater than Nmax”, replace "M less than or equal to N" with " Less than or equal to Nmax”; of course, it is also possible to replace "M is greater than N" with "M is greater than Nmax” and "M is less than or equal to N” with "M is less than or equal to Nmax", and the object of the present application can still be achieved.
  • the target code length M is greater than the maximum mother code length Nmax, and the bit code to be encoded that satisfies the conditions of the Polar code segmentation is subjected to segment coding of the Polar code, and the receiving end performs decoding and completes the combination of the decoding results.
  • the flow chart of Arikan Polar's encoding method and decoding method is shown in Figure 4.
  • the encoding and decoding process includes:
  • N max the mother code length supported by the system
  • the segmentation is continued.
  • a repeated rate matching method is employed in the case where the segmentation coding condition is not satisfied.
  • K+ corresponds to K1 mentioned above
  • K- corresponds to K2 mentioned above
  • M+ corresponds to M1 mentioned above
  • M- corresponds to M2 mentioned above.
  • K + and K - represent K1 and K2
  • M + M - represents M1 and M2.
  • the Polar code segmentation coding condition is determined by the code rate R, and the block length K, the object code length M, or the information bit sequence length Kc to be encoded.
  • the length K of the information block is greater than a preset threshold
  • the target code length M is greater than a preset threshold
  • the information bit sequence length Kc to be encoded is greater than a preset threshold.
  • the conditions of different parameters correspond to different thresholds, and the settings for different Nmax value thresholds may also be different.
  • step (3) uses segmentation coding, the coded bit sequence obtained by encoding each sub-segment is combined to obtain a final coded bit sequence.
  • the receiving end performs corresponding de-rate matching, and finally decodes the sub-segment information according to the encoding rule to complete the merging of the information.
  • Polar code segmentation coding is applicable to the coding and decoding process of PC-Polar.
  • the schematic diagram of the process is shown in Figure 5, including:
  • PC-Polar cascaded CRC bit is taken as an example, also known as PC-CA-Polar, which can be used to assist PC-SCL decoding (error correction).
  • PC-CA-Polar which can be used to assist PC-SCL decoding (error correction).
  • the CRC bits are not used to assist PC-SCL decoding, but can be used for error detection after decoding is complete.
  • PC-Polar segment encoding conditions from the code rate K R, and the length of the information bit sequence to be encoded or the Kc or the length of the target code block length M is determined, wherein C corresponds to the number K of information bits used when Polar code construction.
  • the segmentation coding conditions of the PC-Polar code at different code rates are shown in Table 1. In Table 1, different code rate values and their corresponding segmentation coding conditions are listed, but all code rates and their corresponding segmentation coding conditions cannot be exhausted, and those skilled in the art can formulate suitable segment coding at other code rates. condition.
  • the value range of Kc1 may be an integer belonging to the interval [330-370]; the value range of Kc2 may be an integer belonging to the interval [345-365], and the range of Kc3 may belong to the interval [370] An integer of -380]; the value range of Kc4 may be an integer belonging to the interval [450-460]; the value range of Kc5 may be an integer belonging to the interval [500-510].
  • the range of Kt1 may be an integer belonging to the interval [314-354]
  • the range of Kt2 may be an integer belonging to the interval [329-349]
  • the range of Kt3 may belong to the interval [354]
  • the value range of Kt4 may be an integer belonging to the interval [434-444]
  • the value range of Kt5 may be an integer belonging to the interval [484-494].
  • the range of Mt1 may be an integer belonging to the interval [3768-4248]; the range of Mt2 may be an integer belonging to the interval [1974-2094], and the range of Mt3 may be an interval [1416] An integer of -1456]; the value range of Mt4 may be an integer belonging to the interval [1302-1332]; the value range of Mt5 may be an integer belonging to the interval [1210-1235].
  • the segmentation conditions are shown in Table 2.
  • the value range of Kc1 may be an integer belonging to the interval [200-220]; the value range of Kc2 may be an integer belonging to the interval [205-225], and the value range of Kc3 may belong to the interval [210] An integer of -220]; the value range of Kc4 may be an integer belonging to the interval [120-240]; the value range of Kc5 may be an integer belonging to the interval [265-275].
  • the range of Kt1 may be an integer belonging to the interval [184-204]
  • the range of Kt2 may be an integer belonging to the interval [189-209]
  • the range of Kt3 may belong to the interval [194]
  • the value range of Kt4 may be an integer belonging to the interval [214-224]
  • the value range of Kt5 may be an integer belonging to the interval [249-259].
  • the range of Mt1 may be an integer belonging to the interval [2208-2448]; the range of Mt2 may be an integer belonging to the interval [1134-1254], and the range of Mt3 may be an interval [776] An integer of -856]; the range of Mt4 may be an integer belonging to the interval [642-672]; the range of Mt5 may be an integer belonging to the interval [623-648].
  • Nmax 512
  • the segmentation conditions are shown in Table 3.
  • the preset condition of the present application that is, the segmentation coding condition, each R value in Table 1 - Table 3 and its corresponding Kc threshold constitute a segmentation coding condition, and each R value and its corresponding K threshold constitute one
  • the segmentation coding condition, each R value and its corresponding threshold of M constitute a segmentation coding condition. Therefore, Tables 1-3 are for convenience of presentation only, and the segmentation coding conditions are displayed together, and does not mean that the table as a whole is a segmentation coding condition, that is to say, it does not mean that the table must be simultaneously satisfied. condition.
  • the segmentation coding condition is Kc ⁇ 220, and the segmentation condition is satisfied.
  • the segmentation coding condition is not satisfied, so the segmentation is not continued, and the rate matching adopts a repeated manner: 179 (1203-1024) bits out of 1024 coded bits are repeated, and 1203 coded bits are obtained.
  • the rate matching scheme uses puncturing or shortening: puncturing from 1024 coded bits or shortening to 600 coded bits.
  • Rate matching is performed. If there is a segment coding, the coded bit sequence of each sub-segment is combined to obtain a coded bit sequence of length M.
  • the receiving end processes the received LLR sequence (the LLR sequence corresponding to the bit to be decoded) according to the scheduling rule according to the scheduling information.
  • step (3) After receiving the known encoding parameters (K, M, R, N), it is determined according to step (3) whether the segmentation coding condition is satisfied. If the segmentation coding condition is satisfied, the received LLR sequence is divided into two segments and separately performed. Processing of subsequent steps.
  • the LLR is complemented by 0, complemented by infinity or superimposed (corresponding to the rate matching scheme of puncturing, shortening and repetition), and the LLR sequence after the rate matching is obtained.
  • the rate matching scheme is a repetition, and the repeated 176 (1200-1024) position row LLRs are superimposed in a repeating pattern, and finally the LLR sequence length of each segment is 1024, which is 2 segments in total.
  • the rate matching scheme is a repetition, and the repeated 1376 (2400-1024) position LLRs are superimposed in a repeating pattern to obtain a length of 1024 LLR sequence.
  • the rate matching scheme is shortened, and the LLR complement is infinite.
  • the length of the LLR of 800 is recovered according to the shortening mode, and the shortened 224 (1024-800) positions are set to infinity values to obtain a length of 1024 LLR sequence.
  • step (6) If the encoding end is segment coded, the LLR sequences of the sub-segments obtained in step (5) are respectively decoded by independent PC-SCL, and the decoding results of each sub-segment are output, and finally the decoding of the two sub-segments is performed. The result is merged, at which point the CRC bits are not used to assist PC-SCL decoding.
  • the PC-SCL decoding for each segment can also refer to Figure 6, where the CRC bits are used for assisted decoding.
  • a PC-SCL decoder can output L p candidate information and L p PM values, and combine sub-segment 0 and sub-segment 1 2L p sub-segment candidate paths in pairs to obtain L p ⁇ L p candidate paths. The PM values of the candidate paths of the two sub-segments in each path obtained by the combination are added.
  • the size of the PM is ascending or descending order, selecting the optimal T p which strips the CRC check, check by selecting the first path decode output as candidate paths or the p-T CRC check are performed, selection Verifying the path of the PM value that is optimal in the candidate path passed, where T p ⁇ L p ⁇ L p , Lp is equal to the number of PC-SCL lists, and Tp is the number of candidate paths participating in the CRC check filter.
  • a PC-SCL decoder outputs 8 candidate information and 8 PM values, and combines two decoder outputs for a total of 16 candidate information to obtain 64 candidate information, and adds corresponding PMs, according to The PM size is sorted in ascending order, and the optimal 8 CRC checksums are selected.
  • the first path passed by the CRC check is used as the decoded output.
  • kc 380
  • the solid line is the decoding performance using segment coding
  • the dashed line is the decoding performance using ordinary PC-Polar coding. It can be seen that at the same code rate, the decoding performance of the segmentation coding is better than that of the ordinary PC-Polar coding.
  • the code segmentation coding of the Polar code is applicable to the coding and decoding process of CA-Polar as shown in FIG. 8.
  • the process may include:
  • N max the mother code length supported by the system
  • the CRC length can be 19. If the length of the sub-segment mother code is still greater than the maximum mother code length and the CA-Polar code segmentation coding condition is satisfied, the segmentation is continued, otherwise other rate matching methods are adopted.
  • Rate matching is performed. If there is a segment coding, the coded bit sequence of each sub-segment is combined to obtain a coded bit sequence of length M.
  • the receiving end performs de-rate matching, and performs independent SCL decoding on the sub-segments respectively, and outputs L P sub-segment candidate paths and PM, where L P is the size of the candidate list.
  • the 2L P sliver path segment candidates as combinations of two L P ⁇ L P candidate paths, whichever is the optimal candidate paths T P
  • the CA-Polar cascades the CRC bits to assist in SCL decoding. Therefore, the CRC check can be performed from the path of the optimal P-P candidate path, and the first path through which the CRC check passes is selected. As a decoded output, where T P ⁇ L P ⁇ L P .
  • CA-Polar segment encoding conditions from the code rate K R, and the length of the information bit sequence to be encoded or the Kc or the length of the target code block length M is determined, wherein C corresponds to the number K of information bits used when Polar code construction.
  • the segmentation coding conditions of the PC-Polar code at different code rates are shown in Table 1.
  • the value range of Kc1 may be an integer belonging to the interval [310-340]; the value range of Kc2 may be an integer belonging to the interval [350-365], and the value range of Kc3 may belong to the interval [410] An integer of -450]; the value range of Kc4 may be an integer belonging to the interval [470-495]; the value range of Kc5 may be an integer belonging to the interval [520-530].
  • the value range of Kt1 may be an integer belonging to the interval [291-321]
  • the range of Kt2 may be an integer belonging to the interval [331-346]
  • the range of Kt3 may belong to the interval [391]
  • the value range of Kt4 may be an integer belonging to the interval [451-476]
  • the value range of Kt5 may be an integer belonging to the interval [501-511].
  • the range of Mt1 may be an integer belonging to the interval [3492-3852]; the range of Mt2 may be an integer belonging to the interval [1986-2076], and the range of Mt3 may be an interval [1564] An integer of -1724]; the range of Mt4 may be an integer belonging to the interval [1353-1428]; the range of Mt5 may be an integer belonging to the interval [1253-1278].
  • the CA-Polar segmentation conditions are shown in Table 4.
  • the range of Kc1 may be an integer belonging to the interval [170-190]; the range of Kc2 may be an integer belonging to the interval [185-195], and the range of Kc3 may belong to the interval [210] An integer of -230]; the value range of Kc4 may be an integer belonging to the interval [250-260]; the value range of Kc5 may be an integer belonging to the interval [270-280].
  • the range of Kt1 may be an integer belonging to the interval [151-171]
  • the range of Kt2 may be an integer belonging to the interval [166-176]
  • the range of Kt3 may belong to the interval [191]
  • the value range of Kt4 may be an integer belonging to the interval [231-241]
  • the value range of Kt5 may be an integer belonging to the interval [251-261].
  • the range of Mt1 may be an integer belonging to the interval [1812-2052]; the range of Mt2 may be an integer belonging to the interval [996-1056], and the range of Mt3 may belong to the interval [764] An integer of -844]; the value range of Mt4 may be an integer belonging to the interval [693-723]; the value range of Mt5 may be an integer belonging to the interval [693-723].
  • Nmax 512
  • Nmax 512
  • Kc1 180
  • the segmentation coding conditions are as shown in Table 5.
  • Figure 8 illustrates a CA-Polar segmentation coding and decoding method.
  • the information bits to be encoded include a conventional CRC bit for error detection, but do not include CRC bits for auxiliary SCL decoding.
  • the CRC bits for assisting SCL decoding are divided into two segments, respectively added to sub-segment 0 and sub-segment 1, respectively, and independently coded.
  • the information block is divided into two segments, the length of the sub-segment 0 is K + , and the length of the sub-segment 1 is K ⁇ .
  • the receiving end performs de-rate matching, and performs independent CA-SCL decoding on the sub-segments, respectively outputs decoding results of one sub-segment, and finally combines the decoding results of the two sub-segments.
  • the information bits to be encoded do not include any CRC bits.
  • the CRC bits for assisting SCL decoding are divided into two segments, respectively added to sub-segment 0 and sub-segment 1, respectively, and independently coded. Therefore, if 2 n is greater than the maximum mother code length and the CA-Polar code segmentation coding condition is satisfied, the information block is divided into two segments, the length of the sub-segment 0 is K + , and the length of the sub-segment 1 is K ⁇ .
  • the receiving end performs de-rate matching, and performs independent CA-SCL decoding on the sub-segments, respectively outputs decoding results of one sub-segment, and finally combines the decoding results of the two sub-segments.
  • the punching in the embodiment of the present application includes Quasi-Uniform Puncture (QUP).
  • the mother code length is an integer power greater than or equal to the target code length of 2
  • the punch mode (punch position) is determined according to the mother code length and the target code length.
  • the puncturing mode can be represented by a binary sequence (00...011...1), wherein it is determined that "0" indicates the punching position and "1" indicates the unpunched position.
  • Set the channel capacity corresponding to the punching position to 0 or set the error probability to 1 or the signal-to-noise ratio SNR to infinity
  • the information bits and fixed bit (freeze bits) locations are determined.
  • the encoding end deletes the bit in the punched position after encoding to obtain a polar code.
  • the scheme of shortening the (Shorten) Polar code described in the present application determines that the mother code length is an integer power of 2 or more greater than or equal to the target code length.
  • the coded bits of the shortened position are only related to fixed bits.
  • the process includes: calculating the reliability of the polarized channel according to the mother code, and then determining the Shorten position, the corresponding polarized channel placing a fixed bit, and determining the information bit and the frozen bit (fixed bit) position according to the reliability from the remaining polarized channels, The bit that is in the shortened position after encoding is deleted to obtain a Polar code, and rate matching is achieved.
  • FIG. 11 is a schematic structural diagram of an encoding apparatus 1100 provided by the present application.
  • the encoding apparatus 1100 includes:
  • the acquiring unit 1101 is configured to acquire a target code length M of the information block to be sent and the Polar code;
  • the coding unit 1102 determines a mother code length N used by the Polar code.
  • N the target code length M is greater than N
  • the information bit sequence to be encoded is divided into p sub-segments. Separating Polar coding for P sub-segments respectively, and obtaining p coded bit sequences of lengths of sub-segment mother code lengths, where p is an integer greater than or equal to 2;
  • the rate matching unit 1103 is configured to separately perform rate matching on the p coding results to obtain p coded bit sequences each having a length of the target code length of the sub-segment;
  • the merging unit 1104 is configured to combine and merge the p-coded bit sequences after the rate matching to obtain a coded bit sequence of length M.
  • the coding unit 1102 is further configured to perform a Polar coding on the information bit sequence to be encoded by using the mother code length N, if the coding parameter of the information block does not meet the preset condition, to obtain a length.
  • a first coded bit sequence of N the rate matching unit is configured to repeat at least a part of the bits in the first coded bit sequence to obtain a coded bit sequence of length M;
  • the coding unit 1102 is further configured to perform a second coding on the information bit sequence to be encoded by using a mother code length N if the target code length M is less than or equal to the mother code length N. a bit sequence; the rate matching unit is configured to shorten or punctify the second coded bit sequence to obtain a coded bit sequence of length M.
  • the coding unit 1102 is further configured to: if the target code length Mi is greater than the mother code length Ni, and the coding parameters of the sub-segment corresponding to the Mi do not satisfy the preset condition, use the mother code length Ni to Mi. Performing Polar coding on the sub-segment to obtain a third coding bit sequence of length Ni; the rate matching unit is configured to repeat at least a part of the bits in the third coding bit sequence to obtain a coding sequence of length Mi; or
  • the coding unit 1102 is further configured to: if the target code length Mi is less than or equal to the mother code length Ni, perform a Polar coding on the sub-segment corresponding to Ki by using the mother code length Ni to obtain a fourth coded bit sequence; The unit is configured to shorten or punctify the fourth coded bit sequence to obtain a code sequence of length Mi.
  • FIG. 12 is a schematic structural diagram of another encoding apparatus 1200 provided by the present application.
  • the code apparatus 1200 includes:
  • the processor 1202 is configured to execute the program stored in the memory, obtain the target code length M of the information block to be sent and the Polar code when the program is executed, and determine the code length N of the mother code used by the Polar code.
  • the target code length M is greater than N, if the coding parameter of the information block satisfies a preset condition, the information bit sequence to be coded is divided into p sub-segments, and P sub-segments are separately subjected to independent Polar coding, and p are obtained.
  • a coded bit sequence of lengths of sub-segment mother code lengths where p is an integer greater than or equal to 2; rate matching is performed on p coding results respectively, to obtain p coded bit sequences of lengths of sub-segments respectively; The rate-matched p coded bit sequences obtain a coded bit sequence of length M.
  • the processor 1202 is further configured to: if the coding parameter of the information block does not meet the preset condition, perform a Polar coding on the information bit sequence to be encoded by the mother code length N to obtain a length. Repeating at least a part of the first coded bit sequence for the first coded bit sequence of N to obtain a coded bit sequence of length M;
  • the processor 1202 is further configured to perform a second encoding on the information bit sequence to be encoded by using a mother code length N if the target code length M is less than or equal to the mother code length N. a bit sequence that shortens or punctured the second coded bit sequence to obtain a coded bit sequence of length M.
  • the total length of the information bit sequence to be encoded is Kc
  • the information bit lengths of the p sub-segments are respectively K1, K2, . . . , Kp, p sub-segments respectively, and the lengths of the mother codes respectively used for independent Polar coding are respectively
  • the corresponding target code lengths are M1, M2, ..., Mp
  • Kc K1 + K2, +..., +Kp
  • M M1 + M2, + ..., +Mp
  • the information bit sequence to be encoded includes the information block, Kc is greater than or equal to the length K of the information block
  • the processor 1202 is further configured to: for each Mi, if Mi corresponds to The target code length Mi of the sub-segment is greater than the mother code length Ni, and the coding parameters of the sub-segment corresponding to Ki satisfy the preset condition, and the sub-segments corresponding to Mi are further divided into p sub-seg
  • the encoding apparatus of FIG. 12 may further include a transmitter (not shown) for transmitting a coded bit sequence of length M obtained by the processor.
  • FIG. 13 is a schematic structural diagram of another encoding apparatus 1300 provided by the present application.
  • the encoding apparatus 1300 includes:
  • the signal processor 1302 is configured to obtain a target code length M of the information block to be sent and the Polar code, and determine a mother code length N used by the Polar code, where the target code length M is greater than N, if the information block is encoded.
  • the parameter satisfies the preset condition, and the information bit sequence to be encoded is divided into p sub-segments, and the P sub-segments are separately subjected to independent Polar coding, and p code-length bit sequences whose lengths are respectively sub-segment mother code lengths are obtained, where p is greater than An integer equal to 2; rate matching is performed on each of the p coding results to obtain p coded bit sequences each having a length of the sub-segment of the target code length; combining the rate-matched p coded bit sequences to obtain a length M Coded bit sequence
  • At least one output end 1303 is configured to output a coded bit sequence obtained by the signal processor.
  • the signal processor 1302 is further configured to perform a Polar coding of the information bit sequence to be encoded by using the mother code length N if the coding parameter of the information block does not meet the preset condition. a first coded bit sequence of length N, repeating at least a portion of the bits of the first coded bit sequence to obtain a coded bit sequence of length M; or
  • the signal processor 1302 is further configured to: if the target code length M is less than or equal to the mother code length N, perform a Polar coding on the information bit sequence to be encoded by using a mother code length N to obtain a second Encoding a bit sequence, shortening or puncturing the second coded bit sequence to obtain a coded bit sequence of length M.
  • the total length of the information bit sequence to be encoded is Kc
  • the information bit lengths of the p sub-segments are respectively K1, K2, ..., Kp, p sub-segments respectively
  • the length of the mother code used for independent Polar coding is N1 respectively.
  • the information bit sequence to be encoded includes the information block, Kc is greater than or equal to the length K of the information block;
  • the signal processor 1302 is further configured to: for each Mi, if the target code length Mi of the sub-section corresponding to Mi is greater than the mother code length Ni, and the coding parameter of the sub-section corresponding to Ki satisfies the preset condition,
  • the encoding apparatus of Figure 13 may further comprise a transmitter (not shown) for transmitting a sequence of encoded bits of length M output by the at least one output.
  • the encoding device of Figures 11-13 of the present application may be any device having wireless communication capabilities, such as an access point, a site, a user equipment, a base station, and the like.
  • wireless communication capabilities such as an access point, a site, a user equipment, a base station, and the like.
  • FIG. 14 is a schematic structural diagram of a decoding apparatus 1400 provided by the present application.
  • the decoding apparatus 1400 includes:
  • the receiving unit 1401 is configured to receive a log likelihood ratio LLR corresponding to the bit to be decoded, and the bit length to be decoded is a target code length M when encoding;
  • the rate matching unit 1402 is configured to determine a mother code length N when encoding. When the target code length M is greater than the mother code length N, if the encoding parameter satisfies a preset condition, the LLR corresponding to the bit to be decoded is divided into p. Sub-segments, respectively, performing p-rate matching on p sub-segments, where p is an integer greater than or equal to 2;
  • the decoding unit 1403 is configured to perform independent SCL decoding on the LLRs of the p-sub-segments after the de-rate matching, to obtain decoding results of the p sub-segments;
  • the output unit 1404 combines the decoding results of the p sub-segments and outputs a decoding bit sequence.
  • FIG. 15 is a schematic structural diagram of a decoding apparatus 1500 provided by the present application.
  • the decoding apparatus 1500 includes:
  • a memory 1501 configured to store a program
  • the processor 1502 is configured to execute the program stored in the memory, and when the program is executed, receive a log likelihood ratio LLR corresponding to a bit to be decoded, and the bit length to be decoded is a target code length when encoding M; determining the mother code length N when encoding, when the target code length M is greater than the mother code length N, if the encoding parameter satisfies the preset condition, the LLR corresponding to the bit to be decoded is divided into p sub-segments, p pairs The segments are respectively subjected to de-rate matching; the LLRs of the p-sub-segments after the de-rate matching are respectively subjected to independent SCL decoding to obtain decoding results of p sub-segments; the decoding results of p sub-segments are combined, and the decoding bit sequence is outputted. Where p is an integer greater than or equal to 2.
  • FIG. 16 is a schematic structural diagram of a decoding apparatus 1600 provided by the present application.
  • the decoding apparatus 1600 includes:
  • the at least one input end 1601 is configured to receive a log likelihood ratio LLR corresponding to the bit to be decoded, and the bit length to be decoded is a target code length M when encoding;
  • the signal processor 1602 is configured to receive a log likelihood ratio LLR corresponding to the bit to be decoded, the bit length to be decoded is a target code length M when encoding, and determine a mother code length N when encoding, when the target code length When M is greater than the length of the mother code N, if the coding parameter satisfies the preset condition, the LLR corresponding to the bit to be decoded is divided into p sub-segments, and p sub-segments are respectively subjected to de-rate matching; p sub-segments after de-rate matching
  • the LLRs are separately decoded by SCL to obtain decoding results of p sub-segments; the decoding results of p sub-segments are combined, and a decoding bit sequence is output, where p is an integer greater than or equal to 2;
  • At least one output 1603 is configured to output a decoded bit sequence obtained by the signal processor.
  • the code lengths of the optional p sub-segments are N1, N2, ..., Np, and the target code lengths are M1, M2, ..., Mp, respectively.
  • the corresponding information bit length is K1, K2. ,...,Kp;
  • the LLR sequence of the sub-segment corresponding to Mi is further divided into p sub-segments for de-rate matching and decoding, and the decoding results of the corresponding p sub-segments are obtained, and the decoding results of the p sub-segments are combined to obtain the corresponding Ki.
  • Information bits or
  • the signal processor 1602 is further configured to: when the target code length M is smaller than the mother code length N, recover the LLR of the punched or shortened position, and obtain the LLR of length N after the de-rate matching. The sequence is decoded and a decoded bit sequence is obtained.
  • the decoding device of Figures 14-16 of the present application may be any device having wireless communication capabilities, such as an access point, a site, a user equipment, a base station, and the like.
  • an access point such as an access point, a site, a user equipment, a base station, and the like.
  • the encoding method or the decoding method of the present application can be implemented in hardware or a combination of hardware and software.
  • the communication device in the communication system has a transceiving function at the same time, which can serve as a transmitting end to send information to the receiving end, and can also serve as a receiving end to receive information sent by the transmitting end. Therefore, the communication device has an encoding function and a decoding function.
  • the communication device can be configured as a general purpose processing system, such as generally referred to as a chip, the general purpose processing system comprising: one or more microprocessors providing processor functionality; and external memory providing at least a portion of a storage medium, all of which can be passed
  • the external bus architecture is connected to other support circuits.
  • the communication device can include an ASIC (application specific integrated circuit) having a processor, a bus interface, a user interface, and at least a portion of a storage medium integrated in a single chip.
  • the communication device is comprised of one or more FPGAs (Field Programmable Gate Arrays), PLDs (Programmable Logic Devices), controllers, state machines, gate logic, discrete hardware components, any other suitable circuitry, or capable of performing the present application. Any combination of circuits of various functions described throughout.
  • FIG. 17 is a schematic structural diagram of a communication device 1700 according to an embodiment of the present application (for example, an access device such as an access point, a base station, a station, or a terminal).
  • the communication device 1700 can be implemented by the bus 1701 as a general bus architecture.
  • bus 1701 may include any number of interconnecting buses and bridges.
  • Bus 1701 connects various circuits together, including processor 1702, storage medium 1703, and bus interface 1704.
  • the storage medium is used to store an operating system and data to be transmitted and received data.
  • the communication device 1700 connects the network adapter 1705 or the like via the bus interface 1704 via the bus 1701.
  • the network adapter 1705 can be used to implement signal processing functions of the physical layer in the wireless communication network and to transmit and receive radio frequency signals through the antenna 1707.
  • User interface 1706 can interface with various user input devices such as a keyboard, display, mouse, or joystick.
  • the bus 1701 can also be connected to various other circuits, such as timing sources, peripherals, voltage regulators, or power management circuits, etc., which are well known in the art and therefore will not be described in detail.
  • the processor 1702 is responsible for managing the bus and general processing (including executing software stored on the storage medium 1203).
  • the processor 1702 can be implemented using one or more general purpose processors and/or special purpose processors. Examples of processors include microprocessors, microcontrollers, DSP processors, and other circuits capable of executing software.
  • Software should be interpreted broadly to mean instructions, data, or any combination thereof, whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise.
  • Storage medium 1703 is shown separated from processor 1702 in FIG. 17, however, it will be readily apparent to those skilled in the art that storage medium 1703, or any portion thereof, can be located external to communication device 1700.
  • storage medium 1703 can include transmission lines, carrier waveforms modulated with data, and/or computer products separate from wireless nodes, all of which can be accessed by processor 1702 via bus interface 1704.
  • storage medium 1703, or any portion thereof, may be integrated into processor 1702, for example, may be a cache and/or a general purpose register.
  • the processor 1702 can be used to perform the functions of the processor 1201 and the processor of Figures 12 and 15.
  • the processor 1702 can perform the encoding method and the decoding method described in this application, and the execution process of the processor 1702 is not described herein again.
  • serial cancellation list SCL decoding algorithm in the embodiment of the present application includes other SCL-like decoding algorithms that sequentially decode, provide multiple candidate paths, or an improved algorithm for the SCL decoding algorithm.
  • the encoding device or the decoding device in the embodiment of the present application may be separate devices in actual use; or may be integrated devices for transmitting information to be sent after being encoded, or receiving information. Perform decoding.
  • the unit and method processes of the examples described in the embodiments of the present application can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the solution. The skilled person can use different methods for each particular application to implement the described functionality.
  • the disclosed apparatus and method may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division, and the actual implementation may have another division manner.
  • multiple units or components may be combined or integrated into another system. Some of the steps in the method can be ignored or not executed.
  • the coupling or direct coupling or communication connection of the various units to one another may be achieved through some interfaces, which may be in electrical, mechanical or other form.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above embodiments it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof.
  • software it may be implemented in whole or in part in the form of a computer program product.
  • the computer program product includes one or more computer instructions.
  • the computer program instructions When the computer program instructions are loaded and executed on a computer, the processes or functions described in accordance with embodiments of the present invention are generated in whole or in part.
  • the computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable device.
  • the computer instructions can be stored in or transmitted by a computer readable storage medium.
  • the computer instructions can be from a website site, computer, server or data center to another website site by wire (eg, coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (eg, infrared, wireless, microwave, etc.) Transfer from a computer, server, or data center.
  • wire eg, coaxial cable, fiber optic, digital subscriber line (DSL)
  • wireless eg, infrared, wireless, microwave, etc.
  • the computer readable storage medium can be any available media that can be accessed by a computer or a server, data center, or equivalent data storage device that includes one or more available media.
  • the usable medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape, a USB flash drive, a ROM, a RAM, etc.), an optical medium (eg, a CD, a DVD, etc.), or a semiconductor medium (eg, a solid state hard disk Solid State Disk (SSD) ))Wait.
  • a magnetic medium eg, a floppy disk, a hard disk, a magnetic tape, a USB flash drive, a ROM, a RAM, etc.
  • an optical medium eg, a CD, a DVD, etc.
  • a semiconductor medium eg, a solid state hard disk Solid State Disk (SSD)

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Abstract

本申请实施例提供Polar编码方法和编码装置。该方法包括：获取待发送的信息块和Polar码的目标码长M；确定Polar编码采用的母码码长N，当所述目标码长M大于N，若所述信息块的编码参数满足预设的条件，将待编码的信息比特序列分成p个子段，对P个子段分别进行独立的Polar编码，得到p个长度为分别子段母码长度的编码比特序列，对p个编码结果分别进行速率匹配，得到p个长度分别为子段的目标码长的编码比特序列；合并速率匹配后的p个编码比特序列，得到长度为M的编码比特序列；其中p为大于等于2的整数。该编码方法能减少重复的速率匹配方案的使用次数，减少重复带来的性能损失。

Description

一种数据传输方法及相关设备
本申请要求于2017年03月24日提交中国专利局、申请号为201710184922.6、申请名称为“Ploar编码方法和编码装置、译码方法和译码装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明实施例涉及通信领域，并且更具体地，Ploar编码方法和编码装置、译码方法和译码装置。
背景技术
通信***通常采用信道编码提高数据传输的可靠性，以保证通信的质量。土耳其教授Arikan提出的极化码(Polar codes)是第一个理论上证明可以达到香农容量且具有低编译码复杂度的好码。Polar码是一种线性块码，其编码矩阵为G N，编码过程为
Figure PCTCN2018080394-appb-000001
其中
Figure PCTCN2018080394-appb-000002
是一个二进制的行矢量，长度为N(即母码长度)；G N是一个N×N的矩阵，且
Figure PCTCN2018080394-appb-000003
定义为log 2N个矩阵F 2的克罗内克(Kronecker)乘积。
上述矩阵
Figure PCTCN2018080394-appb-000004
Polar码的编码过程中，
Figure PCTCN2018080394-appb-000005
中的一部分比特用来携带信息，称为信息比特，这些比特的索引的集合记作
Figure PCTCN2018080394-appb-000006
另外的一部分比特设置为收发端预先约定的固定值，称之为固定比特或冻结比特(frozen bits)，其索引的集合用
Figure PCTCN2018080394-appb-000007
的补集
Figure PCTCN2018080394-appb-000008
表示。Polar码的编码过程相当于：
Figure PCTCN2018080394-appb-000009
这里，G N.(A)是G N.中由集合A中的索引对应的那些行得到的子矩阵，G N(A C)是G N中由集合A C中的索引对应的那些行得到的子矩阵。
Figure PCTCN2018080394-appb-000010
为
Figure PCTCN2018080394-appb-000011
中的信息比特集合，信息比特个数为K；
Figure PCTCN2018080394-appb-000012
为
Figure PCTCN2018080394-appb-000013
中的固定比特集合，固定比特个数为(N-K)，是已知比特。这些固定比特通常被设置为0，但是只要收发端预先约定，固定比特可以被任意设置。固定比特设置为0时，Polar码的编码输出可简化为：
Figure PCTCN2018080394-appb-000014
是一个K×N的矩阵。
Polar码的构造过程即集合
Figure PCTCN2018080394-appb-000015
的选取过程，决定了Polar码的性能。Polar码的构造过程通常是，根据母码码长N确定共存在N个极化信道，分别对应编码矩阵的N个行，计算极化信道可靠度，将可靠度较高的前K个极化信道的索引作为集合A的元素，剩余(N-K)个极化信道对应的索引作为固定比特的索引集合
Figure PCTCN2018080394-appb-000016
的元素。集合A决定了信息比特的位置，集合
Figure PCTCN2018080394-appb-000017
决定了固定比特的位置。
从编码矩阵可以看出，原始Polar码(母码)的码长为2的整数次幂，在实际应用中需要通过速率匹配实现任意码长的Polar码。
目前Polar码的速率匹配方案主要有三种，分别是打孔(Puncture)缩短(Shorten)和重复(Repetition)。在前两种方案中，确定母码长度为大于等于目标码长M的2的整数次幂，根据预设的规则确定打孔或者缩短位置，在发送时删除对应位置的编码比特，实现速率匹配。译码前根据预定的规则将对应位置的对数似然比LLR恢复，实现解速率匹配。
为了平衡编码性能和复杂度，通信***中可能根据约定的规则确定采用重复的速率匹配方案。对以母码长度编码的Polar码进行重复，获得大于母码长度的目标码长，从而实现Polar码的速率匹配。与打孔或缩短不同的是，重复通过对已编码为母码长度的编码比特序列按照特定顺序重复发送，直到达到目标码长，实现速率匹配。在译码端，通过对重复位置的LLR进行合并，从而实现解速率匹配，并以确定的母码长度进行译码。采用重复的方式进行速率匹配可以降低译码复杂度、减少时延，并能减小硬件实现面积。但是，在某些情况下重复对Polar码的性能会造成一定的损失。
发明内容
本申请实施例提供编码方法及编码装置、译码方法及译码装置，能减少重复的速率匹配方案的使用次数，减少重复带来的性能损失。
第一方面，提供一种Polar编码方法，包括：
获取待发送的信息块和Polar码的目标码长M；
确定Polar编码采用的母码码长N，当所述目标码长M大于N，若所述信息块的编码参数满足预设的条件，将待编码的信息比特序列分成p个子段，对P个子段分别进行独立的Polar编码，得到p个长度为分别子段母码长度的编码比特序列，其中p为大于等于2的整数；对p个编码结果分别进行速率匹配，得到p个长度分别为子段的目标码长的编码比特序列；合并速率匹配后的p个编码比特序列，得到长度为M的编码比特序列。
在第一方面的第一种可能的实施方式中，若所述信息块的编码参数不满足所述预设的条件，采用所述母码码长N对待编码的信息比特序列进行Polar编码，得到长度为N的第一编码比特序列，重复所述第一编码比特序列中的至少一部分比特，得到长度为M的编码比特序列；
在第一方面的第二种可能的实施方式中，若所述目标码长M小于等于所述母码长度N，采用母码长度N对所述待编码的信息比特序列进行Polar编码得到第二编码比特序列，对所述第二编码比特序列进行缩短或者打孔，得到长度为M的编码比特序列。
结合第一方面及其第一方面的前述的所有可能的实现方式，在第一方面的第三种可能的实现方式中，待编码的信息比特序列总长度为Kc，p个子段的信息比特长度分别为K1，K2，...，Kp，p个子段分别进行独立Polar编码采用的母码长度分别为N1，N2，...，Np，对应的目标码长分别为M1，M2，...，Mp，其中Kc＝K1+K2,+...,+Kp，M＝M1+M2,+...,+Mp，所述待编码的信息比特序列包括所述信息块，Kc大于等于所述信息块的长度K；对于每个Mi，若Mi对应的子段的目标码长Mi大于母码长度Ni，且Ki对应的子段的编码参数满足所述预设的条件，将Mi对应的子段进一步划分为p个子段分别进行独立的编码和速率匹配，得到对应的p个编码比特序列并进行合并，得到目标码长Mi的编码比特序列，其中，i＝1,2,...,p。
结合第一方面的第三种可能的实现方式，在第一方面的第四种可能的实现方式中，若目标码长Mi大于母码长度Ni，且Mi对应子段的编码参数不满足所述预设的条件，采用母码长度Ni对Mi对应的子段进行Polar编码，得到长度为Ni的第三编码比特序列，重复所述第三编码比特序列中的至少一部分比特，得到长度为Mi的编码序列；或者若目标码长Mi小于等于母码长度Ni，采用母码长度Ni对Ki对应的子段进行Polar编码得到第四编码比特序列，对所述第四编码比特序列进行缩短或者打孔，得到长度为Mi的编码序列。
第二方面，提供一种编码装置，包括：
获取单元，用于获取待发送的信息块和Polar码的目标码长M；
编码单元，确定Polar编码采用的母码码长N，当所述目标码长M大于N，若所述信息块的编码参数满足预设的条件，将待编码的信息比特序列分成p个子段，对P个子段分别进行独立的Polar编码，得到p个长度为分别子段母码长度的编码比特序列，其中p为大于等于2的整数；速率匹配单元，用于对p个编码结果分别进行速率匹配，得到p个长度分别为子段的目标码长的编码比特序列；合并单元，用于合并合并所述速率匹配后的p个编码比特序列，得到长度为M的编码比特序列。
在第二方面的第一种可能的实现方式中，所述编码单元用于，若所述信息块的编码参数不满足所述预设的条件，采用所述母码码长N对待编码的信息比特序列进行Polar编码，得到长度为N的第一编码比特序列；所述速率匹配单元用于重复所述第一编码比特序列中的至少一部分比特，得到长度为M的编码比特序列；或
在第二方面的第二种可能的实现方式中，所述编码单元用于，若所述目标码长M小于等于所述母码长度N，采用母码长度N对所述待编码的信息比特序列进行Polar编码得到第二编码比特序列；所述速率匹配单元用于对所述第二编码比特序列进行缩短或者打孔，得到长度为M的编码比特序列。
结合第二方面及其第二方面的前述的所有可能的实现方式，在第二方面的第三种可能的实现方式中，所述编码单元用于，若目标码长Mi大于母码长度Ni，且Mi对应子段的编码参数不满足所述预设的条件，采用母码长度Ni对Mi对应的子段进行Polar编码，得到长度为Ni的第三编码比特序列；所述速率匹配单元用于重复所述第三编码比特序列中的至少一部分比特，得到长度为Mi的编码序列；或者所述编码单元用于，若目标码长Mi小于等于母码长度Ni，采用母码长度Ni对Ki对应的子段进行Polar编码得到第四编码比特序列；所述速率匹配单元用于对所述第四编码比特序列进行缩短或者打孔，得到长度为Mi的编码序列。
第三方面，提供又一种编码装置，包括：
存储器，用于存储程序；处理器，用于执行所述存储器存储的所述程序，当所述程序被执行时，获取待发送的信息块和Polar码的目标码长M；确定Polar编码采用的母码码长N，当所述目标码长M大于N，若所述信息块的编码参数满足预设的条件，将待编码的信息比特序列分成p个子段，对P个子段分别进行独立的Polar编码，得到p个长度为分别子段母码长度的编码比特序列，其中p为大于等于2的整数；对p个编码结果分别进行速率匹配，得到p个长度分别为子段的目标码长的编码比特序列；合并所述速率匹配后的p个编码比特序列，得到长度为M的编码比特序列。
在第三方面的第一种可能的实施方式中，所述处理器用于，若所述信息块的编码参数不满足所述预设的条件，采用所述母码码长N对待编码的信息比特序列进行Polar编码，得到长度为N的第一编码比特序列，重复所述第一编码比特序列中的至少一部分比特，得到长度为M的编码比特序列。
在第三方面的第二种可能的实施方式中，所述处理器用于，若所述目标码长M小于等于所述母码长度N，采用母码长度N对所述待编码的信息比特序列进行Polar编码得到第二编码比特序列，对所述第二编码比特序列进行缩短或者打孔，得到长度为M的编码比特序列。
结合第三方面及其第三方面的前述的所有可能的实现方式，在第三方面的第三种可能的实现方式中，待编码的信息比特序列总长度为Kc，p个子段的信息比特长度分别为K1，K2，...，Kp，p个子段分别进行独立Polar编码采用的母码长度分别为N1，N2，...，Np，对应的目标码长分别为M1，M2，...，Mp，其中Kc＝K1+K2,+...,+Kp，M＝M1+M2,+...,+Mp，所述待编码的信息比特序列包括所述信息块，Kc大于等于所述信息块的长度K；所述处理器用于，对于每个Mi，若Mi对应的子段的目标码长Mi大于母码长度Ni，且Ki对应的子段的编码参数满足所述预设的条件，将Mi对应的子段进一步划分为p个子段分别进行独立的编码和速率匹配，得到对应的p个编码比特序列并进行合并，得到目标码长Mi的编码比特序列，其中，i＝1,2,...,p。
第四方面，提供又一种编码装置，其特征在于，包括：
至少一个输入端，用于接收信息块；信号处理器，用于获取待发送的信息块和Polar 码的目标码长M；确定Polar编码采用的母码码长N，当所述目标码长M大于N，若所述信息块的编码参数满足预设的条件，将待编码的信息比特序列分成p个子段，对P个子段分别进行独立的Polar编码，得到p个长度为分别子段母码长度的编码比特序列，其中p为大于等于2的整数；对p个编码结果分别进行速率匹配，得到p个长度分别为子段的目标码长的编码比特序列；合并所述速率匹配后的p个编码比特序列，得到长度为M的编码比特序列；至少一个输出端，用于输出信号处理器得到的编码比特序列。
在第四方面的第一种可能的实现方式中，所述信号处理器用于，若所述信息块的编码参数不满足所述预设的条件，采用所述母码码长N对待编码的信息比特序列进行Polar编码，得到长度为N的第一编码比特序列，重复所述第一编码比特序列中的至少一部分比特，得到长度为M的编码比特序列。
在第四方面的第二种可能的实现方式中，所述信号处理器用于，若所述目标码长M小于等于所述母码长度N，采用母码长度N对所述待编码的信息比特序列进行Polar编码得到第二编码比特序列，对所述第二编码比特序列进行缩短或者打孔，得到长度为M的编码比特序列。
结合第四方面及其第四方面的前述的所有可能的实现方式，在第四方面的第三种可能的实现方式中，待编码的信息比特序列总长度为Kc，p个子段的信息比特长度分别为K1，K2，...，Kp，p个子段分别进行独立Polar编码采用的母码长度分别为N1，N2，...，Np，对应的目标码长分别为M1，M2，...，Mp，其中Kc＝K1+K2,+...,+Kp，M＝M1+M2,+...,+Mp，所述待编码的信息比特序列包括所述信息块，Kc大于等于所述信息块的长度K；所述信号处理器用于，对于每个Mi，若Mi对应的子段的目标码长Mi大于母码长度Ni，且Ki对应的子段的编码参数满足所述预设的条件，将Mi对应的子段进一步划分为p个子段分别进行独立的编码和速率匹配，得到对应的p个编码比特序列并进行合并，得到目标码长Mi的编码比特序列，其中，i＝1,2,...,p。
第五方面提供一种Polar码译码方法，包括：
接收待译码比特对应的对数似然比LLR，待译码比特长度为编码时的目标码长M；确定编码时的母码长度N，当所述目标码长M大于母码长度N时，若编码参数满足预设的条件，将待译码比特对应的LLR分成p个子段，对p个子段并分别进行解速率匹配，其中p为大于等于2的整数；对解速率匹配后的p个子段的LLR分别进行独立SCL译码，得到p个子段的译码结果；合并p个子段的译码结果，输出译码比特序列。
在第五方面的第一种可能的实施方式中，p个子段的编码时采用的母码长度分别为N1，N2，...，Np，目标码长分别为M1，M2，...，Mp，对应的信息比特长度为K1，K2，...，Kp；对于每个子段Mi，i＝1,2,...,p，若Mi大于母码长度Ni，且Mi对应的子段的编码参数满足所述预设的条件，将Mi对应的子段的LLR序列进一步划分为p个子段分别进行解速率匹配并译码，得到对应的p个子段的译码结果，合并p个子段的译码结果得到对应的Ki个信息比特；或者对于每个子段Mi，i＝1,2,...,p，若Mi小于母码长度Ni，且Mi对应的子段的编码参数不满足所述预设的条件，将重复位置的LLR进行叠加，得到解速率匹配后的长度为Ni的LLR序列并进行译码，得到子段Mi的译码结果。
在第五方面的第二种可能的实施方式中，，当所述目标码长M小于母码长度N时，将打孔或者缩短位置的LLR进行恢复，得到解速率匹配后的长度为N的LLR序列并译码， 得到译码比特序列。
第六方面，提供一种译码装置，包括：
接收单元，用于接收待译码比特对应的对数似然比LLR，待译码比特长度为编码时的目标码长M；解速率匹配单元，用于确定编码时的母码长度N，当所述目标码长M大于母码长度N时，若编码参数满足预设的条件，将待译码比特对应的LLR分成p个子段，对p个子段并分别进行解速率匹配，其中p为大于等于2的整数；译码单元，用于对p个子段的LLR分别进行独立SCL译码，得到p个子段的译码结果；输出单元，合并p个子段的译码结果，输出译码比特序列。
在第六方面的第一种可能的实现方式中，p个子段的编码时采用的母码长度分别为N1，N2，...，Np，目标码长分别为M1，M2，...，Mp，对应的信息比特长度为K1，K2，...，Kp；所述解速率匹配单元用于，对于每个子段Mi，i＝1,2,...,p，若Mi大于母码长度Ni，且Mi对应的子段的编码参数满足所述预设的条件，将Mi对应的子段的LLR序列进一步划分为p个子段分别进行解速率匹配，所述译码单元用于对p个解速率匹配后的LLR并译码，得到对应的p个子段的译码结果，所述合并单元用于合并p个子段的译码结果得到对应的Ki个信息比特；或者所述速率匹配单元用于，对于每个子段Mi，i＝1,2,...,p，若Mi小于母码长度Ni，且Mi对应的子段的编码参数不满足所述预设的条件，将重复位置的LLR进行叠加，得到速率匹配后的长度为Ni的LLR序列；所述译码单元用于对长度为Ni的LLR序列进行译码，得到子段Mi的译码结果。
在第六方面的第二种可能的实现方式中，所述解速率匹配单元，当所述目标码长M小于母码长度N时，将打孔或者缩短位置的LLR进行恢复，得到速率匹配后的长度为N的LLR序列，所述译码单元用于对长度为N的LLR序列进行译码，得到译码比特序列。
第七方面，提供一种译码装置，包括：
存储器，用于存储程序；处理器，用于执行所述存储器存储的所述程序，当所述程序被执行时，接收待译码比特对应的对数似然比LLR，待译码比特长度为编码时的目标码长M；确定编码时的母码长度N，当所述目标码长M大于母码长度N时，若编码参数满足预设的条件，将待译码比特对应的LLR分成p个子段，对p个子段并分别进行解速率匹配；对p个子段的LLR分别进行独立SCL译码，得到p个子段的译码结果；合并p个子段的译码结果，输出译码比特序列，其中p为大于等于2的整数。
在第七方面的第一种可能的实现方式中，p个子段的编码时采用的母码长度分别为N1，N2，...，Np，目标码长分别为M1，M2，...，Mp，对应的信息比特长度为K1，K2，...，Kp；所述处理器用于，对于每个子段Mi，i＝1,2,...,p，若Mi大于母码长度Ni，且Mi对应的子段的编码参数满足所述预设的条件，将Mi对应的子段的LLR序列进一步划分为p个子段分别进行解速率匹配并译码，得到对应的p个子段的译码结果，合并p个子段的译码结果得到对应的Ki个信息比特；或者所述处理器用于，对于每个子段Mi，i＝1,2,...,p，若Mi小于母码长度Ni，且Mi对应的子段的编码参数不满足所述预设的条件，将重复位置的LLR进行叠加，得到解速率匹配后的长度为Ni的LLR序列并进行译码，得到子段Mi的译码结果。
在第七方面的第二种可能的实现方式中，所述处理器用于，当所述目标码长M小于母码长度N时，将打孔或者缩短位置的LLR进行恢复，得到解速率匹配后的长度为N的LLR序列并译码，得到译码比特序列。
第八方面，提供一种译码装置，包括：
至少一个输入端，用于接收待译码比特对应的对数似然比LLR，待译码比特长度为编码时的目标码长M；信号处理器，用于接收待译码比特对应的对数似然比LLR，待译码比特长度为编码时的目标码长M；确定编码时的母码长度N，当所述目标码长M大于母码长度N时，若编码参数满足预设的条件，将待译码比特对应的LLR分成p个子段，对p个子段并分别进行解速率匹配；对解速率匹配后的p个子段的LLR分别进行独立SCL译码，得到p个子段的译码结果；合并p个子段的译码结果，输出译码比特序列，其中p为大于等于2的整数；至少一个输出端，用于输出信号处理器得到的译码比特序列。
在第八方面的第一种可能的实现方式中，p个子段的编码时采用的母码长度分别为N1，N2，...，Np，目标码长分别为M1，M2，...，Mp，对应的信息比特长度为K1，K2，...，Kp；所述信号处理器用于，对于每个子段Mi，i＝1,2,...,p，若Mi大于母码长度Ni，且Mi对应的子段的编码参数满足所述预设的条件，将Mi对应的子段的LLR序列进一步划分为p个子段分别进行解速率匹配并译码，得到对应的p个子段的译码结果，合并p个子段的译码结果得到对应的Ki个信息比特；或者所述信号处理器用于，对于每个子段Mi，i＝1,2,...,p，若Mi小于母码长度Ni，且Mi对应的子段的编码参数不满足所述预设的条件，将重复位置的LLR进行叠加，得到解速率匹配后的长度为Ni的LLR序列并进行译码，得到子段Mi的译码结果。
在第八方面的第二种可能的实现方式中，所述信号处理器用于，当所述目标码长M小于母码长度N时，将打孔或者缩短位置的LLR进行恢复，得到解速率匹配后的长度为N的LLR序列并译码，得到译码比特序列。
在以上任意方面或任意实现方式中，所述编码参数包括以下中的一种：编码码率R待编码的信息比特序列长度Kc、信息块的长度K或目标码长M；所述预设条件包括以下中的任意一种：对于给定的编码码率R，待编码的信息比特序列长度Kc大于预设的阈值；对于给定的编码码率R，所述信息块的长度K大于预设的阈值；或对于给定的编码码率R，目标码长M大于预设的阈值。
在以上任意方面或任意实现方式中，确定母码长度
Figure PCTCN2018080394-appb-000018
表示向上取整，min(·)表示取最小值，N max表示***支持的最大母码长。
以p＝2，Nmax＝1024，Polar编码为PC-Polar编码为例，所述预设条件为以下中的一种：
对于R＝1/12，所述待编码的信息比特序列长度Kc预设阈值Kc1，Kc1属于区间[330,370]的整数；
对于R＝1/6，所述待编码的信息比特序列长度Kc大于预设阈值Kc2，Kc2属于区间[345,365]的整数；
对于R＝1/4，所述待编码的信息比特序列长度Kc大于预设阈值Kc3，Kc3属于区间[370,380]的整数；
对于R＝1/3，所述待编码的信息比特序列长度Kc大于预设阈值Kc4，Kc4属于区间[450,460]的整数；
对于R＝2/5，所述待编码的信息比特序列长度Kc大于预设阈值Kc5，Kc5属于区间[500,510]的整数；
对于R＝1/12，所述信息块的长度K大于预设阈值Kt1，Kt1属于区间[314-354]的整数；
对于R＝1/6，所述信息块的长度K大于预设阈值Kt2，Kt2属于区间[329-349]的整数；
对于R＝1/4，所述信息块的长度K大于预设阈值Kt3，Kt3属于区间[354-364]的整数；
对于R＝1/3，所述信息块的长度K大于预设阈值Kt4，Kt4属于区间[434-444]的整数；
对于R＝2/5，所述信息块的长度K大于预设阈值Kt5，Kt5属于区间[484-494]的整数；
对于R＝1/12，所述目标码长M大于预设阈值Mt1，Mt1属于区间[3768-4248]的整数；
对于R＝1/6，所述目标码长M大于预设阈值Mt2，Mt2属于区间[1974-2094]的整数；
对于R＝1/4，所述目标码长M大于预设阈值Mt3，Mt3属于区间[1416-1456]的整数；
对于R＝1/3，所述目标码长M大于预设阈值Mt4，Mt4属于区间[1302-1332]的整数；或
对于R＝2/5，所述目标码长M大于预设阈值Mt5，Mt5属于区间[1210-1235]的整数。
在一个例子中，上述阈值可以为以下中的任意一个：Kc1＝360，Kc2＝360，Kc3＝380，Kc4＝460，Kc5＝510；Kt1＝344，Kt2＝344，Kt3＝364，Kt4＝444，Kt5＝494；Mt1＝4128，Mt2＝2064，Mt3＝1456，Mt4＝1332，或Mt5＝1235。
以p＝2，Nmax＝1024，Polar编码为CA-Polar编码，所述预设条件为以下中的一种：
对于R＝1/12，所述待编码的信息比特序列长度Kc预设阈值Kc1，Kc1属于区间[310-340]的整数；
对于R＝1/6，所述待编码的信息比特序列长度Kc大于预设阈值Kc2，Kc2属于区间[350-365]的整数；
对于R＝1/4，所述待编码的信息比特序列长度Kc大于预设阈值Kc3，Kc3属于区间[410-450]的整数；
对于R＝1/3，所述待编码的信息比特序列长度Kc大于预设阈值Kc4，Kc4属于区间[470-495]的整数；
对于R＝2/5，所述待编码的信息比特序列长度Kc大于预设阈值Kc5，Kc5属于区间[520-530]的整数；
对于R＝1/12，所述信息块的长度K大于预设阈值Kt1，Kt1属于区间[291-321]的整数；
对于R＝1/6，所述信息块的长度K大于预设阈值Kt2，Kt2属于区间[331-346]的整数；
对于R＝1/4，所述信息块的长度K大于预设阈值Kt3，Kt3属于区间[391-431]的整数；
对于R＝1/3，所述信息块的长度K大于预设阈值Kt4，Kt4属于区间[451-476]的整数；
对于R＝2/5，所述信息块的长度K大于预设阈值Kt5，Kt5属于区间[501-511]的整数；
对于R＝1/12，所述目标码长M大于预设阈值Mt1，Mt1属于区间[3492-3852]的整数；
对于R＝1/6，所述目标码长M大于预设阈值Mt2，Mt2属于区间[1986-2076]的整数；
对于R＝1/4，所述目标码长M大于预设阈值Mt3，Mt3属于区间[1564-1724]的整数；
对于R＝1/3，所述目标码长M大于预设阈值Mt4，Mt4属于区间[1353-1428]的整数；或
对于R＝2/5，所述目标码长M大于预设阈值Mt5，Mt5属于区间[1253-1278]的整数。
在一个例子中，上述阈值可以为以下中的任意一个：Kc1＝320，Kc2＝360，Kc3＝430，Kc4＝490，Kc5＝530；Kt1＝301，Kt2＝341，Kt3＝411，Kt4＝471，Kt5＝511；Mt1＝3612，Mt2＝2046，Mt3＝1644，Mt4＝1413，或Mt5＝1278。
第九方面，提供一种通信装置，包括：总线、处理器、存储介质、总线接口、网络适配器、用户接口、天线；
所述总线，用于连接处理器、存储介质、总线接口和用户接口；
所述处理器，用于执行第一方面的编码方法或其任意一种实现方式，或用于执行第五方面的译码方法或其任意一种实现方式，。
所述存储介质，用于存储操作***，以及待发送或接收的数据
所述总线接口，连接网络适配器；
所述网络适配器，用于实现无线通信网络中物理层的信号处理功能；
所述用户接口，用于连接用户输入设备；
所述天线，用于信号的发送和接收。
本申请的又一方面提了供一种计算机可读存储介质，所述计算机可读存储介质中存储有指令，当其在计算机上运行时，使得计算机执行上述各方面所述的方法。
本申请的又一方面提供了一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行上述各方面所述的方法。
本申请的又一方面提供了一种计算机程序，当其在计算机上运行时，使得计算机执行上述各方面所述的方法。
本申请实施例中，当目标码长超过根据约定规则确定的母码长度的时候，若编码参数满足预设的条件，对待编码的信息比特序列进行分段独立编码，减少了重复速率匹配方法的使用概率，降低了重复带来的性能损失。
附图说明
图1是无线通信发送端和接收端的基本流程示意图；
图2所示为本申请实施例提供的编码方法流程示意图；
图3所示为本申请实施例提供的编码方法流程示意图；
图4为Arikan Polar的编码方法和译码方法流程示意图；
图5为PC-Polar的编码方法和译码方法流程示意图；
图6为PC-CA-SCL译码方法流程示意图；
图7为普通PC-Polar编码和分段PC-Poar编码的译码性能对比图；
图8为CA-Polar的编码方法和译码方法流程示意图；
图9为另一种CA-Polar的编码方法和译码方法流程示意图；
图10为又一种CA-Polar的编码方法和译码方法流程示意图；
图11为本申请实施例的一种编码装置1100的结构示意图；
图12为本申请实施例提供的另外一种编码装置1200的结构示意图；
图13为本申请实施例提供的另外一种编码装置1300的结构示意图；
图14为本申请实施例提供的一种译码装置1400的结构示意图；
图15为本申请实施例提供的一种译码装置1500的结构示意图；
图16为本申请实施例提供的一种译码装置1600的结构示意图；
图17为本申请实施例提供的一种通信装置1700的结构示意图。
具体实施方式
图1是无线通信的基本流程，在发送端，信源依次信源编码、信道编码、数字调制后发出。在接收端，依次通过数字解调、信道解码、信源解码输出信宿。信道编解码可以采用Polar码，由于原始Polar码(母码)的码长为2的整数次幂，在实际应用中需要通过速率匹配实现任意码长的Polar码。图1所示的，在发送端在信道编码后进行速率匹配实现任意的目标码长，在接收端，信道解码之前先进行解速率匹配。
本申请实施例的技术方案可以应用5G通信***，也可以用于其他各种通信***，例如：全球移动通讯(GSM，Global System of Mobile communication)***、码分多址(CDMA，Code Division Multiple Access)***、宽带码分多址(WCDMA，Wideband Code Division Multiple Access)***、通用分组无线业务(GPRS，General Packet Radio Service)长期演进(LTE，Long Term Evolution)***、LTE频分双工(FDD，Frequency Division Duplex)***、LTE时分双工(TDD，Time Division Duplex)通用移动通信***(UMTS，Universal Mobile Telecommunication System)等。
在某些情况下，通信***中通常会根据约定的规则确定一个母码长度，当确定的母码长度大于目标码长的时候，可以通过缩短或者打孔的速率匹配方案实现速率匹配。当确定的母码长度小于目标码长的时候，可以通过重复的速率匹配方案进行速率匹配，重复的方案会带来性能损失。某些通信***还会规定Polar码采用的最大母码长度，例如规定通信***中下行最大母码长度为512，上行最大母码长度为1024之类的。由于Polar码编码有最大母码长度的限制，在目标码长大于Nmax时，单纯重复发送码长为Nmax的Polar码会带来性能损失，且重复的比特越多损失越大。
对Polar码进行分段编码再合并虽然也会带来性能损失，但是一定条件下(例如母码码率即K/N较大时)，分段编码带来的编码增益将会在一定程度上弥补分段编码带来的损失，因此在一定条件下(例如大于一定母码码率时)分段编码性能将优于重复速率匹配方案。
本申请在编码参数满足预设的条件下，采用将待编码的信息比特进行分段编码，降低现有速率匹配方案(重复)对Polar码性能造成的损失。对于目标码长M小于母码长度的情况，可以按照母码长度N进行Polar编码，得到长度为N的编码比特序列，然后通过打孔或者缩短，得到长度为M的编码比特序列。
如图2所示为本申请实施例提供的编码方法流程示意图，该方法包括：
201、获取待发送的信息块和Polar码的目标码长M。
所述信息块的长度为K，编码码率为R，M＝INT(K/R)，INT表示取整。
203、确定母码码长N，当所述目标码长M大于步骤201确定的母码长度时，若所述信息块的编码参数满足预设的条件(也可以叫做分段编码条件)，将待编码的信息比特序列分成p个子段，并对p个子段分别进行独立编码，得到p个编码比特序列，其中，p为大于等于2的整数，待编码的信息比特序列总长度为Kc，p个子段的信息比特长度分别为K1，K2，...，Kp，其中Kc＝K1+K2,+...,+Kp。
具体的，对p个子段分别进行独立Polar编码后的目标码长分别为M1，M2，...，Mp，其中M＝M1+M2,+...,+Mp。根据确定M1，M2，...，Mp每个子段的母码长度分别N1，N2，...，Np，采用母码长度分别N1，N2，...，Np对p个子段分别进行Polar编码。
也就是说，对每个Mi，i＝1,2,...,p，当Mi>Ni时，采用母码码长Ni对Ki对应的子段进行Polar编码，得到长度为Ni的编码比特序列，则后续用采用重复的速率匹配方式。当Mi≤Ni时，采用母码码长Ni对Ki对应的子段进行编码，得到长度为Ni的编码序列，后续采用缩短或者打孔的速率匹配方案。
确定母码码长N有多种方式，下面介绍三种：
(1)若通信***中规定有最大母码长度Nmax，可以根据
Figure PCTCN2018080394-appb-000019
来确定母码长度的值。也就是说，当M>Nmax时，确定N＝Nmax按照传统的方式，采用母码长度N进行编码得到长度为N的编码比特序列，并通过重复至少一部分比特得到长度为M的编码比特序列。当M≤Nmax时，采用
Figure PCTCN2018080394-appb-000020
对进行编码得到长度为N的编码比特序列，采用缩短或者打孔的速率匹配方案，得到长度为M的编码比特序列，其中
Figure PCTCN2018080394-appb-000021
表示向上取整。
(2)N优先选择小于目标码长且满足母码码率小于等于码率门限的值，否则选择
Figure PCTCN2018080394-appb-000022
其中
Figure PCTCN2018080394-appb-000023
表示向上取整。母码码率门限定义为R0＝K/N，N＝2 n，n是小于等于log 2M的整数，K是信息块的长度。例如，码率门限可以设置为1/6或者1/4。假设码率门限为1/4，M＝288，K＝40，满足K/N小于1/4的N值为256，则取N＝256。若K＝80，找不到小于等于256的2的整数次幂的N值能符合80/N小于等于1/4的，则可以确定
Figure PCTCN2018080394-appb-000024
(3)N优先选择小于目标码长且满足M≤N*(1+δ)的值，否则选择
Figure PCTCN2018080394-appb-000025
其中
Figure PCTCN2018080394-appb-000026
表示向上取整。δ可以为常数，例如设置为1/8,1/4或3/8。δ也可以取与母码码率相关的值，δ＝FUNCTION(R0)，R0＝K/N，K是信息块的长度，一般随着R0的增加递减。δ关于码率R的函数可以设计为：δ＝β*(1-R0)，β为预设的常数，例如β可以为1/2，3/8，1/4，1/8或1/16等。也即是说，δ是R1的线性函数，R0越大，δ越小，即允许重复比特数量越少。δ关于码率R的函数可以设计为：δ＝β*(1-R0)^2，β是常数，例如β可以为1/2。即δ是R0的两次函数，R0越大，δ越小，即允许重复比特数量越少。
这三种方式，适用于对待编码的信息比特序列的母码长度选择，也适用于分段后的子段的母码长度选择。
205、对p个子段进行分别进行相应的速率匹配，得到p个长度分别为子段目标码长的编码比特序列。具体的，若每个子段的目标码长Mi大于母码长度Ni，则重复长度为Ni的编码比特序列中的至少一部分比特，得到长度为Mi的编码比特序列。若每个子段的目标码长Mi小于等于母码长度Ni，则采用打孔或缩短的速率匹配方案，删除打孔位置或者缩短位置的编码比特，得到长度为Mi的编码比特序列。
206、合并步骤205得到的p个编码比特序列，得到长度为M的编码比特序列。
可选的，步骤203划分成p个子段之后，还可以将p个子段中编码参数满足预设的条件进一步划分成p个子段并分别进行独立的编码和速率匹配。
也就是说，对于每个Mi，i＝1,2,...,p，若目标码长Mi大于母码长度Ni，且Mi对应的子段的编码参数满足所述预设的条件，将Mi对应的子段进一步划分为p个子段分别进行独立的编码和速率匹配，得到对应的p个编码比特序列并进行合并，得到目标码长Mi的编码比特序列。若目标码长Mi大于母码长度Ni，但Mi对应的子段的编码参数不满足所述预设的条件，采用母码长度Ni对Mi对应的子段进行Polar编码，得到长度为Ni的编码 比特序列，重复所述第三编码比特序列中的至少一部分比特，得到长度为Mi的编码序列。若目标码长Mi小于等于最大母码长度Ni，采用母码长度Ni，对Mi对应的子段进行Polar编码得到编码比特序列，对所述编码比特序列进行缩短或者打孔，得到长度为Mi的编码序列
可选的，当所述目标码长M大于步骤201确定的母码长度时，若所述信息块的编码不参数满足预设的条件(分段编码条件)可以进行步骤204。
204、采用母码长度N对待编码的信息比特序列进行Polar编码并采用重复的速率匹配方案。具体的，Polar编码得到长度为N的编码比特序列，重复所述长度为N的编码比特序列中的至少一部分比特，得到长度为M的编码比特序列；
可选的，若所述目标码长M小于等于所述母码长度N，可以进行步骤202。
202、采用母码长度N对所述待编码的信息比特序列进行Polar编码并采用缩短或者打孔的速率匹配方案。具体的，Polar编码得到长度为N的编码比特序列，对所述长度为N的编码比特序列进行缩短或者打孔，得到长度为M的编码比特序列。
如图3所示为本申请实施例提供的编码方法流程示意图，该方法包括：
301、接收待译码信息比特的LLR，待译码的长度为编码时的目标码长M。
接收端对编码端有关的编码参数可以通过***的调度信息中获取，例如K,M，R，N等值。接收端也可以根据接收到的LLR可以确定目标码长M
303、确定母码长度N，当所述目标码长M大于步骤301确定的母码长度N时，若编码参数满足预设的条件(也可以叫做分段编码条件)，将待译码信息比特的LLR序列划分为p段并分别进行解速率匹配。具体的，将待译码的信息比特的LLR序列分成p个子段，p为大于等于2的整数；待译码的信息比特序列总长度为M，p个子段的信息比特长度分别为M1，M2，...，Mp，其中M＝M1+M2,+...,+Mp。
按照约定的规则确定母码码长N及对应的速率匹配方式，具体方法与编码端一致，可以参考流程中步骤203所介绍的三种方式。
305、对步骤203划分的p个子段并分别进行解速率匹配。具体的，分别确定每个子段的母码长度分别N1，N2，...，Np。对每个Mi，i＝1,2,...,p，当Mi>Ni时，确定发送端采用的是重复的方式进行速率匹配，则将重复位置的LLR进行合并，得到速率匹配后的长度为Ni的LLR序列。当Mi≤Ni时，确定发送端采用的是缩短或打孔的方式进行速率匹配，将缩短或者打孔位置的LLR进行恢复(设为约定的固定值)，得到速率匹配后的长度为Ni的LLR序列。
306、对P个子段分别进行独立的SCL译码，分别得到p个子段的译码结果。具体的，根据速率匹配后的P个子段的LLR进行SCL译码，得到p个译码结果。
307、合并步骤305得到的p个子段的译码结果，输出最终的译码比特序列。
可选的，步骤304划分成p个子段之后，还可以将p个子段中编码参数满足预设的条件进一步划分成p个子段后再分别进行速率匹配和译码，得到p个子段的译码结果并进行合并。
可选的，当所述目标码长M大于母码长度N时，若所述信息块的编码不参数满足预设的条件(分段编码条件)可以进行步骤304。
304、将重复位置的LLR进行合并，得到速率匹配后的长度为N的LLR序列并译码。
可选的，若所述目标码长M小于等于所述母码长度N，可以进行步骤302。
302、将打孔或者缩短位置的LLR进行恢复，得到速率匹配后的长度为N的LLR序列并译码。
本申请实施例涉及的编码方法和解码方法，p个子段可以是均匀的子段，例如待编码比特序列的总长度为Kc，则每个子段的长度为Kc/p，相应的每个子段的目标码长也为M/p，若不能除尽则略作调整。根据不同类型的Polar编码方法，待编码的信息比特序列可能仅包含待发送的信息块，即Kc＝K；也可能包括信息块和CRC比特，此时Kc＝K+Lcrc，Lcrc为CRC的长度。
本申请所说的编码参数，包括以下中的一种或多种：编码码率R，目标码长M，母码长度N，信息块的长度K或CRC长度Lrc等。本申请的预设的条件(分段编码条件)可以包括如下中的任一种：
(1)对于给定的编码码率R，信息块的长度K大于预设的阈值。
(2)对于给定的编码码率R，目标码长M大于预设的阈值。
(3)对于给定的编码码率R，待编码的信息比特序列长度Kc大于预设的阈值。
本申请提到的信息块，是指在通信***中实际要发送的信息。本申请实施例所说的“待编码的信息比特序列”，是指在Polar编码中将通过信息比特索引的集合对应的信息比特携带的信息构成的序列。本文中的“长度”，也可以说是“个数”。
本申请实施例所说的的Polar码，包括但不限于Arikan Polar码，还可以是CA-Polar码、PC-Polar码或者PC-CA-Polar码。Arikan Polar是指原始的Polar码，没有与其它码级联，只有信息比特和冻结比特。CA-Polar码是Polar码级联了循环冗余校验(Cyclic Redundancy Check，简称CRC)的Polar码，PC-Polar码是Polar码级了奇偶校验(Parity Check，简称PC)的码，PC-CA-Polar码是同时级联了CRC和PC的码。PC-Polar、CA-Polar以及PC-CA-Pola是通过级联不同的码来提高Polar码的性能。
本申请在描述“若M大于母码长度N”时，作为一种等价的方式，也可以表示为“若
Figure PCTCN2018080394-appb-000027
大于母码长度N”，因为母码长度为2的整数次幂，所以从效果上来看，“
Figure PCTCN2018080394-appb-000028
大于母码长度N”必然能得出“M大于母码长度N”，反之若“M大于母码长度N”，也必然能得出“
Figure PCTCN2018080394-appb-000029
大于母码长度N”，其中
Figure PCTCN2018080394-appb-000030
表示向上取整。
以下，将结合不同类型的Polar码编码方式介绍不同实施方式中的编码方法和译码方法。在同一个实施方式将把编码方法和译码方法结合在一起介绍，但本领域技术人员能够理解，发送端的编码方法和接收端的译码方法是相互对应但独立的流程。为了描述的方便，下面介绍的实施方式均采用p＝2，即在分段时均匀分成2段。
母码码长的确定方式将以采用编码方法中步骤201介绍的第(1)中方式为例，假设通信***规定了最大母码长度Nmax，根据
Figure PCTCN2018080394-appb-000031
来确定每次编码所采用的母码长度的值，也就是说，当M>Nmax时，N＝Nmax，通常采用重复的速率匹配方案方案，而本申请是进一步判断是否进行分段编码，减少重复带来的损失。因此如果是根据
Figure PCTCN2018080394-appb-000032
来确定N的值，那么本申请的编码和译码方法中的，当M大于N时，可以简化为当M>Nmax或者
Figure PCTCN2018080394-appb-000033
时，若判断编码参数满足预设的条件， 采用分段编码的方法，若不满足预设的条件，仍然采用N＝Nmax进行一次编码并采用重复的速率匹配方法。当M≤N时，
Figure PCTCN2018080394-appb-000034
因此可以简化为当M≤Nmax或者
Figure PCTCN2018080394-appb-000035
时，采用
Figure PCTCN2018080394-appb-000036
进行Polar编码，并采用缩短或者打孔的速率匹配方法得到目标码长。因此，以下实施例在将“M大于N”替换为“
Figure PCTCN2018080394-appb-000037
大于Nmax”，将“M小于等于N”替换为“
Figure PCTCN2018080394-appb-000038
小于等于Nmax”；当然，也可以在将“M大于N”替换为“M大于Nmax”，将“M小于等于N”替换为“M小于等于Nmax”，仍然能够实现本申请的目的。
对于Arikan Polar，信息比特仅携带信息块，因此信息块的长度即是信息比特的个数。将目标码长M大于最大母码长度Nmax，且满足Polar码分段编码条件的待编码比特序列进行Polar码的分段编码，接收端进行译码并完成译码结果的合并。Arikan Polar的编码方法和译码方法流程示意图如图4所示，编译码过程包括：
(1)目标码长M由分配的物理资源，或信息比特个数K和码率R确定，例如M＝INT(K/R)，INT表示取整；
(2)根据目标码长M，确定母码长度N＝min(2 n，N max)，n是大于等于log 2M的最小整数，即
Figure PCTCN2018080394-appb-000039
表示向上取整，min(·)表示取最小值，N max表示***支持的最大母码长度；
(3)若
Figure PCTCN2018080394-appb-000040
大于最大母码长度Nmax且满足Polar码分段编码条件，将信息分为子段0、与子段1分别进行Polar码的编码，即采用(K +，M +)与(K -，M -)分别进行Polar码的分段编码，其中K＝K ++K -，M＝M ++M -。K+为子段0的信息比特个数，M+为子段0的目标码长，M-为子段1的目标码长。若子段0或子段1的母码长度仍大于最大母码长且满足Polar码分段编码条件，继续进行分段。不满足分段编码条件的情况下采用重复的速率匹配方法。
这里K+对应前面说的K1，K-对应前面说的K2，这里M+对应前面说的M1，M-对应前面说的M2，为了描述方便后续统一以K +、K -表示K1和K2，M +、M -表示M1和M2。
Polar码分段编码条件由码率R，以及信息块长度K、目标码长M或者待编码信息比特序列长度Kc确定。对于给定的编码码率R，信息块的长度K大于预设的阈值，目标码长M大于预设的阈值，或者待编码信息比特序列长度Kc大于预设的阈值。不同参数的条件对应的阈值不同，对于不同的Nmax值阈值的设置也可能不同。
(4)进行速率匹配。若第(3)步采用了分段编码，合并对每个子段编码得到的编码比特序列，得到最终的编码比特序列。
(5)接收端进行对应的解速率匹配，最后根据编码规则对子段信息进行译码，完成信息的合并。
Polar码分段编码适用于PC-Polar的编码和译码过程，流程示意图图如图5，包括：
(1)目标码长M由分配的物理资源，或信息比特个数K和码率R确定，M＝INT(K/R)，INT表示取整；例如取K＝30，R＝1/6；则M＝180。
(2)根据目标码长M，确定母码长度N＝min(2 n，N max)，n是大于等于log 2M的最小整数，即
Figure PCTCN2018080394-appb-000041
表示向上取整，min(·)表示取最小值，N max表示***支持的最大母码长；如取M＝180，Nmax＝1024，则n＝8，N＝min(256,1024)＝256；又如取 M＝1800，Nmax＝1024，则n＝11，N＝min(2048,1024)＝1024。
(3)若2 n大于最大母码长度，且满足PC-Polar码分段编码条件，将待编码比特序列进行Polar码的分段编码，即采用(K +，M +)与(K -，M -)分别进行子段0与子段1的PC-Polar码的编码，其中K+L CRC＝K ++K -，M＝M ++M -，其中L CRC为CRC的长度。。其中
Figure PCTCN2018080394-appb-000042
K -＝K+L CRC-K +，
Figure PCTCN2018080394-appb-000043
M -＝M-M +。若子段母码长度仍大于最大母码长且满足PC-Polar码分段编码条件，继续进行分段。若2 n大于最大母码长度Nmax，且不满足PC-Polar码分段编码条件，采用N＝Nmax进行编码，并采用重复的速率匹配方式。若2 n小于等于最大母码长度Nmax，采用N＝2 n进行编码，并采用缩短或者打孔的速率匹配方式。
此处是以PC-Polar级联CRC比特为例，又称为PC-CA-Polar，该CRC比特可以用于辅助PC-SCL译码(纠错)。对于纯PC-Polar来说，CRC比特不用于辅助PC-SCL译码，而可以在译码结束后用于检错。
PC-Polar码的分段编码条件由码率R，以及待编码信息比特序列长度Kc或者信息块长度K或者目标码长M确定，其中K c对应于Polar码构造时采用的信息位个数。不同码率下PC-Polar码的分段编码条件如表1所示。表1中，列出了不同码率值及其对应的分段编码条件，但无法穷举所***率及其对应的分段编码条件，本领域技术人员可以其他码率制定合适的分段编码条件。
R 1/12 1/6 1/4 1/3 2/5
K c ≥Kc1 ≥Kc2 ≥Kc3 ≥Kc4 ≥Kc5
K ≥Kt1 ≥Kt2 ≥Kt3 ≥Kt4 ≥Kt5
M ≥Mt1 ≥Mt2 ≥Mt3 ≥Mt4 ≥Mt5
表1
若Nmax＝1024，Kc1的取值范围可以是属于区间[330-370]的整数；Kc2的取值范围可以是属于区间[345-365]的整数，Kc3的取值范围可以是属于区间[370-380]的整数；Kc4的取值范围可以是属于区间[450-460]的整数；Kc5的取值范围可以是属于区间[500-510]的整数。
若Nmax＝1024，Kt1的取值范围可以是属于区间[314-354]的整数，Kt2的取值范围可以是属于区间[329-349]的整数，Kt3的取值范围可以是属于区间[354-364]的整数；Kt4的取值范围可以是属于区间[434-444]的整数；Kt5的取值范围可以是属于区间[484-494]的整数。
若Nmax＝1024，Mt1的取值范围可以是属于区间[3768-4248]的整数；Mt2的取值范围可以是属于区间[1974-2094]的整数，Mt3的取值范围可以是属于区间[1416-1456]的整数；Mt4的取值范围可以是属于区间[1302-1332]的整数；Mt5的取值范围可以是属于区间[1210-1235]的整数。
若Nmax＝1024，在一个例子中，Kc1＝360，Kc2＝360，Kc3＝380，Kc4＝460，Kc5＝510；Kt1＝344，Kt2＝344，Kt3＝364，Kt4＝444，Kt5＝494；Mt1＝4128，Mt2＝2064，Mt3＝1456，Mt4＝1332，Mt5＝1235。分段编条件如表2所示。
R 1/12 1/6 1/4 1/3 2/5
K c ≥360 ≥360 ≥380 ≥460 ≥510
K ≥344 ≥344 ≥364 ≥444 ≥494
M ≥4128 ≥2064 ≥1456 ≥1332 ≥1235
表2Nmax＝1024
若Nmax＝512，Kc1的取值范围可以是属于区间[200-220]的整数；Kc2的取值范围可以是属于区间[205-225]的整数，Kc3的取值范围可以是属于区间[210-220]的整数；Kc4的取值范围可以是属于区间[120-240]的整数；Kc5的取值范围可以是属于区间[265-275]的整数。
若Nmax＝512，Kt1的取值范围可以是属于区间[184-204]的整数,Kt2的取值范围可以是属于区间[189-209]的整数，Kt3的取值范围可以是属于区间[194-214]的整数；Kt4的取值范围可以是属于区间[214-224]的整数；Kt5的取值范围可以是属于区间[249-259]的整数。
若Nmax＝512，Mt1的取值范围可以是属于区间[2208-2448]的整数；Mt2的取值范围可以是属于区间[1134-1254]的整数，Mt3的取值范围可以是属于区间[776-856]的整数；Mt4的取值范围可以是属于区间[642-672]的整数；Mt5的取值范围可以是属于区间[623-648]的整数。
若Nmax＝512，在一个例子中，若Nmax＝512，在一个例子中，Kc1＝210，Kc2＝220，Kc3＝220，Kc4＝235，Kc5＝270；Kt1＝194，Kt2＝204，Kt3＝204，Kt4＝219，Kt5＝254；Mt1＝2328，Mt2＝1224，Mt3＝816，Mt4＝657，Mt5＝635。分段编条件如表3所示。
R 1/12 1/6 1/4 1/3 2/5
K c ≥210 ≥220 ≥220 ≥235 ≥270
K ≥194 ≥204 ≥204 ≥219 ≥254
M ≥2328 ≥1224 ≥816 ≥657 ≥635
表3
本申请的预设条件，即分段编码条件，表1-表3中每一个R值和其对应的Kc的阈值构成一个分段编码条件，每一个R值和其对应的K的阈值构成一个分段编码条件，每一个R值和其对应的M的阈值构成一个分段编码条件。因此，表1-3仅是为了表示方便，把这种分段编码条件放在一起展示，并不表示表格整体作为一个分段编码条件，也就是说并不表示必须同时满足表里所列的条件。
假设Nmax＝1024，分段编码条件为Kc大于预设的阈值，例如，K＝401，Lcrc＝16，N＝1024，R＝1/6，M＝2406，则Kc＝K+Lcrc＝417。根据表3，分段编码条件为Kc≥220，满足分段条件，则
Figure PCTCN2018080394-appb-000044
K-＝417-209＝208；M+＝2406/2＝1203；M-＝2406-1203＝1203；采用编码参数(Kc,M)编码，所以对两个子段采用(209,1203)和(208,1203)编码。对于两个子段，通过步骤(2)得到均为母码长度N＝Nmax＝1024，M>N
Figure PCTCN2018080394-appb-000045
此时不满足分段编码条件，因此不继续分段，速率匹配采用重复的方式：重复1024个编码比特中的179(1203-1024)个比特，得到1203个编码比特。
假设Nmax＝1024，分段编码条件为Kc大于预设的阈值，K＝800，Lcrc＝16，N＝1024，M＝2400，R＝1/3，Kc＝K+Lcrc＝816，满足分段条件Kc≥460，则K+＝(800+16)/2＝408；K-＝816-208＝408；M+＝2400/2＝1200；M-＝2400-1200＝1200；采用(408,1200)和(408,1200)编码，对于两个子段，通过步骤(2)得到母码长度N＝1024，此时满足重复条件及分段编码条件，继续进行分段。以其中一段(408,1200)举例，K++＝204；M++＝600；K+-＝204；M+-＝600，对(204,600)进行编码，通过步骤(2)得到母码长度N＝1024>M，速率匹配方案采用打孔或者缩短：从1024编码比特打孔或者缩短为600编码比特。
(4)进行速率匹配，若存在分段编码的情况，合并各个子段的编码比特序列，得长度为M的编码比特序列。
(5)经过信道传输之后，接收端根据调度信息按照约定规则对接收的LLR序列(待译码比特对应的LLR序列)进行处理。
a、接收段已知编码参数(K,M,R,N)后，根据步骤(3)判断是否满足分段编码条件，若满足分段编码条件，则将接收LLR序列分成两段并分别进行后续步骤的处理。
(i)假设Nmax＝1024，K＝400，M＝2400，R＝1/6，N＝1024；
Figure PCTCN2018080394-appb-000046
Kc＝400+16＝416>，满足重复条件和分段条件，将接收的2400长LLR分为两段处理。
(ii)假设Nmax＝1024，K＝200，M＝2400，R＝1/12，N＝1024；
Figure PCTCN2018080394-appb-000047
但Kc＝216<360，不满足分段编码条件，接收的长度为2400的LLR序列不进行分段译码。
(iii)假设Nmax＝1024，K＝200，M＝800，R＝1/4，N＝1024；
Figure PCTCN2018080394-appb-000048
不满足分段条件，接收的长度为800的LLR序列不作分段处理。
b、根据速率匹配方案对LLR进行补0，补无穷大或叠加(对应打孔，缩短和重复的速率匹配方案)，获得解速率匹配后的LLR序列。
(i)速率匹配方案为重复，将重复的176个(1200-1024)位置的行LLR进行按照重复模式叠加，最终每段的LLR序列长度为1024，共2段。
(ii)速率匹配方案为重复，将重复的1376个(2400-1024)位置的LLR按照重复模式叠加，得到一段长度为1024的LLR序列。
(iii)速率匹配方案为缩短，进行LLR补无穷大，将长度为800的LLR按照缩短模式恢复，将缩短的224个(1024-800)位置设置为无穷大值，得到一段长度为1024的LLR序列。
(6)若编码端为分段编码，分别对步骤(5)得到的子段的LLR序列进行独立PC-SCL译码，各输出一条子段的译码结果，最后将两条子段的译码结果合并，此时CRC比特没有用于辅助PC-SCL译码。
作为一种可选的方式，对每个分段的PC-SCL译码也可以参考图6，此时CRC比特用于辅助译码。一个PC-SCL译码器可以输出L p条候选信息及L p个PM值，将子段0与子段1共2L p条子段候选路径进行两两组合，得到L p×L p条候选路径，组合得到的每个路径中两个子段的候选路径的PM值相加。根据PM的大小进行升序或降序排序，选择其中最优的T p条进行CRC校验，选择校验通过的第一条路径作为译码输出或者对T p条候选路径均进行CRC校验，选择校验通过的候选路径中PM值最优的路径，其中T p≤L p×L p，Lp等于PC-SCL的list数，Tp是参与CRC校验筛选的候选路径数量。
例如，一个PC-SCL译码器输出8条候选信息及8个PM值，将两个译码器输出共16条候选信息两两组合，得到64条候选信息，并将对应PM相加，根据PM大小升序排序， 选择其中最优的8条参与CRC校验此时原始CRC需要增加log 2(8)＝3比特用于保证虚警概率FAR)，从最优的候选路径开始校验，选择CRC校验通过的第一条路径作为译码输出。
图7是Nmax＝1024下，采用Kc设置分段编码条件的仿真结果图，比较了普通PC-Polar编码和分段Pc-Polar编码在不同码率下的译码性能。图7中kc＝380，实线是采用分段编码的译码性能，虚线是采用普通PC-Polar编码的译码性能。可以看出，在相同码率下，分段编码的译码性能优于普通PC-Polar编码的译码性能。
Polar码分段编码适用于CA-Polar的编码和译码过程如图8所示，该过程可以包括：
(1)目标码长由分配的物理资源或信息比特个数K和码率R确定，M＝INT(K/R)，INT表示取整；
(2)根据目标码长M，确定母码长度N＝min(2 n，N max)，n是大于等于log 2M的最小整数，即
Figure PCTCN2018080394-appb-000049
表示向上取整，min(·)表示取最小值，N max表示***支持的最大母码长；
(3)若2 n大于最大母码长度，且满足CA-Polar码分段编码条件，将将待编码比特序列进行Polar码的分段编码，即采用(K +，M +)与(K -，M -)分别进行子段0与子段1的PC-Polar码的编码，其中K+L CRC＝K ++K -，M＝M ++M -，其中L CRC为CRC的长度，
Figure PCTCN2018080394-appb-000050
K -＝K+L CRC-K +，
Figure PCTCN2018080394-appb-000051
M -＝M-M +。
在一个例子中，CRC长度可以为19。若子段母码长度仍大于最大母码长且满足CA-Polar码分段编码条件，继续进行分段，否则采用其他速率匹配方法。
若2 n大于最大母码长度Nmax，且不满足CA-Polar码分段编码条件，采用N＝Nmax进行编码，并采用重复的速率匹配方式。若2 n小于等于最大母码长度Nmax，采用N＝2 n进行编码，并采用缩短或者打孔的速率匹配方式。
(4)进行速率匹配，若存在分段编码的情况，合并各个子段的编码比特序列，得长度为M的编码比特序列。
(5)接收端进行解速率匹配，并分别对子段进行独立SCL译码，输出L P条子段候选路径及PM，其中L P为候选列表的大小。将2L P条子段候选路径两两组合为L P×L P条候选路径，根据PM值取其中最优T P条候选路径。CA-Polar级联了CRC比特，用于辅助SCL译码，因此可以从并T P条候选路径中，从PM值最优的路径开始进行CRC校验，选择CRC校验通过的第一条路径作为译码输出，其中T P≤L P×L P。
CA-Polar码的分段编码条件由码率R，以及待编码信息比特序列长度Kc或者信息块长度K或者目标码长M确定，其中K c对应于Polar码构造时采用的信息位个数。不同码率下PC-Polar码的分段编码条件如表1所示。
若Nmax＝1024，Kc1的取值范围可以是属于区间[310-340]的整数；Kc2的取值范围可以是属于区间[350-365]的整数，Kc3的取值范围可以是属于区间[410-450]的整数；Kc4的取值范围可以是属于区间[470-495]的整数；Kc5的取值范围可以是属于区间[520-530]的整数。
若Nmax＝1024，Kt1的取值范围可以是属于区间[291-321]的整数，Kt2的取值范围可以是属于区间[331-346]的整数，Kt3的取值范围可以是属于区间[391-431]的整数；Kt4的取值范围可以是属于区间[451-476]的整数；Kt5的取值范围可以是属于区间[501-511]的整数。
若Nmax＝1024，Mt1的取值范围可以是属于区间[3492-3852]的整数；Mt2的取值范围可以是属于区间[1986-2076]的整数，Mt3的取值范围可以是属于区间[1564-1724]的整数；Mt4的取值范围可以是属于区间[1353-1428]的整数；Mt5的取值范围可以是属于区间[1253-1278]的整数。
若Nmax＝1024，在一个例子中，Kc1＝320，Kc2＝360，Kc3＝430，Kc4＝490，Kc5＝530；Kt1＝301，Kt2＝341，Kt3＝411，Kt4＝471，Kt5＝511；Mt1＝3612，Mt2＝2046，Mt3＝1644，Mt4＝1413，Mt5＝1278。CA-Polar分段编条件如表4所示。
R 1/12 1/6 1/4 1/3 2/5
K c ≥320 ≥360 ≥430 ≥490 ≥530
K ≥301 ≥341 ≥411 ≥471 ≥511
M ≥3612 ≥2046 ≥1644 ≥1413 ≥1278
表4
若Nmax＝512，Kc1的取值范围可以是属于区间[170-190]的整数；Kc2的取值范围可以是属于区间[185-195]的整数，Kc3的取值范围可以是属于区间[210-230]的整数；Kc4的取值范围可以是属于区间[250-260]的整数；Kc5的取值范围可以是属于区间[270-280]的整数。
若Nmax＝512，Kt1的取值范围可以是属于区间[151-171]的整数,Kt2的取值范围可以是属于区间[166-176]的整数，Kt3的取值范围可以是属于区间[191-211]的整数；Kt4的取值范围可以是属于区间[231-241]的整数；Kt5的取值范围可以是属于区间[251-261]的整数。
若Nmax＝512，Mt1的取值范围可以是属于区间[1812-2052]的整数；Mt2的取值范围可以是属于区间[996-1056]的整数，Mt3的取值范围可以是属于区间[764-844]的整数；Mt4的取值范围可以是属于区间[693-723]的整数；Mt5的取值范围可以是属于区间[693-723]的整数。
若Nmax＝512，在一个例子中，若Nmax＝512，在一个例子中，Kc1＝180，
Kc2＝190，Kc3＝220，Kc4＝255，Kc5＝275；Kt1＝161，Kt2＝171，Kt3＝201，Kt4＝236，Kt5＝256；Mt1＝1932，Mt2＝1026，Mt3＝804，Mt4＝708，Mt5＝640。分段编码条件如表5所示。
R 1/12 1/6 1/4 1/3 2/5
K c ≥180 ≥190 ≥220 ≥255 ≥275
K ≥161 ≥171 ≥201 ≥236 ≥256
M ≥1932 ≥1026 ≥804 ≥708 ≥640
表5
图8介绍了一种CA-Polar分段编码和译码方法。在另一个实施方式中，如图9所示，CA-Polar分段编码中，待编码信息比特包括常规的用于检错的CRC比特，但不包括辅助SCL译码的CRC比特。可以在对长度为K+Lcrc的信息块划分成子段0和子段1后，将用于辅助SCL译码的CRC比特分成两段，分别加入到子段0和子段1中，分别进行独立编码。若2 n大于最大母码长度，且满足CA-Polar码分段编码条件，将信息块分成两段，子段 0的长度为K +，子段1的长度为K -。将子段0和子段1加入L CRC2的CRC,并采用(K ++L CRC2，M +)与(K -+L CRC2，M -)分别进行Polar码的分段编码，其中K+L CRC＝K ++K -，M＝M ++M -，其中L CRC为CRC的长度。若子段母码长度仍大于最大母码长且满足CA-Polar码分段编码条件，继续进行分段，否则采用其他速率匹配方法。接收端进行解速率匹配，并分别对子段进行独立CA-SCL译码，各输出一条子段的译码结果，最后将两条子段的译码结果合并。
在另一个实施方式中，如图10所示，CA-Polar分段编码中，待编码信息比特不包括任何CRC比特。但可以在对长度为K的信息块划分成子段0和子段1后，将用于辅助SCL译码的CRC比特分成两段，分别加入到子段0和子段1中，分别进行独立编码。因此，若2 n大于最大母码长度，且满足CA-Polar码分段编码条件，将信息块分成两段，子段0的长度为K +，子段1的长度为K -。将子段0和子段1分别加入长度L CRC2的CRC,并采用(K ++L CRC2，M +)与(K -+L CRC2，M -)分别进行Polar码的分段编码，其中K＝K ++K -，M＝M ++M -，其中其中
Figure PCTCN2018080394-appb-000052
K-＝K-K+，
Figure PCTCN2018080394-appb-000053
M-＝M-M+，Kc＝K。若子段母码长度仍大于最大母码长且满足CA-Polar码分段编码条件，继续进行分段，否则采用其他速率匹配方法。接收端进行解速率匹配，并分别对子段进行独立CA-SCL译码，各输出一条子段的译码结果，最后将两条子段的译码结果合并。
本申请描述的方法步骤所采用的标号仅作为标记使用，并不表示步骤被执行的先后顺序。
本申请实施例所说的打孔包括准均匀打孔(Quasi-Uniform Puncture，简称QUP)。首先确定母码长度为大于等于目标码长的2的整数次幂，然后根据母码长度和目标码长确定打孔模式(打孔位置)。打孔模式可以通过二进制序列(00...011...1)表示，其中，确定“0”表示打孔位置，“1”表示未打孔位置。将打孔位置对应的信道容量设为0(或者错误概率设置为1或信噪比SNR设置为无穷小)，利用密度进化、高斯近似或者线性拟合的方法计算极化信道的可靠度并排序，确定信息比特和固定比特(冻结比特)位置。编码端将编码后处于打孔位置的比特删除得到polar码。
本申请所说的缩短(Shorten)Polar码的方案，确定母码长度为大于等于目标码长的2的整数次幂。缩短(Shorten)位置的编码比特只与固定比特有关。过程包括：根据母码计算极化信道的可靠度，然后确定Shorten位置，对应的极化信道放置固定比特，从余下的极化信道中根据可靠度确定信息比特和冻结比特(固定比特)位置，将编码后处于缩短位置的比特删除得到Polar码，实现速率匹配。基于Shorten的编码和速率匹配方案，由于不需要根据缩短位置重新计算极化信道的可靠度，只是将缩短位置对应的极化信道放置固定比特，大大降低Polar码的构造复杂度。
图11所示为本申请提供的一种编码装置1100的结构示意图，编码装置1100包括：
获取单元1101，用于获取待发送的信息块和Polar码的目标码长M；
编码单元1102，确定Polar编码采用的母码码长N，当所述目标码长M大于N，若所述信息块的编码参数满足预设的条件，将待编码的信息比特序列分成p个子段，对P个子段分别进行独立的Polar编码，得到p个长度为分别子段母码长度的编码比特序列，其中p为大于等于2的整数；
速率匹配单元1103，用于对p个编码结果分别进行速率匹配，得到p个长度分别为子段的目标码长的编码比特序列；；
合并单元1104，用于合并合并所述速率匹配后的p个编码比特序列，得到长度为M的编码比特序列。
可选的，所述编码单元1102还用于，若所述信息块的编码参数不满足所述预设的条件，采用所述母码码长N对待编码的信息比特序列进行Polar编码，得到长度为N的第一编码比特序列；所述速率匹配单元用于重复所述第一编码比特序列中的至少一部分比特，得到长度为M的编码比特序列；
可选的，所述编码单元1102还用于，若所述目标码长M小于等于所述母码长度N，采用母码长度N对所述待编码的信息比特序列进行Polar编码得到第二编码比特序列；所述速率匹配单元用于对所述第二编码比特序列进行缩短或者打孔，得到长度为M的编码比特序列。
可选的，所述编码单元1102还用于，若目标码长Mi大于母码长度Ni，且Mi对应子段的编码参数不满足所述预设的条件，采用母码长度Ni对Mi对应的子段进行Polar编码，得到长度为Ni的第三编码比特序列；所述速率匹配单元用于重复所述第三编码比特序列中的至少一部分比特，得到长度为Mi的编码序列；或者
可选的，所述编码单元1102还用于，若目标码长Mi小于等于母码长度Ni，采用母码长度Ni对Ki对应的子段进行Polar编码得到第四编码比特序列；所述速率匹配单元用于对所述第四编码比特序列进行缩短或者打孔，得到长度为Mi的编码序列。
图12所示为本申请提供的另外一种编码装置1200的结构示意图，码装置1200包括：
存储器1201，用于存储程序；
处理器1202，用于执行所述存储器存储的所述程序，当所述程序被执行时，获取待发送的信息块和Polar码的目标码长M；确定Polar编码采用的母码码长N，当所述目标码长M大于N，若所述信息块的编码参数满足预设的条件，将待编码的信息比特序列分成p个子段，对P个子段分别进行独立的Polar编码，得到p个长度为分别子段母码长度的编码比特序列，其中p为大于等于2的整数；对p个编码结果分别进行速率匹配，得到p个长度分别为子段的目标码长的编码比特序列；合并所述速率匹配后的p个编码比特序列，得到长度为M的编码比特序列。
可选的，所述处理器1202还用于，若所述信息块的编码参数不满足所述预设的条件，采用所述母码码长N对待编码的信息比特序列进行Polar编码，得到长度为N的第一编码比特序列，重复所述第一编码比特序列中的至少一部分比特，得到长度为M的编码比特序列；
可选的，所述处理器1202还用于，若所述目标码长M小于等于所述母码长度N，采用母码长度N对所述待编码的信息比特序列进行Polar编码得到第二编码比特序列，对所述第二编码比特序列进行缩短或者打孔，得到长度为M的编码比特序列。
可选的，所述待编码的信息比特序列总长度为Kc，p个子段的信息比特长度分别为K1，K2，...，Kp，p个子段分别进行独立Polar编码采用的母码长度分别为N1，N2，...，Np，对应的目标码长分别为M1，M2，...，Mp，其中Kc＝K1+K2,+...,+Kp，M＝M1+M2,+...,+Mp，所述待编码的信息比特序列包括所述信息块，Kc大于等于所述信息块的长度K；所述处理器1202还用于，对于每个Mi，若Mi对应的子段的目标码长Mi大于 母码长度Ni，且Ki对应的子段的编码参数满足所述预设的条件，将Mi对应的子段进一步划分为p个子段分别进行独立的编码和速率匹配，得到对应的p个编码比特序列并进行合并，得到目标码长Mi的编码比特序列，其中，i＝1,2,...,p。
图12的编码装置还可以进一步包括发送器(图中未示出)，用于发送处理器得到的长度为M的编码比特序列。
图13所示为本申请提供的另外一种编码装置1300的结构示意图，编码装置1300包括：
至少一个输入端1301，用于接收信息块；
信号处理器1302，用于获取待发送的信息块和Polar码的目标码长M；确定Polar编码采用的母码码长N，当所述目标码长M大于N，若所述信息块的编码参数满足预设的条件，将待编码的信息比特序列分成p个子段，对P个子段分别进行独立的Polar编码，得到p个长度为分别子段母码长度的编码比特序列，其中p为大于等于2的整数；对p个编码结果分别进行速率匹配，得到p个长度分别为子段的目标码长的编码比特序列；合并所述速率匹配后的p个编码比特序列，得到长度为M的编码比特序列；
至少一个输出端1303，用于输出信号处理器得到的编码比特序列。
可选的，所述信号处理器1302还用于，若所述信息块的编码参数不满足所述预设的条件，采用所述母码码长N对待编码的信息比特序列进行Polar编码，得到长度为N的第一编码比特序列，重复所述第一编码比特序列中的至少一部分比特，得到长度为M的编码比特序列；或者
可选的，所述信号处理器1302还用于，若所述目标码长M小于等于所述母码长度N，采用母码长度N对所述待编码的信息比特序列进行Polar编码得到第二编码比特序列，对所述第二编码比特序列进行缩短或者打孔，得到长度为M的编码比特序列。
可选的，待编码的信息比特序列总长度为Kc，p个子段的信息比特长度分别为K1，K2，...，Kp，p个子段分别进行独立Polar编码采用的母码长度分别为N1，N2，...，Np，对应的目标码长分别为M1，M2，...，Mp，其中Kc＝K1+K2,+...,+Kp，M＝M1+M2,+...,+Mp，所述待编码的信息比特序列包括所述信息块，Kc大于等于所述信息块的长度K；
所述信号处理器1302还用于，对于每个Mi，若Mi对应的子段的目标码长Mi大于母码长度Ni，且Ki对应的子段的编码参数满足所述预设的条件，将Mi对应的子段进一步划分为p个子段分别进行独立的编码和速率匹配，得到对应的p个编码比特序列并进行合并，得到目标码长Mi的编码比特序列，其中，i＝1,2,...,p。
图13的编码装置还可以进一步包括发送器(图中未示出)，用于发送至少一个输出端输出的长度为M的编码比特序列。
本申请图11-13的编码装置可以是任何具有无线通信功能的设备，例如接入点、站点、用户设备、基站等。编码装置中各个部件所执行的功能及其具体的执行方法可以参考图2图4、图5、图8-10及其实施例中的相关部分，此处不再重复描述。
图14所示为本申请提供的一种译码装置1400的结构示意图，译码装置1400包括：
接收单元1401，用于接收待译码比特对应的对数似然比LLR，待译码比特长度为编码 时的目标码长M；
解速率匹配单元1402，用于确定编码时的母码长度N，当所述目标码长M大于母码长度N时，若编码参数满足预设的条件，将待译码比特对应的LLR分成p个子段，对p个子段并分别进行解速率匹配，其中p为大于等于2的整数；
译码单元1403，用于对解速率匹配后的p个子段的LLR分别进行独立SCL译码，得到p个子段的译码结果；
输出单元1404，合并p个子段的译码结果，输出译码比特序列。
图15所示为本申请提供的一种译码装置1500的结构示意图，译码装置1500包括：
存储器1501，用于存储程序；
处理器1502，用于执行所述存储器存储的所述程序，当所述程序被执行时，接收待译码比特对应的对数似然比LLR，待译码比特长度为编码时的目标码长M；确定编码时的母码长度N，当所述目标码长M大于母码长度N时，若编码参数满足预设的条件，将待译码比特对应的LLR分成p个子段，对p个子段并分别进行解速率匹配；对解速率匹配后的p个子段的LLR分别进行独立SCL译码，得到p个子段的译码结果；合并p个子段的译码结果，输出译码比特序列，其中p为大于等于2的整数。
图16所示为本申请提供的一种译码装置1600的结构示意图，译码装置1600包括：
至少一个输入端1601，用于接收待译码比特对应的对数似然比LLR，待译码比特长度为编码时的目标码长M；
信号处理器1602，用于接收待译码比特对应的对数似然比LLR，待译码比特长度为编码时的目标码长M；确定编码时的母码长度N，当所述目标码长M大于母码长度N时，若编码参数满足预设的条件，将待译码比特对应的LLR分成p个子段，对p个子段并分别进行解速率匹配；对解速率匹配后的p个子段的LLR分别进行独立SCL译码，得到p个子段的译码结果；合并p个子段的译码结果，输出译码比特序列，其中p为大于等于2的整数；
至少一个输出端1603，用于输出信号处理器得到的译码比特序列。
可选的p个子段的编码时采用的母码长度分别为N1，N2，...，Np，目标码长分别为M1，M2，...，Mp，对应的信息比特长度为K1，K2，...，Kp；
所述信号处理器1602还用于，对于每个子段Mi，i＝1,2,...,p，若Mi大于母码长度Ni，且Mi对应的子段的编码参数满足所述预设的条件，将Mi对应的子段的LLR序列进一步划分为p个子段分别进行解速率匹配并译码，得到对应的p个子段的译码结果，合并p个子段的译码结果得到对应的Ki个信息比特；或者
所述信号处理器1602还用于，对于每个子段Mi，i＝1,2,...,p，若Mi小于母码长度Ni，且Mi对应的子段的编码参数不满足所述预设的条件，将重复位置的LLR进行叠加，得到解速率匹配后的长度为Ni的LLR序列并进行译码，得到子段Mi的译码结果。
可选的，所述信号处理器1602还用于，当所述目标码长M小于母码长度N时，将打孔或者缩短位置的LLR进行恢复，得到解速率匹配后的长度为N的LLR序列并译码，得到译码比特序列。
本申请图14-16的译码装置可以是任何具有无线通信功能的设备，例如接入点、站点、用户设备、基站等。译码装置中各个部件所执行的功能及其具体的执行方法可以参考图3-6、图8-10及其实施例中的相关部分，此处不再重复描述。
本领域技术人员可以理解，本申请的编码方法或译码方法可以硬件或者软硬件结合的方式实现。许多情况下，通信***中的通信装置同时具有收发功能，既能作为发送端给接收端发送信息，又能作为接收端接收发送端发送的信息。因此该通信装置具有编码功能，也有解码功能。该通信装置可配置成通用处理***，例如通称为芯片，该通用处理***包括:提供处理器功能的一个或多个微处理器；以及提供存储介质的至少一部分的外部存储器，所有这些都可以通过外部总线体系结构与其它支持电路连接在一起。
通信装置可以包括具有处理器、总线接口、用户接口的ASIC(专用集成电路)；以及集成在单个芯片中的存储介质的至少一部分。或者，通信装置由一个或多个FPGA(现场可编程门阵列)、PLD(可编程逻辑器件)、控制器、状态机、门逻辑、分立硬件部件、任何其它适合的电路、或者能够执行本申请通篇所描述的各种功能的电路的任意组合。
图17为本申请实施例所提供的一种通信装置1700的结构示意图(例如接入点、基站、站点或者终端等通信装置)。如图17所示，通信装置1700，可以由总线1701作一般性的总线体系结构来实现。根据通信装置1700的具体应用和整体设计约束条件，总线1701可以包括任意数量的互连总线和桥接。总线1701将各种电路连接在一起，这些电路包括处理器1702、存储介质1703和总线接口1704。存储介质用于存储操作***以及待发送的数据、接收的数据。可选的，通信装置1700使用总线接口1704将网络适配器1705等经由总线1701连接。网络适配器1705可用于实现无线通信网络中物理层的信号处理功能，并通过天线1707实现射频信号的发送和接收。用户接口1706可以连接各种用户输入设备，例如：键盘、显示器、鼠标或者操纵杆等。总线1701还可以连接各种其它电路，如定时源、***设备、电压调节器或者功率管理电路等，这些电路是本领域所熟知的，因此不再详述。
其中，处理器1702负责管理总线和一般处理(包括执行存储在存储介质1203上的软件)。处理器1702可以使用一个或多个通用处理器和/或专用处理器来实现。处理器的例子包括微处理器、微控制器、DSP处理器和能够执行软件的其它电路。应当将软件广义地解释为表示指令、数据或其任意组合，而不论是将其称作为软件、固件、中间件、微代码、硬件描述语言还是其它。
在图17存储介质1703被示为与处理器1702分离，然而，本领域技术人员很容易明白，存储介质1703或其任意部分可位于通信装置1700之外。举例来说，存储介质1703可以包括传输线、用数据调制的载波波形、和/或与无线节点分离开的计算机制品，这些介质均可以由处理器1702通过总线接口1704来访问。可替换地，存储介质1703或其任意部分可以集成到处理器1702中，例如，可以是高速缓存和/或通用寄存器。
处理器1702可以用于执行图12和15中处理器1201和处理器的功能。处理器1702可执行本申请描述的编码方法和译码方法，在此不再对处理器1702的执行过程进行赘述。
本申请实施例所说的串行抵消列表SCL译码算法，包括其他按顺序译码、提供多条候选路径的类似SCL的译码算法或者对SCL译码算法的改进算法。
本申请实施例所说的编码装置或译码装置，在实际使用中可能是分别独立的设备；也可能是集成在一起的设备，用于待发送信息进行编码后发送，或者对接收到的信息进行译 码。
本申请实施例描述的各示例的单元及方法过程，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能。
在本申请所提供的几个实施例中，应该理解到，所揭露的装置和方法，可以通过其它的方式实现。以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式。例如多个单元或组件可以结合或者可以集成到另一个***。方法中的一些步骤可以忽略，或不执行。此外，各个单元相互之间的耦合或直接耦合或通信连接可以是通过一些接口实现，这些接口可以是电性、机械或其它的形式。
作为分离部件说明的单元可以是或者也可以不是物理上分开的，既可以位于一个地方，也可以分布到多个网络单元上。另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时，全部或部分地产生按照本发明实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者通过所述计算机可读存储介质进行传输。所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线(DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心、等数据存储设备。所述可用介质可以是磁性介质，(例如，软盘、硬盘、磁带、U盘、ROM、RAM等)、光介质(例如，CD、DVD等)、或者半导体介质(例如固态硬盘Solid State Disk(SSD))等。
以上实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (29)

  1. 一种Polar码的编码方法，其特征在于，包括：
    获取待发送的信息块和Polar码的目标码长M；
    确定Polar编码采用的母码码长N，当所述目标码长M大于N，若所述信息块的编码参数满足预设的条件，将待编码的信息比特序列分成p个子段，对P个子段分别进行独立的Polar编码，得到p个长度为分别子段母码长度的编码比特序列，其中p为大于等于2的整数；
    对p个编码结果分别进行速率匹配，得到p个长度分别为子段的目标码长的编码比特序列；
    合并速率匹配后的p个编码比特序列，得到长度为M的编码比特序列。
  2. 根据权利要求1所述的方法，其特征在于，若所述信息块的编码参数不满足所述预设的条件，采用所述母码码长N对待编码的信息比特序列进行Polar编码，得到长度为N的第一编码比特序列，重复所述第一编码比特序列中的至少一部分比特，得到长度为M的编码比特序列；或者
    若所述目标码长M小于等于所述母码长度N，采用母码长度N对所述待编码的信息比特序列进行Polar编码得到第二编码比特序列，对所述第二编码比特序列进行缩短或者打孔，得到长度为M的编码比特序列。
  3. 根据权利要求1或2所述的方法，其特征在于，待编码的信息比特序列总长度为Kc，p个子段的信息比特长度分别为K1，K2，...，Kp，p个子段分别进行独立Polar编码采用的母码长度分别为N1，N2，...，Np，对应的目标码长分别为M1，M2，...，Mp，其中Kc＝K1+K2,+...,+Kp，M＝M1+M2,+...,+Mp，所述待编码的信息比特序列包括所述信息块，Kc大于等于所述信息块的长度K；
    对于每个Mi，若Mi对应的子段的目标码长Mi大于母码长度Ni，且Ki对应的子段的编码参数满足所述预设的条件，将Mi对应的子段进一步划分为p个子段分别进行独立的编码和速率匹配，得到对应的p个编码比特序列并进行合并，得到目标码长Mi的编码比特序列，其中，i＝1,2,...,p。
  4. 根据权利要求3所述的方法，其特征在于，若目标码长Mi大于母码长度Ni，且Mi对应子段的编码参数不满足所述预设的条件，采用母码长度Ni对Mi对应的子段进行Polar编码，得到长度为Ni的第三编码比特序列，重复所述第三编码比特序列中的至少一部分比特，得到长度为Mi的编码序列；或者
    若目标码长Mi小于等于母码长度Ni，采用母码长度Ni对Ki对应的子段进行Polar编码得到第四编码比特序列，对所述第四编码比特序列进行缩短或者打孔，得到长度为Mi的编码序列。
  5. 根据权利要求1-4任意一项所述的方法，其特征在于，所述编码参数包括以下中的一种：编码码率R待编码的信息比特序列长度Kc、信息块的长度K或目标码长M；
    所述预设条件包括以下中的任意一种：
    对于给定的编码码率R，待编码的信息比特序列长度Kc大于预设的阈值；
    对于给定的编码码率R，所述信息块的长度K大于预设的阈值；或
    对于给定的编码码率R，目标码长M大于预设的阈值。
  6. 根据权利要求1-5任意一项所述的方法，其特征在于，确定母码长度
    Figure PCTCN2018080394-appb-100001
    表示向上取整，min(·)表示取最小值，N max表示***支持的最大母码长。
  7. 根据权利要求6所述的方法，其特征在于，
    p＝2，Nmax＝1024，所述Polar编码为PC-Polar编码，所述预设条件为以下中的一种：
    对于R＝1/12，所述待编码的信息比特序列长度Kc预设阈值Kc1，Kc1属于区间[330,370]的整数；
    对于R＝1/6，所述待编码的信息比特序列长度Kc大于预设阈值Kc2，Kc2属于区间[345,365]的整数；
    对于R＝1/4，所述待编码的信息比特序列长度Kc大于预设阈值Kc3，Kc3属于区间[370,380]的整数；
    对于R＝1/3，所述待编码的信息比特序列长度Kc大于预设阈值Kc4，Kc4属于区间[450,460]的整数；
    对于R＝2/5，所述待编码的信息比特序列长度Kc大于预设阈值Kc5，Kc5属于区间[500,510]的整数；
    对于R＝1/12，所述信息块的长度K大于预设阈值Kt1，Kt1属于区间[314-354]的整数；
    对于R＝1/6，所述信息块的长度K大于预设阈值Kt2，Kt2属于区间[329-349]的整数；
    对于R＝1/4，所述信息块的长度K大于预设阈值Kt3，Kt3属于区间[354-364]的整数；
    对于R＝1/3，所述信息块的长度K大于预设阈值Kt4，Kt4属于区间[434-444]的整数；
    对于R＝2/5，所述信息块的长度K大于预设阈值Kt5，Kt5属于区间[484-494]的整数；
    对于R＝1/12，所述目标码长M大于预设阈值Mt1，Mt1属于区间[3768-4248]的整数；
    对于R＝1/6，所述目标码长M大于预设阈值Mt2，Mt2属于区间[1974-2094]的整数；
    对于R＝1/4，所述目标码长M大于预设阈值Mt3，Mt3属于区间[1416-1456]的整数；
    对于R＝1/3，所述目标码长M大于预设阈值Mt4，Mt4属于区间[1302-1332]的整数；或
    对于R＝2/5，所述目标码长M大于预设阈值Mt5，Mt5属于区间[1210-1235]的整数。
  8. 根据权利要求6所述的方法，其特征在于，p＝2，Nmax＝1024，所述Polar编码为CA-Polar编码，所述预设条件为以下中的一种：
    对于R＝1/12，所述待编码的信息比特序列长度Kc预设阈值Kc1，Kc1属于区间[310-340]的整数；
    对于R＝1/6，所述待编码的信息比特序列长度Kc大于预设阈值Kc2，Kc2属于区间[350-365]的整数；
    对于R＝1/4，所述待编码的信息比特序列长度Kc大于预设阈值Kc3，Kc3属于区间[410-450]的整数；
    对于R＝1/3，所述待编码的信息比特序列长度Kc大于预设阈值Kc4，Kc4属于区间[470-495]的整数；
    对于R＝2/5，所述待编码的信息比特序列长度Kc大于预设阈值Kc5，Kc5属于区间[520-530]的整数；
    对于R＝1/12，所述信息块的长度K大于预设阈值Kt1，Kt1属于区间[291-321]的整数；
    对于R＝1/6，所述信息块的长度K大于预设阈值Kt2，Kt2属于区间[331-346]的整数；
    对于R＝1/4，所述信息块的长度K大于预设阈值Kt3，Kt3属于区间[391-431]的整数；
    对于R＝1/3，所述信息块的长度K大于预设阈值Kt4，Kt4属于区间[451-476]的整数；
    对于R＝2/5，所述信息块的长度K大于预设阈值Kt5，Kt5属于区间[501-511]的整数；
    对于R＝1/12，所述目标码长M大于预设阈值Mt1，Mt1属于区间[3492-3852]的整数；
    对于R＝1/6，所述目标码长M大于预设阈值Mt2，Mt2属于区间[1986-2076]的整数；
    对于R＝1/4，所述目标码长M大于预设阈值Mt3，Mt3属于区间[1564-1724]的整数；
    对于R＝1/3，所述目标码长M大于预设阈值Mt4，Mt4属于区间[1353-1428]的整数；或
    对于R＝2/5，所述目标码长M大于预设阈值Mt5，Mt5属于区间[1253-1278]的整数。
  9. 一种编码装置，其特征在于，包括：
    获取单元，用于获取待发送的信息块和Polar码的目标码长M；
    编码单元，确定Polar编码采用的母码码长N，当所述目标码长M大于N，若所述信息块的编码参数满足预设的条件，将待编码的信息比特序列分成p个子段，对P个子段分别进行独立的Polar编码，得到p个长度为分别子段母码长度的编码比特序列，其中p为大于等于2的整数；
    速率匹配单元，用于对p个编码结果分别进行速率匹配，得到p个长度分别为子段的目标码长的编码比特序列；
    合并单元，用于合并合并所述速率匹配后的p个编码比特序列，得到长度为M的编码比特序列。
  10. 根据权利要求9所述的装置，其特征在于，所述编码单元用于，若所述信息块的编码参数不满足所述预设的条件，采用所述母码码长N对待编码的信息比特序列进行Polar编码，得到长度为N的第一编码比特序列；所述速率匹配单元用于重复所述第一编码比特序列中的至少一部分比特，得到长度为M的编码比特序列；或
    所述编码单元用于，若所述目标码长M小于等于所述母码长度N，采用母码长度N对所述待编码的信息比特序列进行Polar编码得到第二编码比特序列；所述速率匹配单元用于对所述第二编码比特序列进行缩短或者打孔，得到长度为M的编码比特序列。
  11. 根据权利要求9或10所述的装置，其特征在于，所述编码单元用于，若目标码长Mi大于母码长度Ni，且Mi对应子段的编码参数不满足所述预设的条件，采用母码长度Ni对Mi对应的子段进行Polar编码，得到长度为Ni的第三编码比特序列；所述速率匹配单元用于重复所述第三编码比特序列中的至少一部分比特，得到长度为Mi的编码序列；或者
    所述编码单元用于，若目标码长Mi小于等于母码长度Ni，采用母码长度Ni对Ki对应的子段进行Polar编码得到第四编码比特序列；所述速率匹配单元用于对所述第四编码比特序列进行缩短或者打孔，得到长度为Mi的编码序列。
  12. 一种编码装置，其特征在于，包括：
    存储器，用于存储程序；
    处理器，用于执行所述存储器存储的所述程序，当所述程序被执行时，获取待发送的信息块和Polar码的目标码长M；确定Polar编码采用的母码码长N，当所述目标码长M大于N，若所述信息块的编码参数满足预设的条件，将待编码的信息比特序列分成p个子 段，对P个子段分别进行独立的Polar编码，得到p个长度为分别子段母码长度的编码比特序列，其中p为大于等于2的整数；对p个编码结果分别进行速率匹配，得到p个长度分别为子段的目标码长的编码比特序列；合并所述速率匹配后的p个编码比特序列，得到长度为M的编码比特序列。
  13. 根据权利要求12所述的装置，其特征在于，
    所述处理器用于，若所述信息块的编码参数不满足所述预设的条件，采用所述母码码长N对待编码的信息比特序列进行Polar编码，得到长度为N的第一编码比特序列，重复所述第一编码比特序列中的至少一部分比特，得到长度为M的编码比特序列；或者
    所述处理器用于，若所述目标码长M小于等于所述母码长度N，采用母码长度N对所述待编码的信息比特序列进行Polar编码得到第二编码比特序列，对所述第二编码比特序列进行缩短或者打孔，得到长度为M的编码比特序列。
  14. 根据权利要求12或13所述的装置，其特征在于，
    待编码的信息比特序列总长度为Kc，p个子段的信息比特长度分别为K1，K2，...，Kp，p个子段分别进行独立Polar编码采用的母码长度分别为N1，N2，...，Np，对应的目标码长分别为M1，M2，...，Mp，其中Kc＝K1+K2,+...,+Kp，M＝M1+M2,+...,+Mp，所述待编码的信息比特序列包括所述信息块，Kc大于等于所述信息块的长度K；
    所述处理器用于，对于每个Mi，若Mi对应的子段的目标码长Mi大于母码长度Ni，且Ki对应的子段的编码参数满足所述预设的条件，将Mi对应的子段进一步划分为p个子段分别进行独立的编码和速率匹配，得到对应的p个编码比特序列并进行合并，得到目标码长Mi的编码比特序列，其中，i＝1,2,...,p。
  15. 一种编码装置，其特征在于，包括：
    至少一个输入端，用于接收信息块；
    信号处理器，用于获取待发送的信息块和Polar码的目标码长M；确定Polar编码采用的母码码长N，当所述目标码长M大于N，若所述信息块的编码参数满足预设的条件，将待编码的信息比特序列分成p个子段，对P个子段分别进行独立的Polar编码，得到p个长度为分别子段母码长度的编码比特序列，其中p为大于等于2的整数；对p个编码结果分别进行速率匹配，得到p个长度分别为子段的目标码长的编码比特序列；合并所述速率匹配后的p个编码比特序列，得到长度为M的编码比特序列；
    至少一个输出端，用于输出信号处理器得到的编码比特序列。
  16. 根据权利要求15所述的装置，其特征在于，
    所述信号处理器用于，若所述信息块的编码参数不满足所述预设的条件，采用所述母码码长N对待编码的信息比特序列进行Polar编码，得到长度为N的第一编码比特序列，重复所述第一编码比特序列中的至少一部分比特，得到长度为M的编码比特序列；或者
    所述信号处理器用于，若所述目标码长M小于等于所述母码长度N，采用母码长度N对所述待编码的信息比特序列进行Polar编码得到第二编码比特序列，对所述第二编码比特序列进行缩短或者打孔，得到长度为M的编码比特序列。
  17. 根据权利要求15或16所述的装置，其特征在于，
    待编码的信息比特序列总长度为Kc，p个子段的信息比特长度分别为K1，K2，...，Kp，p个子段分别进行独立Polar编码采用的母码长度分别为N1，N2，...，Np，对应的目 标码长分别为M1，M2，...，Mp，其中Kc＝K1+K2,+...,+Kp，M＝M1+M2,+...,+Mp，所述待编码的信息比特序列包括所述信息块，Kc大于等于所述信息块的长度K；
    所述信号处理器用于，对于每个Mi，若Mi对应的子段的目标码长Mi大于母码长度Ni，且Ki对应的子段的编码参数满足所述预设的条件，将Mi对应的子段进一步划分为p个子段分别进行独立的编码和速率匹配，得到对应的p个编码比特序列并进行合并，得到目标码长Mi的编码比特序列，其中，i＝1,2,...,p。
  18. 一种Polar码译码方法，其特征在于，包括：
    接收待译码比特对应的对数似然比LLR，待译码比特长度为编码时的目标码长M；
    确定编码时的母码长度N，当所述目标码长M大于母码长度N时，若编码参数满足预设的条件，将待译码比特对应的LLR分成p个子段，对p个子段并分别进行解速率匹配，其中p为大于等于2的整数；
    对解速率匹配后的p个子段的LLR分别进行独立SCL译码，得到p个子段的译码结果；
    合并p个子段的译码结果，输出译码比特序列。
  19. 根据权利要求18所述的译码方法，其特征在于，p个子段的编码时采用的母码长度分别为N1，N2，...，Np，目标码长分别为M1，M2，...，Mp，对应的信息比特长度为K1，K2，...，Kp；
    对于每个子段Mi，i＝1,2,...,p，若Mi大于母码长度Ni，且Mi对应的子段的编码参数满足所述预设的条件，将Mi对应的子段的LLR序列进一步划分为p个子段分别进行解速率匹配并译码，得到对应的p个子段的译码结果，合并p个子段的译码结果得到对应的Ki个信息比特；或者
    对于每个子段Mi，i＝1,2,...,p，若Mi小于母码长度Ni，且Mi对应的子段的编码参数不满足所述预设的条件，将重复位置的LLR进行叠加，得到解速率匹配后的长度为Ni的LLR序列并进行译码，得到子段Mi的译码结果。
  20. 根据权利要求18所述的译码方法，其特征在于，当所述目标码长M小于母码长度N时，将打孔或者缩短位置的LLR进行恢复，得到解速率匹配后的长度为N的LLR序列并译码，得到译码比特序列。
  21. 一种译码装置，其特征在于，包括：
    接收单元，用于接收待译码比特对应的对数似然比LLR，待译码比特长度为编码时的目标码长M；
    解速率匹配单元，用于确定编码时的母码长度N，当所述目标码长M大于母码长度N时，若编码参数满足预设的条件，将待译码比特对应的LLR分成p个子段，对p个子段并分别进行解速率匹配，其中p为大于等于2的整数；
    译码单元，用于对p个子段的LLR分别进行独立SCL译码，得到p个子段的译码结果；
    输出单元，合并p个子段的译码结果，输出译码比特序列。
  22. 根据权利要求21所述的装置，其特征在于，
    p个子段的编码时采用的母码长度分别为N1，N2，...，Np，目标码长分别为M1，M2，...，Mp，对应的信息比特长度为K1，K2，...，Kp；
    所述解速率匹配单元用于，对于每个子段Mi，i＝1,2,...,p，若Mi大于母码长度Ni， 且Mi对应的子段的编码参数满足所述预设的条件，将Mi对应的子段的LLR序列进一步划分为p个子段分别进行解速率匹配，所述译码单元用于对p个解速率匹配后的LLR并译码，得到对应的p个子段的译码结果，所述合并单元用于合并p个子段的译码结果得到对应的Ki个信息比特；或者
    所述速率匹配单元用于，对于每个子段Mi，i＝1,2,...,p，若Mi小于母码长度Ni，且Mi对应的子段的编码参数不满足所述预设的条件，将重复位置的LLR进行叠加，得到速率匹配后的长度为Ni的LLR序列；所述译码单元用于对长度为Ni的LLR序列进行译码，得到子段Mi的译码结果。
  23. 根据权利要求21所述的装置，其特征在于，
    所述解速率匹配单元，当所述目标码长M小于母码长度N时，将打孔或者缩短位置的LLR进行恢复，得到速率匹配后的长度为N的LLR序列，所述译码单元用于对长度为N的LLR序列进行译码，得到译码比特序列。
  24. 一种译码装置，其特征在于，包括：
    存储器，用于存储程序；
    处理器，用于执行所述存储器存储的所述程序，当所述程序被执行时，接收待译码比特对应的对数似然比LLR，待译码比特长度为编码时的目标码长M；确定编码时的母码长度N，当所述目标码长M大于母码长度N时，若编码参数满足预设的条件，将待译码比特对应的LLR分成p个子段，对p个子段并分别进行解速率匹配；对p个子段的LLR分别进行独立SCL译码，得到p个子段的译码结果；合并p个子段的译码结果，输出译码比特序列，其中p为大于等于2的整数。
  25. 根据权利要求24所述的装置，其特征在于，
    p个子段的编码时采用的母码长度分别为N1，N2，...，Np，目标码长分别为M1，M2，...，Mp，对应的信息比特长度为K1，K2，...，Kp；
    所述处理器用于，对于每个子段Mi，i＝1,2,...,p，若Mi大于母码长度Ni，且Mi对应的子段的编码参数满足所述预设的条件，将Mi对应的子段的LLR序列进一步划分为p个子段分别进行解速率匹配并译码，得到对应的p个子段的译码结果，合并p个子段的译码结果得到对应的Ki个信息比特；或者
    所述处理器用于，对于每个子段Mi，i＝1,2,...,p，若Mi小于母码长度Ni，且Mi对应的子段的编码参数不满足所述预设的条件，将重复位置的LLR进行叠加，得到解速率匹配后的长度为Ni的LLR序列并进行译码，得到子段Mi的译码结果。
  26. 根据权利要求24所述的装置，其特征在于，所述处理器用于，当所述目标码长M小于母码长度N时，将打孔或者缩短位置的LLR进行恢复，得到解速率匹配后的长度为N的LLR序列并译码，得到译码比特序列。
  27. 一种译码装置，其特征在于，包括：
    至少一个输入端，用于接收待译码比特对应的对数似然比LLR，待译码比特长度为编码时的目标码长M；
    信号处理器，用于接收待译码比特对应的对数似然比LLR，待译码比特长度为编码时的目标码长M；确定编码时的母码长度N，当所述目标码长M大于母码长度N时，若编码参数满足预设的条件，将待译码比特对应的LLR分成p个子段，对p个子段并分别进行解速率匹配；对p个子段的LLR分别进行独立SCL译码，得到p个子段的译码结果；合 并p个子段的译码结果，输出译码比特序列，其中p为大于等于2的整数；
    至少一个输出端，用于输出信号处理器得到的译码比特序列。
  28. 根据权利要求27所述的装置，其特征在于，
    p个子段的编码时采用的母码长度分别为N1，N2，...，Np，目标码长分别为M1，M2，...，Mp，对应的信息比特长度为K1，K2，...，Kp；
    所述信号处理器用于，对于每个子段Mi，i＝1,2,...,p，若Mi大于母码长度Ni，且Mi对应的子段的编码参数满足所述预设的条件，将Mi对应的子段的LLR序列进一步划分为p个子段分别进行解速率匹配并译码，得到对应的p个子段的译码结果，合并p个子段的译码结果得到对应的Ki个信息比特；或者
    所述信号处理器用于，对于每个子段Mi，i＝1,2,...,p，若Mi小于母码长度Ni，且Mi对应的子段的编码参数不满足所述预设的条件，将重复位置的LLR进行叠加，得到解速率匹配后的长度为Ni的LLR序列并进行译码，得到子段Mi的译码结果。
  29. 根据权利要求27所述的装置，其特征在于，所述信号处理器用于，当所述目标码长M小于母码长度N时，将打孔或者缩短位置的LLR进行恢复，得到解速率匹配后的长度为N的LLR序列并译码，得到译码比特序列。
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