WO2018168180A1 - Solar cell and method for manufacturing same - Google Patents

Solar cell and method for manufacturing same Download PDF

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Publication number
WO2018168180A1
WO2018168180A1 PCT/JP2018/001079 JP2018001079W WO2018168180A1 WO 2018168180 A1 WO2018168180 A1 WO 2018168180A1 JP 2018001079 W JP2018001079 W JP 2018001079W WO 2018168180 A1 WO2018168180 A1 WO 2018168180A1
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semiconductor layer
conductive
thin film
region
layer
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PCT/JP2018/001079
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French (fr)
Japanese (ja)
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貴久 藤本
小西　克典
足立　大輔
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株式会社カネカ
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Definitions

  • the present invention relates to a solar cell and a manufacturing method thereof.
  • the back contact type solar cell includes both a p-type semiconductor layer and an n-type semiconductor layer on the back side of the semiconductor substrate, and includes electrodes on these conductive semiconductor layers. Since the back contact solar cell has an electrode only on the back surface of the semiconductor substrate and no electrode on the light receiving surface, there is no shadowing loss due to the electrode, and high conversion efficiency can be realized. Since the back contact solar cell has both the p-type semiconductor layer and the n-type semiconductor layer on the back side of the semiconductor substrate, it is necessary to pattern the semiconductor layer so that the effective region is wide and no leakage between pn occurs. There is.
  • FIG. 4A to 4J are conceptual diagrams of the manufacturing process on the back side of the back contact solar cell disclosed in Patent Document 1.
  • FIG. 4A the intrinsic semiconductor layer 431 and the first conductive type semiconductor layer 432 are sequentially formed on the back surface (upper side of the drawing) of the semiconductor substrate 1 (FIG. 4A), and the insulating layer 451 is formed on the first conductive type semiconductor layer 432. (FIG. 4B).
  • a part of the insulating layer 451 is removed by etching and patterning is performed (FIG. 4C).
  • the first conductive type semiconductor layer 432 and the intrinsic semiconductor layer 431 exposed thereunder are formed. Is etched and patterned (FIG. 4D).
  • an intrinsic semiconductor layer 441 and a second conductivity type semiconductor layer 442 are formed on the entire back surface (FIG. 4E).
  • the second conductive semiconductor layer 442, the intrinsic semiconductor layer 441, and the insulating layer 451 provided on the patterned first conductive semiconductor layer 432 are etched and patterned to expose the first conductive semiconductor layer 432. .
  • a pattern resist is provided on the second semiconductor layer 442, and the second conductive semiconductor layer 442 and the intrinsic semiconductor layer 441 on the insulating layer 451 are removed by etching (FIG. 4F).
  • the insulating layer 451 is etched with an acid-based etchant such as hydrofluoric acid using the second conductivity type semiconductor layer 442 as a mask (FIG. 4G).
  • the intrinsic semiconductor layer 431 and the first conductivity type semiconductor layer are formed on the semiconductor substrate 1 at the boundary between the formation region of the first conductivity type semiconductor layer 432 and the formation region of the second conductivity type semiconductor layer 442.
  • a boundary region 450 is formed in which 432, an insulating layer 451, an intrinsic semiconductor layer 441, and a second conductivity type semiconductor layer 442 are provided in this order.
  • a conductive thin film 443 made of a conductive oxide or metal is formed on the entire back surface (FIG. 4H).
  • the conductive thin film on or near the boundary region is removed by etching, laser processing, or the like, so that the conductive thin film 443a on the first conductive type semiconductor layer 432 and the conductive thin film 443b on the second conductive type semiconductor layer 442 are obtained.
  • FIG. 4I By forming metal electrodes 435 and 445 on the conductive thin films 443a and 443b, a back contact solar cell is completed (FIG. 4J).
  • the first conductive type semiconductor layer and the second conductive type semiconductor layer overlap with each other, so that the effective power generation amount region. Since an insulating layer is provided between the first conductive semiconductor layer and the second conductive semiconductor layer, leakage between pn can be prevented.
  • the second conductive semiconductor layer 442 is etched on the second conductive semiconductor layer 442 on the first conductive semiconductor layer 432 (FIG. 4F).
  • a resist is provided on the substrate, and the resist is removed after etching. Therefore, the second conductivity type semiconductor layer 442 comes into contact with a chemical solution such as a resist solution or a stripping solution.
  • the insulating layer 451 is etched using an etchant such as hydrofluoric acid with the second conductivity type semiconductor layer 442 as a mask (FIG. 4G)
  • the etchant contacts the second conductivity type semiconductor layer 442.
  • the etchant also contacts the first conductive semiconductor layer 432 exposed by etching the insulating layer 451. As described above, when the semiconductor layer and the insulating layer are patterned, if the semiconductor layer comes into contact with the chemical solution, the semiconductor layer is damaged, and the power generation characteristics of the solar cell deteriorate due to an increase in contact resistance or a decrease in open-circuit voltage. There is.
  • an object of the present invention is to provide a back-contact solar cell that is excellent in carrier recovery efficiency and in which deterioration of characteristics due to patterning or the like is suppressed.
  • the present invention relates to a back contact solar cell in which a first conductivity type region and a second conductivity type region are alternately arranged along a first direction on a first main surface of a semiconductor substrate, and a manufacturing method thereof.
  • a boundary region that is in contact with and separates the first conductivity type region and the second conductivity type region is provided.
  • a first conductive type semiconductor layer, a second conductive type semiconductor layer, a first conductive thin film, a second conductive thin film, and an insulating layer are provided on the first main surface of the semiconductor substrate.
  • the first conductivity type semiconductor layer and the second conductivity type semiconductor layer have different conductivity types, one is p-type and the other is n-type.
  • Each layer on the first main surface of the semiconductor substrate is patterned.
  • the first conductive type semiconductor layer and the first conductive thin film are provided across the entire surface of the first conductive type region and the boundary region.
  • the second conductive type semiconductor layer and the second conductive thin film are provided across the entire surface of the second conductive type region and the boundary region.
  • the insulating layer is provided on the entire boundary region.
  • first conductivity type region a first conductivity type semiconductor layer and a first conductive thin film are provided in this order on a semiconductor substrate.
  • second conductivity type region the second conductivity type semiconductor layer and the second conductive thin film are provided in this order on the semiconductor substrate.
  • the first conductive thin film is preferably provided in the first boundary region in contact with the first conductivity type region and not in the second boundary region in contact with the second conductivity type region.
  • the side surface of the first conductive thin film is covered with the insulating layer at the boundary portion between the first boundary region and the second boundary region.
  • a first conductive type semiconductor layer, a first conductive thin film, and an insulating layer are provided in this order on the semiconductor substrate.
  • a second conductive semiconductor layer and a second conductive thin film may be provided in this order on the insulating layer.
  • the second conductive type semiconductor layer and the second conductive thin film are provided in this order on the insulating layer.
  • the first conductive thin film is not provided between the semiconductor substrate and the insulating layer.
  • the first conductivity type semiconductor layer may or may not be provided between the semiconductor substrate and the insulating layer.
  • a first intrinsic semiconductor layer is provided between the semiconductor substrate and the first conductivity type semiconductor layer.
  • a second intrinsic semiconductor layer is preferably provided between the semiconductor substrate and the second conductivity type semiconductor layer.
  • a pattern layer in which a first conductive type semiconductor layer, a first conductive thin film, and an insulating layer are laminated in this order is formed in the first conductive type region and the boundary region; A second conductive type semiconductor layer and a second conductive thin film are sequentially formed on the region; the insulating layer provided in the first conductive type region can be removed by etching.
  • the second conductive type semiconductor layer and the second conductive thin film are patterned so as to have an opening in the first conductive type region, and the insulating layer is exposed under the opening of the second conductive type semiconductor layer. Therefore, the insulating layer provided in the first conductivity type region can be selectively removed by etching. For example, a second conductive type semiconductor layer and a second conductive thin film are sequentially formed on the entire surface of the substrate, and the second conductive type semiconductor layer and the second conductive thin film provided in the first conductive type region are removed by etching. Thus, an opening is formed in the second conductive type semiconductor layer and the second conductive thin film.
  • the first conductive thin film is not provided at both ends of the pattern layer, and the side surfaces of the first conductive thin film are covered with an insulating layer.
  • the second conductive type semiconductor layer and the second conductive thin film are formed, and the insulating layer exposed under the opening of the second conductive type semiconductor layer is etched to thereby form the first boundary region and the first conductive layer.
  • a solar cell in which the side surface of the first conductive thin film is covered with the insulating layer at the boundary portion between the two boundary regions is obtained.
  • a first conductive thin film having openings at both ends of the pattern layer forming region is formed on the first conductive type semiconductor layer, an insulating layer is formed on the entire surface of the substrate, and then provided in the second conductive type region. By etching away the formed layer, a pattern layer in which the first conductive thin film is not provided at both ends can be formed.
  • the conductive thin film is provided on the first conductivity type semiconductor layer in the boundary region, the carriers that have reached the boundary region can be effectively collected. Further, since the conductive thin film provided on the first conductivity type semiconductor layer in the boundary region is covered with the insulating layer, leakage between pn can be prevented and high conversion characteristics can be realized. Furthermore, since the conductive thin film is provided on each of the first conductive type semiconductor layer and the second conductive type semiconductor layer, contact between the semiconductor layer and a chemical solution such as an etchant in the manufacturing process of the solar cell is prevented. The damage to the semiconductor layer can be reduced and the characteristics of the solar cell can be improved.
  • FIG. 2 is a schematic plan view for explaining the shapes of the first conductivity type region and the second conductivity type region in the back contact solar cell.
  • FIG. 1 is a schematic cross-sectional view of a back contact solar cell according to an embodiment of the present invention, and corresponds to a cross section in the left-right direction (x direction) of FIG.
  • the lower side (second main surface) in FIG. 1 is the light receiving surface of the solar cell, and the upper side (first main surface) is the back surface of the solar cell.
  • the first conductivity type regions 30 and the second conductivity type regions 40 are alternately arranged along the first direction (x direction).
  • the first conductivity type region 30 and the second conductivity type region 40 each extend along a second direction (y direction) orthogonal to the first direction.
  • the first conductivity type region 30 and the second conductivity type region 40 are provided in a comb shape that meshes with each other.
  • the shape of the first conductivity type region 30 and the second conductivity type region 40 does not have to be a comb shape.
  • the first conductivity type region 30 and the second conductivity type region 40 may have a shape that extends in the x direction and connects the comb teeth (so-called bus bar portion). Good.
  • the first conductivity type region 30 is provided with a first conductivity type semiconductor layer 32
  • the second conductivity type region 40 is provided with a second conductivity type semiconductor layer 42.
  • the first conductivity type semiconductor layer 32 and the second conductivity type semiconductor layer 42 have different conductivity types, one is p-type and the other is n-type.
  • a boundary region 50 in contact with both is provided, and the first conductivity type region 30 and the second conductivity type region 40 are separated from each other. .
  • the width of the first conductivity type region 30 and the width of the second conductivity type region 40 are not particularly limited, and may be equal to or different from each other.
  • the width of the first conductivity type region 30 and the width of the second conductivity type region 40 are, for example, about 100 to 1500 ⁇ m.
  • the width of the boundary region 50 is not particularly limited.
  • the width of the boundary region is, for example, about 10 to 500 ⁇ m.
  • the width of the boundary region 50 is preferably as small as possible within a range in which leakage between pn and leakage between the first conductive thin film 33 and the second conductivity type semiconductor layer 42 can be prevented.
  • a first intrinsic semiconductor layer 31 In the back contact solar cell shown in FIG. 1, on the first main surface of the semiconductor substrate 1, a first intrinsic semiconductor layer 31, a first conductive semiconductor layer 32, a first conductive thin film 33, an insulating layer 51, a second An intrinsic semiconductor layer 41, a second conductive type semiconductor layer 42, and a second conductive thin film 43 are provided. Each of these layers is patterned on the first major surface.
  • the first conductivity type is p-type and the second conductivity type is n-type.
  • the solar cell of the present invention may be n-type for the first conductivity type and p-type for the second conductivity type.
  • the p-type semiconductor layer 32 is provided across the p-type region 30 and the boundary region 50.
  • the n-type semiconductor layer 42 is provided across the n-type region 40 and the boundary region 50.
  • an insulating layer 51 is provided between the p-type semiconductor layer 32 and the n-type semiconductor layer 42.
  • the insulating layer 51 is provided on the entire boundary region 50. In other words, the region where the insulating layer 51 is provided is the boundary region 50. In the boundary region 50, the insulating layer 51 prevents leakage between the p-type semiconductor layer 32 and the n-type semiconductor layer 42.
  • the first conductive thin film 33 is provided across the p-type region 30 and the boundary region 50. In the p-type region 30, the first conductive thin film 33 is provided on the p-type semiconductor layer 32, and the first metal electrode 35 is provided thereon.
  • the first conductive thin film 33 is provided on the p-type semiconductor layer 32, and the insulating layer 51 is provided thereon.
  • the solar cell shown in FIG. 4J since no conductive layer is provided on the first conductive type semiconductor layer 432 in the boundary region 450, a recovery loss of carriers reaching this region is likely to occur.
  • the solar cell shown in FIG. 1 can improve the recovery efficiency of the carriers that have reached the boundary region 50.
  • the first conductive thin film 33 is not provided on the p-type semiconductor layer 32, and the p-type semiconductor layer 32 and the insulating layer 51 are in contact with each other. Preferably it is.
  • the side surface of the first conductive thin film 33 is covered with the insulating layer 51 at the boundary portion between the first boundary region 101 and the second boundary region 102. It has been broken.
  • a second conductive thin film 43 is provided on the n-type semiconductor layer 42.
  • the second conductive thin film 43 is provided on the n-type semiconductor layer 42, and the second metal electrode 45 is provided thereon. Similar to the n-type semiconductor layer 42, the second conductive thin film 43 may be provided across the n-type region 40 and the boundary region 50.
  • the second conductive thin film 43 is preferably provided on the entire surface of the n-type semiconductor layer 42.
  • the second metal electrode 45 on the second conductive thin film 43 may protrude from the boundary region 50.
  • the p-type semiconductor layer 32 and the first conductive thin film 33 are formed on the semiconductor substrate 1 in the first boundary region 101.
  • An insulating layer 51, an n-type semiconductor layer 42, and a second conductive thin film 43 are provided in this order; in the second boundary region 102, a p-type semiconductor layer 32, an insulating layer 51, and an n-type semiconductor are formed on the semiconductor substrate 1.
  • a layer 42 and a second conductive thin film 43 are provided in this order.
  • the first intrinsic semiconductor layer 31 is preferably provided between the semiconductor substrate 1 and the p-type semiconductor layer 32. That is, the first intrinsic semiconductor layer 31 is preferably provided across the p-type region 30 and the boundary region 50.
  • the p-type semiconductor layer 32 may not be provided in the second boundary region 102.
  • the insulating layer 51 is provided on the semiconductor substrate 1 or in contact with the first intrinsic semiconductor layer 31 (see FIGS. 7 and 8).
  • the second intrinsic semiconductor layer 41 is preferably provided between the semiconductor substrate 1 and the n-type semiconductor layer 42.
  • the second intrinsic semiconductor layer 41 may be provided between the insulating layer 51 and the n-type semiconductor layer 42.
  • the second intrinsic semiconductor layer 41 may be provided across the n-type region 40 and the boundary region 50.
  • [Solar cell manufacturing process] 3A to 3I are process conceptual diagrams showing an example of the manufacturing process of the back contact solar cell shown in FIG. Below, with reference to these figures, the process of film-forming and patterning of each layer on the 1st main surface of a solar cell is demonstrated.
  • the semiconductor substrate 1 is prepared.
  • the semiconductor substrate 1 is preferably a crystalline silicon substrate.
  • the crystalline silicon substrate may be either single crystal silicon or polycrystalline silicon.
  • the conductivity type of the crystalline silicon substrate may be either n-type or p-type.
  • the thickness of the semiconductor substrate is, for example, about 100 to 300 ⁇ m.
  • a texture structure is preferably formed on the surface of the second main surface (light receiving surface) of the semiconductor substrate 1.
  • a texture structure may also be formed on the first main surface of the semiconductor substrate. By providing a texture structure on the surface of the semiconductor substrate, surface reflection is reduced, and the amount of light incident on the semiconductor substrate can be increased.
  • a pyramidal texture can be formed by anisotropic etching.
  • a pattern layer forming region 100 provided with a pattern layer 13 and an exposed region 200 where the first main surface of the semiconductor substrate is exposed are formed on the first main surface of the semiconductor substrate 1.
  • the exposed region 200 corresponds to the n-type region (second conductivity type region) 40 of the completed solar cell.
  • the pattern layer 13 has a configuration in which a p-type semiconductor layer 32, a first conductive thin film 33, and an insulating layer 51 are sequentially stacked.
  • a p-type semiconductor layer 32 and an insulating layer 51 are provided on the entire surface of the pattern layer forming region 100.
  • An intrinsic semiconductor layer 31 is preferably provided between the semiconductor substrate 1 and the p-type semiconductor layer 32.
  • the first conductive thin film 33 is not provided, and the p-type semiconductor layer 32 and the insulating layer 51 are in contact with each other.
  • the pattern layer forming region 100 preferably has a central region 103 where the first conductive thin film 33 is provided and an end region 102 where the first conductive thin film 33 is not provided. In the completed solar cell, this end region 102 corresponds to the second boundary region 102 of the boundary region 50.
  • the insulating layer 51 is provided over the entire pattern layer forming region 100, and the side surface of the first conductive thin film 33 is covered with the insulating layer 51 at the boundary between the central region 103 and the end region 102.
  • the first conductive thin film 33 and the insulating layer 51 are provided on the p-type semiconductor layer 32, and in the end region 102 where the first conductive thin film 33 is not provided, the semiconductor layer An insulating layer 51 is provided in contact with the substrate.
  • the respective layers are formed in a state where the exposed region 200 is shielded by a mask.
  • the first conductive thin film 33 is formed with the end regions 102 at both ends of the pattern layer forming region 100 in addition to the exposed region 200 being shielded by the mask.
  • a pattern layer in which the insulating layer 51 covers the side surface of the first conductive thin film 33 can be formed.
  • the pattern layer 13 is formed by repeatedly performing film formation and etching on the entire surface of the substrate.
  • the film may not be formed in a non-power generation region such as an end portion of the substrate.
  • a p-type semiconductor layer 32 is formed on the entire first main surface of the semiconductor substrate 1.
  • the p-type semiconductor layer 32 is a semiconductor thin film to which a p-type dopant is added, and is preferably a p-type silicon-based layer to which boron is added. From the viewpoint of suppressing impurity diffusion and reducing series resistance, the p-type semiconductor layer 32 is preferably a p-type amorphous silicon-based layer, and a p-type amorphous silicon layer is particularly preferable.
  • the thickness of the p-type semiconductor layer 32 is, for example, about 2 to 50 nm.
  • the intrinsic semiconductor layers 31 and 41 are preferably provided between the semiconductor substrate 1 and the p-type semiconductor layer 32 and between the semiconductor substrate 1 and the n-type semiconductor layer 42.
  • the intrinsic semiconductor layers 31 and 41 are provided on the semiconductor substrate 1, surface passivation of the semiconductor substrate 1 can be effectively performed. Further, by providing the intrinsic semiconductor layers 31 and 41, it is possible to suppress the diffusion of impurities to the semiconductor substrate 1 when forming the conductive semiconductor layers 32 and 42.
  • As the intrinsic semiconductor layer an intrinsic amorphous silicon thin film composed of silicon and hydrogen is preferable. Since the intrinsic semiconductor layers 31 and 41 do not directly contribute to the generation and recovery of photocarriers, the film thickness is set in a range where a passivation effect can be obtained, and is, for example, about 0.1 to 25 nm.
  • a plasma CVD method is preferable as a method for forming the intrinsic semiconductor layer and the conductive semiconductor layer.
  • a silicon-containing gas such as SiH 4 or Si 2 H 6 or a mixed gas of silicon-based gas and H 2 is preferably used for forming a silicon-based semiconductor thin film by the plasma CVD method.
  • B 2 H 6 or PH 3 is preferably used as the dopant gas for forming the p-type or n-type silicon-based thin film.
  • the first conductive thin film 33 is formed on the p-type semiconductor layer 32.
  • the first conductive thin film 33 has a function of collecting optical carriers from the p-type semiconductor layer 32 in the completed solar cell.
  • the first conductive thin film 33 serves to protect the surface of the p-type semiconductor layer 32 from a chemical solution such as an etchant.
  • the second conductive thin film 43 has a function of recovering optical carriers from the n-type semiconductor layer 42 in the completed solar cell, and plays a role of protecting the n-type semiconductor layer 42 from the chemical solution in the manufacturing process of the solar cell. .
  • a metal thin film, a conductive oxide thin film, or the like is preferable.
  • metal oxides such as indium oxide, zinc oxide, tin oxide, and titanium oxide are preferable because they have high durability against chemicals and excellent protection against semiconductor layers.
  • the conductive oxide may be a composite metal oxide.
  • the material of the conductive thin films 33 and 43 is preferably an indium oxide mainly composed of indium oxide because of its excellent conductivity and long-term reliability, and indium tin oxide (ITO) is particularly preferable.
  • the film thickness of the conductive thin films 33 and 43 is, for example, about 10 nm to 200 nm.
  • a method for forming the conductive thin film is not particularly limited, but a dry process such as a physical vapor deposition method such as sputtering or a chemical vapor deposition (MOCVD) method using a reaction between an organometallic compound and oxygen or water is preferable. .
  • a dry process such as a physical vapor deposition method such as sputtering or a chemical vapor deposition (MOCVD) method using a reaction between an organometallic compound and oxygen or water is preferable.
  • the patterning of the first conductive thin film 33 is performed, and an opening 33a is formed as shown in FIG. 3C.
  • the patterning of the first conductive thin film 33 is performed, for example, by photolithography.
  • photolithography a resist film is formed in a portion where the first conductive thin film 33 should remain, and the first conductive thin film 33 exposed under the opening of the resist film is removed by etching.
  • etching a chemical solution that dissolves the first conductive thin film 33 and hardly dissolves the underlying semiconductor layer is used.
  • the first conductive thin film 33 is a conductive oxide such as ITO, an aqueous iron chloride solution, hydrochloric acid, or the like is preferably used as an etchant.
  • patterning may be performed using an etching paste or an etching ink.
  • an etching paste or an etching ink may be applied to a portion where the first conductive thin film 33 is to be removed (a portion where the opening 33a is provided) by screen printing, ink jet printing, or the like.
  • an insulating layer 51 is formed on the patterned first conductive thin film. Since the first conductive thin film 33 is patterned, when an insulating layer is formed on the entire surface of the first main surface, the insulating layer 51 is formed in contact with the p-type semiconductor layer 32 in the opening 33a. The side surface of the thin film 33 is covered with the insulating layer 51.
  • the material of the insulating layer 51 is not particularly limited as long as it has insulating properties and can suppress leakage between the p-type semiconductor layer 32 and the n-type semiconductor layer 42. Since the patterning by etching is easy, the material of the insulating layer 51 is preferably a material mainly composed of a silicon alloy such as silicon oxide, silicon nitride, or silicon oxynitride, and silicon oxide is particularly preferable.
  • the insulating layer 51 is preferably formed by a dry process such as a sputtering method or a plasma CVD method.
  • Each layer provided on the region 200 is removed by etching to expose the semiconductor substrate 1 as shown in FIG. 3E.
  • the insulating layer may be patterned by photolithography using a resist, an etching paste, or the like.
  • an acid-based etchant such as a hydrofluoric acid aqueous solution is preferably used.
  • the first conductive thin film 33, the p-type semiconductor layer 32 exposed between the insulating layers, and the intrinsic semiconductor layer 31 provided thereunder are removed by etching.
  • an aqueous iron chloride solution, hydrochloric acid, or the like is preferably used for etching the conductive thin film.
  • an aqueous solution containing hydrofluoric acid is used, and in particular, a mixed acid of hydrofluoric acid and nitric acid is preferably used.
  • FIG. 3D shows a form in which the opening 33a is formed only in a portion corresponding to the end region 102 of the pattern layer 13, the opening 33a of the first conductive thin film 33 is formed in the exposed region 200 as shown in FIG. May also be formed.
  • the opening 33a of the first conductive thin film 33 is provided in the entire region 200, the first conductive film is formed when each layer provided on the region 200 is removed by etching after the insulating layer 33 is formed. There is no need to perform etching of the thin film 33.
  • the end region 102 of the pattern layer 13 (region where the first conductive thin film 33 is not provided) ) May be patterned so as to be wide.
  • the semiconductor substrate 1 is exposed in the exposed region 200 as shown in FIG. 3E.
  • the surface of the insulating layer 51 or the surface of the semiconductor substrate 1 in the exposed region 200 may be contaminated by the residue or etchant of the film removed by the etching. . Therefore, it is preferable to clean the substrate after forming the pattern layer and before forming the semiconductor layer on the exposed region 200.
  • the cleaning liquid used for cleaning is not particularly limited as long as the surface of the semiconductor substrate can be cleaned. Since the cleaning effect is high, it is preferable to use an aqueous solution containing hydrofluoric acid as the cleaning liquid.
  • the first conductive thin film 33 and the insulating layer 51 are provided on the p-type semiconductor layer 32, damage to the p-type semiconductor layer due to contact with the cleaning liquid is prevented. it can.
  • the conductive layer comes into contact with the cleaning liquid in the cleaning process, metal ions eluted in the cleaning liquid cause contamination of the semiconductor substrate.
  • the conductive material constituting the first conductive thin film does not elute into the cleaning liquid, which is caused by metal ions or the like eluted into the cleaning liquid. The contamination of the semiconductor substrate can be prevented.
  • ⁇ N-type semiconductor layer and second conductive thin film> After the pattern layer 13 is formed and the substrate surface is cleaned as necessary, as shown in FIG. 3H, a patterned n-type semiconductor layer 42 having an opening 42a in the central region 30 of the pattern layer forming region 100 is formed. Then, the second conductive thin film 43 is formed. An intrinsic semiconductor layer 41 is preferably formed between the semiconductor substrate 1 and the n-type semiconductor layer 42. An intrinsic semiconductor layer 41 may be provided between the insulating layer 51 and the n-type semiconductor layer 42.
  • each layer is formed while the p-type region 30 is shielded by a mask; and on the substrate
  • Examples include a method of forming each layer on the entire surface and sequentially patterning by etching or the like.
  • FIGS. 3F to 3H a description will be given of a form in which the patterned n-type semiconductor layer 42 and the second conductive thin film 43 are formed by repeating film formation and etching on the entire surface of the substrate. .
  • an n-type semiconductor layer 42 is formed so as to cover the entire surface of the substrate.
  • the n-type semiconductor layer 42 is a semiconductor thin film layer to which an n-type dopant is added, and is preferably an n-type silicon-based layer to which phosphorus is added. From the viewpoint of suppressing impurity diffusion and reducing series resistance, the n-type semiconductor layer 42 is preferably an n-type amorphous silicon-based layer, and n-type amorphous silicon is particularly preferable.
  • the thickness of the n-type semiconductor layer 42 is, for example, about 2 to 50 nm.
  • the second conductive thin film 43 is formed on the n-type semiconductor layer 42.
  • the material of the second conductive thin film 43 is preferably a metal thin film or a conductive oxide thin film.
  • the second conductive thin film 43, the n-type semiconductor layer 42 and the intrinsic semiconductor layer 41 in the central region 30 of the pattern layer forming region 100 are removed by etching to form an opening 42a as shown in FIG.
  • the insulating layer 51 is exposed.
  • an alkaline aqueous solution containing KOH, NaOH, or the like is preferably used for the etching of the n-type semiconductor layer 42 and the intrinsic semiconductor layer 41.
  • the resist is provided on the second conductive thin film 43. Therefore, the surface of the n-type semiconductor layer 42 does not come into contact with a chemical solution such as a resist solution, a developer solution, or a stripping solution, and damage to the semiconductor layer due to contact with the chemical solution can be prevented.
  • ⁇ Insulating layer patterning> The insulating layer 51 exposed under the opening 42a in the central region 30 of the pattern layer forming region 100 is removed by etching, so that the first conductive thin film 33 is exposed as shown in FIG. 3I.
  • an acid-based etchant such as a hydrofluoric acid aqueous solution is preferably used for etching the insulating layer 51.
  • the region where the insulating layer 51 is removed corresponds to the p-type region 30 of the solar cell, and the region where the insulating layer remains without being removed corresponds to the boundary region 50 of the solar cell.
  • the insulating layer 51 exposed under the opening 42a of the n-type semiconductor layer 42 is removed by etching, the side surfaces of the n-type semiconductor layer 42 and the side surfaces of the insulating layer 51 are aligned.
  • a solar cell in which the n-type semiconductor layer 42 is provided on the entire surface (both the first boundary region 101 and the second boundary region 102) is obtained.
  • the first conductive thin film 33 is exposed. Since the first conductive thin film 33 is provided on the p-type semiconductor layer 42, an etchant used for etching the insulating layer is prevented from contacting the p-type semiconductor layer, and damage to the p-type semiconductor layer is prevented. it can. In the region where the insulating layer is not etched (the region other than the p-type region 30), the second conductive thin film 43 is provided on the n-type semiconductor layer 42. Therefore, the n-type semiconductor layer is brought into contact with the etchant. Damage to 42 can be prevented.
  • the first conductivity for the purpose of carrier recovery from the p-type semiconductor layer and protection from the chemical solution of the p-type semiconductor layer on the p-type semiconductor layer 32 as the first conductivity type semiconductor layer After forming the conductive thin film 33, the insulating layer 51 is formed, and then the n-type semiconductor layer 42 as the second conductivity type semiconductor layer is formed. After forming the second conductive thin film 43 for the purpose of carrier recovery from the n-type semiconductor layer and protection of the n-type semiconductor layer from the chemical solution on the n-type semiconductor layer 42, the second conductive thin film by etching and the n-type semiconductor are formed. Patterning of the layer 42 and the insulating layer 51 is performed. Thus, by providing the first conductive thin film 33 and the second conductive thin film 43 in the first conductive semiconductor layer 32 and the second conductive semiconductor layer 42, respectively, the semiconductor layer caused by contact with the chemical solution Can be prevented, and the characteristics of the solar cell can be improved.
  • the first conductive thin film 33 is not provided in the second boundary region 102 in contact with the second conductivity type region 40, and the side surface of the first conductive thin film 33 is formed by the insulating layer 51. If it is covered, the leakage current from the first conductive thin film 33 to the second conductive type semiconductor layer 42 can be suppressed.
  • the side surface of the first conductivity type semiconductor layer 32 may be covered with an insulating layer 51. If the side surface of the first conductivity type semiconductor layer 32 is covered with the insulating layer 51, the leakage between the first conductivity type semiconductor layer 32 and the second conductivity type semiconductor layer 42 can be further reduced.
  • the side surface of the first intrinsic semiconductor layer 31 is not covered with the insulating layer 51, and the first intrinsic semiconductor layer 31 is provided on the entire boundary region 50.
  • the first intrinsic semiconductor layer 41 or the second intrinsic semiconductor layer 42 is provided on the entire first main surface of the semiconductor substrate 1, the passivation effect of the semiconductor substrate is enhanced, and the first conductivity type semiconductor is provided. Since the side surface of the layer 32 is covered with the insulating layer 51, the leakage between pn can be more reliably reduced.
  • a first metal electrode 35 and a second metal electrode 45 are formed on the first conductive thin film 33 and the second conductive thin film 43, respectively.
  • the formation method of the metal electrodes 35 and 45 is not particularly limited, and may be formed by, for example, a dry process such as sputtering, printing, plating, or the like.
  • the thickness of the metal electrodes 35 and 45 is set to, for example, about 50 nm to 100 ⁇ m.
  • the metal electrodes 35 and 45 may have a laminated structure including a plurality of layers. For example, Cu or the like may be formed by electrolytic plating on a metal layer formed by printing such as Ag paste.
  • the metal may be deposited on the conductive thin films 33 and 43 as a conductive base.
  • a conductive base layer may be provided on the conductive thin films 33 and 34 by printing or the like, and a metal electrode may be formed thereon by plating.
  • the metal grows not only in the thickness direction but also in the width direction. Therefore, the electrode formation region is limited so that a short circuit between the first metal electrode 35 and the second metal electrode 45 does not occur. It is preferable.
  • an insulating layer such as a resist film may be formed on the first conductive thin film 33 and the second conductive thin film 43, and a metal may be deposited on the opening of the insulating layer by plating.
  • the plated metal is deposited on the opening portion of the insulating layer 59.
  • the insulating layer 59 may be provided before or after the formation of the base seed metal layer. After forming the base seed metal layers 35a and 45b on the conductive thin films 33 and 43, an insulating layer 59 is formed on the entire surface of the substrate as shown in FIG. 9A, and the base seed metal layer 35a as shown in FIG. 9B. , 45b may be selectively formed on the seed metal layers 35a, 45a to selectively deposit the plating metals 35b, 45b.
  • the insulating layer 59 is formed during or after the formation.
  • the surface shape of the base seed metal layer is changed, and a crack-like opening 59a can be formed in the insulating layer 59 provided thereon.
  • the seed metal layers 35a and 45a exposed under the openings 59a of the insulating layer 59 serve as starting points for plating, the plated metal layers 35b and 45b are selectively formed in the areas where the base seed metal layers 35a and 45a are printed.
  • Can be formed see, for example, WO2013 / 077038. Due to the unevenness of the seed metal layers 35a and 45a, an opening 59a can be formed in the insulating layer 59 formed thereon (see, for example, WO2011 / 045287).
  • the second main surface which is the light receiving surface, does not directly contribute to power generation and current extraction. Therefore, the configuration on the second main surface is not particularly limited as long as it does not hinder the reception of sunlight.
  • a light-receiving surface intrinsic semiconductor layer 2 a light-receiving surface conductive semiconductor layer 3 and a light-receiving surface protective layer 4 are provided in this order on the second main surface of the semiconductor substrate 1.
  • the light-receiving surface intrinsic semiconductor layer 2 is preferably a silicon-based thin film such as an intrinsic amorphous silicon thin film.
  • a silicon-based thin film such as an intrinsic amorphous silicon thin film.
  • passivation of the substrate surface can be performed effectively. Since the light-receiving surface intrinsic semiconductor layer 2 does not directly contribute to the generation and collection of optical carriers, it is preferable to set the film thickness so as to obtain a passivation effect without preventing light reception.
  • the film thickness of the light-receiving surface intrinsic semiconductor layer 2 is, for example, about 0.1 to 25 nm.
  • the light-receiving surface protective layer 4 is capable of protecting the layers (for example, the light-receiving surface intrinsic semiconductor layer 2 and the light-receiving surface conductive semiconductor layer 3) existing under the light-receiving surface protective layer 4 and has light transmittance.
  • the material is not particularly limited.
  • a material for the light-receiving surface protective layer 4 a material mainly composed of a silicon alloy such as silicon oxide, silicon nitride, or silicon oxynitride is preferable.
  • the film thickness of the light-receiving surface protective layer 4 is not particularly limited, but it is preferable to set the film thickness from the viewpoint of providing an antireflection function and increasing the amount of light taken into the semiconductor substrate 1, and is preferably about 80 nm to 1 ⁇ m.
  • a light-receiving surface conductive semiconductor layer 3 may be formed between the light-receiving surface intrinsic semiconductor layer 2 and the light-receiving surface protective layer 4.
  • the light-receiving surface conductive semiconductor layer 3 preferably has the same conductivity type as the semiconductor substrate 1.
  • an n-type semiconductor layer is preferably formed as the light-receiving surface conductive semiconductor layer 3.
  • the light-receiving surface conductive semiconductor layer 3 is preferably a silicon-based thin film, and more preferably amorphous silicon.
  • the film thickness of the light-receiving surface conductive semiconductor layer 3 is, for example, about 1 to 25 nm.
  • the method for forming the semiconductor layers 2 and 3 and the protective layer 4 on the second main surface of the semiconductor substrate 1 is not particularly limited. A membrane is preferred.
  • the timing at which the semiconductor layers 2 and 3 and the protective layer 4 are formed on the second main surface is not particularly limited. Which is the first of the deposition of each layer on the first major surface and the deposition of each layer on the second major surface? May be done. From the viewpoint of effectively performing passivation of the second main surface of the semiconductor substrate, the light-receiving surface intrinsic semiconductor layer on the second main surface is formed before the first conductive thin film 33 is formed on the first main surface (FIG. 3B). It is preferable to perform film formation of No.2.

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Abstract

A solar cell is provided with a first electrically conductive area (30) and a second electrically conductive area (40) on a first main surface of a semiconductor substrate (1), and is also provided with a boundary area (50) that is in contact with each of the first electrically conductive area and the second electrically conductive area and separates the same. A first electrically conductive thin film is provided straddling the entire surface of the first electrically conductive area and the boundary area. In a first boundary area (101) of the boundary area that contacts the first electrically conductive area, a first electrically conductive semiconductor layer (32), a first electrically conductive thin film (33), and an insulating layer (51) are provided in the stated order on the semiconductor substrate.

Description

太陽電池およびその製造方法Solar cell and method for manufacturing the same
　本発明は、太陽電池およびその製造方法に関する。 The present invention relates to a solar cell and a manufacturing method thereof.
　バックコンタクト型太陽電池は、半導体基板の裏面側にｐ型半導体層およびｎ型半導体層の両方を備え、これらの導電型半導体層上に電極を備えている。バックコンタクト型太陽電池は、半導体基板の裏面にのみ電極を有し受光面には電極を有していないため、電極に起因するシャドーイングロスがなく、高変換効率を実現可能である。バックコンタクト型太陽電池では、半導体基板の裏面側にｐ型半導体層およびｎ型半導体層の両方を有するため、有効領域が広く、かつｐｎ間のリークが生じないように半導体層のパターニングを行う必要がある。 The back contact type solar cell includes both a p-type semiconductor layer and an n-type semiconductor layer on the back side of the semiconductor substrate, and includes electrodes on these conductive semiconductor layers. Since the back contact solar cell has an electrode only on the back surface of the semiconductor substrate and no electrode on the light receiving surface, there is no shadowing loss due to the electrode, and high conversion efficiency can be realized. Since the back contact solar cell has both the p-type semiconductor layer and the n-type semiconductor layer on the back side of the semiconductor substrate, it is necessary to pattern the semiconductor layer so that the effective region is wide and no leakage between pn occurs. There is.
　図４Ａ～Ｊは、特許文献１に開示されているバックコンタクト型太陽電池の裏面側の製造工程の概念図である。まず、半導体基板１の裏面（図の上側）に真性半導体層４３１および第一導電型半導体層４３２が順に形成され（図４Ａ）、第一導電型半導体層４３２上に絶縁層４５１が形成される（図４Ｂ）。次に、絶縁層４５１の一部をエッチングにより除去してパターニングを行い（図４Ｃ）、パターニングされた絶縁層４５１をマスクとして、その下に露出した第一導電型半導体層４３２および真性半導体層４３１をエッチングして、パターニングを行う（図４Ｄ）。 4A to 4J are conceptual diagrams of the manufacturing process on the back side of the back contact solar cell disclosed in Patent Document 1. FIG. First, the intrinsic semiconductor layer 431 and the first conductive type semiconductor layer 432 are sequentially formed on the back surface (upper side of the drawing) of the semiconductor substrate 1 (FIG. 4A), and the insulating layer 451 is formed on the first conductive type semiconductor layer 432. (FIG. 4B). Next, a part of the insulating layer 451 is removed by etching and patterning is performed (FIG. 4C). Using the patterned insulating layer 451 as a mask, the first conductive type semiconductor layer 432 and the intrinsic semiconductor layer 431 exposed thereunder are formed. Is etched and patterned (FIG. 4D).
　その後、裏面の全面に真性半導体層４４１および第二導電型半導体層４４２を形成する（図４Ｅ）。パターニングされた第一導電型半導体層４３２上に設けられた第二導電型半導体層４４２、真性半導体層４４１および絶縁層４５１をエッチングして、パターニングを行い、第一導電型半導体層４３２を露出させる。この工程では、まず第二半導体層４４２上にパターンレジストを設け、絶縁層４５１上の第二導電型半導体層４４２および真性半導体層４４１をエッチングにより除去する（図４Ｆ）。その後、第二導電型半導体層４４２をマスクとして、フッ酸等の酸系エッチャントにより絶縁層４５１のエッチングが行われる（図４Ｇ）。 Thereafter, an intrinsic semiconductor layer 441 and a second conductivity type semiconductor layer 442 are formed on the entire back surface (FIG. 4E). The second conductive semiconductor layer 442, the intrinsic semiconductor layer 441, and the insulating layer 451 provided on the patterned first conductive semiconductor layer 432 are etched and patterned to expose the first conductive semiconductor layer 432. . In this step, first, a pattern resist is provided on the second semiconductor layer 442, and the second conductive semiconductor layer 442 and the intrinsic semiconductor layer 441 on the insulating layer 451 are removed by etching (FIG. 4F). Thereafter, the insulating layer 451 is etched with an acid-based etchant such as hydrofluoric acid using the second conductivity type semiconductor layer 442 as a mask (FIG. 4G).
　これらの工程により、第一導電型半導体層４３２の形成領域と第二導電型半導体層４４２の形成領域との境界部分には、半導体基板１上に、真性半導体層４３１、第一導電型半導体層４３２、絶縁層４５１、真性半導体層４４１および第二導電型半導体層４４２が順に設けられた境界領域４５０が形成される。 Through these steps, the intrinsic semiconductor layer 431 and the first conductivity type semiconductor layer are formed on the semiconductor substrate 1 at the boundary between the formation region of the first conductivity type semiconductor layer 432 and the formation region of the second conductivity type semiconductor layer 442. A boundary region 450 is formed in which 432, an insulating layer 451, an intrinsic semiconductor layer 441, and a second conductivity type semiconductor layer 442 are provided in this order.
　半導体層および絶縁層をパターニング後に、裏面の全面に導電性酸化物または金属等からなる導電性薄膜４４３を形成する（図４Ｈ）。エッチングまたはレーザ加工等により、境界領域上または境界領域近傍の導電性薄膜を除去して、第一導電型半導体層４３２上の導電性薄膜４４３ａと第二導電型半導体層４４２上の導電性薄膜４４３ｂとにパターニングする（図４Ｉ）。導電性薄膜４４３ａ，４４３ｂ上に、金属電極４３５，４４５を形成することにより、バックコンタクト型太陽電池が完成する（図４Ｊ）。 After patterning the semiconductor layer and the insulating layer, a conductive thin film 443 made of a conductive oxide or metal is formed on the entire back surface (FIG. 4H). The conductive thin film on or near the boundary region is removed by etching, laser processing, or the like, so that the conductive thin film 443a on the first conductive type semiconductor layer 432 and the conductive thin film 443b on the second conductive type semiconductor layer 442 are obtained. (FIG. 4I). By forming metal electrodes 435 and 445 on the conductive thin films 443a and 443b, a back contact solar cell is completed (FIG. 4J).
　このように、第一導電型半導体層形成領域と第二導電型半導体層形成領域との境界領域４５０において、第一導電型半導体層と第二導電型半導体層とが重なり合うことにより有効発電量領域を拡大でき、第一導電型半導体層と第二導電型半導体層との間に絶縁層が設けられることによりｐｎ間のリークを防止できる。 As described above, in the boundary region 450 between the first conductive type semiconductor layer forming region and the second conductive type semiconductor layer forming region, the first conductive type semiconductor layer and the second conductive type semiconductor layer overlap with each other, so that the effective power generation amount region. Since an insulating layer is provided between the first conductive semiconductor layer and the second conductive semiconductor layer, leakage between pn can be prevented.
ＷＯ２０１２／１３２７２９号パンフレットWO2012 / 132729 pamphlet
　図４Ａ～Ｊに示すバックコンタクト型太陽電池の製造工程では、第一導電型半導体層４３２上の第二導電型半導体層４４２をエッチングする際（図４Ｆ）に、第二導電型半導体層４４２上にレジストを設け、エッチング後にレジストを除去する。そのため、第二導電型半導体層４４２がレジスト液、剥離液等の薬液に触れる。その後、第二導電型半導体層４４２をマスクとしてフッ酸等のエッチャントを用いて絶縁層４５１をエッチングする際（図４Ｇ）に、第二導電型半導体層４４２にエッチャントが接触する。また、絶縁層４５１のエッチングにより露出した第一導電型半導体層４３２にもエッチャントが接触する。このように、半導体層および絶縁層のパターニングの際に、半導体層が薬液と接触すると、半導体層がダメージを受け、コンタクト抵抗の増加や開放電圧の低下等により太陽電池の発電特性が低下する場合がある。 In the manufacturing process of the back contact solar cell shown in FIGS. 4A to 4J, the second conductive semiconductor layer 442 is etched on the second conductive semiconductor layer 442 on the first conductive semiconductor layer 432 (FIG. 4F). A resist is provided on the substrate, and the resist is removed after etching. Therefore, the second conductivity type semiconductor layer 442 comes into contact with a chemical solution such as a resist solution or a stripping solution. Thereafter, when the insulating layer 451 is etched using an etchant such as hydrofluoric acid with the second conductivity type semiconductor layer 442 as a mask (FIG. 4G), the etchant contacts the second conductivity type semiconductor layer 442. The etchant also contacts the first conductive semiconductor layer 432 exposed by etching the insulating layer 451. As described above, when the semiconductor layer and the insulating layer are patterned, if the semiconductor layer comes into contact with the chemical solution, the semiconductor layer is damaged, and the power generation characteristics of the solar cell deteriorate due to an increase in contact resistance or a decrease in open-circuit voltage. There is.
　また、図４Ｊに示すバックコンタクト型太陽電池では、境界領域４５０の第一導電型半導体層４３２上に導電層が設けられていないため、この領域に到達した光キャリアは、導電性薄膜４４３ａに到達するまでに、第一導電型半導体層４３２の面内を移動する距離が長い。そのため、キャリア再結合に起因する発電ロスが生じやすく、太陽電池の発電特性を低下させる原因となる。 In the back contact solar cell shown in FIG. 4J, since no conductive layer is provided on the first conductive semiconductor layer 432 in the boundary region 450, the photocarriers that reach this region reach the conductive thin film 443a. By the time, the distance which moves in the surface of the 1st conductivity type semiconductor layer 432 is long. For this reason, power generation loss due to carrier recombination is likely to occur, which causes a decrease in power generation characteristics of the solar cell.
　上記に鑑み、本発明は、キャリア回収効率に優れ、パターニング等に起因する特性低下が抑制されたバックコンタクト型太陽電池の提供を目的とする。 In view of the above, an object of the present invention is to provide a back-contact solar cell that is excellent in carrier recovery efficiency and in which deterioration of characteristics due to patterning or the like is suppressed.
　本発明は、半導体基板の第一主面上に、第一方向に沿って第一導電型領域と第二導電型領域とが交互に配置されたバックコンタクト型太陽電池およびその製造方法に関する。半導体基板の第一主面上には、第一導電型領域と第二導電型領域のそれぞれに接して両者を離間する境界領域が設けられている。 The present invention relates to a back contact solar cell in which a first conductivity type region and a second conductivity type region are alternately arranged along a first direction on a first main surface of a semiconductor substrate, and a manufacturing method thereof. On the first main surface of the semiconductor substrate, a boundary region that is in contact with and separates the first conductivity type region and the second conductivity type region is provided.
　半導体基板の第一主面上には、第一導電型半導体層、第二導電型半導体層、第一導電性薄膜、第二導電性薄膜、および絶縁層が設けられている。第一導電型半導体層と第二導電型半導体層とは異なる導電型を有し、一方がｐ型、他方がｎ型である。半導体基板の第一主面上の各層はパターニングされている。 A first conductive type semiconductor layer, a second conductive type semiconductor layer, a first conductive thin film, a second conductive thin film, and an insulating layer are provided on the first main surface of the semiconductor substrate. The first conductivity type semiconductor layer and the second conductivity type semiconductor layer have different conductivity types, one is p-type and the other is n-type. Each layer on the first main surface of the semiconductor substrate is patterned.
　第一導電型半導体層および第一導電性薄膜は、第一導電型領域の全面および境界領域に跨って設けられている。第二導電型半導体層および第二導電性薄膜は、第二導電型領域の全面および境界領域に跨って設けられている。絶縁層は境界領域の全面に設けられている。 The first conductive type semiconductor layer and the first conductive thin film are provided across the entire surface of the first conductive type region and the boundary region. The second conductive type semiconductor layer and the second conductive thin film are provided across the entire surface of the second conductive type region and the boundary region. The insulating layer is provided on the entire boundary region.
　第一導電型領域では、半導体基板上に、第一導電型半導体層および第一導電性薄膜がこの順に設けられている。第二導電型領域では、半導体基板上に、第二導電型半導体層および第二導電性薄膜がこの順に設けられている。 In the first conductivity type region, a first conductivity type semiconductor layer and a first conductive thin film are provided in this order on a semiconductor substrate. In the second conductivity type region, the second conductivity type semiconductor layer and the second conductive thin film are provided in this order on the semiconductor substrate.
　第一導電性薄膜は、境界領域のうち、第一導電型領域に接する第一境界領域に設けられ、第二導電型領域に接する第二境界領域には設けられていないことが好ましい。この形態では、第一境界領域と第二境界領域との境界部分において、第一導電性薄膜の側面が絶縁層により覆われている。 The first conductive thin film is preferably provided in the first boundary region in contact with the first conductivity type region and not in the second boundary region in contact with the second conductivity type region. In this embodiment, the side surface of the first conductive thin film is covered with the insulating layer at the boundary portion between the first boundary region and the second boundary region.
　第一境界領域では、半導体基板上に、第一導電型半導体層、第一導電性薄膜、および絶縁層がこの順に設けられている。第一境界領域において、絶縁層上には第二導電型半導体層および第二導電性薄膜がこの順に設けられていてもよい。 In the first boundary region, a first conductive type semiconductor layer, a first conductive thin film, and an insulating layer are provided in this order on the semiconductor substrate. In the first boundary region, a second conductive semiconductor layer and a second conductive thin film may be provided in this order on the insulating layer.
　第二境界領域では、絶縁層上に第二導電型半導体層および第二導電性薄膜がこの順に設けられている。第二境界領域では、半導体基板と絶縁層との間には、第一導電性薄膜が設けられていない。第二境界領域では、半導体基板と絶縁層との間に第一導電型半導体層が設けられていてもよく、設けられていなくてもよい。第二境界領域に第一導電型半導体層が設けられていない場合は、第一境界領域と第二境界領域との境界部分において、第一導電型半導体層の側面が絶縁層により覆われている。 In the second boundary region, the second conductive type semiconductor layer and the second conductive thin film are provided in this order on the insulating layer. In the second boundary region, the first conductive thin film is not provided between the semiconductor substrate and the insulating layer. In the second boundary region, the first conductivity type semiconductor layer may or may not be provided between the semiconductor substrate and the insulating layer. When the first conductivity type semiconductor layer is not provided in the second boundary region, the side surface of the first conductivity type semiconductor layer is covered with the insulating layer at the boundary portion between the first boundary region and the second boundary region. .
　半導体基板と第一導電型半導体層との間には第一真性半導体層が設けられていることが好ましい。半導体基板と第二導電型半導体層との間には第二真性半導体層が設けられていることが好ましい。 It is preferable that a first intrinsic semiconductor layer is provided between the semiconductor substrate and the first conductivity type semiconductor layer. A second intrinsic semiconductor layer is preferably provided between the semiconductor substrate and the second conductivity type semiconductor layer.
　上記の太陽電池は、第一導電型領域および境界領域に、第一導電型半導体層、第一導電性薄膜および絶縁層がこの順に積層されたパターン層を形成し；第二導電型領域および境界領域上に、第二導電型半導体層および第二導電性薄膜を順に形成し；第一導電型領域に設けられた絶縁層をエッチング除去することにより作製できる。 In the above solar cell, a pattern layer in which a first conductive type semiconductor layer, a first conductive thin film, and an insulating layer are laminated in this order is formed in the first conductive type region and the boundary region; A second conductive type semiconductor layer and a second conductive thin film are sequentially formed on the region; the insulating layer provided in the first conductive type region can be removed by etching.
　第二導電型半導体層、および第二導電性薄膜は、第一導電型領域に開口を有するようにパターニングされており、第二導電型半導体層の開口下に絶縁層が露出している。そのため、第一導電型領域に設けられた絶縁層を選択的にエッチング除去できる。例えば、基板上の全面に第二導電型半導体層および第二導電性薄膜を順に形成し、第一導電型領域に設けられた第二導電型半導体層および第二導電性薄膜をエッチング除去することにより、第二導電型半導体層および第二導電性薄膜に開口が形成される。 The second conductive type semiconductor layer and the second conductive thin film are patterned so as to have an opening in the first conductive type region, and the insulating layer is exposed under the opening of the second conductive type semiconductor layer. Therefore, the insulating layer provided in the first conductivity type region can be selectively removed by etching. For example, a second conductive type semiconductor layer and a second conductive thin film are sequentially formed on the entire surface of the substrate, and the second conductive type semiconductor layer and the second conductive thin film provided in the first conductive type region are removed by etching. Thus, an opening is formed in the second conductive type semiconductor layer and the second conductive thin film.
　パターン層の両端部には第一導電性薄膜が設けられておらず、第一導電性薄膜の側面が絶縁層により覆われていることが好ましい。このパターン層を形成後に、第二導電型半導体層および第二導電性薄膜を製膜し、第二導電型半導体層の開口下に露出した絶縁層をエッチングすることにより、第一境界領域と第二境界領域との境界部分において第一導電性薄膜の側面が絶縁層により覆われた太陽電池が得られる。例えば、第一導電型半導体層上に、パターン層形成領域の両端部に開口を有する第一導電性薄膜を形成し、基板上の全面に絶縁層を形成した後、第二導電型領域に設けられた層をエッチング除去することにより、両端部に第一導電性薄膜が設けられていないパターン層を形成できる。 It is preferable that the first conductive thin film is not provided at both ends of the pattern layer, and the side surfaces of the first conductive thin film are covered with an insulating layer. After forming this pattern layer, the second conductive type semiconductor layer and the second conductive thin film are formed, and the insulating layer exposed under the opening of the second conductive type semiconductor layer is etched to thereby form the first boundary region and the first conductive layer. A solar cell in which the side surface of the first conductive thin film is covered with the insulating layer at the boundary portion between the two boundary regions is obtained. For example, a first conductive thin film having openings at both ends of the pattern layer forming region is formed on the first conductive type semiconductor layer, an insulating layer is formed on the entire surface of the substrate, and then provided in the second conductive type region. By etching away the formed layer, a pattern layer in which the first conductive thin film is not provided at both ends can be formed.
　本発明の太陽電池は、境界領域の第一導電型半導体層上に導電性薄膜が設けられているため、境界領域に到達したキャリアを有効に回収できる。また、境界領域において第一導電型半導体層上に設けられた導電性薄膜が絶縁層により覆われているため、ｐｎ間のリークを防止でき、高い変換特性を実現できる。さらには、第一導電型半導体層上および第二導電型半導体層上のそれぞれに導電性薄膜が設けられているため、太陽電池の製造工程における半導体層とエッチャント等の薬液との接触を防止し、半導体層へのダメージを低減して、太陽電池の特性を向上できる。 In the solar cell of the present invention, since the conductive thin film is provided on the first conductivity type semiconductor layer in the boundary region, the carriers that have reached the boundary region can be effectively collected. Further, since the conductive thin film provided on the first conductivity type semiconductor layer in the boundary region is covered with the insulating layer, leakage between pn can be prevented and high conversion characteristics can be realized. Furthermore, since the conductive thin film is provided on each of the first conductive type semiconductor layer and the second conductive type semiconductor layer, contact between the semiconductor layer and a chemical solution such as an etchant in the manufacturing process of the solar cell is prevented. The damage to the semiconductor layer can be reduced and the characteristics of the solar cell can be improved.
本発明の一実施形態の太陽電池の構成断面図である。It is a structure sectional view of the solar cell of one embodiment of the present invention. バックコンタクト型太陽電池における半導体層形成領域の形状の一例を示す平面図である。It is a top view which shows an example of the shape of the semiconductor layer formation area | region in a back contact type solar cell. 太陽電池の製造工程を説明するための模式断面図である。It is a schematic cross section for demonstrating the manufacturing process of a solar cell. 太陽電池の製造工程を説明するための模式断面図である。It is a schematic cross section for demonstrating the manufacturing process of a solar cell. 太陽電池の製造工程を説明するための模式断面図である。It is a schematic cross section for demonstrating the manufacturing process of a solar cell. 太陽電池の製造工程を説明するための模式断面図である。It is a schematic cross section for demonstrating the manufacturing process of a solar cell. 太陽電池の製造工程を説明するための模式断面図である。It is a schematic cross section for demonstrating the manufacturing process of a solar cell. 太陽電池の製造工程を説明するための模式断面図である。It is a schematic cross section for demonstrating the manufacturing process of a solar cell. 太陽電池の製造工程を説明するための模式断面図である。It is a schematic cross section for demonstrating the manufacturing process of a solar cell. 太陽電池の製造工程を説明するための模式断面図である。It is a schematic cross section for demonstrating the manufacturing process of a solar cell. 太陽電池の製造工程を説明するための模式断面図である。It is a schematic cross section for demonstrating the manufacturing process of a solar cell. 太陽電池の製造工程を説明するための模式断面図である。It is a schematic cross section for demonstrating the manufacturing process of a solar cell. 従来技術の太陽電池の製造工程を説明するための模式断面図である。It is a schematic cross section for demonstrating the manufacturing process of the solar cell of a prior art. 従来技術の太陽電池の製造工程を説明するための模式断面図である。It is a schematic cross section for demonstrating the manufacturing process of the solar cell of a prior art. 従来技術の太陽電池の製造工程を説明するための模式断面図である。It is a schematic cross section for demonstrating the manufacturing process of the solar cell of a prior art. 従来技術の太陽電池の製造工程を説明するための模式断面図である。It is a schematic cross section for demonstrating the manufacturing process of the solar cell of a prior art. 従来技術の太陽電池の製造工程を説明するための模式断面図である。It is a schematic cross section for demonstrating the manufacturing process of the solar cell of a prior art. 従来技術の太陽電池の製造工程を説明するための模式断面図である。It is a schematic cross section for demonstrating the manufacturing process of the solar cell of a prior art. 従来技術の太陽電池の製造工程を説明するための模式断面図である。It is a schematic cross section for demonstrating the manufacturing process of the solar cell of a prior art. 従来技術の太陽電池の製造工程を説明するための模式断面図である。It is a schematic cross section for demonstrating the manufacturing process of the solar cell of a prior art. 従来技術の太陽電池の製造工程を説明するための模式断面図である。It is a schematic cross section for demonstrating the manufacturing process of the solar cell of a prior art. 従来技術の太陽電池の製造工程を説明するための模式断面図である。It is a schematic cross section for demonstrating the manufacturing process of the solar cell of a prior art. 太陽電池の製造工程の途中における導電性薄膜のパターニング形状の一例を示す模式断面図である。It is a schematic cross section which shows an example of the patterning shape of the electroconductive thin film in the middle of the manufacturing process of a solar cell. 太陽電池の製造工程の途中に形成されるパターン層の形状の一例を示す模式断面図である。It is a schematic cross section which shows an example of the shape of the pattern layer formed in the middle of the manufacturing process of a solar cell. 太陽電池の絶縁領域の積層構成の一例を示す模式断面図である。It is a schematic cross section which shows an example of the laminated structure of the insulation area | region of a solar cell. 太陽電池の絶縁領域の積層構成の一例を示す模式断面図である。It is a schematic cross section which shows an example of the laminated structure of the insulation area | region of a solar cell. 金属電極の形成方法の一例について説明するための模式断面図である。It is a schematic cross section for demonstrating an example of the formation method of a metal electrode. 金属電極の形成方法の一例について説明するための模式断面図である。It is a schematic cross section for demonstrating an example of the formation method of a metal electrode.
［太陽電池の構成］
　図２は、バックコンタクト型太陽電池における第一導電型領域および第二導電型領域の形状を説明するための模式的平面図である。図１は本発明の一実施形態にかかるバックコンタクト型太陽電池の模式的断面図であり、図２の左右方向（ｘ方向）の断面に相当する。図１の下側（第二主面）が太陽電池の受光面であり、上側（第一主面）が太陽電池の裏面である。 [Configuration of solar cell]
FIG. 2 is a schematic plan view for explaining the shapes of the first conductivity type region and the second conductivity type region in the back contact solar cell. FIG. 1 is a schematic cross-sectional view of a back contact solar cell according to an embodiment of the present invention, and corresponds to a cross section in the left-right direction (x direction) of FIG. The lower side (second main surface) in FIG. 1 is the light receiving surface of the solar cell, and the upper side (first main surface) is the back surface of the solar cell.
　第一導電型領域３０および第二導電型領域４０は、第一方向（ｘ方向）に沿って交互に配置されている。第一導電型領域３０および第二導電型領域４０は、それぞれ第一方向に直交する第二方向（ｙ方向）に沿って延在している。図２において、第一導電型領域３０と第二導電型領域４０とは、互いに噛み合う櫛型に設けられている。第一導電型領域３０および第二導電型領域４０の形状は櫛型である必要はなく、例えば、ｘ方向に延在して櫛歯を繋ぐ部分（いわゆるバスバー部分）が設けられていない形状でもよい。 The first conductivity type regions 30 and the second conductivity type regions 40 are alternately arranged along the first direction (x direction). The first conductivity type region 30 and the second conductivity type region 40 each extend along a second direction (y direction) orthogonal to the first direction. In FIG. 2, the first conductivity type region 30 and the second conductivity type region 40 are provided in a comb shape that meshes with each other. The shape of the first conductivity type region 30 and the second conductivity type region 40 does not have to be a comb shape. For example, the first conductivity type region 30 and the second conductivity type region 40 may have a shape that extends in the x direction and connects the comb teeth (so-called bus bar portion). Good.
　第一導電型領域３０には第一導電型半導体層３２が設けられており、第二導電型領域４０には、第二導電型半導体層４２が設けられている。第一導電型半導体層３２と第二導電型半導体層４２とは異なる導電型を有し、一方がｐ型、他方がｎ型である。第一導電型領域３０と第二導電型領域４０との間には、両者に接する境界領域５０が設けられており、第一導電型領域３０と第二導電型領域４０とを離間している。 The first conductivity type region 30 is provided with a first conductivity type semiconductor layer 32, and the second conductivity type region 40 is provided with a second conductivity type semiconductor layer 42. The first conductivity type semiconductor layer 32 and the second conductivity type semiconductor layer 42 have different conductivity types, one is p-type and the other is n-type. Between the first conductivity type region 30 and the second conductivity type region 40, a boundary region 50 in contact with both is provided, and the first conductivity type region 30 and the second conductivity type region 40 are separated from each other. .
　第一導電型領域３０の幅、および第二導電型領域４０の幅は、いずれも特に限定されず、互いに等しくても異なっていてもよい。第一導電型領域３０の幅および第二導電型領域４０の幅は、例えば１００～１５００μｍ程度である。境界領域５０の幅も特に限定されない。境界領域の幅は、例えば１０～５００μｍ程度である。ｐｎ間のリークおよび第一導電性薄膜３３と第二導電型半導体層４２とのリークを防止可能な範囲で、境界領域５０の幅はできる限り小さいことが好ましい。 The width of the first conductivity type region 30 and the width of the second conductivity type region 40 are not particularly limited, and may be equal to or different from each other. The width of the first conductivity type region 30 and the width of the second conductivity type region 40 are, for example, about 100 to 1500 μm. The width of the boundary region 50 is not particularly limited. The width of the boundary region is, for example, about 10 to 500 μm. The width of the boundary region 50 is preferably as small as possible within a range in which leakage between pn and leakage between the first conductive thin film 33 and the second conductivity type semiconductor layer 42 can be prevented.
　図１に示すバックコンタクト型太陽電池では、半導体基板１の第一主面上に、第一真性半導体層３１、第一導電型半導体層３２、第一導電性薄膜３３、絶縁層５１、第二真性半導体層４１、第二導電型半導体層４２、および第二導電性薄膜４３が設けられている。第一主面上において、これらの各層はパターニングされている。以下では第一導電型をｐ型、第二導電型をｎ型として説明するが、本発明の太陽電池は、第一導電型がｎ型、第二導電型がｐ型でもよい。 In the back contact solar cell shown in FIG. 1, on the first main surface of the semiconductor substrate 1, a first intrinsic semiconductor layer 31, a first conductive semiconductor layer 32, a first conductive thin film 33, an insulating layer 51, a second An intrinsic semiconductor layer 41, a second conductive type semiconductor layer 42, and a second conductive thin film 43 are provided. Each of these layers is patterned on the first major surface. In the following description, the first conductivity type is p-type and the second conductivity type is n-type. However, the solar cell of the present invention may be n-type for the first conductivity type and p-type for the second conductivity type.
　ｐ型半導体層３２は、ｐ型領域３０と境界領域５０とに跨って設けられている。ｎ型半導体層４２は、ｎ型領域４０と境界領域５０とに跨って設けられている。境界領域５０では、ｐ型半導体層３２とｎ型半導体層４２との間に絶縁層５１が設けられている。 The p-type semiconductor layer 32 is provided across the p-type region 30 and the boundary region 50. The n-type semiconductor layer 42 is provided across the n-type region 40 and the boundary region 50. In the boundary region 50, an insulating layer 51 is provided between the p-type semiconductor layer 32 and the n-type semiconductor layer 42.
　絶縁層５１は境界領域５０の全面に設けられている。換言すると、絶縁層５１が設けられている領域が境界領域５０である。境界領域５０では、絶縁層５１により、ｐ型半導体層３２とｎ型半導体層４２との間のリークを防止している。 The insulating layer 51 is provided on the entire boundary region 50. In other words, the region where the insulating layer 51 is provided is the boundary region 50. In the boundary region 50, the insulating layer 51 prevents leakage between the p-type semiconductor layer 32 and the n-type semiconductor layer 42.
　第一導電性薄膜３３は、ｐ型領域３０と境界領域５０とに跨って設けられている。ｐ型領域３０では、ｐ型半導体層３２上に第一導電性薄膜３３が設けられ、その上に第一金属電極３５が設けられている。 The first conductive thin film 33 is provided across the p-type region 30 and the boundary region 50. In the p-type region 30, the first conductive thin film 33 is provided on the p-type semiconductor layer 32, and the first metal electrode 35 is provided thereon.
　境界領域５０において、ｐ型領域３０側の第一境界領域１０１では、ｐ型半導体層３２上に第一導電性薄膜３３が設けられ、その上に絶縁層５１が設けられている。図４Ｊに示すバックコンタクト型太陽電池では、境界領域４５０の第一導電型半導体層４３２上に導電層が設けられていないため、この領域に到達したキャリアの回収ロスが生じやすい。これに対して、図１に示す太陽電池は、境界領域においてｐ型半導体層３２上に第一導電性薄膜３３が設けられているため、境界領域５０に到達したキャリアの回収効率を向上できる。 In the boundary region 50, in the first boundary region 101 on the p-type region 30 side, the first conductive thin film 33 is provided on the p-type semiconductor layer 32, and the insulating layer 51 is provided thereon. In the back contact solar cell shown in FIG. 4J, since no conductive layer is provided on the first conductive type semiconductor layer 432 in the boundary region 450, a recovery loss of carriers reaching this region is likely to occur. On the other hand, since the first conductive thin film 33 is provided on the p-type semiconductor layer 32 in the boundary region, the solar cell shown in FIG. 1 can improve the recovery efficiency of the carriers that have reached the boundary region 50.
　境界領域５０のｎ型領域４０側の第二境界領域１０２では、ｐ型半導体層３２上に第一導電性薄膜３３が設けられておらず、ｐ型半導体層３２と絶縁層５１とが接していることが好ましい。第二境界領域１０２に第一導電性薄膜３３が設けられていない場合、第一境界領域１０１と第二境界領域１０２との境界部分では、第一導電性薄膜３３の側面が絶縁層５１により覆われている。境界領域５０において、第一導電性薄膜３３の側面を絶縁層５１で覆うことにより、第一導電性薄膜３３とｎ型半導体層４２との間のリークを防止できる。 In the second boundary region 102 on the n-type region 40 side of the boundary region 50, the first conductive thin film 33 is not provided on the p-type semiconductor layer 32, and the p-type semiconductor layer 32 and the insulating layer 51 are in contact with each other. Preferably it is. When the first conductive thin film 33 is not provided in the second boundary region 102, the side surface of the first conductive thin film 33 is covered with the insulating layer 51 at the boundary portion between the first boundary region 101 and the second boundary region 102. It has been broken. By covering the side surface of the first conductive thin film 33 with the insulating layer 51 in the boundary region 50, leakage between the first conductive thin film 33 and the n-type semiconductor layer 42 can be prevented.
　ｎ型半導体層４２上には、第二導電性薄膜４３が設けられている。ｎ型領域４０では、ｎ型半導体層４２上に第二導電性薄膜４３が設けられ、その上に第二金属電極４５が設けられている。ｎ型半導体層４２と同様、第二導電性薄膜４３も、ｎ型領域４０と境界領域５０とに跨って設けられていてもよい。第二導電性薄膜４３は、ｎ型半導体層４２上の全面に設けられていることが好ましい。第二導電性薄膜４３上の第二金属電極４５は、境界領域５０にはみ出して設けられていてもよい。 A second conductive thin film 43 is provided on the n-type semiconductor layer 42. In the n-type region 40, the second conductive thin film 43 is provided on the n-type semiconductor layer 42, and the second metal electrode 45 is provided thereon. Similar to the n-type semiconductor layer 42, the second conductive thin film 43 may be provided across the n-type region 40 and the boundary region 50. The second conductive thin film 43 is preferably provided on the entire surface of the n-type semiconductor layer 42. The second metal electrode 45 on the second conductive thin film 43 may protrude from the boundary region 50.
　境界領域５０の全面にｎ型半導体層４２および第二導電性薄膜４３が設けられている場合、第一境界領域１０１では、半導体基板１上に、ｐ型半導体層３２、第一導電性薄膜３３、絶縁層５１、ｎ型半導体層４２および第二導電性薄膜４３が順に設けられており；第二境界領域１０２では、半導体基板１上に、ｐ型半導体層３２、絶縁層５１、ｎ型半導体層４２および第二導電性薄膜４３が順に設けられている。 When the n-type semiconductor layer 42 and the second conductive thin film 43 are provided over the entire boundary region 50, the p-type semiconductor layer 32 and the first conductive thin film 33 are formed on the semiconductor substrate 1 in the first boundary region 101. , An insulating layer 51, an n-type semiconductor layer 42, and a second conductive thin film 43 are provided in this order; in the second boundary region 102, a p-type semiconductor layer 32, an insulating layer 51, and an n-type semiconductor are formed on the semiconductor substrate 1. A layer 42 and a second conductive thin film 43 are provided in this order.
　ｐ型領域３０および境界領域５０では、半導体基板１とｐ型半導体層３２との間に、第一真性半導体層３１が設けられていることが好ましい。すなわち、第一真性半導体層３１は、ｐ型領域３０と境界領域５０とに跨って設けられていることが好ましい。 In the p-type region 30 and the boundary region 50, the first intrinsic semiconductor layer 31 is preferably provided between the semiconductor substrate 1 and the p-type semiconductor layer 32. That is, the first intrinsic semiconductor layer 31 is preferably provided across the p-type region 30 and the boundary region 50.
　第二境界領域１０２にはｐ型半導体層３２が設けられていなくてもよい。この場合、第二境界領域１０２では、半導体基板１上または第一真性半導体層３１に接して絶縁層５１が設けられる（図７および図８参照）。 The p-type semiconductor layer 32 may not be provided in the second boundary region 102. In this case, in the second boundary region 102, the insulating layer 51 is provided on the semiconductor substrate 1 or in contact with the first intrinsic semiconductor layer 31 (see FIGS. 7 and 8).
　ｎ型領域４０では、半導体基板１とｎ型半導体層４２との間に、第二真性半導体層４１が設けられていることが好ましい。境界領域５０において、絶縁層５１とｎ型半導体層４２との間に第二真性半導体層４１が設けられていてもよい。第二真性半導体層４１は、ｎ型領域４０と境界領域５０とに跨って設けられていてもよい。 In the n-type region 40, the second intrinsic semiconductor layer 41 is preferably provided between the semiconductor substrate 1 and the n-type semiconductor layer 42. In the boundary region 50, the second intrinsic semiconductor layer 41 may be provided between the insulating layer 51 and the n-type semiconductor layer 42. The second intrinsic semiconductor layer 41 may be provided across the n-type region 40 and the boundary region 50.
［太陽電池の製造工程］
　図３Ａ～Ｉは、図１に示すバックコンタクト型太陽電池の製造工程の一例を示す工程概念図である。以下では、これらの図を参照して、太陽電池の第一主面上への各層の製膜およびパターニングの工程を説明する。 [Solar cell manufacturing process]
3A to 3I are process conceptual diagrams showing an example of the manufacturing process of the back contact solar cell shown in FIG. Below, with reference to these figures, the process of film-forming and patterning of each layer on the 1st main surface of a solar cell is demonstrated.
＜半導体基板＞
　まず、半導体基板１を準備する。半導体基板１は、好ましくは結晶シリコン基板である。結晶シリコン基板は、単結晶シリコンおよび多結晶シリコンのいずれでもよい。結晶シリコン基板の導電型は、ｎ型、ｐ型のいずれでもよい。半導体基板の厚みは、例えば、１００～３００μｍ程度である。半導体基板１の第二主面（受光面）には、表面にテクスチャ構造が形成されることが好ましい。半導体基板の第一主面にもテクスチャ構造が形成されていてもよい。半導体基板の表面にテクスチャ構造が設けられることにより、表面反射が低減し、半導体基板に入射する光量を増大できる。半導体基板が単結晶シリコン基板である場合には、異方性エッチングによりピラミッド形状のテクスチャを形成できる。 <Semiconductor substrate>
First, the semiconductor substrate 1 is prepared. The semiconductor substrate 1 is preferably a crystalline silicon substrate. The crystalline silicon substrate may be either single crystal silicon or polycrystalline silicon. The conductivity type of the crystalline silicon substrate may be either n-type or p-type. The thickness of the semiconductor substrate is, for example, about 100 to 300 μm. A texture structure is preferably formed on the surface of the second main surface (light receiving surface) of the semiconductor substrate 1. A texture structure may also be formed on the first main surface of the semiconductor substrate. By providing a texture structure on the surface of the semiconductor substrate, surface reflection is reduced, and the amount of light incident on the semiconductor substrate can be increased. When the semiconductor substrate is a single crystal silicon substrate, a pyramidal texture can be formed by anisotropic etching.
＜パターン層形成＞
　図３Ｅに示すように、半導体基板１の第一主面上に、パターン層１３が設けられたパターン層形成領域１００と、半導体基板の第一主面が露出した露出領域２００とが形成される。露出領域２００は、完成後の太陽電池のｎ型領域（第二導電型領域）４０に相当する。 <Pattern layer formation>
As shown in FIG. 3E, a pattern layer forming region 100 provided with a pattern layer 13 and an exposed region 200 where the first main surface of the semiconductor substrate is exposed are formed on the first main surface of the semiconductor substrate 1. . The exposed region 200 corresponds to the n-type region (second conductivity type region) 40 of the completed solar cell.
　パターン層１３は、ｐ型半導体層３２、第一導電性薄膜３３および絶縁層５１が順に積層された構成を有する。図３Ｅにおいては、パターン層形成領域１００の全面にｐ型半導体層３２および絶縁層５１が設けられている。半導体基板１とｐ型半導体層３２との間には、真性半導体層３１が設けられることが好ましい。 The pattern layer 13 has a configuration in which a p-type semiconductor layer 32, a first conductive thin film 33, and an insulating layer 51 are sequentially stacked. In FIG. 3E, a p-type semiconductor layer 32 and an insulating layer 51 are provided on the entire surface of the pattern layer forming region 100. An intrinsic semiconductor layer 31 is preferably provided between the semiconductor substrate 1 and the p-type semiconductor layer 32.
　パターン層形成領域１００の両端部の露出領域２００に隣接する端部領域１０２では、第一導電性薄膜３３が設けられておらず、ｐ型半導体層３２と絶縁層５１とが接していることが好ましい。換言すると、パターン層形成領域１００は、第一導電性薄膜３３が設けられている中央領域１０３と、第一導電性薄膜３３が設けられていない端部領域１０２とを有することが好ましい。完成後の太陽電池においては、この端部領域１０２が、境界領域５０の第二境界領域１０２に相当する。 In the end region 102 adjacent to the exposed region 200 at both ends of the pattern layer forming region 100, the first conductive thin film 33 is not provided, and the p-type semiconductor layer 32 and the insulating layer 51 are in contact with each other. preferable. In other words, the pattern layer forming region 100 preferably has a central region 103 where the first conductive thin film 33 is provided and an end region 102 where the first conductive thin film 33 is not provided. In the completed solar cell, this end region 102 corresponds to the second boundary region 102 of the boundary region 50.
　絶縁層５１はパターン層形成領域１００の全体に設けられており、中央領域１０３と端部領域１０２との境界部分では、第一導電性薄膜３３の側面が絶縁層５１により覆われている。換言すると、中央領域１０３では、ｐ型半導体層３２上に第一導電性薄膜３３および絶縁層５１が設けられており、第一導電性薄膜３３が設けられていない端部領域１０２では、半導体層に接して絶縁層５１が設けられている。 The insulating layer 51 is provided over the entire pattern layer forming region 100, and the side surface of the first conductive thin film 33 is covered with the insulating layer 51 at the boundary between the central region 103 and the end region 102. In other words, in the central region 103, the first conductive thin film 33 and the insulating layer 51 are provided on the p-type semiconductor layer 32, and in the end region 102 where the first conductive thin film 33 is not provided, the semiconductor layer An insulating layer 51 is provided in contact with the substrate.
　真性半導体層３１、ｐ型半導体層３２、第一導電性薄膜３３および絶縁層５１が順に積層されたパターン層１３を形成する方法としては、露出領域２００をマスクにより遮蔽した状態で各層の製膜を行う方法；および半導体基板１上の全面に各層を形成してエッチング等により順次パターニングする方法等が挙げられる。マスク製膜によるパターニングとエッチングによるパターニングとを併用してもよい。マスクにより遮蔽して各層の製膜を行う場合、露出領域２００に加えてパターン層形成領域１００の両端の端部領域１０２をマスクにより遮蔽した状態で第一導電性薄膜３３の製膜を行えば、図３Ｅに示すように、絶縁層５１が第一導電性薄膜３３の側面を覆うパターン層を形成できる。 As a method of forming the patterned layer 13 in which the intrinsic semiconductor layer 31, the p-type semiconductor layer 32, the first conductive thin film 33, and the insulating layer 51 are sequentially laminated, the respective layers are formed in a state where the exposed region 200 is shielded by a mask. And a method in which each layer is formed on the entire surface of the semiconductor substrate 1 and sequentially patterned by etching or the like. Patterning by mask film formation and patterning by etching may be used in combination. When each layer is formed by shielding with a mask, the first conductive thin film 33 is formed with the end regions 102 at both ends of the pattern layer forming region 100 in addition to the exposed region 200 being shielded by the mask. As shown in FIG. 3E, a pattern layer in which the insulating layer 51 covers the side surface of the first conductive thin film 33 can be formed.
　以下では、図３Ａ～Ｅを参照して、基板上の全面への製膜とエッチングとを繰り返し実施してパターン層１３を形成する形態について説明する。なお、半導体層、導電性薄膜、絶縁層等を基板上の全面に製膜する際に、基板の端部等の非発電領域には製膜が行われない場合があってもよい。 Hereinafter, with reference to FIGS. 3A to 3E, a mode in which the pattern layer 13 is formed by repeatedly performing film formation and etching on the entire surface of the substrate will be described. Note that when a semiconductor layer, a conductive thin film, an insulating layer, or the like is formed over the entire surface of the substrate, the film may not be formed in a non-power generation region such as an end portion of the substrate.
（ｐ型半導体層形成）
　図３Ａに示すように、半導体基板１の第一主面の全面にｐ型半導体層３２が形成される。ｐ型半導体層３２はｐ型のドーパントが添加された半導体薄膜であり、ボロンが添加されたｐ型シリコン系層であることが好ましい。不純物拡散の抑制や直列抵抗低減の観点から、ｐ型半導体層３２としては、ｐ型非晶質シリコン系層が好ましく、ｐ型非晶質シリコン層が特に好ましい。ｐ型半導体層３２の膜厚は、例えば２～５０ｎｍ程度である。 (P-type semiconductor layer formation)
As shown in FIG. 3A, a p-type semiconductor layer 32 is formed on the entire first main surface of the semiconductor substrate 1. The p-type semiconductor layer 32 is a semiconductor thin film to which a p-type dopant is added, and is preferably a p-type silicon-based layer to which boron is added. From the viewpoint of suppressing impurity diffusion and reducing series resistance, the p-type semiconductor layer 32 is preferably a p-type amorphous silicon-based layer, and a p-type amorphous silicon layer is particularly preferable. The thickness of the p-type semiconductor layer 32 is, for example, about 2 to 50 nm.
　前述のように、半導体基板１とｐ型半導体層３２との間、および半導体基板１とｎ型半導体層４２との間には、真性半導体層３１，４１が設けられることが好ましい。半導体基板１上に真性半導体層３１，４１を設けることにより、半導体基板１の表面パッシベーションを有効に行うことができる。また、真性半導体層３１，４１を設けることにより、導電型半導体層３２，４２製膜時の半導体基板１への不純物の拡散を抑制できる。真性半導体層としては、シリコンと水素で構成される真性非晶質シリコン薄膜が好ましい。真性半導体層３１，４１は光キャリアの生成および回収には直接寄与しないため、その膜厚は、パッシベーション効果が得られる範囲で設定され、例えば０．１～２５ｎｍ程度である。 As described above, the intrinsic semiconductor layers 31 and 41 are preferably provided between the semiconductor substrate 1 and the p-type semiconductor layer 32 and between the semiconductor substrate 1 and the n-type semiconductor layer 42. By providing the intrinsic semiconductor layers 31 and 41 on the semiconductor substrate 1, surface passivation of the semiconductor substrate 1 can be effectively performed. Further, by providing the intrinsic semiconductor layers 31 and 41, it is possible to suppress the diffusion of impurities to the semiconductor substrate 1 when forming the conductive semiconductor layers 32 and 42. As the intrinsic semiconductor layer, an intrinsic amorphous silicon thin film composed of silicon and hydrogen is preferable. Since the intrinsic semiconductor layers 31 and 41 do not directly contribute to the generation and recovery of photocarriers, the film thickness is set in a range where a passivation effect can be obtained, and is, for example, about 0.1 to 25 nm.
　真性半導体層および導電型半導体層の製膜方法としては、プラズマＣＶＤ法が好ましい。プラズマＣＶＤ法によるシリコン系半導体薄膜の製膜には、ＳｉＨ４、Ｓｉ２Ｈ６等のシリコン含有ガス、またはシリコン系ガスとＨ２との混合ガスが好ましく用いられる。ｐ型またはｎ型のシリコン系薄膜を形成するためのドーパントガスとしては、Ｂ２Ｈ６またはＰＨ３等が好ましく用いられる。 A plasma CVD method is preferable as a method for forming the intrinsic semiconductor layer and the conductive semiconductor layer. A silicon-containing gas such as SiH 4 or Si 2 H 6 or a mixed gas of silicon-based gas and H 2 is preferably used for forming a silicon-based semiconductor thin film by the plasma CVD method. B 2 H 6 or PH 3 is preferably used as the dopant gas for forming the p-type or n-type silicon-based thin film.
（第一導電性薄膜形成）
　図３Ｂに示すように、ｐ型半導体層３２上に第一導電性薄膜３３が形成される。第一導電性薄膜３３は、完成後の太陽電池においてｐ型半導体層３２から光キャリアを回収する作用を有する。また、太陽電池の製造工程においては、第一導電性薄膜３３がエッチャント等の薬液からｐ型半導体層３２の表面を保護する役割を果たす。第二導電性薄膜４３は、完成後の太陽電池においてｎ型半導体層４２から光キャリアを回収する作用を有し、太陽電池の製造工程においてはｎ型半導体層４２を薬液から保護する役割を果たす。 (First conductive thin film formation)
As shown in FIG. 3B, the first conductive thin film 33 is formed on the p-type semiconductor layer 32. The first conductive thin film 33 has a function of collecting optical carriers from the p-type semiconductor layer 32 in the completed solar cell. In the solar cell manufacturing process, the first conductive thin film 33 serves to protect the surface of the p-type semiconductor layer 32 from a chemical solution such as an etchant. The second conductive thin film 43 has a function of recovering optical carriers from the n-type semiconductor layer 42 in the completed solar cell, and plays a role of protecting the n-type semiconductor layer 42 from the chemical solution in the manufacturing process of the solar cell. .
　導電性薄膜３３，４３としては、金属薄膜や導電性酸化物薄膜等が好ましい。特に、薬液に対する耐久性が高く、半導体層に対する保護性に優れることから、酸化インジウム、酸化亜鉛、酸化錫、および酸化チタン等の金属酸化物が好ましい。導電性酸化物は複合金属酸化物でもよい。導電性薄膜３３，４３の材料は、導電性および長期信頼性等に優れることから、酸化インジウムを主成分とするインジウム系酸化物が好ましく、中でも酸化インジウム錫（ＩＴＯ）が特に好ましい。導電性薄膜３３，４３の膜厚は、例えば、１０ｎｍ～２００ｎｍ程度である。導電性薄膜の製膜方法は特に限定されないが、スパッタ法等の物理気相堆積法、有機金属化合物と酸素または水との反応を利用した化学気相堆積（ＭＯＣＶＤ）法等のドライプロセスが好ましい。 As the conductive thin films 33 and 43, a metal thin film, a conductive oxide thin film, or the like is preferable. In particular, metal oxides such as indium oxide, zinc oxide, tin oxide, and titanium oxide are preferable because they have high durability against chemicals and excellent protection against semiconductor layers. The conductive oxide may be a composite metal oxide. The material of the conductive thin films 33 and 43 is preferably an indium oxide mainly composed of indium oxide because of its excellent conductivity and long-term reliability, and indium tin oxide (ITO) is particularly preferable. The film thickness of the conductive thin films 33 and 43 is, for example, about 10 nm to 200 nm. A method for forming the conductive thin film is not particularly limited, but a dry process such as a physical vapor deposition method such as sputtering or a chemical vapor deposition (MOCVD) method using a reaction between an organometallic compound and oxygen or water is preferable. .
　第一導電性薄膜３３のパターニングが行われ、図３Ｃに示すように、開口３３ａが形成される。第一導電性薄膜３３のパターニングは、例えばフォトリソグラフィーにより行われる。フォトリソグラフィーでは、第一導電性薄膜３３を残存させるべき部分にレジスト膜を形成し、レジスト膜の開口下に露出した第一導電性薄膜３３をエッチングにより除去する。エッチングには、第一導電性薄膜３３を溶解し、下地となる半導体層を溶解し難い薬液が用いられる。第一導電性薄膜３３がＩＴＯ等の導電性酸化物である場合には、エッチャントとして塩化鉄水溶液や、塩酸等が好ましく用いられる。 The patterning of the first conductive thin film 33 is performed, and an opening 33a is formed as shown in FIG. 3C. The patterning of the first conductive thin film 33 is performed, for example, by photolithography. In photolithography, a resist film is formed in a portion where the first conductive thin film 33 should remain, and the first conductive thin film 33 exposed under the opening of the resist film is removed by etching. For the etching, a chemical solution that dissolves the first conductive thin film 33 and hardly dissolves the underlying semiconductor layer is used. When the first conductive thin film 33 is a conductive oxide such as ITO, an aqueous iron chloride solution, hydrochloric acid, or the like is preferably used as an etchant.
　フォトリソグラフィーに代えて、エッチングペーストやエッチングインクを用いてパターニングを行ってもよい。この場合には、スクリーン印刷やインクジェット印刷等により、第一導電性薄膜３３を除去するべき部分（開口３３ａを設ける部分）にエッチングペーストまたはエッチングインクを塗布すればよい。 Instead of photolithography, patterning may be performed using an etching paste or an etching ink. In this case, an etching paste or an etching ink may be applied to a portion where the first conductive thin film 33 is to be removed (a portion where the opening 33a is provided) by screen printing, ink jet printing, or the like.
（絶縁層形成）
　図３Ｄに示すように、パターニングされた第一導電性薄膜上に、絶縁層５１が形成される。第一導電性薄膜３３はパターニングされているため、第一主面の全面に絶縁層を製膜すると、開口３３ａではｐ型半導体層３２に接するように絶縁層５１が形成され、第一導電性薄膜３３の側面が絶縁層５１により覆われる。 (Insulating layer formation)
As shown in FIG. 3D, an insulating layer 51 is formed on the patterned first conductive thin film. Since the first conductive thin film 33 is patterned, when an insulating layer is formed on the entire surface of the first main surface, the insulating layer 51 is formed in contact with the p-type semiconductor layer 32 in the opening 33a. The side surface of the thin film 33 is covered with the insulating layer 51.
　絶縁層５１は、絶縁性を有し、ｐ型半導体層３２とｎ型半導体層４２とのリークを抑制できるものであれば、その材料は特に限定されない。エッチングによるパターニングが容易であることから、絶縁層５１の材料としては、酸化シリコン、窒化シリコン、酸窒化シリコン等のシリコン合金を主成分とするものが好ましく、中でも酸化シリコンが特に好ましい。絶縁層５１は、スパッタ法やプラズマＣＶＤ法等のドライプロセスにより製膜することが好ましい。 The material of the insulating layer 51 is not particularly limited as long as it has insulating properties and can suppress leakage between the p-type semiconductor layer 32 and the n-type semiconductor layer 42. Since the patterning by etching is easy, the material of the insulating layer 51 is preferably a material mainly composed of a silicon alloy such as silicon oxide, silicon nitride, or silicon oxynitride, and silicon oxide is particularly preferable. The insulating layer 51 is preferably formed by a dry process such as a sputtering method or a plasma CVD method.
（パターニング）
　領域２００上に設けられた各層をエッチングにより除去して、図３Ｅに示すように、半導体基板１を露出させる。絶縁層は、レジストを用いたフォトリソグラフィーやエッチングペースト等によりパターニングすればよい。絶縁層５１のエッチングには、フッ酸水溶液等の酸系エッチャントが好ましく用いられる。 (Patterning)
Each layer provided on the region 200 is removed by etching to expose the semiconductor substrate 1 as shown in FIG. 3E. The insulating layer may be patterned by photolithography using a resist, an etching paste, or the like. For etching the insulating layer 51, an acid-based etchant such as a hydrofluoric acid aqueous solution is preferably used.
　領域２００の絶縁層５１を除去後、絶縁層の間に露出した第一導電性薄膜３３，ｐ型半導体層３２およびその下に設けられた真性半導体層３１をエッチングにより除去する。前述のように、導電性薄膜のエッチングには、塩化鉄水溶液や、塩酸等が好ましく用いられる。ｐ型半導体層３２および真性半導体層３１のエッチングには、例えばフッ酸を含む水溶液が用いられ、中でもフッ酸と硝酸の混酸が好ましく用いられる。 After removing the insulating layer 51 in the region 200, the first conductive thin film 33, the p-type semiconductor layer 32 exposed between the insulating layers, and the intrinsic semiconductor layer 31 provided thereunder are removed by etching. As described above, an aqueous iron chloride solution, hydrochloric acid, or the like is preferably used for etching the conductive thin film. For the etching of the p-type semiconductor layer 32 and the intrinsic semiconductor layer 31, for example, an aqueous solution containing hydrofluoric acid is used, and in particular, a mixed acid of hydrofluoric acid and nitric acid is preferably used.
　図３Ｄでは、パターン層１３の端部領域１０２に対応する部分にのみ開口３３ａを形成する形態を示したが、図５に示すように、第一導電性薄膜３３の開口３３ａは、露出領域２００にも形成されてもよい。領域２００の全体に第一導電性薄膜３３の開口３３ａが設けられている場合は、絶縁層３３を製膜後、領域２００上に設けられた各層をエッチングにより除去する際に、第一導電性薄膜３３のエッチングを実施する必要がない。 Although FIG. 3D shows a form in which the opening 33a is formed only in a portion corresponding to the end region 102 of the pattern layer 13, the opening 33a of the first conductive thin film 33 is formed in the exposed region 200 as shown in FIG. May also be formed. In the case where the opening 33a of the first conductive thin film 33 is provided in the entire region 200, the first conductive film is formed when each layer provided on the region 200 is removed by etching after the insulating layer 33 is formed. There is no need to perform etching of the thin film 33.
　第一導電性薄膜３３の側面からのリークをより確実に防止する等の観点から、図６に示すように、パターン層１３の端部領域１０２（第一導電性薄膜３３が設けられていない領域）の幅が広くなるようにパターニングを行ってもよい。 From the standpoint of preventing leakage from the side surface of the first conductive thin film 33 more reliably, as shown in FIG. 6, the end region 102 of the pattern layer 13 (region where the first conductive thin film 33 is not provided) ) May be patterned so as to be wide.
＜洗浄＞
　領域１００にパターン層１３を形成後の段階では、図３Ｅに示すように、露出領域２００に半導体基板１が露出している。エッチングにより絶縁層や半導体層のパターニングを実施すると、絶縁層５１の表面や、露出領域２００の半導体基板１の表面が、エッチングにより除去された膜の残渣やエッチャントにより汚染されている可能性がある。そのため、パターン層を形成後、露出領域２００上に半導体層を製膜する前に、基板の洗浄を実施することが好ましい。洗浄に用いられる洗浄液は、半導体基板の表面を清浄化可能であれば特に限定されない。洗浄効果が高いことから、洗浄液としてフッ酸を含有する水溶液を用いることが好ましい。 <Washing>
At a stage after forming the pattern layer 13 in the region 100, the semiconductor substrate 1 is exposed in the exposed region 200 as shown in FIG. 3E. When the insulating layer or the semiconductor layer is patterned by etching, the surface of the insulating layer 51 or the surface of the semiconductor substrate 1 in the exposed region 200 may be contaminated by the residue or etchant of the film removed by the etching. . Therefore, it is preferable to clean the substrate after forming the pattern layer and before forming the semiconductor layer on the exposed region 200. The cleaning liquid used for cleaning is not particularly limited as long as the surface of the semiconductor substrate can be cleaned. Since the cleaning effect is high, it is preferable to use an aqueous solution containing hydrofluoric acid as the cleaning liquid.
　洗浄工程においては、図３Ｅに示すように、ｐ型半導体層３２上に第一導電性薄膜３３および絶縁層５１が設けられているため、洗浄液との接触によるｐ型半導体層へのダメージを防止できる。洗浄工程において導電層が洗浄液と接触すると、洗浄液中に溶出した金属イオン等が半導体基板を汚染する原因となる。第一導電性薄膜３３の主面および側面が絶縁層５１により覆われていれば、第一導電性薄膜を構成する導電性物質が洗浄液に溶出しないため、洗浄液に溶出した金属イオン等に起因する半導体基板の汚染を防止できる。 In the cleaning process, as shown in FIG. 3E, since the first conductive thin film 33 and the insulating layer 51 are provided on the p-type semiconductor layer 32, damage to the p-type semiconductor layer due to contact with the cleaning liquid is prevented. it can. When the conductive layer comes into contact with the cleaning liquid in the cleaning process, metal ions eluted in the cleaning liquid cause contamination of the semiconductor substrate. If the main surface and the side surface of the first conductive thin film 33 are covered with the insulating layer 51, the conductive material constituting the first conductive thin film does not elute into the cleaning liquid, which is caused by metal ions or the like eluted into the cleaning liquid. The contamination of the semiconductor substrate can be prevented.
＜ｎ型半導体層および第二導電性薄膜＞
　パターン層１３を形成し、必要に応じて基板表面の洗浄を実施した後、図３Ｈに示すように、パターン層形成領域１００の中央の領域３０に開口４２ａを有するパターン状のｎ型半導体層４２および第二導電性薄膜４３を形成する。半導体基板１とｎ型半導体層４２との間には、真性半導体層４１が形成されることが好ましい。絶縁層５１とｎ型半導体層４２との間にも真性半導体層４１が設けられていてもよい。 <N-type semiconductor layer and second conductive thin film>
After the pattern layer 13 is formed and the substrate surface is cleaned as necessary, as shown in FIG. 3H, a patterned n-type semiconductor layer 42 having an opening 42a in the central region 30 of the pattern layer forming region 100 is formed. Then, the second conductive thin film 43 is formed. An intrinsic semiconductor layer 41 is preferably formed between the semiconductor substrate 1 and the n-type semiconductor layer 42. An intrinsic semiconductor layer 41 may be provided between the insulating layer 51 and the n-type semiconductor layer 42.
　真性半導体層４１、ｎ型半導体層４２、および第二導電性薄膜４３に開口４２ａを設ける方法としては、ｐ型領域３０をマスクにより遮蔽した状態で各層の製膜を行う方法；および基板上の全面に各層を形成してエッチング等により順次パターニングする方法等が挙げられる。以下では、図３Ｆ～Ｈを参照して、基板上の全面への製膜とエッチングとを繰り返すことによりパターン状のｎ型半導体層４２、および第二導電性薄膜４３を形成する形態について説明する。 As a method of providing the opening 42a in the intrinsic semiconductor layer 41, the n-type semiconductor layer 42, and the second conductive thin film 43, each layer is formed while the p-type region 30 is shielded by a mask; and on the substrate Examples include a method of forming each layer on the entire surface and sequentially patterning by etching or the like. In the following, with reference to FIGS. 3F to 3H, a description will be given of a form in which the patterned n-type semiconductor layer 42 and the second conductive thin film 43 are formed by repeating film formation and etching on the entire surface of the substrate. .
（ｎ型半導体層形成）
　図３Ｆに示すように、基板上の全面を覆うようにｎ型半導体層４２が形成される。ｎ型半導体層４２はｎ型のドーパントが添加された半導体薄膜層であり、リンが添加されたｎ型シリコン系層であることが好ましい。不純物拡散の抑制や直列抵抗低減の観点から、ｎ型半導体層４２としては、ｎ型非晶質シリコン系層が好ましく、ｎ型非晶質シリコンが特に好ましい。ｎ型半導体層４２の膜厚は、例えば２～５０ｎｍ程度である。ｎ型半導体層４２を製膜する前に真性半導体層４１を製膜することにより、半導体基板１とｎ型半導体層４２との間、および絶縁層５１とｎ型半導体層４２との間に、真性半導体層４１が設けられる。 (N-type semiconductor layer formation)
As shown in FIG. 3F, an n-type semiconductor layer 42 is formed so as to cover the entire surface of the substrate. The n-type semiconductor layer 42 is a semiconductor thin film layer to which an n-type dopant is added, and is preferably an n-type silicon-based layer to which phosphorus is added. From the viewpoint of suppressing impurity diffusion and reducing series resistance, the n-type semiconductor layer 42 is preferably an n-type amorphous silicon-based layer, and n-type amorphous silicon is particularly preferable. The thickness of the n-type semiconductor layer 42 is, for example, about 2 to 50 nm. By forming the intrinsic semiconductor layer 41 before forming the n-type semiconductor layer 42, between the semiconductor substrate 1 and the n-type semiconductor layer 42 and between the insulating layer 51 and the n-type semiconductor layer 42, An intrinsic semiconductor layer 41 is provided.
（第二導電性薄膜形成）
　図３Ｇに示すように、ｎ型半導体層４２上に第二導電性薄膜４３が形成される。前述のように、第二導電性薄膜４３の材料としては、金属薄膜や導電性酸化物薄膜が好ましい。 (Second conductive thin film formation)
As shown in FIG. 3G, the second conductive thin film 43 is formed on the n-type semiconductor layer 42. As described above, the material of the second conductive thin film 43 is preferably a metal thin film or a conductive oxide thin film.
（ｎ型半導体層および第二導電性薄膜のパターニング）
　パターン層形成領域１００の中央の領域３０における第二導電性薄膜４３、ｎ型半導体層４２および真性半導体層４１をエッチングにより除去して、図３Ｈに示すように、開口４２ａを形成し、開口下に絶縁層５１を露出させる。ｎ型半導体層４２および真性半導体層４１のエッチングには、ＫＯＨやＮａＯＨ等を含むアルカリ水溶液が好ましく用いられる。レジストを用いたフォトリソグラフィーによりパターニングを行う場合は、第二導電性薄膜４３上にレジストが設けられる。そのため、ｎ型半導体層４２の表面が、レジスト液、現像液、剥離液等の薬液に触れることがなく、薬液との接触に起因する半導体層へのダメージを防止できる。 (Patterning of n-type semiconductor layer and second conductive thin film)
The second conductive thin film 43, the n-type semiconductor layer 42 and the intrinsic semiconductor layer 41 in the central region 30 of the pattern layer forming region 100 are removed by etching to form an opening 42a as shown in FIG. The insulating layer 51 is exposed. For the etching of the n-type semiconductor layer 42 and the intrinsic semiconductor layer 41, an alkaline aqueous solution containing KOH, NaOH, or the like is preferably used. When patterning is performed by photolithography using a resist, the resist is provided on the second conductive thin film 43. Therefore, the surface of the n-type semiconductor layer 42 does not come into contact with a chemical solution such as a resist solution, a developer solution, or a stripping solution, and damage to the semiconductor layer due to contact with the chemical solution can be prevented.
＜絶縁層のパターニング＞
　パターン層形成領域１００中央の領域３０の開口４２ａ下に露出した絶縁層５１をエッチングにより除去して、図３Ｉに示すように、第一導電性薄膜３３を露出させる。前述のように、絶縁層５１のエッチングには、フッ酸水溶液等の酸系エッチャントが好ましく用いられる。 <Insulating layer patterning>
The insulating layer 51 exposed under the opening 42a in the central region 30 of the pattern layer forming region 100 is removed by etching, so that the first conductive thin film 33 is exposed as shown in FIG. 3I. As described above, an acid-based etchant such as a hydrofluoric acid aqueous solution is preferably used for etching the insulating layer 51.
　絶縁層５１が除去された領域が太陽電池のｐ型領域３０に該当し、絶縁層が除去されずに残存している領域が太陽電池の境界領域５０に該当する。ｎ型半導体層４２の開口４２ａ下に露出した絶縁層５１をエッチングにより除去する場合、ｎ型半導体層４２の側面と絶縁層５１の側面の位置が揃うため、ｎ型領域４０と境界領域５０の全面（第一境界領域１０１および第二境界領域１０２の両方）にｎ型半導体層４２が設けられた太陽電池が得られる。 The region where the insulating layer 51 is removed corresponds to the p-type region 30 of the solar cell, and the region where the insulating layer remains without being removed corresponds to the boundary region 50 of the solar cell. When the insulating layer 51 exposed under the opening 42a of the n-type semiconductor layer 42 is removed by etching, the side surfaces of the n-type semiconductor layer 42 and the side surfaces of the insulating layer 51 are aligned. A solar cell in which the n-type semiconductor layer 42 is provided on the entire surface (both the first boundary region 101 and the second boundary region 102) is obtained.
　ｐ型領域３０の絶縁層５１をエッチングにより除去すると、第一導電性薄膜３３が露出する。ｐ型半導体層４２上には第一導電性薄膜３３が設けられているため、絶縁層のエッチングに用いられるエッチャントのｐ型半導体層への接触を防止し、ｐ型半導体層へのダメージを防止できる。また、絶縁層のエッチングを実施しない領域（ｐ型領域３０以外の領域）では、ｎ型半導体層４２上に第二導電性薄膜４３が設けられているため、エッチャントとの接触によるｎ型半導体層４２へのダメージを防止できる。 When the insulating layer 51 in the p-type region 30 is removed by etching, the first conductive thin film 33 is exposed. Since the first conductive thin film 33 is provided on the p-type semiconductor layer 42, an etchant used for etching the insulating layer is prevented from contacting the p-type semiconductor layer, and damage to the p-type semiconductor layer is prevented. it can. In the region where the insulating layer is not etched (the region other than the p-type region 30), the second conductive thin film 43 is provided on the n-type semiconductor layer 42. Therefore, the n-type semiconductor layer is brought into contact with the etchant. Damage to 42 can be prevented.
［第一主面の構成の概括および変形例］
　絶縁層をパターニングして第一導電性薄膜３３を露出させた後、第一導電性薄膜３３上および第二導電性薄膜４３上のそれぞれに第一金属電極３５および第二金属電極４５を形成することにより、図１に示すバックコンタクト型太陽電池の第一主面上の各層の形成が完了する。 [Overview of the configuration of the first main surface and modifications]
After patterning the insulating layer to expose the first conductive thin film 33, the first metal electrode 35 and the second metal electrode 45 are formed on the first conductive thin film 33 and the second conductive thin film 43, respectively. Thereby, formation of each layer on the 1st main surface of the back contact type solar cell shown in FIG. 1 is completed.
　図３Ａ～Ｉに示す製造工程では、第一導電型半導体層としてのｐ型半導体層３２上にｐ型半導体層からのキャリア回収とｐ型半導体層の薬液からの保護を目的とした第一導電性薄膜３３を形成後に、絶縁層５１が形成され、その後に第二導電型半導体層としてのｎ型半導体層４２が形成される。ｎ型半導体層４２上にｎ型半導体層からのキャリア回収とｎ型半導体層の薬液からの保護を目的とした第二導電性薄膜４３を形成後に、エッチングによる第二導電性薄膜、ｎ型半導体層４２および絶縁層５１のパターニングが行われる。このように、第一導電型半導体層３２および第二導電型半導体層４２のそれぞれに、第一導電性薄膜３３および第二導電性薄膜４３を設けることにより、薬液との接触に起因する半導体層へのダメージを防止し、太陽電池の特性を向上できる。 In the manufacturing process shown in FIGS. 3A to 3I, the first conductivity for the purpose of carrier recovery from the p-type semiconductor layer and protection from the chemical solution of the p-type semiconductor layer on the p-type semiconductor layer 32 as the first conductivity type semiconductor layer. After forming the conductive thin film 33, the insulating layer 51 is formed, and then the n-type semiconductor layer 42 as the second conductivity type semiconductor layer is formed. After forming the second conductive thin film 43 for the purpose of carrier recovery from the n-type semiconductor layer and protection of the n-type semiconductor layer from the chemical solution on the n-type semiconductor layer 42, the second conductive thin film by etching and the n-type semiconductor are formed. Patterning of the layer 42 and the insulating layer 51 is performed. Thus, by providing the first conductive thin film 33 and the second conductive thin film 43 in the first conductive semiconductor layer 32 and the second conductive semiconductor layer 42, respectively, the semiconductor layer caused by contact with the chemical solution Can be prevented, and the characteristics of the solar cell can be improved.
　前述のように、境界領域５０において、第二導電型領域４０に接する第二境界領域１０２に第一導電性薄膜３３が設けられておらず、第一導電性薄膜３３の側面が絶縁層５１により覆われていれば、第一導電性薄膜３３から第二導電型半導体層４２へのリーク電流を抑制できる。図７および図８に示すように、境界領域５０において、第一導電性薄膜３３に加えて、第一導電型半導体層３２の側面も絶縁層５１により覆われていてもよい。第一導電型半導体層３２の側面が絶縁層５１により覆われていれば、第一導電型半導体層３２と第二導電型半導体層４２との間のリークをさらに低減できる。 As described above, in the boundary region 50, the first conductive thin film 33 is not provided in the second boundary region 102 in contact with the second conductivity type region 40, and the side surface of the first conductive thin film 33 is formed by the insulating layer 51. If it is covered, the leakage current from the first conductive thin film 33 to the second conductive type semiconductor layer 42 can be suppressed. As shown in FIGS. 7 and 8, in the boundary region 50, in addition to the first conductive thin film 33, the side surface of the first conductivity type semiconductor layer 32 may be covered with an insulating layer 51. If the side surface of the first conductivity type semiconductor layer 32 is covered with the insulating layer 51, the leakage between the first conductivity type semiconductor layer 32 and the second conductivity type semiconductor layer 42 can be further reduced.
　図７に示す形態では、第一真性半導体層３１の側面が絶縁層５１により覆われておらず、境界領域５０の全面に第一真性半導体層３１が設けられている。この形態では、半導体基板１の第一主面の全面に第一真性半導体層４１または第二真性半導体層４２が設けられているため、半導体基板のパッシベーション効果が高められ、かつ第一導電型半導体層３２の側面が絶縁層５１により覆われているため、ｐｎ間のリークをより確実に低減できる。 In the form shown in FIG. 7, the side surface of the first intrinsic semiconductor layer 31 is not covered with the insulating layer 51, and the first intrinsic semiconductor layer 31 is provided on the entire boundary region 50. In this embodiment, since the first intrinsic semiconductor layer 41 or the second intrinsic semiconductor layer 42 is provided on the entire first main surface of the semiconductor substrate 1, the passivation effect of the semiconductor substrate is enhanced, and the first conductivity type semiconductor is provided. Since the side surface of the layer 32 is covered with the insulating layer 51, the leakage between pn can be more reliably reduced.
［金属電極形成］
　図３Ｊに示すように、第一導電性薄膜３３上および第二導電性薄膜４３上に、それぞれ、第一金属電極３５および第二金属電極４５が形成される。金属電極３５，４５の形成方法は特に限定されず、例えば、スパッタ等のドライプロセス、印刷、めっき等により形成すればよい。金属電極３５，４５の厚みは、例えば５０ｎｍ～１００μｍ程度に設定される。金属電極３５，４５は複数層からなる積層構造でもよい。例えば、Ａｇペースト等の印刷により形成された金属層を下地として、その上に電解めっきによりＣｕ等を形成してもよい。 [Metal electrode formation]
As shown in FIG. 3J, a first metal electrode 35 and a second metal electrode 45 are formed on the first conductive thin film 33 and the second conductive thin film 43, respectively. The formation method of the metal electrodes 35 and 45 is not particularly limited, and may be formed by, for example, a dry process such as sputtering, printing, plating, or the like. The thickness of the metal electrodes 35 and 45 is set to, for example, about 50 nm to 100 μm. The metal electrodes 35 and 45 may have a laminated structure including a plurality of layers. For example, Cu or the like may be formed by electrolytic plating on a metal layer formed by printing such as Ag paste.
　めっきにより金属電極３５，４５を形成する場合、導電性薄膜３３，４３を導電性下地としてその上に金属を析出させればよい。導電性薄膜３３，３４上に印刷等により導電性下地層を設け、その上にめっきにより金属電極を形成してもよい。 When the metal electrodes 35 and 45 are formed by plating, the metal may be deposited on the conductive thin films 33 and 43 as a conductive base. A conductive base layer may be provided on the conductive thin films 33 and 34 by printing or the like, and a metal electrode may be formed thereon by plating.
　めっきにより金属電極を形成する場合、厚み方向だけでなく幅方向にも金属が成長するため、第一金属電極３５と第二金属電極４５との短絡が生じないように、電極形成領域を制限することが好ましい。例えば、第一導電性薄膜３３上および第二導電性薄膜４３上にレジスト膜等の絶縁層を形成し、絶縁層の開口部分にめっきにより金属を析出させればよい。 When a metal electrode is formed by plating, the metal grows not only in the thickness direction but also in the width direction. Therefore, the electrode formation region is limited so that a short circuit between the first metal electrode 35 and the second metal electrode 45 does not occur. It is preferable. For example, an insulating layer such as a resist film may be formed on the first conductive thin film 33 and the second conductive thin film 43, and a metal may be deposited on the opening of the insulating layer by plating.
　導電性薄膜３３，４３上に、印刷により下地シード金属層３５ａ，４５ａを形成し、その上にめっき金属層３５ｂ，４５ｂを形成する場合も、絶縁層５９の開口部分にめっき金属を析出させることが好ましい。絶縁層５９は、下地シード金属層の形成前後のいずれに設けてもよい。導電性薄膜３３，４３上に、下地シード金属層３５ａ，４５ｂを形成後、図９Ａに示すように、基板上の全面に絶縁層５９を形成し、図９Ｂに示すように下地シード金属層３５ａ，４５ｂ上に選択的に開口５９ａを形成することにより、下地シード金属層３５ａ，４５ａ上に選択的にめっき金属３５ｂ，４５ｂを析出させてもよい。 Even when the base seed metal layers 35a and 45a are formed on the conductive thin films 33 and 43 by printing and the plated metal layers 35b and 45b are formed thereon, the plated metal is deposited on the opening portion of the insulating layer 59. Is preferred. The insulating layer 59 may be provided before or after the formation of the base seed metal layer. After forming the base seed metal layers 35a and 45b on the conductive thin films 33 and 43, an insulating layer 59 is formed on the entire surface of the substrate as shown in FIG. 9A, and the base seed metal layer 35a as shown in FIG. 9B. , 45b may be selectively formed on the seed metal layers 35a, 45a to selectively deposit the plating metals 35b, 45b.
　例えば、Ａｇペースト等の導電性ペーストの印刷により下地シード金属層３５ａ，４５ａを形成し、ドライプロセスにより酸化シリコン等の絶縁層を形成する方法では、絶縁層５９の製膜時または製膜後の加熱により、下地シード金属層の表面形状を変化させ、その上に設けられた絶縁層５９にき裂状の開口５９ａを形成できる。絶縁層５９の開口５９ａの下に露出した下地シード金属層３５ａ，４５ａがめっきの起点となるため、下地シード金属層３５ａ，４５ａが印刷された領域に、選択的にめっき金属層３５ｂ，４５ｂを形成できる（例えばＷＯ２０１３/０７７０３８号参照）。下地シード金属層３５ａ，４５ａの凹凸により、その上に製膜された絶縁層５９に開口５９ａを形成することもできる（例えばＷＯ２０１１/０４５２８７号参照）。 For example, in the method in which the base seed metal layers 35a and 45a are formed by printing a conductive paste such as Ag paste and an insulating layer such as silicon oxide is formed by a dry process, the insulating layer 59 is formed during or after the formation. By heating, the surface shape of the base seed metal layer is changed, and a crack-like opening 59a can be formed in the insulating layer 59 provided thereon. Since the seed metal layers 35a and 45a exposed under the openings 59a of the insulating layer 59 serve as starting points for plating, the plated metal layers 35b and 45b are selectively formed in the areas where the base seed metal layers 35a and 45a are printed. Can be formed (see, for example, WO2013 / 077038). Due to the unevenness of the seed metal layers 35a and 45a, an opening 59a can be formed in the insulating layer 59 formed thereon (see, for example, WO2011 / 045287).
［第二主面上の構成］
　バックコンタクト型太陽電池において、受光面である第二主面は、発電および電流の取り出しには直接寄与しない。そのため、第二主面上の構成は、太陽光の受光を妨げない限り、特に制限はない。図１に示す太陽電池では、半導体基板１の第二主面上に、受光面真性半導体層２、受光面導電型半導体層３および受光面保護層４がこの順に設けられている。 [Configuration on the second main surface]
In the back contact solar cell, the second main surface, which is the light receiving surface, does not directly contribute to power generation and current extraction. Therefore, the configuration on the second main surface is not particularly limited as long as it does not hinder the reception of sunlight. In the solar cell shown in FIG. 1, a light-receiving surface intrinsic semiconductor layer 2, a light-receiving surface conductive semiconductor layer 3 and a light-receiving surface protective layer 4 are provided in this order on the second main surface of the semiconductor substrate 1.
　受光面真性半導体層２としては、真性非晶質シリコン薄膜等のシリコン系薄膜が好ましい。受光面真性半導体層２が設けられることにより、基板表面のパッシベーションを有効に行うことができる。受光面真性半導体層２は光キャリアの生成および回収に直接寄与しないため、受光を妨げず、パッシベーション効果が得られるように膜厚を設定することが好ましい。受光面真性半導体層２の膜厚は、例えば０．１～２５ｎｍ程度である。 The light-receiving surface intrinsic semiconductor layer 2 is preferably a silicon-based thin film such as an intrinsic amorphous silicon thin film. By providing the light-receiving surface intrinsic semiconductor layer 2, passivation of the substrate surface can be performed effectively. Since the light-receiving surface intrinsic semiconductor layer 2 does not directly contribute to the generation and collection of optical carriers, it is preferable to set the film thickness so as to obtain a passivation effect without preventing light reception. The film thickness of the light-receiving surface intrinsic semiconductor layer 2 is, for example, about 0.1 to 25 nm.
　受光面真性半導体層２上には、反射防止層としても機能する受光面保護層４が形成されることが好ましい。受光面保護層４は、その下に存在する層（例えば受光面真性半導体層２や受光面導電型半導体層３）を、太陽電池の製造工程において保護可能であり、光透過性を有していれば、その材料は特に制限されない。受光面保護層４の材料としては、酸化シリコン、窒化シリコン、酸窒化シリコン等のシリコン合金を主成分とするものが好ましい。受光面保護層４の膜厚は特に限定されないが、反射防止機能を付与して半導体基板１への光取り込み量を増大させる観点から膜厚を設定することが好ましく、８０ｎｍ～１μｍ程度が好ましい。 On the light-receiving surface intrinsic semiconductor layer 2, it is preferable to form a light-receiving surface protective layer 4 that also functions as an antireflection layer. The light-receiving surface protective layer 4 is capable of protecting the layers (for example, the light-receiving surface intrinsic semiconductor layer 2 and the light-receiving surface conductive semiconductor layer 3) existing under the light-receiving surface protective layer 4 and has light transmittance. The material is not particularly limited. As a material for the light-receiving surface protective layer 4, a material mainly composed of a silicon alloy such as silicon oxide, silicon nitride, or silicon oxynitride is preferable. The film thickness of the light-receiving surface protective layer 4 is not particularly limited, but it is preferable to set the film thickness from the viewpoint of providing an antireflection function and increasing the amount of light taken into the semiconductor substrate 1, and is preferably about 80 nm to 1 μm.
　受光面真性半導体層２と受光面保護層４との間には、受光面導電型半導体層３が形成されてもよい。受光面導電型半導体層３は、半導体基板１と同一の導電型を有することが好ましい。例えば、半導体基板１がｎ型シリコン基板である場合、受光面導電型半導体層３としてｎ型半導体層が形成されることが好ましい。受光面導電型半導体層３は、シリコン系薄膜であることが好ましく、中でも非晶質シリコンがより好ましい。受光面導電型半導体層３の膜厚は、例えば１～２５ｎｍ程度である。 A light-receiving surface conductive semiconductor layer 3 may be formed between the light-receiving surface intrinsic semiconductor layer 2 and the light-receiving surface protective layer 4. The light-receiving surface conductive semiconductor layer 3 preferably has the same conductivity type as the semiconductor substrate 1. For example, when the semiconductor substrate 1 is an n-type silicon substrate, an n-type semiconductor layer is preferably formed as the light-receiving surface conductive semiconductor layer 3. The light-receiving surface conductive semiconductor layer 3 is preferably a silicon-based thin film, and more preferably amorphous silicon. The film thickness of the light-receiving surface conductive semiconductor layer 3 is, for example, about 1 to 25 nm.
　半導体基板１の第二主面への半導体層２，３や保護層４の形成方法は特に限定されないが、第一主面上への半導体層や絶縁層の形成と同様、プラズマＣＶＤ法による製膜が好ましい。第二主面に半導体層２，３や保護層４を形成するタイミングは特に限定されず、第一主面への各層の製膜と第二主面への各層の製膜とは、どちらが先に行われてもよい。半導体基板の第二主面のパッシベーションを有効に行う観点から、第一主面への第一導電性薄膜３３の製膜（図３Ｂ）の前に、第二主面への受光面真性半導体層２の製膜を行うことが好ましい。 The method for forming the semiconductor layers 2 and 3 and the protective layer 4 on the second main surface of the semiconductor substrate 1 is not particularly limited. A membrane is preferred. The timing at which the semiconductor layers 2 and 3 and the protective layer 4 are formed on the second main surface is not particularly limited. Which is the first of the deposition of each layer on the first major surface and the deposition of each layer on the second major surface? May be done. From the viewpoint of effectively performing passivation of the second main surface of the semiconductor substrate, the light-receiving surface intrinsic semiconductor layer on the second main surface is formed before the first conductive thin film 33 is formed on the first main surface (FIG. 3B). It is preferable to perform film formation of No.2.
　　　１　　　　　　半導体基板
　　３１，４１　　　真性半導体層
　　３２，４２　　　導電型半導体層
　　３３，４３　　　導電性薄膜
　　３５，４５　　　金属電極
　　５１　　　　　　絶縁層
　　３０　　　　　　第一導電型領域
　　４０　　　　　　第二導電型領域
　　５０　　　　　　境界領域
　１０１　　　　　　第一境界領域
　１０２　　　　　　第二境界領域 1 Semiconductor substrate 31, 41 Intrinsic semiconductor layer 32, 42 Conductive semiconductor layer 33, 43 Conductive thin film 35, 45 Metal electrode 51 Insulating layer 30 First conductivity type region 40 Second conductivity type region 50 Boundary region 101 First boundary region 102 Second boundary region

Claims (12)

  1. 　半導体基板の第一主面上に、第一方向に沿って第一導電型領域と第二導電型領域とが交互に配置され、第一導電型領域および第二導電型領域のそれぞれに接して両者を離間する境界領域を有する太陽電池であって、
    　前記第一導電型領域の全面および前記境界領域に跨って設けられた第一導電型半導体層；
    　前記第二導電型領域の全面および前記境界領域に跨って設けられ、前記第一導電型半導体層とは異なる導電型を有する第二導電型半導体層；
    　前記第一導電型領域の全面および前記境界領域に跨って設けられた第一導電性薄膜；
    　前記第二導電型領域の全面および前記境界領域に跨って設けられた第二導電性薄膜；および
    　前記境界領域の全面に設けられた絶縁層、を半導体基板の第一主面上に備え、
    　前記第一導電型領域では、前記半導体基板上に、前記第一導電型半導体層、および前記第一導電性薄膜がこの順に設けられており、
    　前記第二導電型領域では、前記半導体基板上に、前記第二導電型半導体層、および前記第二導電性薄膜がこの順に設けられており、
    　前記境界領域は、前記第一導電型領域に接する第一境界領域と前記第二導電型領域に接する第二境界領域とを有し、
    　前記第一境界領域では、前記半導体基板上に、前記第一導電型半導体層、前記第一導電性薄膜、および前記絶縁層がこの順に設けられており、
    　前記第二境界領域では、前記半導体基板と前記絶縁層との間に前記第一導電性薄膜が設けられておらず、前記絶縁層上に、前記第二導電型半導体層、および前記第二導電性薄膜がこの順に設けられており、
    　前記第一境界領域と前記第二境界領域との境界部分において、前記第一導電性薄膜の側面が前記絶縁層により覆われている、太陽電池。     On the first main surface of the semiconductor substrate, first conductivity type regions and second conductivity type regions are alternately arranged along the first direction, and are in contact with the first conductivity type region and the second conductivity type region, respectively. A solar cell having a boundary region separating the two,
    A first conductivity type semiconductor layer provided across the entire surface of the first conductivity type region and the boundary region;
    A second conductivity type semiconductor layer provided across the entire surface of the second conductivity type region and the boundary region and having a conductivity type different from that of the first conductivity type semiconductor layer;
    A first conductive thin film provided across the entire surface of the first conductivity type region and the boundary region;
    A second conductive thin film provided across the entire surface of the second conductivity type region and the boundary region; and an insulating layer provided over the entire surface of the boundary region, on the first main surface of the semiconductor substrate,
    In the first conductivity type region, the first conductivity type semiconductor layer and the first conductive thin film are provided in this order on the semiconductor substrate,
    In the second conductivity type region, the second conductivity type semiconductor layer and the second conductive thin film are provided in this order on the semiconductor substrate,
    The boundary region has a first boundary region in contact with the first conductivity type region and a second boundary region in contact with the second conductivity type region;
    In the first boundary region, the first conductive semiconductor layer, the first conductive thin film, and the insulating layer are provided in this order on the semiconductor substrate,
    In the second boundary region, the first conductive thin film is not provided between the semiconductor substrate and the insulating layer, and the second conductive semiconductor layer and the second conductive layer are formed on the insulating layer. The functional thin film is provided in this order,
    The solar cell, wherein a side surface of the first conductive thin film is covered with the insulating layer at a boundary portion between the first boundary region and the second boundary region.
  2. 　前記第二導電型半導体層および前記第二導電性薄膜が、前記境界領域の全面に設けられており、
    　前記第一境界領域では、前記半導体基板上に、前記第一導電型半導体層、前記第一導電性薄膜、前記第二導電型半導体層、および前記第二導電性薄膜がこの順に設けられている、請求項１に記載の太陽電池。     The second conductive semiconductor layer and the second conductive thin film are provided on the entire boundary region,
    In the first boundary region, the first conductive semiconductor layer, the first conductive thin film, the second conductive semiconductor layer, and the second conductive thin film are provided in this order on the semiconductor substrate. The solar cell according to claim 1.
  3. 　前記第一導電型半導体層が、前記境界領域の全面に設けられており、
    　前記第二境界領域では、前記半導体基板上に、前記第一導電型半導体層、前記絶縁層、前記第二導電型半導体層、および前記第二導電性薄膜がこの順に設けられている、請求項１または２に記載の太陽電池。     The first conductivity type semiconductor layer is provided over the entire boundary region;
    In the second boundary region, the first conductive semiconductor layer, the insulating layer, the second conductive semiconductor layer, and the second conductive thin film are provided in this order on the semiconductor substrate. The solar cell according to 1 or 2.
  4. 　前記第二境界領域には前記第一導電型半導体層が設けられておらず、
    　前記第一境界領域と前記第二境界領域との境界部分において、前記第一導電型半導体層の側面が前記絶縁層により覆われている、請求項１または２に記載の太陽電池。     The second conductive region is not provided with the first conductivity type semiconductor layer,
    3. The solar cell according to claim 1, wherein a side surface of the first conductivity type semiconductor layer is covered with the insulating layer at a boundary portion between the first boundary region and the second boundary region.
  5. 　前記半導体基板と前記第一導電型半導体層との間に第一真性半導体層を備え、前記半導体基板と前記第二導電型半導体層との間に第二真性半導体層を備える、請求項１～４のいずれか１項に記載の太陽電池。 A first intrinsic semiconductor layer is provided between the semiconductor substrate and the first conductive semiconductor layer, and a second intrinsic semiconductor layer is provided between the semiconductor substrate and the second conductive semiconductor layer. 5. The solar cell according to any one of 4 above.
  6. 　半導体基板の第一主面上に、第一方向に沿って第一導電型領域と第二導電型領域とが交互に配置され、第一導電型領域および第二導電型領域のそれぞれに接して両者を離間する境界領域を有する太陽電池の製造方法であって、
    　半導体基板の第一主面上の第一導電型領域および境界領域に、第一導電型半導体層、第一導電性薄膜および絶縁層がこの順に積層されたパターン層を形成する工程；
    　半導体基板の第一主面上の第二導電型領域および境界領域上に、前記第一導電型半導体層とは異なる導電型を有する第二導電型半導体層、および第二導電性薄膜を、順に形成する工程；および
    　前記第一導電型領域に設けられた絶縁層をエッチングにより除去して前記第一導電性薄膜を露出させる工程
    　を順に有し、
    　前記第二導電型半導体層および前記第二導電性薄膜は、前記第一導電型領域に開口を有するようにパターニングされており、前記第二導電型半導体層の開口下に露出した絶縁層がエッチングにより除去される、太陽電池の製造方法。     On the first main surface of the semiconductor substrate, first conductivity type regions and second conductivity type regions are alternately arranged along the first direction, and are in contact with the first conductivity type region and the second conductivity type region, respectively. A method of manufacturing a solar cell having a boundary region that separates the two,
    Forming a patterned layer in which a first conductive type semiconductor layer, a first conductive thin film and an insulating layer are laminated in this order on the first conductive type region and the boundary region on the first main surface of the semiconductor substrate;
    A second conductive type semiconductor layer having a conductivity type different from that of the first conductive type semiconductor layer, and a second conductive thin film are sequentially formed on the second conductive type region and the boundary region on the first main surface of the semiconductor substrate. And in order to remove the insulating layer provided in the first conductivity type region by etching and expose the first conductive thin film,
    The second conductive type semiconductor layer and the second conductive thin film are patterned so as to have an opening in the first conductive type region, and the insulating layer exposed under the opening of the second conductive type semiconductor layer is etched. The manufacturing method of the solar cell removed by this.
  7. 　前記パターン層の両端部には前記第一導電性薄膜が設けられておらず、前記第一導電性薄膜の側面が前記絶縁層により覆われている、請求項６に記載の太陽電池の製造方法。 The method for manufacturing a solar cell according to claim 6, wherein the first conductive thin film is not provided at both ends of the pattern layer, and side surfaces of the first conductive thin film are covered with the insulating layer. .
  8. 　前記第一導電型半導体層上に、パターン層形成領域の両端部に開口を有する第一導電性薄膜を形成する工程；
    　前記第一導電性薄膜および第一導電性薄膜の開口下に露出した第一導電型半導体層上に前記絶縁層を形成する工程；および
    　第二導電型領域に設けられた層をエッチングにより除去して前記半導体基板の第一主面を露出させる工程、
    　を順に実施することにより、前記パターン層が形成される、請求項７に記載の太陽電池の製造方法。     Forming a first conductive thin film having openings at both ends of the pattern layer forming region on the first conductive type semiconductor layer;
    Forming the insulating layer on the first conductive thin film and the first conductive type semiconductor layer exposed under the opening of the first conductive thin film; and removing the layer provided in the second conductive type region by etching. Exposing the first main surface of the semiconductor substrate;
    The manufacturing method of the solar cell according to claim 7, wherein the pattern layer is formed by sequentially performing the steps.
  9. 　半導体基板の第一主面上の全面に、前記第二導電型半導体層および前記第二導電性薄膜を順に形成する工程；および
    　前記第一導電型領域に設けられた前記第二導電型半導体層および前記第二導電性薄膜をエッチングにより除去して、前記絶縁層を露出させる工程、
    　を順に実施することにより、前記第一導電型領域に開口を有するようにパターニングされた第二導電型半導体層および第二導電性薄膜が形成される、請求項６～８のいずれか１項に記載の太陽電池の製造方法。     Forming the second conductive semiconductor layer and the second conductive thin film in order on the entire first main surface of the semiconductor substrate; and the second conductive semiconductor layer provided in the first conductive region. And removing the second conductive thin film by etching to expose the insulating layer,
    9. The second conductive semiconductor layer and the second conductive thin film that are patterned so as to have an opening in the first conductive type region are formed by sequentially performing the steps described above. The manufacturing method of the solar cell of description.
  10. 　前記半導体基板上に前記第一導電型半導体層を形成する前に、第一真性半導体層が形成され；前記パターン層を形成後、前記第二導電型半導体層を形成する前に、第二真性半導体層が形成される、請求項６～９のいずれか１項に記載の太陽電池の製造方法。 A first intrinsic semiconductor layer is formed before forming the first conductive semiconductor layer on the semiconductor substrate; a second intrinsic semiconductor layer is formed after forming the pattern layer and before forming the second conductive semiconductor layer. The method for manufacturing a solar cell according to any one of claims 6 to 9, wherein a semiconductor layer is formed.
  11. 　前記第一導電性薄膜上に第一金属電極が設けられ、前記第二導電性薄膜上に第二金属電極が設けられる、請求項６～１０のいずれか１項に記載の太陽電池の製造方法。 The method for manufacturing a solar cell according to any one of claims 6 to 10, wherein a first metal electrode is provided on the first conductive thin film, and a second metal electrode is provided on the second conductive thin film. .
  12. 　前記第一金属電極および前記第二金属電極の少なくとも一部が電解めっきにより形成される、請求項１１に記載の太陽電池の製造方法。

          The method for manufacturing a solar cell according to claim 11, wherein at least a part of the first metal electrode and the second metal electrode is formed by electrolytic plating.

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