WO2018157279A1 - 导电桥半导体器件及其制备方法 - Google Patents

导电桥半导体器件及其制备方法 Download PDF

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WO2018157279A1
WO2018157279A1 PCT/CN2017/075141 CN2017075141W WO2018157279A1 WO 2018157279 A1 WO2018157279 A1 WO 2018157279A1 CN 2017075141 W CN2017075141 W CN 2017075141W WO 2018157279 A1 WO2018157279 A1 WO 2018157279A1
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barrier layer
conductive bridge
ion barrier
ion
conductive
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PCT/CN2017/075141
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English (en)
French (fr)
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刘琦
赵晓龙
刘森
刘明
吕杭炳
龙世兵
王艳
伍法才
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中国科学院微电子研究所
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Priority to PCT/CN2017/075141 priority Critical patent/WO2018157279A1/zh
Priority to US16/489,266 priority patent/US11223013B2/en
Publication of WO2018157279A1 publication Critical patent/WO2018157279A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
    • H10N70/245—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies the species being metal cations, e.g. programmable metallization cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/041—Modification of switching materials after formation, e.g. doping
    • H10N70/043—Modification of switching materials after formation, e.g. doping by implantation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/828—Current flow limiting means within the switching material region, e.g. constrictions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx

Definitions

  • the present invention relates to the field of microelectronics memory technology, and more particularly to a conductive bridge semiconductor device and a method of fabricating the same.
  • FLASH storage technology is facing a series of bottlenecks, such as floating gates can not be unrestricted thinning with the development of technology, data retention time is limited, operating voltage is too large and so on.
  • resistive memory has become the research focus of the new non-volatile memory due to its low operating power consumption, good endurance, simple structure and small device area.
  • the device based on the conductive bridge can be applied to the resistive memory after the external bias is removed, and the non-volatile device can be applied to the resistive memory; after the bias is removed, the conductive path cannot be maintained, and the volatile device can be applied.
  • a selector in the resistive memory cross array to eliminate read and write crosstalk caused by leakage channels in the cross array greatly impairs the memory characteristics of the conductive bridge resistive memory, that is, the retention characteristics of the resistive state, and is not conducive to the low power consumption characteristics of the device under low current limit.
  • the read operation in the array has a problem of crosstalk, resulting in erroneous reading of the stored information.
  • the most common solution to the problem of crosstalk is the choice of a resistor integrated with a resistive memory, including a transistor with a RRAM (1T1R) structure, a unidirectional diode, a RRAM (1D1R), and a bidirectional selector, a RRAM (1S1R). )structure.
  • the area of the memory cell in the 1T1R structure mainly depends on the area of the transistor, and it cannot take advantage of the excellent shrinkability of the RRAM; the diode in the 1T1R structure usually has only one-way conduction characteristics; the selector in the 1S1R structure is divided into two types, one type It is an electronic type selector that is dominated by electronic conduction. This type of selector usually has a slowly changing electrical characteristic, a small selection ratio, and cannot provide a high operating current to the resistive memory. The other is a conductive bridge selector dominated by an active metal conductive bridge. This type of selector is based on the fragile retention characteristics of the conductive bridge, and typically has abrupt electrical characteristics and a high selectivity ratio. However, when the type selector operates at a large operating current, the conductive bridge maintains a characteristic change, is not easily broken, becomes a non-volatile storage characteristic, and cannot perform gate strobing of the device.
  • the present invention provides a conductive bridge semiconductor device and a method of fabricating the same to at least partially solve the above-mentioned technical problems.
  • a conductive bridge semiconductor device includes a lower electrode, a resistive functional layer, an ion barrier layer and an active upper electrode from bottom to top, wherein the ion barrier layer is provided with a hole through which the active conductive ions pass.
  • the conductive bridge device of the present invention is a conductive bridge resistive memory, and the number of holes in the ion barrier layer is one, and the radial width of the hole is between 5 nm and 200 nm.
  • the hole is located at a central position of the ion barrier layer.
  • the ion barrier layer is prepared by using a graphene material, and the radial width of the holes is between 5 nm and 100 nm.
  • the conductive bridge device of the present invention is a conductive bridge selector, the number of holes on the ion barrier layer is greater than or equal to one, and the radial width of the holes is less than 5 nm.
  • the holes are randomly distributed on the ion barrier layer, and the areal density is between 10 7 /cm 2 and 10 14 /cm 2 .
  • the ion barrier layer is prepared using a graphene material, and the areal density of the holes is n ⁇ 10 10 /cm 2 , and n is a positive integer.
  • the shape of the hole is a rectangle, an ellipse, a triangle or a hexagon.
  • the lower electrode is a layered structure prepared by one or more of the following materials: one or more materials of TaN, TiN, W, Al, Ru, Ti and Pt
  • the thickness of the resistive functional layer is one or more of the following materials: TaO x , MgO, HfO 2 , Al 2 O 3 , TiO 2 , SiO 2 and ZrO 2 , the thickness of which is between 3 nm and 100 nm
  • the ion barrier layer is a layered structure prepared by one or more of the following materials: Ta, TaN, TiN, TiW, single or multi-layer graphene, thickness thereof
  • the active upper electrode is a single-element electrode such as Ag, Cu, Ni or an alloy electrode containing at least one of the elements, and has a thickness of between 10 nm and 200 nm.
  • the preparation method comprises: sequentially forming a lower electrode, a resistive functional layer and an ion barrier layer; processing a hole on the ion barrier layer; and preparing an active upper electrode on the ion barrier layer having the hole.
  • the holes are processed on the ion barrier layer by optical exposure combined with focused ion beam etching.
  • the number of holes on the ion barrier layer is greater than one; the holes are processed on the ion barrier layer by bombarding the ion barrier layer by high energy ions, the holes being randomly on the ion barrier layer
  • the distribution has an areal density of between 10 7 /cm 2 and 10 14 /cm 2 .
  • the high-energy ion for bombardment is obtained by an ion implanter or a particle accelerator, and the energy thereof is higher than 2KeV to 200KeV, the incident angle is between 80° and 100°, and the dose is greater than 10 5 .
  • the material of the ion barrier layer is a graphene material, and the dose of high energy ions for bombardment is between 10 12 and 10 14 .
  • a single nano-scale hole can promote the concentrated distribution of the conductive path, improve the resistance state retention characteristics, and can realize the non-volatile resistance change characteristic under a small operating current, thereby effectively reducing the conductive bridge resistance.
  • the array of holes on the ion barrier layer can promote the discrete distribution of the conductive paths, reduce the retention characteristics of the conductive paths, and realize the volatile resistance characteristics under the large operating current, thereby improving the selection of the conductive bridge.
  • the drive current and selection ratio of the device can promote the discrete distribution of the conductive paths, reduce the retention characteristics of the conductive paths, and realize the volatile resistance characteristics under the large operating current, thereby improving the selection of the conductive bridge.
  • FIG. 1A is a schematic view showing the structure and conduction path regulation of a conductive bridge resistive memory of a single hole in an ion barrier layer according to a first embodiment of the present invention.
  • FIG. 1B is a schematic diagram of a single hole in the ion barrier layer of the conductive bridge resistive memory shown in FIG. 1A.
  • FIG. 2 is a flow chart of fabricating the conductive bridge resistive memory of FIG. 1A in accordance with an embodiment of the present invention.
  • 3 and 4 are characteristic IV curves of a conventional Cu/HfO 2 /Pt device and a Cu/single-hole graphene/HfO 2 /Pt device prepared according to the first embodiment of the present invention at 1 ⁇ A, respectively.
  • 5A is a schematic diagram showing the structure and conduction path regulation of a conductive bridge selector having an array of holes in an ion barrier layer according to a second embodiment of the present invention.
  • Figure 5B is a schematic illustration of an array of holes in the ion barrier layer of the conductive bridge selector of Figure 5A.
  • Figure 6 is a Raman spectrum of graphene after bombardment of unprocessed graphene with a certain conditional ion.
  • Figure 9 is a characteristic IV curve of an Ag/porous graphene/SiO 2 /Pt device with a current limit of 100 ⁇ A after the implantation dose is increased to D3 on the ion barrier layer.
  • Figure 10 is a characteristic IV curve of the Ag/porous graphene/SiO 2 /Pt device at a maximum volatile current limit of 500 ⁇ A after the implantation dose is increased to D3 on the ion barrier layer.
  • Figure 11 is a characteristic IV curve obtained by testing an Ag/porous graphene/SiO 2 /Pt device in series with a Cu/HfO 2 /Pt device through a peripheral circuit.
  • CF-single conductive path CF 1 , CF 2 , CF 3 - multiple conductive paths.
  • the key to the implementation of the low-power conductive bridge resistive memory and the high-current conductive bridge selector function is to regulate the retention characteristics of the conductive bridge. Therefore, it is important to optimize the performance of the resistive memory and the selector based on the conductive bridge by regulating the retention characteristics of the conductive paths.
  • the invention introduces an ion barrier layer containing a hole on the basis of the active upper electrode/resistive functional layer/lower electrode structure to form an active upper electrode/ion barrier layer/resistive functional layer/lower electrode structure with pores, and regulate ions
  • the number, aperture and density of the holes in the barrier layer enable precise regulation of the conductive path of the conductive bridge-based memory and the selector.
  • a conductive bridge resistive memory is provided.
  • 1A is a schematic view showing the structure and conduction path regulation of a conductive bridge resistive memory having a single hole in an ion barrier layer according to a first embodiment of the present invention.
  • FIG. 1B is a schematic diagram of a single hole in the ion barrier layer of the conductive bridge resistive memory shown in FIG. 1A.
  • the conductive bridge resistive memory includes a lower electrode 10, a resistive functional layer 20, an ion barrier layer 30 and an active upper electrode 40 from bottom to top.
  • the ion barrier layer is provided with a single hole 31 through which the active conductive ions pass.
  • the lower electrode 10 it may be prepared using one or more of TaN, TiN, W, Al, Ru, Ti, and Pt.
  • the thickness of the lower electrode 10 is between 10 nm and 200 nm.
  • a layered structure prepared by one or more of the following materials: TaO x , MgO, HfO 2 , Al 2 O 3 , TiO 2 , SiO 2 and ZrO 2 .
  • the thickness of the resistive functional layer 30 is between 3 nm and 100 nm.
  • ion barrier layer 30 a layered structure prepared by one or more of the following materials: Ta, TaN, TiN, TiW, single layer or multilayer graphene, and the like.
  • the ion barrier layer 20 has a thickness of less than 10 nm.
  • the active upper electrode 40 a single-element electrode such as Ag, Cu, Ni or an alloy electrode containing at least one of the elements may be employed.
  • the active upper electrode 40 has a thickness of between 10 nm and 200 nm.
  • the active upper electrode is not limited to the species listed above, and other electrodes capable of generating active conductive ions may be employed.
  • the lower electrode is not limited to the ones listed above, and electrodes made of other conductive materials may be used.
  • the resistive functional layer can be prepared using other materials having resistive properties.
  • the ion barrier layer is not limited to the ones listed above, and it is possible to use a structurally dense film made of other materials.
  • the ion barrier layer 30 there is only one hole 31 in the ion barrier layer 30.
  • the hole 31 is a nanometer-scale (5 nm to 200 nm) hole.
  • the ion barrier layer of a single hole can promote the concentrated distribution of the conductive paths to form a single conductive path (CF), which enhances its resistive state retention characteristics, especially improves Conductive
  • CF conductive path
  • the shape of the hole in the ion barrier layer may be any shape such as a rectangle, a square, a circle, an ellipse, a triangle, or a hexagon, and the radial width of the hole is between 5 nm and 100 nm.
  • the holes are preferably circular in view of the uniformity of current transport in various directions.
  • a single hole in the ion barrier layer is preferably located at the center of the ion barrier layer, as shown in Figure 1A.
  • the single conductive via CF is positioned at the center of the ion barrier layer, which is more advantageous for device design and processing than for the periphery.
  • FIG. 2 is a flow chart of fabricating the conductive bridge resistive memory of FIG. 1A in accordance with an embodiment of the present invention.
  • a method for preparing a conductive bridge resistive memory having a single hole in an ion barrier layer includes:
  • Step S202 forming a lower electrode 10, a resistive functional layer 20 and an ion barrier layer 30 in sequence;
  • Step S204 processing a single hole on the ion barrier layer 30;
  • the method for processing a single hole in the ion barrier layer 30 in this step includes:
  • Sub-step S204a coating a photoresist on the ion barrier layer
  • Sub-step S204b using electron beam or nanoimprint lithography technology to accurately expose a single hole of different diameters on the nanometer scale to form a photoresist pattern
  • Sub-step S204c using the photoresist as an ion barrier layer, directly etching the ion barrier layer by focusing ion beam technology, etching the unmasked ion barrier layer in the hole, thereby forming a single hole on the ion barrier layer;
  • Step S204d removing the photoresist above the ion barrier layer to obtain an ion barrier layer having a single hole, and step S204 is completed.
  • Step S206 the active upper electrode 40 is prepared on the ion barrier layer having a single hole, and thus, the preparation of the conductive bridge resistive memory having a single hole on the ion barrier layer as shown in FIG. 1A is completed.
  • 3 and 4 are characteristic IV curves of a conventional Cu/HfO 2 /Pt device and a Cu/single-hole graphene/HfO 2 /Pt device prepared according to the first embodiment of the present invention at 1 ⁇ A, respectively.
  • graphene has a single pore diameter of between 5 and 100 nm.
  • a conductive bridge selector is also provided.
  • 5A is a schematic diagram showing the structure and conductive path regulation of a conductive bridge selector having an array of holes in an ion barrier layer in accordance with an embodiment of the present invention.
  • Figure 5B is a schematic illustration of an array of holes in the ion barrier layer of the conductive bridge selector of Figure 5A.
  • the present embodiment differs from the previous embodiment in that the ion barrier layer 30' has a plurality of holes (31', 32', 33', etc.) of atomic scale (less than 5 nm). An array of holes is formed.
  • the conductive path can be discretely distributed to form a plurality of conductive paths (CF 1 , CF 2 , CF 3 , etc.), thereby greatly reducing the retention characteristics. Increase the maximum current that the conductive bridge selector can provide, increasing its drive capability and selection ratio.
  • the pores in the ion barrier layer 20 are porous, the pores follow a random distribution on the ion barrier layer with an areal density between 10 7 /cm 2 and 10 14 /cm 2 .
  • This setting is mainly to avoid excessive concentration of conductive channels and improve the response speed of the selector. It is verified by experiments that when the defect density of graphene pores is n ⁇ 10 10 /cm 2 , the device performance reaction speed is faster, and the switching speed is within 1 ⁇ s, where n is a positive integer.
  • the preparation method is similar to the conductive bridge resistive memory having a single hole on the ion barrier layer shown in FIG. 2A, except that the porous barrier layer is fabricated.
  • the method provides the following two specific methods:
  • the energy of the bombarding ions is higher than 2KeV to 200KeV, the incident angle is between 80° and 100°, and the dose is greater than 10 5 .
  • the pore size formed by the ion bombardment method is at the atomic scale, and this type of graphene defect can be characterized by testing Raman spectroscopy.
  • Figure 6 is a Raman spectrum of graphene after bombardment of unprocessed graphene with a certain conditional ion.
  • the G peak is a characteristic peak of the C sp 2 structure, reflecting the symmetry and the degree of crystallization, and the 2D peak is a two-phonon inelastic scattering peak.
  • the D peak, the D' peak and the D+D' peak are Raman peaks associated with graphene defects.
  • the relative ratio between the peaks after particle bombardment changes greatly, and the intensity ratio of the D peak to the G peak can be qualitatively measured by I D /I G .
  • the relationship is as follows: I D /I G ⁇ 1/L 2 D ⁇ .
  • the porous ion barrier layer is mainly used to disperse the conductive path, weaken its retention characteristics, increase the maximum current that the conductive bridge selector can provide, and increase the selection ratio.
  • Figure 7 and Figure 8 are characteristic IV curves of Ag/porous graphene/SiO 2 /Pt devices implanted at a dose of D1, D2 at a maximum volatile current limit of 100 ⁇ A. It can be seen that both doses of Ag/porous graphene/SiO 2 /Pt devices exhibit unipolar characteristics and can therefore be used as unipolar conductive bridge selectors.
  • Figure 9 is a characteristic IV curve of an Ag/porous graphene/SiO 2 /Pt device with a current limit of 100 ⁇ A after the implant dose is increased to D3.
  • the Ag/porous graphene/SiO 2 /Pt device changes from unipolar to bipolar as the implant dose is increased to D3.
  • As the implant dose increases more active metal ions enter the resistive functional layer to form a conductive channel and accumulate at the lower electrode, which also results in a unipolar to bipolar transition.
  • Figure 10 is a characteristic IV curve of an Ag/porous graphene/SiO 2 /Pt device with a maximum volatile current limit of 500 ⁇ A after the injection dose is increased to D3. It can be seen that the Ag/porous graphene/SiO 2 /Pt device still maintains the two-way volatile property at a higher current limit of 500 ⁇ A.
  • the porous ion barrier layer can indeed disperse the conductive path, weaken its retention characteristics, increase the maximum current that the conductive bridge selector can provide, and increase the selection ratio, Ag/porous graphite.
  • the olefin/SiO 2 /Pt device has a maximum volatile current limit of 500 ⁇ A at a dose of D3 and a selectivity ratio of 5 ⁇ 10 8 .
  • Figure 11 is a characteristic IV curve obtained by testing an Ag/porous graphene/SiO 2 /Pt device in series with a Cu/HfO 2 /Pt device through a peripheral circuit.
  • the characteristic IV curve shows that the Ag/porous graphene/SiO 2 /Pt selector has a good selection effect and the selection ratio reaches 10 8 .
  • the lower electrode may also be in the form of a conductive oxide such as ITO;
  • the resistive functional layer can be replaced by a novel two-dimensional material such as BN, MoS x , graphene oxide or the like.
  • the present invention provides a conductive bridge semiconductor device based on an active upper electrode/hole-containing ion barrier layer/resistive functional layer/lower electrode structure, by adjusting the diameter, number and density of holes in the ion barrier layer, Achieve regulation of the size and number of conductive paths of conductive bridge-based memories and selectors:
  • Processing a single nanometer-scale hole in the ion barrier layer can promote the concentrated distribution of the conductive path, improve the resistance state retention characteristic, and realize the nonvolatile resistance change characteristic under a small operating current, thereby effectively reducing the conductive bridge resistance.
  • Processing a plurality of atomic-scale holes in the ion barrier layer can promote the discrete distribution of the conductive paths, reduce the retention characteristics of the conductive paths, and realize the volatile resistance characteristics under a large operating current, thereby improving the conductive bridge selector. Drive current and selection ratio.
  • the conductive bridge semiconductor device and the preparation method thereof have the advantages of high performance, easy integration, low cost, and the like, and have good application prospects.

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Abstract

一种导电桥半导体器件及其制备方法。导电桥半导体器件自下而上包括：下电极（10）、阻变功能层（20）、离子阻挡层（30）和活性上电极（40），其中，离子阻挡层（30）上开设有供活性导电离子通过的孔洞（31）。基于此结构可以制备导电桥阻变存储器以及导电桥选择器，通过调控离子阻挡层孔洞的数量、直径及密度，实现对基于导电桥的存储器与选择器的导电通路的精确调控。

Description

导电桥半导体器件及其制备方法 技术领域
本发明涉及微电子行业存储器技术领域，尤其涉及一种导电桥半导体器件及其制备方法。
背景技术
随着微电子及半导体技术的不断革新，FLASH存储技术正面临一系列的瓶颈问题，如浮栅不可能随技术发展而无限制减薄，数据保持时间有限，操作电压过大等问题。诸多新型存储器中，阻变存储器由于具备较低操作功耗、耐久力(Endurance)好、结构简单、器件面积小等优点而逐渐成为目前新型非易失性存储器中的研究重点。基于导电桥的器件，外加偏压去除后，导电通路依然保持，则该非易失性器件可应用于阻变存储器；外加偏压去除后，导电通路不能保持，则该易失性器件可应用于阻变存储器交叉阵列中的选择器，用以消除交叉阵列中漏电通道引起的读写串扰问题。然而，非易失性阻变存储器导电通路的随机形成，极大的削弱了导电桥阻变存储器的记忆特性，即阻态的保持特性，更不利于实现低限流下器件的低功耗特性。
同时，基于交叉阵列架构的阻变存储器，在阵列中的读取操作存在交叉串扰的问题，导致所存储信息的错误读取。对于如何解决交叉串扰问题，最常见的是选择器与阻变存储器集成的解决方案，包括一个晶体管一个RRAM(1T1R)结构，一个单向二极管一个RRAM(1D1R)和一个双向选择器一个RRAM(1S1R)结构。1T1R结构中存储器单元面积主要取决于晶体管的面积，无法发挥RRAM优良的可缩小性优势；1T1R结构中二极管通常仅有单向导通的特性；1S1R结构中的选择器分为两种类型，一种是以电子导电为主导的电子型选择器，该类型选择器通常具有缓变的电学特性，较小的选择比，并且不能给阻变存储器提供较高的操作电流。另外一种是以活性金属导电桥为主导的导电桥选择器，该类型选择器基于导电桥脆弱的保持特性，通常具有突变的电学特性，较高的选择比。然而，该类型选择器在较大操作电流运行时，导电桥保持特性发生变化，不易断裂，变为非挥发的存储特性，无法实现器件的选通。
发明内容
(一)要解决的技术问题
本发明提供了一种导电桥半导体器件及其制备方法，以至少部分解决以上所提出的技术问题。
(二)技术方案
根据本发明的一个方面，提供了一种导电桥半导体器件。该导电桥半导体器件自下而上包括：下电极、阻变功能层、离子阻挡层和活性上电极，其中，离子阻挡层上开设有供活性导电离子通过的孔洞。
优选地，本发明导电桥器件为导电桥阻变存储器，离子阻挡层上的孔洞为1个，该孔洞的径向宽度介于5nm～200nm之间。
优选地，本发明导电桥器件中，孔洞位于离子阻挡层的中央位置。
优选地，本发明导电桥器件中，离子阻挡层采用石墨烯材料制备，孔洞的径向宽度介于5nm～100nm之间。
优选地，本发明导电桥器件为导电桥选择器，离子阻挡层上的孔洞的数量大于或等于1个，孔洞的径向宽度小于5nm。
优选地，本发明导电桥器件中，孔洞在离子阻挡层上随机分布，其面密度介于107/cm2～1014/cm2之间。
优选地，本发明导电桥器件中，离子阻挡层采用石墨烯材料制备，孔洞的面密度为n×1010/cm2，n为正整数。
优选地，本发明导电桥器件中，孔洞的形状为长方形、椭圆形、三角形或六边形。
优选地，本发明导电桥器件中，下电极为以下材料其中的一种或多种制备的层状结构：TaN、TiN、W、Al、Ru、Ti与Pt中的一种或多种材料制备，其厚度介于10nm～200nm之间；阻变功能层为以下材料其中的一种或多种制备的层状结构：TaOx、MgO、HfO2、Al2O3、TiO2、SiO2与ZrO2，其厚度介于3nm～100nm之间；离子阻挡层为以下材料其中的一种或多种制备的层状结构：Ta、TaN、TiN、TiW、单层或多层石墨烯，其厚度小于10nm；活性上电极采用Ag，Cu，Ni等单元素电极或者包含至少其中一种元素的合金电极，其厚度介于10nm～200nm之间。
根据本发明的另一个方面，还提供了一种如上述导电桥器件的制备方 法。该制备方法包括：依次形成下电极、阻变功能层和离子阻挡层；在离子阻挡层上加工孔洞；以及在具有孔洞的离子阻挡层上制备活性上电极。
优选地，本发明导电桥器件的制备方法中，用光学曝光结合聚焦离子束刻蚀的方式在离子阻挡层上加工孔洞。
优选地，本发明导电桥器件的制备方法中，离子阻挡层上的孔洞的数量大于1个；通过高能离子轰击离子阻挡层来在离子阻挡层上加工孔洞，所述孔洞在离子阻挡层上随机分布，其面密度介于107/cm2～1014/cm2之间。
优选地，本发明导电桥器件的制备方法中，用于轰击的高能离子由离子注入机或粒子加速器获得，其能量高于2KeV～200KeV，入射角度介于80°～100°之间，剂量大于105。
优选地，本发明导电桥器件的制备方法中，离子阻挡层的材料为石墨烯材料，用于轰击的高能离子的剂量介于1012～1014之间。
(三)有益效果
从上述技术方案可以看出，本发明导电桥半导体器件及其制备方法至少具有以下有益效果其中之一：
(1)通过引入含孔洞的离子阻挡层，提供了一种新颖的包括活性上电极/具有孔洞的离子阻挡层/阻变功能层/下电极的导电桥半导体器件结构；
(2)通过调控离子阻挡层孔洞的数量、直径及密度，实现对基于导电桥的存储器与选择器的导电通路的精确调控；
(3)对于导电桥阻变存储器，单个纳米级孔洞可促使导电通路集中分布，提高阻态保持特性，在较小的操作电流下仍能实现非易失阻变特性，从而有效降低导电桥阻变存储器的功耗；
(4)对于导电桥选择器，离子阻挡层上的孔洞阵列可促使导电通路离散分布，降低导电通路保持特性，在大的工作电流下仍能实现易失性阻变特性，从而提高导电桥选择器的驱动电流和选择比。
附图说明
图1A为根据本发明第一实施例离子阻挡层上单个孔洞的导电桥阻变存储器的结构和导电通路调控的示意图。
图1B为图1A所示导电桥阻变存储器中离子阻挡层上单个孔洞的示意图。
图2为根据本发明实施例制备图1A所示导电桥阻变存储器的流程图。
图3和图4分别为传统的Cu/HfO2/Pt器件与根据本发明第一实施例制备的Cu/单孔石墨烯/HfO2/Pt器件在1μA时的特征I-V曲线。
图5A为根据本发明第二实施例离子阻挡层上有孔洞阵列的导电桥选择器的结构和导电通路调控的示意图。
图5B为图5A所示导电桥选择器中离子阻挡层上孔洞阵列的示意图。
图6为未加工石墨烯与某一条件离子轰击后的石墨烯的拉曼光谱图。
图7和图8分别为在离子阻挡层上形成多孔时注入剂量为D1，D2的Ag/多孔石墨烯/SiO2/Pt器件在最大易失性限流100μA时的特征I-V曲线。
图9为在离子阻挡层上形成多孔时注入剂量增加到D3后Ag/多孔石墨烯/SiO2/Pt器件在限流100μA时的特征I-V曲线。
图10为在离子阻挡层上形成多孔时注入剂量增加到D3后Ag/多孔石墨烯/SiO2/Pt器件在最大易失性限流500μA时的特征I-V曲线。
图11为将Ag/多孔石墨烯/SiO2/Pt器件与Cu/HfO2/Pt器件通过***电路串联后测试得到的特征I-V曲线。
【附图中本发明实施例主要元件符号说明】
10-下电极；
20-阻变功能层；
40-活性上电极；
30-具有单个孔洞的离子阻挡层；31-单个孔洞；
30′-具有孔洞阵列的离子阻挡层；31′、32′、33′-孔洞；
CF-单根导电通路；CF1、CF2、CF3-多根导电通路。
具体实施方式
低功耗的导电桥阻变存储器与高电流的导电桥选择器功能的实现关键在于调控导电桥的保持特性。因此，通过调控导电通路的保持特性来优化基于导电桥的阻变存储器与选择器的性能就显得十分重要。
本发明在活性上电极/阻变功能层/下电极结构基础上，引入含孔洞的离子阻挡层，形成活性上电极/具有孔洞的离子阻挡层/阻变功能层/下电极结构，通过调控离子阻挡层上孔洞的数量，孔径及密度，实现对基于导电桥的存储器与选择器的导电通路的精确调控。
为使本发明的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本发明进一步详细说明。
在本发明的第一个示例性实施例中，提供了一种导电桥阻变存储器。图1A为根据本发明第一实施例离子阻挡层上有单个孔洞的导电桥阻变存储器的结构和导电通路调控的示意图。图1B为图1A所示导电桥阻变存储器中离子阻挡层上单个孔洞的示意图。如图1A和图1B所示，该导电桥阻变存储器自下而上包括：下电极10、阻变功能层20、离子阻挡层30和活性上电极40。其中，离子阻挡层上开设有供活性导电离子通过的单个孔洞31。
以下分别对本实施例导电桥阻变存储器的各个部分进行详细描述。
关于下电极10，可采用TaN、TiN、W、Al、Ru、Ti与Pt中的一种或多种材料制备。该下电极10的厚度介于10nm～200nm之间。
关于阻变功能层20，为以下材料其中的一种或多种制备的层状结构：TaOx、MgO、HfO2、Al2O3、TiO2、SiO2与ZrO2。该阻变功能层30的厚度介于3nm～100nm之间。
关于离子阻挡层30，为以下材料其中的一种或多种制备的层状结构：Ta、TaN、TiN、TiW、单层或多层石墨烯等。该离子阻挡层20的厚度小于10nm。
关于活性上电极40，可采用Ag，Cu，Ni等单元素电极或者至少包含其中一种元素的合金电极。该活性上电极40的厚度介于10nm～200nm之间。
本领域技术人员应当清楚，活性上电极并不局限于以上列出的种类，其还可以采用其他能够产生活性导电离子的电极。同样，下电极也并不局限于以上列出的种类，其可以采用其他导电材料制成的电极。同样，阻变功能层还可以采用其他具有阻变性质的材料制备。同样，离子阻挡层也并不局限于以上列出的种类，其可以采用其他材料制成的结构致密的薄膜。
本实施例中，离子阻挡层30上仅有一个孔洞31。该孔洞31为纳米尺度(5nm～200nm)的孔洞。对于图1A所示的导电桥阻变存储器而言，单个孔洞的离子阻挡层可促使导电通路集中分布，形成单根导电通路(Conductive filament，简称CF)，增强其阻态保持特性，特别是提高导电 桥阻变存储器低限流下的阻态保持特性，有利于实现器件稳定地低功耗操作。
关于离子阻挡层上孔洞的形状，可以是长方形、正方形、圆形、椭圆形、三角形、六边形等各个形状，孔洞的径向宽度介于5nm～100nm之间。优选地，考虑到电流在各个方向上传输的均匀性，孔洞优选为圆形。
本实施例中，离子阻挡层上的单个孔洞优选的位于离子阻挡层中央的位置，如图1A所示。在这种情况下，单根导电通路CF定位于离子阻挡层中央，相比于设置在***，这样的设置方式更有利于器件的设计与加工。
图2为根据本发明实施例制备图1A所示导电桥阻变存储器的流程图。请参照图1A和图2所示，离子阻挡层上具有单个孔洞的导电桥阻变存储器的制备方法包括：
步骤S202，依次形成下电极10、阻变功能层20和离子阻挡层30；
步骤S204，在离子阻挡层30上加工单个孔洞；
本步骤在离子阻挡层30上加工单个孔洞的方法包括：
子步骤S204a，在离子阻挡层上涂覆光刻胶；
子步骤S204b，采用电子束或者纳米压印光刻技术精确曝光不同直径纳米尺度的单个孔洞，形成光刻胶图案；
子步骤S204c，以光刻胶为离子阻挡层掩蔽层，以聚焦离子束技术直接定位刻蚀离子阻挡层，刻蚀孔内未被掩蔽的离子阻挡层，从而在离子阻挡层上形成单个孔洞；
子步骤S204d，去除离子阻挡层上方的光刻胶，得到具有单个孔洞的离子阻挡层，至此步骤S204完成。
步骤S206，在具有单个孔洞的离子阻挡层上制备活性上电极40，至此，完成如图1A所示的离子阻挡层上具有单个孔洞的导电桥阻变存储器的制备。
为突出单个孔洞的离子阻挡层对导电桥阻变存储器性能的影响，对传统阻变存储器与根据本发明实施例制备的导电桥阻变存储器进行了性能测试。
图3和图4分别为传统的Cu/HfO2/Pt器件与根据本发明第一实施例制备的Cu/单孔石墨烯/HfO2/Pt器件在1μA时的特征I-V曲线。在Cu/单孔 石墨烯/HfO2/Pt器件中，石墨烯单孔直径介于5～100nm之间。
由图3和图4可知，没有石墨烯阻挡层的Cu/HfO2/Pt器件在1μA限流下表现出易失性特点，而Cu/单孔石墨烯/HfO2/Pt器件在该限流下表现出非易失性的特点。
在本发明的另一个示例性实施例中，还提供了一种导电桥选择器。图5A为根据本发明实施例离子阻挡层上有孔洞阵列的导电桥选择器的结构和导电通路调控的示意图。图5B为图5A所示导电桥选择器中离子阻挡层上孔洞阵列的示意图。如图5A和图5B所示，本实施例与上一实施例的区别在于：离子阻挡层30′上具有多个原子尺度(小于5nm)的孔洞(31′、32′、33′等)，形成孔洞阵列。
如图5A所示，对于形成孔洞阵列的离子阻挡层而言，其可促使导电通路离散分布，形成多根导电通路(CF1、CF2、CF3等)，从而极大削弱其保持特性，提高导电桥选择器所能提供的最大电流，提高其驱动能力和选择比。
优选地，如果离子阻挡层20上的孔洞为多孔，则该多孔在离子阻挡层上遵循随机分布，其面密度介于107/cm2～1014/cm2之间。如此设置主要是避免导电通道过于集中，提高选择器反应速度。经过实验验证，石墨烯孔洞缺陷密度在n×1010/cm2时，器件性能反应速度较快，开关速度在1μs以内，其中n为正整数。
对于离子阻挡层上有多个孔洞的导电桥选择器而言，其制备方法与图2A所示的离子阻挡层上有单个孔洞的导电桥阻变存储器类似，区别在于离子阻挡层上多孔的制作方法，提供以下两种具体方法：
(1)采用类似子步骤S204a～S204dd的光刻曝光+离子束刻蚀的方法在离子阻挡层上形成多个孔洞组成的阵列；
(2)由离子注入机或粒子加速器加速的高能离子直接轰击离子阻挡层，通过控制轰击能量与剂量，形成直径及密度可调控的多孔离子阻挡层。在一定的范围内，孔洞的孔径大小主要由轰击离子的能量与入射角度决定，而孔洞的密度主要由轰击离子的剂量决定。
优选地，离子轰击过程中，轰击离子的能量高于2KeV～200KeV，入射角度介于80°～100°之间，剂量大于105。
离子轰击的方法所形成的孔洞孔径在原子尺度，可通过测试拉曼光谱对这种类型的石墨烯缺陷进行表征。
图6为未加工石墨烯与某一条件离子轰击后的石墨烯的拉曼光谱图。图6中，G峰为C sp2结构的特征峰，反映对称性和结晶程度，2D峰为双声子非弹性散射峰。D峰，D’峰及D+D’峰为与石墨烯缺陷相关的拉曼峰。较图6中的(a)图和(b)图可知，经粒子轰击后，各个峰之间的相对比发生较大的变化，可用D峰与G峰的强度比ID/IG来定性衡量缺陷的平均距离LD与缺陷密度σ。其相互关系如下：ID/IG∝1/L2 D∝σ。多孔离子阻挡层主要用于分散导电通路，削弱其保持特性，提高导电桥选择器所能提供的最大电流，提高选择比。
为突出多孔离子阻挡层对导电桥选择器性能的影响，我们制备了Ag/多孔石墨烯/SiO2/Pt器件。使用离子注入机，以Si为轰击离子源，注入能量10KeV，注入剂量D1，D2和D3(D1＜D2＜D3)，其中D1＝1012；D2＝5×1012，D3＝1013，从而得到了三种具有不同石墨烯孔洞密度的Ag/多孔石墨烯/SiO2/Pt器件。
图7和图8分别为注入剂量为D1，D2的Ag/多孔石墨烯/SiO2/Pt器件在最大易失性限流100μA时的特征I-V曲线。可以看出，两个剂量的Ag/多孔石墨烯/SiO2/Pt器件都表现出单极性的特点，因此可用作单极性的导电桥选择器。
图9为注入剂量增加到D3后Ag/多孔石墨烯/SiO2/Pt器件在限流100μA时的特征I-V曲线。如图9所示，随着注入剂量增加到D3，Ag/多孔石墨烯/SiO2/Pt器件由单极性转变为双极性。随着注入剂量增加，更多的活性金属离子进入阻变功能层形成导电通道并在下电极积累，这也导致了单极性到双极性的转变。
图10为注入剂量增加到D3后Ag/多孔石墨烯/SiO2/Pt器件在最大易失性限流500μA时的特征I-V曲线。可见，在更高限流500μA时，该Ag/多孔石墨烯/SiO2/Pt器件依然保持着双向易失性特点。
由此可知，如图5B所示导电桥选择器中，多孔离子阻挡层的确可以分散导电通路，削弱其保持特性，提高导电桥选择器所能提供的最大电流，提高选择比，Ag/多孔石墨烯/SiO2/Pt器件在D3的剂量下最大易失性限流 达到500μA，选择比达到了5×108。
进一步地，为检测本实施例Ag/多孔石墨烯/SiO2/Pt导电桥选择器的效果，我们将Ag/多孔石墨烯/SiO2/Pt器件与Cu/HfO2/Pt器件通过***电路串联。
图11为将Ag/多孔石墨烯/SiO2/Pt器件与Cu/HfO2/Pt器件通过***电路串联后测试得到的特征I-V曲线。该特征I-V曲线显示，Ag/多孔石墨烯/SiO2/Pt选择器具有很好的选择效果，并且选择比达到108。
为了达到简要说明的目的，上述第一实施例中任何可作相同应用的技术特征叙述皆并于此，无需再重复相同叙述。
至此，本发明第二实施例导电桥选择器介绍完毕。
本领域技术人员应当清楚，除了导电桥阻变存储器和导电桥选择器之外，其他应用导电桥原理的半导体器件仍然适用本发明，此处不再赘述。
还需要说明的是，在附图或说明书正文中，未绘示或描述的实现方式，均为所属技术领域中普通技术人员所知的形式，并未进行详细说明。此外，上述对各元件和方法的定义并不仅限于实施例中提到的各种具体结构、形状、尺寸或方式，本领域普通技术人员可对其进行简单地更改或替换，例如：
(1)下电极还可以是ITO等导电氧化物的形式；
(2)阻变功能层可以用新型二维材料如BN、MoSx、氧化石墨烯等来代替。
至此，已经结合附图对本发明实施例进行了详细描述。依据以上描述，本领域技术人员应当对本发明导电桥半导体器件及其制备方法有了清楚的认识。
综上所述，本发明提供了中基于活性上电极/具有孔洞的离子阻挡层/阻变功能层/下电极结构的导电桥半导体器件，通过调控离子阻挡层中孔洞的直径，数量及密度，实现对基于导电桥的存储器与选择器的导电通路尺寸和数量的调控：
(1)对离子阻挡层加工单个纳米尺度的孔洞，可促使导电通路集中分布，提高阻态保持特性，在较小的操作电流下仍能实现非易失阻变特性，从而有效降低导电桥阻变存储器的功耗；
(2)对离子阻挡层加工多个原子尺度的孔洞，可促使导电通路离散分布，降低导电通路保持特性，在大的工作电流下仍能实现易失性阻变特性，从而提高导电桥选择器的驱动电流和选择比。
本发明的导电桥半导体器件及其制备方法具有高性能，易集成，低成本等优点，具有较好的推广应用前景。
还需要说明的是，本文可提供包含特定值的参数的示范，但这些参数无需确切等于相应的值，而是可在可接受的误差容限或设计约束内近似于相应值。实施例中提到的方向用语，例如“上”、“下”、“前”、“后”、“左”、“右”等，仅是参考附图的方向，并非用来限制本发明的保护范围。此外，除非特别描述或必须依序发生的步骤，上述步骤的顺序并无限制于以上所列，且可根据所需设计而变化或重新安排。并且上述实施例可基于设计及可靠度的考虑，彼此混合搭配使用或与其他实施例混合搭配使用，即不同实施例中的技术特征可以自由组合形成更多的实施例。
应注意，贯穿附图，相同的元素由相同或相近的附图标记来表示。在以下描述中，一些具体实施例仅用于描述目的，而不应该理解为对本发明有任何限制，而只是本发明实施例的示例。在可能导致对本发明的理解造成混淆时，将省略常规结构或构造。应注意，图中各部件的形状和尺寸不反映真实大小和比例，而仅示意本发明实施例的内容。
以上所述的具体实施例，对本发明的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本发明的具体实施例而已，并不用于限制本发明，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (14)

  1. 一种导电桥半导体器件，其特征在于，自下而上包括：下电极、阻变功能层、离子阻挡层和活性上电极，其中，所述离子阻挡层上开设有供活性导电离子通过的孔洞。
  2. 根据权利要求1所述的导电桥器件，其特征在于，该导电桥器件为导电桥阻变存储器，所述离子阻挡层上的孔洞为1个，该孔洞的径向宽度介于5nm～200nm之间。
  3. 根据权利要求2所述的导电桥器件，其特征在于，所述孔洞位于离子阻挡层的中央位置。
  4. 根据权利要求2所述的导电桥器件，其特征在于，所述离子阻挡层采用石墨烯材料制备，所述孔洞的径向宽度介于5nm～100nm之间。
  5. 根据权利要求1所述的导电桥器件，其特征在于，该导电桥器件为导电桥选择器，所述离子阻挡层上的孔洞的数量大于1个，所述孔洞的径向宽度小于5nm。
  6. 根据权利要求5所述的导电桥器件，其特征在于，所述孔洞在离子阻挡层上随机分布，其面密度介于107/cm2～1014/cm2之间。
  7. 根据权利要求6所述的导电桥器件，其特征在于，所述离子阻挡层采用石墨烯材料制备，所述孔洞的面密度为n×1010/cm2，n为正整数。
  8. 根据权利要求1至7中任一项所述的导电桥半导体器件，其特征在于，所述孔洞的形状为长方形、椭圆形、三角形或六边形。
  9. 根据权利要求1至7中任一项所述的导电桥半导体器件，其特征在于：
    所述下电极为以下材料其中的一种或多种制备的层状结构：TaN、TiN、W、Al、Ru、Ti与Pt中的一种或多种材料制备，其厚度介于10nm～200nm之间；
    所述阻变功能层为以下材料其中的一种或多种制备的层状结构：TaOx、MgO、HfO2、Al2O3、TiO2、SiO2与ZrO2，其厚度介于3nm～100nm之间；
    所述离子阻挡层为以下材料其中的一种或多种制备的层状结构：Ta、TaN、TiN、TiW、单层或多层石墨烯，其厚度小于10nm；
    所述活性上电极采用Ag，Cu，Ni等单元素电极或者包含至少其中一 种元素的合金电极，其厚度介于10nm～200nm之间。
  10. 一种如权利要求1所述导电桥器件的制备方法，其特征在于，包括：
    依次形成所述下电极、阻变功能层和离子阻挡层；
    在所述离子阻挡层上加工孔洞；以及
    在具有孔洞的离子阻挡层上制备活性上电极。
  11. 根据权利要求10所述的制备方法，其特征在于，用光学曝光结合聚焦离子束刻蚀的方式在离子阻挡层上加工孔洞。
  12. 根据权利要求10所述的制备方法，其特征在于：
    所述离子阻挡层上的孔洞的数量大于1个；
    通过高能离子轰击离子阻挡层来在离子阻挡层上加工孔洞，所述孔洞在离子阻挡层上随机分布，其面密度介于107/cm2～1014/cm2之间。
  13. 根据权利要求12所述的制备方法，其特征在于，用于轰击的高能离子由离子注入机或粒子加速器获得，其能量高于2KeV～200KeV，入射角度介于80°～100°之间，剂量大于105。
  14. 根据权利要求13所述的制备方法，其特征在于，所述离子阻挡层的材料为石墨烯材料，用于轰击的高能离子的剂量介于1012～1014之间。
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