WO2018149139A1 - 薄膜晶体管及其制作方法、显示基板及显示装置 - Google Patents

薄膜晶体管及其制作方法、显示基板及显示装置 Download PDF

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WO2018149139A1
WO2018149139A1 PCT/CN2017/103381 CN2017103381W WO2018149139A1 WO 2018149139 A1 WO2018149139 A1 WO 2018149139A1 CN 2017103381 W CN2017103381 W CN 2017103381W WO 2018149139 A1 WO2018149139 A1 WO 2018149139A1
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conductive pattern
film transistor
thin film
region
active layer
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PCT/CN2017/103381
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English (en)
French (fr)
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包智颖
王世君
白璐
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京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Priority to US15/777,339 priority Critical patent/US20200313004A1/en
Publication of WO2018149139A1 publication Critical patent/WO2018149139A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0002—Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio

Definitions

  • the accuracy of the array substrate exposure apparatus used in the low-generation line is generally low, so that the TFT (thin film transistor) channel length L is relatively long and cannot be further shortened. Since the on-state current of the thin film transistor is proportional to the channel width-to-length ratio W/L of the TFT, the on-state current of the thin film transistor is relatively small. As the PPI (Pixel Density) of high-end display products is getting higher and higher, in order to meet the charging rate requirement of display products, it is necessary to increase the on-state current of the thin film transistor. Therefore, it is necessary to design the channel width of the thin film transistor to be relatively large, which is serious. The aperture ratio of the display substrate is affected, and the load on the display substrate is also relatively large, resulting in a significant increase in power consumption of the display device.
  • the technical problem to be solved by the present disclosure is to provide a thin film transistor, a method for fabricating the same, a display substrate, and a display device, which can improve the on-state current of the thin film transistor, so that the channel width of the thin film transistor can be designed to be relatively small.
  • a thin film transistor including a source electrode, a drain electrode, and an active layer formed on a substrate, wherein the active layer includes a source electrode contact region for contacting the source electrode, a drain electrode contact region contacting the drain electrode and a channel region between the source electrode contact region and the drain electrode contact region; and a first conductive pattern distributed in a channel region of the active layer and Channel region contact.
  • the thin film transistor further includes: a second conductive pattern contacting the source electrode contact region of the active layer and spaced apart from the first conductive pattern; and/or a leakage current from the active layer a third conductive pattern that is contacted by the pole contact region and spaced apart from the first conductive pattern.
  • a plurality of the first conductive patterns arranged in an array are distributed in a channel region of the active layer.
  • an extending direction of each of the first conductive patterns is substantially parallel to a first direction from the source electrode to the drain electrode.
  • the length of the first conductive pattern is smaller than a vertical distance between the source electrode and the drain electrode.
  • the length of each of the first conductive patterns is Lx
  • the distance between two adjacent first conductive patterns in the first direction is Ly
  • the ratio of Ly and Lx ranges from 0.3 to 0.7.
  • an extending direction of each of the first conductive patterns is not parallel to a first direction from the source electrode to the drain electrode, and a projection of each of the first conductive patterns in the first direction
  • the length is Lx
  • the projection pitch of the adjacent two first conductive patterns in the first direction in the extending direction of the first conductive pattern is Ly
  • the ratio of Ly and Lx ranges from 0.3 to 0.7.
  • the first conductive pattern, the second conductive pattern, and the third conductive pattern are all metal nanowires.
  • the length of the first conductive pattern is less than 1000 nm.
  • the first conductive pattern has a cross section having a diameter of less than 100 nm.
  • Embodiments of the present disclosure also provide a display substrate including the thin film transistor as described above.
  • Embodiments of the present disclosure also provide a display device including the display substrate as described above.
  • An embodiment of the present disclosure further provides a method of fabricating a thin film transistor, comprising: forming a source electrode, a drain electrode, and an active layer on a substrate, wherein the active layer includes a source electrode for contacting the source electrode a contact region, a drain electrode contact region in contact with the drain electrode, and a channel region between the source electrode contact region and the drain electrode contact region, and forming a first conductive pattern, wherein the first conductive pattern Distributed in the channel region of the active layer and in contact with the channel region.
  • the forming the first conductive pattern comprises: forming the first conductive pattern a photoresist is coated on the substrate; the pattern on the template is transferred onto the photoresist by imprinting to form a photoresist retention region and a photoresist unretained region, and the photoresist unretained region corresponds to the pattern Depositing a conductive layer, the conductive layer comprising a first portion on the photoresist retention region and a second portion in contact with the substrate in the unretained region of the photoresist; and exposing and developing the photoresist a photoresist of the photoresist retention region and the first portion, the second portion remaining to form the first conductive pattern.
  • the manufacturing method further includes: forming a second conductive pattern and/or a third conductive pattern while forming the first conductive pattern, wherein the second conductive pattern and a source electrode of the active layer A contact region is in contact with and spaced apart from the first conductive pattern, the third conductive pattern being in contact with a drain electrode contact region of the active layer and spaced apart from the first conductive pattern.
  • the thin film transistor includes a first conductive pattern in contact with the channel region of the active layer, and the first conductive pattern can increase the electron transport channel of the channel region on the one hand, and increase the electron transport of the channel region on the other hand.
  • Rate which can significantly shorten the channel length of the thin film transistor, greatly improve the on-state current of the thin film transistor, so that the thin film transistor can easily meet the charging rate requirement of the high PPI display product, so that the width design of the channel region of the thin film transistor can be compared. Small, it is beneficial to increase the aperture ratio of the display substrate and reduce the power consumption of the display device.
  • 1 is a schematic view showing a channel region of a conventional thin film transistor
  • FIG. 2 is a schematic diagram of a channel region of a thin film transistor, in accordance with some embodiments of the present disclosure
  • FIG. 4 is a schematic illustration of effective spacing between adjacent two conductive patterns and effective length of a conductive pattern, in accordance with some embodiments of the present disclosure
  • FIG. 5 is a schematic diagram of a channel region of a thin film transistor, in accordance with some embodiments of the present disclosure.
  • FIG. 6 is a schematic illustration of effective spacing between adjacent two conductive patterns and effective length of a conductive pattern, in accordance with some embodiments of the present disclosure
  • FIG. 7-12 are schematic views of forming an active layer of a conductive pattern and a thin film transistor according to an embodiment of the present disclosure.
  • the conventional thin film transistor includes a source electrode 1, a drain electrode 2, and an active layer 3, and the active layer 3 includes a source electrode contact region in contact with the source electrode 1, and a drain electrode contact region in contact with the drain electrode 2. And a channel region between the source electrode contact region and the drain electrode contact region.
  • the larger the aspect ratio W/L0 of the channel region is, the larger the on-state current Ion of the thin film transistor is.
  • the accuracy of the array substrate exposure equipment used in the low-generation line is generally low, so that the TFT channel length L0 is relatively long and cannot be further shortened due to the on-state current of the thin film transistor and the channel width-to-length ratio of the TFT. /L0 is proportional, and therefore, the on-state current of the thin film transistor is relatively small.
  • the embodiment of the present disclosure is directed to the problem that the on-state current of the thin film transistor is relatively small in the related art, and provides a thin film transistor, a manufacturing method thereof, a display substrate, and a display device, which can improve an on-state current of the thin film transistor, thereby enabling a thin film transistor
  • the channel width is designed to be relatively small.
  • the present embodiment provides a thin film transistor, as shown in FIG. 2, comprising a source electrode 1, a drain electrode 2 and an active layer 3 formed on a substrate, the active layer 3 being included for use with the source electrode 1 a source electrode contact region in contact, a drain electrode contact region in contact with the drain electrode 2, and a channel region between the source electrode contact region and the drain electrode contact region, as shown in FIG.
  • the transistor also includes:
  • the first conductive pattern 41 is electrically conductive, on the one hand, the electron transport channel of the channel region can be increased, and on the other hand, the electron mobility of the channel region can be increased, thereby significantly shortening the channel length of the thin film transistor and greatly improving the film.
  • the on-state current of the transistor makes it easy for the thin film transistor to meet the charging rate requirement of the high PPI display product, so that the width of the channel region of the thin film transistor can be designed to be relatively small. It is beneficial to increase the aperture ratio of the display substrate and reduce the power consumption of the display device.
  • the first conductive pattern 41 may be located on the active layer 3 or under the active layer 3 as long as it can be in contact with the channel region of the active layer 3. It is worth noting that each of the first conductive patterns The 41 may be in contact only with a partial region of the channel region such that the first conductive pattern 41 does not conduct the source electrode 1 and the drain electrode 2. For example, the two ends of the first conductive pattern are not located at the source electrode contact region and the drain electrode contact region, respectively.
  • the shape of the first conductive pattern 41 is not limited as long as it has an effective length in the first direction from the source electrode 1 to the drain electrode 2.
  • a plurality of first conductive patterns 41 may be distributed in the channel region of the active layer 3, and a first conductive pattern 41 may be distributed.
  • a plurality of first conductive patterns 41 may be distributed in the channel region of the active layer 3, and the plurality of first conductive patterns 41 are arranged in an array, which can increase in the channel region.
  • the electron transport channel greatly increases the on-state current of the thin film transistor.
  • the length of the channel region that can be shortened by the first conductive pattern 41 is related to the effective length of the first conductive pattern 41 in the first direction.
  • the extending direction of each of the first conductive patterns 41 is from the source electrode 1 to the leakage current.
  • the first direction of the poles 2 is parallel such that the length of the channel region that each of the first conductive patterns 41 can shorten is equal to the length of the first conductive pattern 41.
  • each of the first conductive patterns 41 has a length Lx, a pitch between adjacent first conductive patterns 41 in the first direction is Ly, and n channels are distributed in the first direction in the channel region.
  • a conductive pattern 41, the vertical distance between the source electrode 1 and the drain electrode 2 is L1, where n is an integer greater than or equal to 1.
  • the width-to-length ratio W/L0 of the channel region After the first conductive pattern 41 is set, when calculating the width-to-length ratio W/L0 of the channel region, the parameter L0 can be lowered to L1-n*Lx, and it can be seen that L0 is greatly reduced, and therefore, the width and length of the channel region are The ratio is improved, and the on-state current of the thin film transistor can be greatly improved, so that the thin film transistor can easily meet the charging rate requirement of the high PPI display product. Therefore, the width W of the channel region of the thin film transistor can be designed to be relatively small, and the size of the thin film transistor can be reduced, which is advantageous for increasing the aperture ratio of the display substrate and reducing the power consumption of the display device.
  • the first conductive pattern 41 can adopt a nano-scale metal line, which can effectively increase the electron mobility of the channel region.
  • the diameter of the cross-section of the first conductive pattern 41 can be less than 100 nm, and the length of the first conductive pattern 41 can be less than 1000 nm. .
  • the value of Ly/Lx can be designed to be 0.3-0.7, and when such a parameter is used, the electron mobility of the channel region can be effectively increased.
  • a first conductive pattern 41 distributed at least in a channel region of the active layer 3, the first conductive pattern 41 being in contact with a channel region of the active layer 3;
  • a second conductive pattern 42 in contact with the source electrode contact region of the active layer 3 and spaced apart from the first conductive pattern 41;
  • a third conductive pattern 43 that is in contact with the drain electrode contact region of the active layer 3 and spaced apart from the first conductive pattern 41.
  • the first conductive pattern 41 is electrically conductive, by distributing the first conductive pattern 41 in the region where the active layer 3 is located, on the one hand, the electron transport channel of the channel region can be increased, and on the other hand, the electron transport of the channel region can be increased. Rate, which can significantly shorten the channel length of the thin film transistor, greatly improve the on-state current of the thin film transistor, so that the thin film transistor can easily meet the charging rate requirement of the high PPI display product, so that the width design of the channel region of the thin film transistor can be compared. Small, it is beneficial to increase the aperture ratio of the display substrate and reduce the power consumption of the display device.
  • the second conductive pattern 42 or the third conductive pattern 43 may be disposed, or the second conductive pattern 42 and the third conductive pattern 43 may be simultaneously disposed. In the embodiment shown in FIG. 3, the second conductive pattern 42 and the third conductive pattern 43 are simultaneously provided.
  • the second conductive pattern 42 is electrically conductive
  • the second conductive pattern 42 is disposed in the source electrode contact region such that the second conductive pattern 42 can be formed in parallel with the source electrode contact region, reducing the resistance of the source electrode contact region
  • the conductive pattern 43 is electrically conductive, and therefore, the third conductive pattern 43 is disposed in the drain electrode contact region such that the third conductive pattern 43 can be formed in parallel with the drain electrode contact region, reducing the resistance of the drain electrode contact region.
  • the first conductive pattern 41, the second conductive pattern 42, and the third conductive pattern 43 may all be located on the active layer 3, or may be located under the active layer 3, or partially on the active layer 3, and the other portion. Located under the active layer, as long as it can be in contact with the active layer 3, it is noted that the first conductive pattern 41 is only in contact with a partial region of the channel region, and is adjacent to the second conductive pattern 42 and the third conductive pattern. 43 are spaced apart so that the first conductive pattern 41, the second conductive pattern 42, and the third conductive pattern 43 do not turn on the source electrode 1 and the drain electrode 2.
  • the shapes of the first conductive pattern 41, the second conductive pattern 42, and the third conductive pattern 43 are not limited as long as they have an effective length in the first direction from the source electrode 1 to the drain electrode 2.
  • a plurality of first conductive patterns 41, a plurality of second conductive patterns 42 and a plurality of third conductive patterns 43 may be distributed in the channel region of the active layer 3, and one first conductive pattern 41 and one second may be distributed.
  • a plurality of first conductive patterns 41, a plurality of second conductive patterns 42 and a plurality of third conductive patterns 43 may be distributed in the channel region of the active layer 3, and a plurality of A conductive pattern 41, a plurality of second conductive patterns 42 and a plurality of third conductive patterns 43 are arranged in an array, which can add a plurality of electron transport channels in the channel region, and greatly increase the on-state current of the thin film transistors.
  • the length of the channel region which the first conductive pattern 41 can shorten is related to the effective length of the first conductive pattern 41 in the first direction.
  • each of the first conductive patterns 41 extends in a direction parallel to the first direction from the source electrode 1 to the drain electrode 2, such that the length of the channel region that can be shortened by each of the first conductive patterns 41 is equal to the first conductive pattern. The length of 41.
  • each of the first conductive patterns 41 has a length Lx, a pitch between adjacent first conductive patterns 41 in the first direction is Ly, and a plurality of first portions are distributed in the first direction in the channel region.
  • a conductive pattern 41 the number of intervals between the plurality of first conductive patterns 41 in the first direction is m, and the vertical distance between the source electrode 1 and the drain electrode 2 is L1, after the first conductive pattern 41 is disposed,
  • W/L0 width-to-length ratio
  • the aspect ratio of the channel region is improved, and the on-state current of the thin film transistor can be greatly improved, so that the thin film transistor can easily satisfy the charging rate requirement of the high PPI display product, and thus the width W of the channel region of the thin film transistor can also be designed.
  • the value of Ly/Lx can be designed to be 0.3-0.7, and when such a parameter is used, the electron mobility of the channel region can be effectively increased.
  • the first conductive pattern 41, the second conductive pattern 42, and the third conductive pattern 43 may adopt a nano-scale metal line, which can effectively increase the electron mobility of the channel region, and the first conductive pattern 41 and the second conductive pattern 42.
  • the diameter of the cross section of the third conductive pattern 43 may be less than 100 nm, the first conductive
  • the length of the pattern 41, the second conductive pattern 42, and the third conductive pattern 43 may be less than 1000 nm.
  • the present embodiment provides a thin film transistor, as shown in FIG. 5, including a source electrode 1, a drain electrode 2 and an active layer 3 formed on a substrate, and the active layer 3 includes a source electrode for contacting the source electrode 1. a contact region, a drain electrode contact region in contact with the drain electrode 2, and a channel region between the source electrode contact region and the drain electrode contact region, the thin film transistor further comprising:
  • a first conductive pattern 41 distributed at least in a channel region of the active layer 3, the first conductive pattern 41 being in contact with a channel region of the active layer 3;
  • a second conductive pattern 42 in contact with the source electrode contact region of the active layer 3 and spaced apart from the first conductive pattern 41;
  • a third conductive pattern 43 that is in contact with the drain electrode contact region of the active layer 3 and spaced apart from the first conductive pattern 41.
  • the first conductive pattern 41 is electrically conductive, by distributing the first conductive pattern 41 in the region where the active layer 3 is located, on the one hand, the electron transport channel of the channel region can be increased, and on the other hand, the electron transport of the channel region can be increased. Rate, which can significantly shorten the channel length of the thin film transistor, greatly improve the on-state current of the thin film transistor, so that the thin film transistor can easily meet the charging rate requirement of the high PPI display product, so that the width design of the channel region of the thin film transistor can be compared. Small, it is beneficial to increase the aperture ratio of the display substrate and reduce the power consumption of the display device.
  • the second conductive pattern 42 is electrically conductive
  • the second conductive pattern 42 is disposed in the source electrode contact region such that the second conductive pattern 42 can be formed in parallel with the source electrode contact region, reducing the resistance of the source electrode contact region
  • the conductive pattern 43 is electrically conductive, and therefore, the third conductive pattern 43 is disposed in the drain electrode contact region such that the third conductive pattern 43 can be formed in parallel with the drain electrode contact region, reducing the resistance of the drain electrode contact region.
  • the first conductive pattern 41, the second conductive pattern 42, and the third conductive pattern 43 may all be located on the active layer 3, or may be located under the active layer 3, or partially on the active layer 3, and the other portion. Located under the active layer, as long as it can be in contact with the active layer 3, it is noted that the first conductive pattern 41 is only in contact with a partial region of the channel region, and is adjacent to the second conductive pattern 42 and the third conductive pattern. 43 are spaced apart so that the first conductive pattern 41, the second conductive pattern 42, and the third conductive pattern 43 do not turn on the source electrode 1 and the drain electrode 2.
  • the shapes of the first conductive pattern 41, the second conductive pattern 42, and the third conductive pattern 43 are not limited as long as they have an effective length in the first direction from the source electrode 1 to the drain electrode 2.
  • a plurality of first conductive patterns 41, a plurality of second conductive patterns 42 and a plurality of third conductive patterns 43 may be distributed in the channel region of the active layer 3, and one first conductive pattern 41 and one second may be distributed.
  • a plurality of first conductive patterns 41, a plurality of second conductive patterns 42 and a plurality of third conductive patterns 43 may be distributed in the channel region of the active layer 3, and a plurality of A conductive pattern 41, a plurality of second conductive patterns 42 and a plurality of third conductive patterns 43 are arranged in an array, which can add a plurality of electron transport channels in the channel region, and greatly increase the on-state current of the thin film transistors.
  • the length of the channel region that can be shortened by the first conductive pattern 41 is related to the effective length of the first conductive pattern 41 in the first direction.
  • the extension of each of the first conductive patterns 41 is shown in FIG.
  • the direction is at an angle from the first direction from the source electrode 1 to the drain electrode 2, the angle being less than 90° greater than 0°, and the length of the channel region that each of the first conductive patterns 41 can shorten is equal to the first conductive pattern 41
  • the length of the projection in the first direction is related to the effective length of the first conductive pattern 41 in the first direction.
  • the on-state current of the thin film transistor is greatly improved, so that the thin film transistor can easily meet the charging rate requirement of the high PPI display product, so that the width W of the channel region of the thin film transistor can be designed to be smaller, the size of the thin film transistor can be reduced, and the thin film transistor can be improved.
  • the aperture ratio of the substrate is displayed to reduce the power consumption of the display device.
  • the value of Ly/Lx can be designed to be 0.3-0.7, and when such a parameter is used, the electron mobility of the channel region can be effectively increased.
  • the first conductive pattern 41, the second conductive pattern 42, and the third conductive pattern 43 may adopt a nano-scale metal line, which can effectively increase the electron mobility of the channel region, and the first conductive pattern 41 and the second conductive pattern 42.
  • the diameter of the cross section of the third conductive pattern 43 may be less than 100 nm, and the lengths of the first conductive pattern 41, the second conductive pattern 42, and the third conductive pattern 43 may be less than 1000 nm.
  • This embodiment provides a display substrate including the thin film transistor as described above.
  • the embodiment provides a display device including the display substrate as described above.
  • the display device may be any product or component having a display function, such as a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device further includes a flexible circuit board, a printed circuit board, and a backboard.
  • the embodiment provides a method for fabricating the above thin film transistor, comprising the steps of forming a source electrode, a drain electrode and an active layer on a substrate, the active layer including a source electrode contact for contacting the source electrode a region, a drain electrode contact region in contact with the drain electrode, and a channel region between the source electrode contact region and the drain electrode contact region, the manufacturing method further includes:
  • the first conductive pattern is electrically conductive, by distributing the first conductive pattern in the region where the active layer is located, on the one hand, the electron transport channel of the channel region can be increased, and on the other hand, the electron mobility of the channel region can be increased, thereby
  • the channel length of the thin film transistor can be significantly shortened, and the on-state current of the thin film transistor is greatly improved, so that the thin film transistor can easily satisfy the charging rate requirement of the high PPI display product, so that the width of the channel region of the thin film transistor can be designed to be relatively small. It is beneficial to increase the aperture ratio of the display substrate and reduce the power consumption of the display device.
  • the fabricating method further includes the step of forming a second conductive pattern;
  • the method further includes the step of forming a third conductive pattern when further including a third conductive pattern that is in contact with the drain electrode contact region of the active layer and spaced apart from the first conductive pattern.
  • the first conductive pattern, the second conductive pattern, and the third conductive pattern may be formed by a patterning process, or the first conductive pattern, the second conductive pattern, and the third conductive pattern may be formed by imprinting.
  • the step of forming the first conductive pattern includes:
  • Step 1 As shown in FIG. 7, a template 7 is provided, and the substrate 5 on which the first conductive pattern is to be formed is provided. Applying a photoresist 6 thereon;
  • the thin film transistor such as the source electrode 1 and the drain electrode 2, may be formed on the substrate 5, and other components of the thin film transistor may not be formed.
  • the pattern of the template 7 coincides with the pattern of the first conductive pattern to be formed.
  • Step 2 as shown in FIG. 8 and FIG. 9, the pattern on the template 7 is transferred onto the photoresist 6 by imprinting to form a photoresist retention region and a photoresist unreserved region. It can be seen that the photolithography The pattern of the unretained area of the glue is consistent with the pattern of the template 7;
  • Step 3 in depositing a conductive layer 8, the conductive layer 8 includes a first portion on the photoresist retention region and a second portion in the photoresist unretained region in contact with the substrate;
  • the conductive layer 8 is made of metal.
  • the conductive layer 8 can also be made of other conductive materials such as transparent conductive metal oxide materials.
  • the conductive layer 8 can be made of Al, Mo, Ti, etc. metallic material.
  • Step 4 as shown in FIG. 11, exposing and developing the photoresist to remove the photoresist in the photoresist remaining region, and the first portion on the photoresist in the photoresist retention region is also detached from the substrate 5. Only the second portion is left to form the first conductive pattern 41.
  • the active layer 3 may be formed on the substrate 5 on which the first conductive pattern 41 is formed. If the first conductive pattern 41 is formed on the active layer 3, the active layer 3 has been formed on the substrate 5 referred to in the step 1.
  • the thin film transistor formed in this embodiment includes a first conductive pattern in contact with a channel region of the active layer, and the first conductive pattern can increase the electron transport channel of the channel region on the one hand, and increase the electron of the channel region on the other hand.
  • the mobility can significantly shorten the channel length of the thin film transistor and greatly increase the on-state current of the thin film transistor, so that the thin film transistor can easily meet the charging rate requirement of the high PPI display product, and thus the width of the channel region of the thin film transistor can be designed. Smaller, it is beneficial to increase the aperture ratio of the display substrate and reduce the power consumption of the display device.
  • the second conductive pattern and/or the third conductive pattern may be formed while forming the first conductive pattern. If the first conductive pattern, the second conductive pattern, and/or the third conductive pattern are formed by imprinting, the pattern of the provided template is consistent with the pattern of the first conductive pattern, the second conductive pattern, and/or the third conductive pattern The second conductive pattern and/or the third conductive pattern may be formed while forming the first conductive pattern.

Abstract

一种薄膜晶体管及其制作方法、显示基板及显示装置。薄膜晶体管，包括：形成在衬底上的源电极（1）、漏电极（2）和有源层（3），其中所述有源层（3）包括用于与所述源电极接触的源电极接触区、与所述漏电极接触的漏电极接触区以及位于所述源电极接触区和所述漏电极接触区之间的沟道区；以及第一导电图形，分布在所述有源层的沟道区且与所述沟道区接触。

Description

薄膜晶体管及其制作方法、显示基板及显示装置
相关申请的交叉引用
本申请要求于2017年2月16日提交中国专利局、申请号为201710083390.7的优先权，其全部内容据此通过引用并入本申请。
技术领域
本公开涉及显示技术领域，特别是指一种薄膜晶体管及其制作方法、显示基板及显示装置。
背景技术
现有TFT-LCD(薄膜晶体管液晶显示器)行业中低世代线采用的阵列基板曝光设备精度普遍较低，使得TFT(薄膜晶体管)沟道长度L比较长，无法进一步缩短。由于薄膜晶体管的开态电流与TFT的沟道宽长比W/L成正比，因此，会导致薄膜晶体管的开态电流比较小。随着高端显示产品PPI(像素密度)越来越高，为了满足显示产品的充电率需求，需要提高薄膜晶体管的开态电流，因此需要将薄膜晶体管的沟道宽度设计的比较大，这样就严重影响了显示基板的开口率，同时还会导致显示基板的负载比较大，导致显示装置的功耗显著上升。
发明内容
本公开要解决的技术问题是提供一种薄膜晶体管及其制作方法、显示基板及显示装置，能够提高薄膜晶体管的开态电流，从而可以将薄膜晶体管的沟道宽度设计的比较小。
为解决上述技术问题，本公开的实施例提供技术方案如下：
一方面，提供一种薄膜晶体管，包括形成在衬底上的源电极、漏电极和有源层，其中所述有源层包括用于与所述源电极接触的源电极接触区、与所述漏电极接触的漏电极接触区以及位于所述源电极接触区和所述漏电极接触区之间的沟道区；以及第一导电图形，分布在所述有源层的沟道区且与所述沟道区 接触。
可选地，所述薄膜晶体管还包括：与所述有源层的源电极接触区接触且与所述第一导电图形间隔开的第二导电图形；和/或与所述有源层的漏电极接触区接触且与所述第一导电图形间隔开的第三导电图形。
可选地，在所述有源层的沟道区分布有呈阵列排布的多个所述第一导电图形。
可选地，每一所述第一导电图形的延伸方向与从所述源电极到所述漏电极的第一方向大致平行。
可选地，所述第一导电图形的长度小于所述源电极到所述漏电极之间的垂直距离。
可选地，每一所述第一导电图形的长度为Lx，在第一方向上相邻两个第一导电图形之间的间距为Ly，Ly与Lx比值的取值范围为0.3～0.7。
可选地，每一所述第一导电图形的延伸方向与从所述源电极到所述漏电极的第一方向不平行，每一所述第一导电图形在所述第一方向上的投影长度为Lx，在所述第一导电图形的延伸方向上相邻两个第一导电图形在所述第一方向上的投影间距为Ly，Ly与Lx比值的取值范围为0.3～0.7。
可选地，所述第一导电图形、所述第二导电图形和所述第三导电图形均是金属纳米线。
可选地，所述第一导电图形的长度小于1000nm。
可选地，所述第一导电图形横截面的直径小于100nm。
本公开实施例还提供了一种显示基板，包括如上所述的薄膜晶体管。
本公开实施例还提供了一种显示装置，包括如上所述的显示基板。
本公开实施例还提供了一种薄膜晶体管的制作方法，包括：在衬底上形成源电极、漏电极和有源层，其中所述有源层包括用于与所述源电极接触的源电极接触区、与所述漏电极接触的漏电极接触区以及位于所述源电极接触区和所述漏电极接触区之间的沟道区，以及形成第一导电图形，其中所述第一导电图形分布在所述有源层的沟道区且与所述沟道区接触。
可选地，所述形成所述第一导电图形，包括：在待形成所述第一导电图形 的衬底上涂覆光刻胶；通过压印将模板上的图案转印在光刻胶上，形成光刻胶保留区域和光刻胶未保留区域，光刻胶未保留区域对应所述图案；沉积导电层，所述导电层包括位于光刻胶保留区域上的第一部分和位于光刻胶未保留区域与所述衬底相接触的第二部分；以及对光刻胶进行曝光显影，去除光刻胶保留区域的光刻胶和所述第一部分，保留所述第二部分形成所述第一导电图形。
可选地，所述制作方法还包括：在形成所述第一导电图形的同时形成第二导电图形和/或第三导电图形，其中所述第二导电图形与所述有源层的源电极接触区接触且与所述第一导电图形间隔开，所述第三导电图形与所述有源层的漏电极接触区接触且与所述第一导电图形间隔开。
本公开的实施例具有以下有益效果：
上述方案中，薄膜晶体管包括与有源层的沟道区接触的第一导电图形，第一导电图形一方面可以增加沟道区的电子输运通道，另一方面可以增加沟道区的电子迁移率，从而能够显著缩短薄膜晶体管的沟道长度，大大提升薄膜晶体管的开态电流，使得薄膜晶体管很容易满足高PPI显示产品的充电率要求，因而可以将薄膜晶体管沟道区的宽度设计的比较小，有利于提升显示基板的开口率，降低显示装置的功耗。
附图说明
图1为现有薄膜晶体管沟道区域的示意图；
图2为根据本公开一些实施例的薄膜晶体管的沟道区域的示意图；
图3为根据本公开一些实施例的薄膜晶体管的沟道区域的示意图；
图4为根据本公开一些实施例的相邻两个导电图形之间的有效间距和导电图形的有效长度的示意图；
图5为根据本公开一些实施例的薄膜晶体管的沟道区域的示意图；
图6为根据本公开一些实施例的相邻两个导电图形之间的有效间距和导电图形的有效长度的示意图；以及
图7-图12为本公开实施例形成导电图形和薄膜晶体管的有源层的示意图。
附图标记
1源电极 2漏电极 3有源层 41第一导电图形
42第二导电图形 43第三导电图形
5衬底 6光刻胶 7模板 8导电层
具体实施方式
为使本公开的实施例要解决的技术问题、技术方案和优点更加清楚，下面将结合附图及具体实施例进行详细描述。
如图1所示，现有薄膜晶体管包括源电极1、漏电极2和有源层3，有源层3包括与源电极1接触的源电极接触区、与漏电极2接触的漏电极接触区以及位于源电极接触区和漏电极接触区之间的沟道区。其中，沟道区的宽长比W/L0越大，则薄膜晶体管的开态电流Ion越大。
现有TFT-LCD行业中低世代线采用的阵列基板曝光设备精度普遍较低，使得TFT沟道长度L0比较长，无法进一步缩短，由于薄膜晶体管的开态电流与TFT的沟道宽长比W/L0成正比，因此，会导致薄膜晶体管的开态电流比较小。
本公开的实施例针对相关技术中薄膜晶体管的开态电流比较小的问题，提供一种薄膜晶体管及其制作方法、显示基板及显示装置，能够提高薄膜晶体管的开态电流，从而可以将薄膜晶体管的沟道宽度设计的比较小。
实施例一
本实施例提供一种薄膜晶体管，如图2所示，包括形成在衬底上的源电极1、漏电极2和有源层3，所述有源层3包括用于与所述源电极1接触的源电极接触区、与所述漏电极2接触的漏电极接触区以及位于所述源电极接触区和所述漏电极接触区之间的沟道区，如图2所示，所述薄膜晶体管还包括：
至少分布在所述有源层3的沟道区的第一导电图形41，所述第一导电图形41与所述有源层3的沟道区接触。
由于第一导电图形41是导电的，一方面可以增加沟道区的电子输运通道，另一方面可以增加沟道区的电子迁移率，从而能够显著缩短薄膜晶体管的沟道长度，大大提升薄膜晶体管的开态电流，使得薄膜晶体管很容易满足高PPI显示产品的充电率要求，因而可以将薄膜晶体管沟道区的宽度设计的比较小， 有利于提升显示基板的开口率，降低显示装置的功耗。
其中，第一导电图形41可以位于有源层3上，也可以位于有源层3下，只要能够与有源层3的沟道区接触即可，值得注意的是，每一第一导电图形41可以仅与沟道区的部分区域相接触，这样第一导电图形41不会导通源电极1和漏电极2。例如，第一导电图形的两端不同时分别位于所述源电极接触区和所述漏电极接触区。
第一导电图形41的形状不做限定，只要能够在从源电极1到漏电极2的第一方向上具有有效长度即可。在有源层3的沟道区可以分布有多个第一导电图形41，也可以分布有一个第一导电图形41。
本实施例中，如图2所示，可以在有源层3的沟道区分布有多个第一导电图形41，多个第一导电图形41呈阵列排布，能够在沟道区增加多条电子输运通道，大大提升薄膜晶体管的开态电流。
第一导电图形41所能够缩短的沟道区的长度与第一导电图形41在第一方向上的有效长度有关，优选地，每一第一导电图形41的延伸方向与从源电极1到漏电极2的第一方向平行，这样每一第一导电图形41所能够缩短的沟道区的长度等于第一导电图形41的长度。
如图4所示，每一第一导电图形41的长度为Lx，在第一方向上相邻第一导电图形41之间的间距为Ly，在沟道区沿第一方向分布有n个第一导电图形41，源电极1和漏电极2之间的垂直距离为L1，其中n为大于或等于1的整数。在设置第一导电图形41后，在计算沟道区的宽长比W/L0时，参数L0能够降到L1-n*Lx，可以看出，L0大大降低，因此，沟道区的宽长比得以提升，能够大大提升薄膜晶体管的开态电流，使得薄膜晶体管很容易满足高PPI显示产品的充电率要求。因而还可以将薄膜晶体管沟道区的宽度W设计的比较小，减少薄膜晶体管的尺寸，有利于提升显示基板的开口率，降低显示装置的功耗。
具体地，第一导电图形41可以采用纳米级的金属线，能够有效增加沟道区的电子迁移率，第一导电图形41横截面的直径可以小于100nm，第一导电图形41的长度可以小于1000nm。经过大量的数据验证，在设计第一导电图形41时，可以将Ly/Lx的取值设计为0.3～0.7，采用该种参数时，能够有效增加沟道区的电子迁移率。
实施例二
本实施例提供一种薄膜晶体管，如图3所示，包括形成在衬底上的源电极1、漏电极2和有源层3，所述有源层3包括用于与所述源电极1接触的源电极接触区、与所述漏电极2接触的漏电极接触区以及位于所述源电极接触区和所述漏电极接触区之间的沟道区，如图3所示，所述薄膜晶体管还包括：
至少分布在所述有源层3的沟道区的第一导电图形41，所述第一导电图形41与所述有源层3的沟道区接触；
与有源层3的源电极接触区接触且与第一导电图形41间隔开的第二导电图形42；和/或
与有源层3的漏电极接触区接触且与第一导电图形41间隔开的第三导电图形43。
由于第一导电图形41是导电的，这样通过在有源层3所在区域分布第一导电图形41，一方面可以增加沟道区的电子输运通道，另一方面可以增加沟道区的电子迁移率，从而能够显著缩短薄膜晶体管的沟道长度，大大提升薄膜晶体管的开态电流，使得薄膜晶体管很容易满足高PPI显示产品的充电率要求，因而可以将薄膜晶体管沟道区的宽度设计的比较小，有利于提升显示基板的开口率，降低显示装置的功耗。
其中，可以仅设置第二导电图形42或第三导电图形43，也可以同时设置第二导电图形42和第三导电图形43。图3所示的实施例中，是同时设置有第二导电图形42和第三导电图形43。
由于第二导电图形42是导电的，因此，在源电极接触区设置第二导电图形42，使得第二导电图形42可以与源电极接触区形成并联，降低源电极接触区的电阻；由于第三导电图形43是导电的，因此，在漏电极接触区设置第三导电图形43，使得第三导电图形43可以与漏电极接触区形成并联，降低漏电极接触区的电阻。
其中，第一导电图形41、第二导电图形42和第三导电图形43可以都位于有源层3上，也可以都位于有源层3下，也可以部分位于有源层3上，另一部分位于有源层下，只要能够与有源层3接触即可，值得注意的是，第一导电图形41仅与沟道区的部分区域相接触，且与第二导电图形42和第三导电图形 43分别间隔设置，这样第一导电图形41、第二导电图形42和第三导电图形43不会导通源电极1和漏电极2。
第一导电图形41、第二导电图形42和第三导电图形43的形状不做限定，只要能够在从源电极1到漏电极2的第一方向上具有有效长度即可。在有源层3的沟道区可以分布有多个第一导电图形41、多个第二导电图形42和多个第三导电图形43，也可以分布有一个第一导电图形41、一个第二导电图形42和一个第三导电图形43。
本实施例中，如图3所示，可以在有源层3的沟道区分布有多个第一导电图形41，多个第二导电图形42和多个第三导电图形43，多个第一导电图形41、多个第二导电图形42和多个第三导电图形43呈阵列排布，能够在沟道区增加多条电子输运通道，大大提升薄膜晶体管的开态电流。
第一导电图形41所能够缩短的沟道区的长度与第一导电图形41在第一方向上的有效长度有关。优选地，每一第一导电图形41的延伸方向与从源电极1到漏电极2的第一方向平行，这样每一第一导电图形41所能够缩短的沟道区的长度等于第一导电图形41的长度。
如图4所示，每一第一导电图形41的长度为Lx，在第一方向上相邻第一导电图形41之间的间距为Ly，在沟道区沿第一方向分布有多个第一导电图形41，在第一方向上多个第一导电图形41之间的间隔数为m，源电极1和漏电极2之间的垂直距离为L1，则在设置第一导电图形41后，在计算沟道区的宽长比W/L0时，参数L0能够从L1降到m*Ly，可以看出，L0大大降低。因此，沟道区的宽长比得以提升，能够大大提升薄膜晶体管的开态电流，使得薄膜晶体管很容易满足高PPI显示产品的充电率要求，因而还可以将薄膜晶体管沟道区的宽度W设计的比较小，减少薄膜晶体管的尺寸，有利于提升显示基板的开口率，降低显示装置的功耗。
经过大量的数据验证，在设计第一导电图形41时，可以将Ly/Lx的取值设计为0.3～0.7，采用该种参数时，能够有效增加沟道区的电子迁移率。
具体地，第一导电图形41、第二导电图形42和第三导电图形43可以采用纳米级的金属线，能够有效增加沟道区的电子迁移率，第一导电图形41、第二导电图形42和第三导电图形43横截面的直径可以小于100nm，第一导电 图形41、第二导电图形42和第三导电图形43的长度可以小于1000nm。
实施例三
本实施例提供一种薄膜晶体管，如图5所示，包括形成在衬底上的源电极1、漏电极2和有源层3，有源层3包括用于与源电极1接触的源电极接触区、与漏电极2接触的漏电极接触区以及位于源电极接触区和漏电极接触区之间的沟道区，所述薄膜晶体管还包括：
至少分布在所述有源层3的沟道区的第一导电图形41，所述第一导电图形41与所述有源层3的沟道区接触；
与有源层3的源电极接触区接触且与第一导电图形41间隔开的第二导电图形42；
与有源层3的漏电极接触区接触且与第一导电图形41间隔开的第三导电图形43。
由于第一导电图形41是导电的，这样通过在有源层3所在区域分布第一导电图形41，一方面可以增加沟道区的电子输运通道，另一方面可以增加沟道区的电子迁移率，从而能够显著缩短薄膜晶体管的沟道长度，大大提升薄膜晶体管的开态电流，使得薄膜晶体管很容易满足高PPI显示产品的充电率要求，因而可以将薄膜晶体管沟道区的宽度设计的比较小，有利于提升显示基板的开口率，降低显示装置的功耗。
由于第二导电图形42是导电的，因此，在源电极接触区设置第二导电图形42，使得第二导电图形42可以与源电极接触区形成并联，降低源电极接触区的电阻；由于第三导电图形43是导电的，因此，在漏电极接触区设置第三导电图形43，使得第三导电图形43可以与漏电极接触区形成并联，降低漏电极接触区的电阻。
其中，第一导电图形41、第二导电图形42和第三导电图形43可以都位于有源层3上，也可以都位于有源层3下，也可以部分位于有源层3上，另一部分位于有源层下，只要能够与有源层3接触即可，值得注意的是，第一导电图形41仅与沟道区的部分区域相接触，且与第二导电图形42和第三导电图形43分别间隔设置，这样第一导电图形41、第二导电图形42和第三导电图形43不会导通源电极1和漏电极2。
第一导电图形41、第二导电图形42和第三导电图形43的形状不做限定，只要能够在从源电极1到漏电极2的第一方向上具有有效长度即可。在有源层3的沟道区可以分布有多个第一导电图形41、多个第二导电图形42和多个第三导电图形43，也可以分布有一个第一导电图形41、一个第二导电图形42和一个第三导电图形43。
本实施例中，如图3所示，可以在有源层3的沟道区分布有多个第一导电图形41，多个第二导电图形42和多个第三导电图形43，多个第一导电图形41、多个第二导电图形42和多个第三导电图形43呈阵列排布，能够在沟道区增加多条电子输运通道，大大提升薄膜晶体管的开态电流。
第一导电图形41所能够缩短的沟道区的长度与第一导电图形41在第一方向上的有效长度有关，本实施例中，如图5所示，每一第一导电图形41的延伸方向与从源电极1到漏电极2的第一方向成一定角度，该角度小于90°大于0°，每一第一导电图形41所能够缩短的沟道区的长度等于第一导电图形41在第一方向上投影的长度。
如图6所示，第一导电图形41在第一方向上投影的长度为Lx，在第一方向上相邻第一导电图形41之间的间距为Ly，在沟道区沿第一方向分布有多个第一导电图形41，在第一方向上多个第一导电图形41之间的间隔数为m，源电极1和漏电极2之间的垂直距离为L1，则在设置第一导电图形41后，在计算沟道区的宽长比W/L0时，参数L0能够从L1降到m*Ly，可以看出，L0大大降低，因此，沟道区的宽长比得以提升，能够大大提升薄膜晶体管的开态电流，使得薄膜晶体管很容易满足高PPI显示产品的充电率要求，因而还可以将薄膜晶体管沟道区的宽度W设计的比较小，减少薄膜晶体管的尺寸，有利于提升显示基板的开口率，降低显示装置的功耗。
经过大量的数据验证，在设计第一导电图形41时，可以将Ly/Lx的取值设计为0.3～0.7，采用该种参数时，能够有效增加沟道区的电子迁移率。
具体地，第一导电图形41、第二导电图形42和第三导电图形43可以采用纳米级的金属线，能够有效增加沟道区的电子迁移率，第一导电图形41、第二导电图形42和第三导电图形43横截面的直径可以小于100nm，第一导电图形41、第二导电图形42和第三导电图形43的长度可以小于1000nm。
实施例四
本实施例提供了一种显示基板，包括如上所述的薄膜晶体管。
实施例五
本实施例提供了一种显示装置，包括如上所述的显示基板。所述显示装置可以为：液晶电视、液晶显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件，其中，所述显示装置还包括柔性电路板、印刷电路板和背板。
实施例六
本实施例提供了一种上述薄膜晶体管的制作方法，包括在衬底上形成源电极、漏电极和有源层的步骤，所述有源层包括用于与所述源电极接触的源电极接触区、与所述漏电极接触的漏电极接触区以及位于所述源电极接触区和所述漏电极接触区之间的沟道区，所述制作方法还包括：
形成至少分布在所述有源层的沟道区的第一导电图形，所述第一导电图形与所述沟道区接触。
由于第一导电图形是导电的，这样通过在有源层所在区域分布第一导电图形，一方面可以增加沟道区的电子输运通道，另一方面可以增加沟道区的电子迁移率，从而能够显著缩短薄膜晶体管的沟道长度，大大提升薄膜晶体管的开态电流，使得薄膜晶体管很容易满足高PPI显示产品的充电率要求，因而可以将薄膜晶体管沟道区的宽度设计的比较小，有利于提升显示基板的开口率，降低显示装置的功耗。
进一步地，在薄膜晶体管还包括与有源层的源电极接触区接触且与第一导电图形间隔开的第二导电图形时，所述制作方法还包括形成第二导电图形的步骤；在薄膜晶体管还包括与有源层的漏电极接触区接触且与第一导电图形间隔开的第三导电图形时，所述制作方法还包括形成第三导电图形的步骤。
其中，可以采用构图工艺形成第一导电图形、第二导电图形和第三导电图形，也可以采用压印的方式形成第一导电图形、第二导电图形和第三导电图形。
具体地，在采用压印的方式形成第一导电图形时，形成所述第一导电图形的步骤包括：
步骤1、如图7所示，提供一模板7，并在待形成第一导电图形的衬底5 上涂覆光刻胶6；
其中，衬底5上可以已经形成有薄膜晶体管的其他组成部分，比如源电极1和漏电极2，也可以未形成薄膜晶体管的其他组成部分。
模板7的图案与待形成的第一导电图形的图案一致。
步骤2、如图8和图9所示，通过压印将模板7上的图案转印在光刻胶6上，形成光刻胶保留区域和光刻胶未保留区域，可以看出，光刻胶未保留区域的图案与模板7的图案一致；
步骤3、如图10所示，在沉积导电层8，导电层8包括位于光刻胶保留区域上的第一部分和位于光刻胶未保留区域与所述衬底相接触的第二部分；
导电层8采用金属制成，当然导电层8还可以采用其他导电材料比如透明导电金属氧化物材料制成，在导电层8采用金属制成时，导电层8具体可以采用Al、Mo、Ti等金属材料。
步骤4、如图11所示，对光刻胶进行曝光显影，去除光刻胶保留区域的光刻胶，光刻胶保留区域的光刻胶上的第一部分也随之从衬底5上脱落，仅保留第二部分形成第一导电图形41。
如果第一导电图形41是制作在有源层3之下，之后如图12所示，可以在形成有第一导电图形41的衬底5上再制作有源层3。如果第一导电图形41是制作在有源层3上，则步骤1中所指的衬底5上已经形成有有源层3。
本实施例形成的薄膜晶体管包括与有源层的沟道区接触的第一导电图形，第一导电图形一方面可以增加沟道区的电子输运通道，另一方面可以增加沟道区的电子迁移率，从而能够显著缩短薄膜晶体管的沟道长度，大大提升薄膜晶体管的开态电流，使得薄膜晶体管很容易满足高PPI显示产品的充电率要求，因而可以将薄膜晶体管沟道区的宽度设计的比较小，有利于提升显示基板的开口率，降低显示装置的功耗。
进一步地，在薄膜晶体管还包括有第二导电图形和/或第三导电图形时，可以在形成第一导电图形的同时形成第二导电图形和/或第三导电图形。如果采用压印的方式形成第一导电图形、第二导电图形和/或第三导电图形，则提供的模板的图案与第一导电图形、第二导电图形和/或第三导电图形的图案一致，即可在形成第一导电图形的同时形成第二导电图形和/或第三导电图形。
在本公开各方法实施例中，所述各步骤的序号并不能用于限定各步骤的先后顺序，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，对各步骤的先后变化也在本公开的保护范围之内。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件″上″或″下″时，该元件可以″直接″位于另一元件″上″或″下″，或者可以存在中间元件。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (15)

  1. 一种薄膜晶体管，包括：
    形成在衬底上的源电极、漏电极和有源层，其中所述有源层包括用于与所述源电极接触的源电极接触区、与所述漏电极接触的漏电极接触区以及位于所述源电极接触区和所述漏电极接触区之间的沟道区；以及
    第一导电图形，分布在所述有源层的沟道区且与所述沟道区接触。
  2. 根据权利要求1所述的薄膜晶体管，其中，所述薄膜晶体管还包括：
    与所述有源层的源电极接触区接触且与所述第一导电图形间隔开的第二导电图形；和/或
    与所述有源层的漏电极接触区接触且与所述第一导电图形间隔开的第三导电图形。
  3. 根据权利要求1或2所述的薄膜晶体管，其中，在所述有源层的沟道区分布有呈阵列排布的多个所述第一导电图形。
  4. 根据权利要求3所述的薄膜晶体管，其中，每一所述第一导电图形的延伸方向与从所述源电极到所述漏电极的第一方向大致平行。
  5. 根据权利要求4所述所述的薄膜晶体管，其中，所述第一导电图形的长度小于所述源电极到所述漏电极之间的垂直距离。
  6. 根据权利要求4所述的薄膜晶体管，其中，每一所述第一导电图形的长度为Lx，在第一方向上相邻两个第一导电图形之间的间距为Ly，Ly与Lx比值的取值范围为0.3～0.7。
  7. 根据权利要求3所述的薄膜晶体管，其中，每一所述第一导电图形的延伸方向与从所述源电极到所述漏电极的第一方向不平行，每一所述第一导电图形在所述第一方向上的投影长度为Lx，在所述第一导电图形的延伸方向上相邻两个第一导电图形在所述第一方向上的投影间距为Ly，Ly与Lx比值的取值范围为0.3～0.7。
  8. 根据权利要求2-7任一项所述的薄膜晶体管，其中，所述第一导电图形、所述第二导电图形和所述第三导电图形均是金属纳米线。
  9. 根据权利要求1-8任一项所述的薄膜晶体管，其中，所述第一导电图 形的长度小于1000nm。
  10. 根据权利要求1-9任一项所述的薄膜晶体管，其中，所述第一导电图形横截面的直径小于100nm。
  11. 一种显示基板，包括如权利要求1-10中任一项所述的薄膜晶体管。
  12. 一种显示装置，包括如权利要求11所述的显示基板。
  13. 一种薄膜晶体管的制作方法，包括：
    在衬底上形成源电极、漏电极和有源层，其中所述有源层包括用于与所述源电极接触的源电极接触区、与所述漏电极接触的漏电极接触区以及位于所述源电极接触区和所述漏电极接触区之间的沟道区；以及
    形成第一导电图形，其中所述第一导电图形分布在所述有源层的沟道区且与所述沟道区接触。
  14. 根据权利要求13所述的薄膜晶体管的制作方法，所述形成所述第一导电图形，包括：
    在待形成所述第一导电图形的衬底上涂覆光刻胶；
    通过压印将模板上的图案转印在所述光刻胶上，形成光刻胶保留区域和光刻胶未保留区域，光刻胶未保留区域对应所述图案；
    沉积导电层，所述导电层包括位于光刻胶保留区域上的第一部分和位于光刻胶未保留区域与所述衬底相接触的第二部分；
    对光刻胶进行曝光显影，去除光刻胶保留区域的光刻胶和所述第一部分，保留所述第二部分形成所述第一导电图形。
  15. 根据权利要求13或14所述的薄膜晶体管的制作方法，还包括：
    在形成所述第一导电图形的同时形成第二导电图形和/或第三导电图形，其中所述第二导电图形与所述有源层的源电极接触区接触且与所述第一导电图形间隔开，所述第三导电图形与所述有源层的漏电极接触区接触且与所述第一导电图形间隔开。
PCT/CN2017/103381 2017-02-16 2017-09-26 薄膜晶体管及其制作方法、显示基板及显示装置 WO2018149139A1 (zh)

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