WO2018133224A1 - 一种斜面沟道的SiC MOSFET器件及其制备方法 - Google Patents

一种斜面沟道的SiC MOSFET器件及其制备方法 Download PDF

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WO2018133224A1
WO2018133224A1 PCT/CN2017/081000 CN2017081000W WO2018133224A1 WO 2018133224 A1 WO2018133224 A1 WO 2018133224A1 CN 2017081000 W CN2017081000 W CN 2017081000W WO 2018133224 A1 WO2018133224 A1 WO 2018133224A1
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layer
region
sic mosfet
mosfet device
mask layer
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French (fr)
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倪炜江
袁俊
张敬伟
牛喜平
崔志勇
李明山
徐妙玲
季莎
卢小东
孙安信
胡羽中
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北京世纪金光半导体有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the invention belongs to the field of semiconductors, and in particular relates to a slab channel SiC MOSFET device and a preparation method thereof.
  • the process of high temperature activation annealing degrades the surface and deteriorates the morphology, thereby increasing the surface scattering of the channel electrons.
  • the higher the temperature of the activation annealing the higher the activation rate and the defect repair rate, but the surface degradation is more serious.
  • the growth of SiC MOS gate dielectric itself is very difficult. Therefore, the current channel mobility of SiC MOSFET devices is very low, only 20-30cm 2 /Vs, which requires better design or further improvement of the process.
  • UMOSFET U-channel MOSFET structure
  • the UMOSFET structure has a higher cell density and a gate width per unit area.
  • the p-well of the channel is formed by an epitaxial method, and thus has higher channel mobility and current density, but the channel is formed on the surface of the etch layer, and defects and surface roughness caused by etching are inevitably applied to the MOS gate. Quality has an impact.
  • Another method is the VMOSFET structure, as shown in Figure 3.
  • the V-shaped groove of the VMOSFET structure is formed by the inconsistent corrosion rate of each crystal plane caused by the anisotropy of SiC under high temperature corrosion, and there is a problem that the process is difficult to control. At the same time, the sharp corners at the bottom of the trough are also likely to cause electric field concentration and poor reliability.
  • a bevel channel SiC MOSFET device that utilizes a plane of high electron mobility as a channel plane and a high quality secondary epitaxial SiC surface. Forming the channel can effectively improve the quality of the MOS gate and the channel mobility, and reduce the on-resistance of the device.
  • Another object of the present invention is to provide a method of fabricating a bevel channel SiC MOSFET device.
  • the present invention adopts the following technical solutions:
  • a bevel channel SiC MOSFET device the cell structure of the active region of the SiC MOSFET device is a drain, an n++ substrate (concentration greater than 1E18 cm -3 ), an n-drift layer, and a bilaterally symmetric arrangement from bottom to top.
  • a rectangular injection n layer, a secondary epitaxial p-type layer and the implanted n layer are sequentially provided with an "arched" gate oxide layer, a polysilicon layer and an isolation passivation layer.
  • n-type buffer layer is preferably provided between the n-drift layer and the conductive substrate, and the buffer layer has a concentration of about 1E18 cm -3 and a thickness of about 1 ⁇ m.
  • the length of the secondary epitaxial p-type layer on the inclined surface is 0.2-1 ⁇ m; the angle between the secondary epitaxial p-type layer and the base substrate is 20-80°.
  • the secondary epitaxial p-type layer has a concentration of 1E15-1E18 cm -3 and a thickness of 200 nm to 500 nm.
  • the mesa top of the cell structure has a width of 1.5-6 ⁇ m.
  • the n-type and the p-type are relatively applicable to the p+ type substrate, and the other layers have opposite conductivity types.
  • planar structure of the cells in the device structure may be various structures such as a strip shape, a rectangle shape, a hexagon shape, and the like.
  • the device structure is also applicable to other semiconductor materials such as Si, GaN, GaO, etc., and is not limited to SiC materials.
  • the preparation method will be different.
  • a method of fabricating a beveled channel SiC MOSFET device comprising the steps of:
  • the first mask layer is formed;
  • SiC is etched by ICP method, and the SiC/SiO 2 selection ratio is controlled to control the slope angle of the SiC mesa; after the etching is completed, the remaining SiO 2 is used as a mask for ion implantation, and Al ions are implanted, and the slope is also under the slope. Ions are implanted to form doping of the p-well region and doping of the junction termination region;
  • the implanted ions can be N ions or P ions, and the depth and concentration of the implanted doping
  • the p layer is larger than the second epitaxial layer, and the n-type doping is formed after the p-type doping, and is connected with the JFET region; the second mask layer is removed, and the third mask layer is removed after cleaning, and then N ions or P are performed.
  • the fifth mask layer is formed, the first JTE region is etched by the fifth mask layer; the fifth mask layer is removed, the sixth mask layer is cleaned, and the sixth mask layer is used for etching. a second JTE region; removing the sixth mask layer, performing a seventh mask layer after cleaning, etching the device isolation region by using the seventh mask layer; performing sacrificial oxidation, and removing the oxide layer with diluted HF or BOE;
  • the thermal oxidation method is to grow a 50-60 nm SiO 2 layer, and then anneal after oxidation;
  • a first passivation layer depositing a metal on the back side, performing rapid thermal annealing to form an ohmic contact; lithography, etching, etching a dielectric window in the source region, depositing a metal in the window, and etching by photolithography
  • the method is patterned; then rapid thermal annealing is performed to form an ohmic contact in the source region; the ohmic contact of the drain and the source can also be annealed after the metal is sequentially deposited; and the second passivation layer is deposited in the source region.
  • the doping concentration of the p-well region doping and the junction termination region in the step 2) is between 1E18 and 5E19 cm -3 and the depth is between 0.3 ⁇ m and 1 ⁇ m.
  • the thickness of the sacrificial oxide layer is between 10 nm and 100 nm, and the concentration of the second epitaxial p-type layer is between 1E15 and 1E18 cm -3 and the thickness is between 200 nm and 1000 nm.
  • the concentration of the N ion or P ion implantation in the step 4) is greater than 1E19 cm -3 and the depth is between 200 and 1000 nm; the temperature of the high temperature activation annealing is between 1700 ° C and 1950 ° C for a time between 1 and 30 minutes.
  • the thickness of the sacrificial oxide layer is between 10 nm and 50 nm, the thickness of the SiO 2 layer is 50-60 nm, the thermal oxidation temperature is 1200 ° C to 1500 ° C, and the annealing temperature is 1200 ° C to 1350 ° C.
  • the atmosphere is under N 2 O or NO atmosphere.
  • the first passivation layer is 200 nm thick SiO 2 ;
  • the second passivation layer is SiO 2 /SiN, the thickness is 200 nm / 300 nm, respectively, or SiO x N y ;
  • the medium thickness electrode metal is Ti/Al or Ti/AlSi or Ti/AlSiCu or Ti/AlCu, Ti has a thickness of 20 to 200 nm, and Al or AlSi or AlSiCu or AlCu has a thickness of about 4 to 8 ⁇ m.
  • the present application utilizes a crystal plane with high electron mobility as a channel plane, and forms a channel on a high quality secondary epitaxial SiC surface, which can effectively improve the quality and channel mobility of the MOS gate and reduce the on-resistance of the device.
  • FIG. 1 is a schematic cross-sectional structural view of a cell structure of a planar SiC MOSFET in the prior art
  • FIG. 2 is a schematic cross-sectional structural view showing a cell structure of a U-shaped trench SiC MOSFET in the prior art
  • FIG. 3 is a schematic cross-sectional structural view of a cell structure of a V-type trench SiC MOSFET in the prior art
  • FIG. 4 is a schematic cross-sectional structural view showing a cell structure of a SiC MOSFET of the present invention.
  • Figure 5 is a plan view of a SiC MOSFET device of the present invention.
  • FIG. 6 is a schematic structural view of the SiC MOSFET in the preparation process of the cell structure of the present invention after the first mask layer is completed;
  • FIG. 7 is a schematic structural view of a SiC mesa after ion implantation after etching a cell structure of a SiC MOSFET according to the present invention.
  • FIG. 8 is a schematic structural view of a second epitaxially grown p-type layer in a process for preparing a SiC MOSFET cell structure according to the present invention
  • FIG. 9 is a schematic structural view showing completion of ion implantation and activation annealing of each region in the preparation process of the SiC MOSFET cell structure of the present invention.
  • FIG. 10 is a schematic structural view of a SiC MOSFET cell structure in the preparation process of JTE etching and thermal oxidation to form a gate dielectric;
  • FIG. 11 is a schematic structural view of the SiC MOSFET in the preparation process of the cell structure of the SiC MOSFET after completion of contact;
  • FIG. 12 is a schematic structural view of a source and drain ohmic contact in a process for preparing a SiC MOSFET cell structure according to the present invention
  • FIG. 13 is a schematic structural view of the SiC MOSFET cell structure after completion of the preparation of the present invention.
  • the present invention provides a bevel channel SiC MOSFET device.
  • the cell structure of the active region of the SiC MOSFET device is a drain, an n++ substrate, an n-drift layer, and left and right from bottom to top.
  • Two p-well layers symmetrically arranged, p++ and n++ regions disposed on the p-well layer, source electrodes disposed on the p++ region and the n++ region; opposite sides of the two p-well layers are inclined upward
  • An arc-shaped, upper portion of the curved portion of the p-well layer is provided with a secondary epitaxial p-type layer inclined to the vertical central axis of the cell structure, and two of the second epitaxial p-type layers are provided with a rectangular cross section
  • the implanted n-layer, the secondary epitaxial p-type layer and the implanted n-layer are sequentially provided with an "arched" gate oxide layer, a polysilicon layer and an isolation passivation layer.
  • the invention forms an inclined mesa by etching, and then grows a high-quality p-type layer by a secondary epitaxy method, and forms a MOS gate structure in the bevel portion after thermal oxidation.
  • the gate applied voltage is turned on to form a channel, and electrons pass from the source region through the channel to the top of the mesa, and then flow from the top of the mesa through the JFET region and the drift region to the drain region.
  • the length of the bevel and the tilt angle between the bevel and the substrate can be controlled by an etching process.
  • the length of the secondary epitaxial p-type layer determines the length of the channel, and generally controls the length of the secondary epitaxial p-type layer to be between 0.2 and 1 ⁇ m.
  • the angle between the secondary epitaxial p-type layer and the substrate determines the angle of the channel plane, and the crystal plane with higher channel electron mobility can be selected as the channel plane, and the inclination angle of the general secondary epitaxial p-type layer Between 20-80 °.
  • the secondary epitaxial p-type layer has a concentration of 1E15-1E18 cm -3 and a thickness of 200 nm to 1000 nm. The choice of concentration is related to the design of the threshold voltage.
  • the entire device structure consists of an active region and a junction termination region (including dicing trenches).
  • a simple parallel connection of multiple cells forms an active region, and all gate regions of the active region are electrically interconnected and are on one side of the active region.
  • the gate electrode compact is taken out. All of the source regions are also electrically interconnected. In the upper portion of the active region, the source electrode compact is taken out by dielectric isolation from other portions of the active region.
  • the junction termination structure of the device can be a field limiting ring structure or a JTE structure, or a JTE combined field limiting ring structure.
  • the width of the mesa is designed to take into account the resistance of the JFET region. It also takes into account the pinch-off effect of the p-well region on the JFET region, which reduces the electric field at the gate dielectric on the mesa and increases the gate reliability.
  • the mesogenic structure has a mesa width of 1.5-6 ⁇ m.
  • the invention also provides a method for preparing a slab channel SiC MOSFET device, the specific steps are as follows:
  • the schematic diagram contains only one cell, but also includes the gate and source electrode pads and the junction termination structure.
  • a first mask layer is formed, and the first mask can be made of a medium, such as SiO 2 .
  • the dielectric mask layer pattern can be formed by ICP etching, and the morphology of the photoresist and the etching selectivity of the SiO 2 /glue can be controlled to control the morphology of the SiO 2 mask.
  • the doping concentration and thickness of the epitaxial layer are determined by the breakdown voltage design of the device.
  • SiC is etched by ICP, and by controlling the SiC/SiO 2 selection ratio, the slope angle of the SiC mesa can be controlled.
  • the remaining SiO2 is used as a mask for ion implantation, and Al ions are implanted, and ions are also implanted under the slope to form doping of the p-well region and doping of the termination region.
  • the doping concentration is between 1E18 and 5E19 cm -3 and the depth is between 0.3 ⁇ m and 1 ⁇ m.
  • the thickness of the mask layer must be able to block the p-well ion implantation after the etching is consumed.
  • the first mask layer is removed and the RCA is cleaned. Sacrificial oxidation is carried out and the oxide layer is removed with diluted HF or BOE.
  • the thickness of the oxide layer is between about 10 nm and 100 nm. Sacrificial oxidation removes defects and surface damage layers from etching and improves surface roughness.
  • a secondary epitaxial growth is performed to grow a p-type layer.
  • the concentration of the secondary epitaxial p-type layer may be between 1E15-1E18 cm -3 and the thickness may be between 200 nm and 1000 nm, and the thickness shall take into account the consumption of sacrificial oxidation and thermal oxidation in subsequent processes. The choice of concentration is related to the design of the threshold voltage.
  • a second mask layer is formed.
  • the second mask layer can be a dielectric or a photoresist.
  • the mask protects the rest of the surface, revealing the top of the countertop.
  • Ion implantation is performed, and the implanted ions may be N ions or P ions, and the implanted p-layers having a depth and concentration greater than that of the second epitaxy are implanted, and the n-type doping is formed after the p-type doping, and is connected to the JFET region.
  • the second mask layer is removed, and after cleaning, the third mask layer is formed.
  • the third mask layer may be a medium or a photoresist, and N ions or P ions are implanted at a concentration of about 1E19-3E20 cm -3 , and the depth is About 200-1000 nm, slightly larger than the epitaxial p-layer, forming n++ source region doping.
  • the third mask layer is removed, and the fourth mask layer is formed after cleaning.
  • the fourth mask layer may be a dielectric or a photoresist, and Al ions are implanted to form a source region p++ doped, and the p++ concentration is greater than 1E19 cm -3 , and the depth is Slightly larger than the epitaxial p-layer, in electrical communication with the p-well.
  • a thin layer of graphite is deposited on the surface and subjected to high temperature activation annealing at a temperature between 1700 ° C and 1950 ° C for a period of between 1 minute and 30 minutes.
  • the fifth mask layer is formed, and the first JTE region is etched using the fifth mask layer.
  • the fifth mask layer is removed, the sixth mask layer is formed after cleaning, and the second JTE region is etched by the sixth mask layer.
  • the sixth mask layer is removed, and after cleaning, the seventh mask layer is formed, and the device isolation region is etched by the seventh mask layer.
  • the JTE area of the junction terminal can be one area or multiple areas. For a typical 900V-3300V SiC MOSFET, two areas are suitable, and multiple JTE areas can be set for higher withstand voltage requirements. Sacrificial oxidation is carried out and the oxide layer is removed with diluted HF or BOE.
  • the thickness of the oxide layer is between about 10 nm and 50 nm.
  • Sacrificial oxidation removes defects and surface damage layers from etching and improves surface roughness.
  • the 50-60 nm SiO 2 layer is grown by thermal oxidation, and the thermal oxidation temperature is preferably from 1200 ° C to 1500 ° C.
  • Annealing (POA) is carried out after oxidation, and the annealing temperature is preferably 1200 ° C to 1350 ° C, and the atmosphere is preferably N 2 O or NO. POA annealing can effectively passivate interface defects and reduce interface states.
  • a highly doped polysilicon layer is formed.
  • the polysilicon doping may be on-site doping during CVD growth, or may be performed by implant annealing after deposition to form doping. This process is well known to those skilled in the art and will not be described herein. Etching and patterning of the polysilicon is then performed to form a gate contact.
  • a first passivation layer such as 200 nm SiO2 is deposited.
  • the metal is deposited on the back side and subjected to rapid thermal annealing to form an ohmic contact.
  • the source region is photolithographically etched, etched out of the dielectric window, and metal is deposited in the window and patterned by photolithographic etching.
  • a rapid thermal anneal is then performed to form an ohmic contact in the source region.
  • the ohmic contact of the drain and source can also be completed by one annealing after the metal is sequentially deposited.
  • a second passivation layer such as SiO2/SiN, is deposited to a thickness of 200 nm/300 nm, or may be SiOxNy, and a window is etched in a region where the source region and the gate electrode block metal are interconnected with the gate region.
  • the first and second passivation layers form an isolation passivation layer between the source electrode compact metal and the cell.
  • the thickness of Ti is 20-200 nm
  • the thickness of Al or AlSi or AlSiCu or AlCu is approximately 4-8 ⁇ m
  • the metal at the non-electrode briquettes is etched away.
  • the gate electrode block metal is electrically connected to the gate of each cell (not shown).
  • the coating and patterning of the polyimide is carried out, followed by baking and curing to form an effective surface passivation protective layer.
  • the electrode metal on the back side is deposited, such as TiNiAg or VNiAg. This process is well known to engineers in the field.

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Abstract

一种斜面沟道的SiC MOSFET器件及其制作方法，该SiC MOSFET器件有源区的原胞结构从下至上依次为漏极、n++衬底、n‑漂移层、左右对称设置的两个p‑well层、p++区和n++区、源电极；p‑well层相对的一侧均呈向上倾斜的弧形，p‑well层的弧形部分的上方设置有向原胞结构的竖向中轴线倾斜的二次外延p型层，两个二次外延p型层的中间设置有注入n层，二次外延p型层和注入n层的上方依次设置有呈"拱形"的栅氧化层、多晶硅层和隔离钝化层。

Description

一种斜面沟道的SiC MOSFET器件及其制备方法 技术领域
本发明属于半导体领域，具体涉及一种斜面沟道的SiC MOSFET器件及其制备方法。
背景技术
平面型SiC MOSFET经过行业内多年的研究，已经有一些厂商率先推出了商业化产品。但是，依旧存在MOS沟道迁移率低和产品阈值电压一致性难控制等问题。这是由于常规的SiC平面型MOSFET的结构和工艺所致，常规MOSFET中p阱(p-well)是通过离子注入实现p型掺杂的，这是业界的一般方法，结构如图1所示。这种注入后再高温激活退火形成掺杂的方法，不可避免的存在一些问题。首先是无法完全消除或修复注入带来的缺陷，其次是高温激活退火的过程会使表面退化，形貌变差，从而增加沟道电子的表面散射。另外，激活退火的温度越高，激活率和缺陷的修复率也越高，但是表面退化更严重。同时，SiC MOS栅介质生长本身就有很大的难度。因此，当前SiC MOSFET器件的沟道迁移率都非常低，只有20-30cm2/Vs，需要更好的设计或工艺进一步改善。
为了改善这种情况，目前主要是采用两种方法，一种是采用U型沟槽MOSFET结构(UMOSFET)，如图2所示，UMOSFET结构具有更高的原胞密度和单位面积栅宽，同时沟道的p阱是外延方法形成的，因此具有更高的沟道迁移率和电流密度，但是沟道是在刻蚀层表面形成的，刻蚀产生的缺陷和表面粗糙不可避免地对MOS栅质量有影响。另一种方法是VMOSFET结构，如图3所示。VMOSFET结构的V形槽用SiC在高温腐蚀下的各项异性导致的各晶面腐蚀速率不一致所形成，存在着工艺难以控制的问题。同时槽底部的尖角也容易引起电场集中，可靠性差。
发明内容
针对现有技术中存在的问题，本发明的目的在于提供一种斜面沟道的SiC MOSFET器件，其利用高电子迁移率的晶面作为沟道平面，并且在高质量的二次外延的SiC表面形成沟道，可以有效提高MOS栅的质量和沟道迁移率，减低器件的导通电阻。本发明的另一目的在于提供一种制备斜面沟道的SiC MOSFET器件的方法。
为实现上述目的，本发明采用以下技术方案：
一种斜面沟道的SiC MOSFET器件，所述SiC MOSFET器件有源区的原胞结构从下至上依次为漏极、n++衬底(浓度大于1E18cm-3)、n-漂移层、左右对称设置的两个p-well层、设置在所述p-well层上的p++区和n++区、设置在所述p++区和n++区上的源电极；两个p-well层相对的一侧均呈向上倾斜的弧形，p-well层的弧形部分的上方设置有向原胞结构的竖向中轴线倾斜的二次外延p型层，两个所述二次外延p型层的中间设置有截面呈长方形的注入n层，二次外延p型层和所述注入n层的上方依次设置有呈“拱形”的栅氧化层、多晶硅层和隔离钝化层。
进一步，在所述的n-漂移层和导电衬底之间优选地有一薄层n型缓冲层，缓冲层浓度在1E18cm-3左右，厚度约1μm左右。
进一步，所述斜面上二次外延p型层的长度为0.2-1μm；二次外延p型层与衬底基板之间的夹角为20-80°。
进一步，所述二次外延p型层的浓度为1E15-1E18cm-3，厚度为200nm-500nm。
进一步，所述原胞结构的台面顶部宽度为1.5-6μm。
进一步，所述器件结构中n型与p型相对而言，即同样适用于p+型衬底上，其他层的导电类型也相反即可。
进一步，所述器件结构中原胞的平面结构可以是条形、矩形、六角形等各种结构。
进一步，所述器件结构也可适用于Si、GaN、GaO等其他半导体材料，并不仅限于SiC材料。制备方法会有所区别。
一种制备斜面沟道的SiC MOSFET器件的方法，所述方法包括如下步骤：
1)在SiC外延材料上，做上第一掩膜层；
2)用ICP的方法刻蚀SiC，通过控制SiC/SiO2选择比，控制SiC台面的斜面角度；刻蚀完成后，剩余的SiO2作为离子注入的掩膜，注入Al离子，同时斜面下也注入了离子，形成p-well区掺杂和结终端区的掺杂；
3)去除第一掩膜层，RCA清洗；进行牺牲氧化，并用稀释的HF或BOE去除氧化层；然后进行二次外延生长，生长一层p型层；
4)做上第二掩膜层，用第二掩膜层保护表面的其他部分，露出台面的顶部；进行离子注入，注入的离子可以为N离子或者P离子，注入形成掺杂的深度和浓度都大于二次外延的p层，中和p型掺杂后形成n型掺杂，与JFET区连通；去除第二掩膜层，清洗后做上第三掩膜层，之后进行N离子或P离子注入，形成n++源区掺杂；去除第三掩膜层，清洗后做上第四掩膜层，Al离子注入，形成源区p++掺杂，与p-well形成电连通；去除第四掩膜层，RCA 清洗；表面淀积一层石墨层，进行高温激活退火；
5)做上第五掩膜层，利用第五掩膜层刻蚀出第一JTE区；去除第五掩膜层，清洗后做上第六掩膜层，利用第六掩膜层刻蚀出第二JTE区；去除第六掩膜层，清洗后做上第七掩膜层，利用第七掩膜层刻蚀出器件隔离区域；进行牺牲氧化，并用稀释的HF或BOE去除氧化层；用热氧化的方法生长50-60nm的SiO2层，氧化后再进行退火；
6)制作高掺杂的多晶硅层；然后进行多晶硅的刻蚀和图形化，形成栅接触；
7)淀积第一钝化层，背面淀积金属，进行快速热退火形成欧姆接触；源区进行光刻、刻蚀，刻蚀出介质窗口，在窗口内淀积金属并通过光刻刻蚀的方法图形化；再进行快速热退火，在源区形成欧姆接触；漏极、源极的欧姆接触也可以在依次淀积完金属后一次退火完成；淀积第二钝化层，在源区、栅电极压块金属与栅区互联的区域刻蚀出窗口；第一、第二钝化层形成源电极压块金属与原胞之间的隔离钝化层；
8)淀积厚电极金属，刻蚀掉非电极压块处的金属；进行聚酰亚胺的涂布和图形化，再进行烘烤固化，形成有效的表面钝化保护层；最后淀积背面的电极金属。
进一步，步骤2)中的p-well区掺杂和结终端区的掺杂的浓度在1E18-5E19cm-3之间，深度在0.3μm-1μm之间。
进一步，步骤3)中牺牲氧化的氧化层的厚度在10nm-100nm之间，二次外延p型层的浓度在1E15-1E18cm-3之间，厚度在200nm-1000nm之间。
进一步，步骤4)中N离子或P离子注入的浓度大于1E19cm-3，深度在200-1000nm之间；高温激活退火的温度在1700℃-1950℃之间，时间在1-30分钟之间。
进一步，步骤5)中牺牲氧化的氧化层的厚度在10nm-50nm之间，所述SiO2层的厚度为50-60nm，热氧化温度为1200℃-1500℃，退火温度为1200℃-1350℃，气氛在N2O或NO气氛下。
进一步，步骤7)中第一钝化层为200nm厚的SiO2；第二钝化层为SiO2/SiN，厚度分别为200nm/300nm，或者为SiOxNy；步骤8)中厚电极金属为Ti/Al或Ti/AlSi或Ti/AlSiCu或Ti/AlCu，Ti的厚度为20-200nm，Al或AlSi或AlSiCu或AlCu的厚度大概是4-8μm。
本发明具有以下有益技术效果：
本申请利用高电子迁移率的晶面作为沟道平面，并且在高质量的二次外延的SiC表面形成沟道，可以有效提高MOS栅的质量和沟道迁移率，减低器件的导通电阻。
附图说明
图1为现有技术中的平面型SiC MOSFET原胞结构的剖面结构示意图；
图2为现有技术中U型沟槽SiC MOSFET原胞结构的剖面结构示意图；
图3为现有技术中V型沟槽SiC MOSFET原胞结构的剖面结构示意图；
图4为本发明的SiC MOSFET原胞结构的剖面结构示意图；
图5为本发明的SiC MOSFET器件的平面视图；
图6为本发明的SiC MOSFET原胞结构制备过程中做完第一掩膜层后的结构示意图；
图7为本发明的SiC MOSFET原胞结构制备过程中刻蚀完SiC台面进行离子注入后的结构示意图；
图8为本发明的SiC MOSFET原胞结构制备过程中二次外延生长p型层后的结构示意图；
图9为本发明的SiC MOSFET原胞结构制备过程中各个区域完成离子注入和激活退火后的结构示意图；
图10为本发明的SiC MOSFET原胞结构制备过程中JTE刻蚀、热氧化形成栅介质后的结构示意图；
图11为本发明的SiC MOSFET原胞结构制备过程中多晶硅栅接触完成后的结构示意图；
图12为本发明的SiC MOSFET原胞结构制备过程中源、漏欧姆接触完成后的结构示意图；
图13为本发明的SiC MOSFET原胞结构制备完成后的结构示意图。
具体实施方式
下面，参考附图，对本发明进行更全面的说明，附图中示出了本发明的示例性实施例。
然而，本发明可以体现为多种不同形式，并不应理解为局限于这里叙述的示例性实施例。
而是，提供这些实施例，从而使本发明全面和完整，并将本发明的范围完全地传达给本领域的普通技术人员。
如图4所示，本发明了提供了一种斜面沟道的SiC MOSFET器件，该SiC MOSFET器件有源区的原胞结构从下至上依次为漏极、n++衬底、n-漂移层、左右对称设置的两个p-well层、设置在p-well层上的p++区和n++区、设置在p++区和n++区上的源电极；两个p-well层相对的一侧均呈向上倾斜的弧形，p-well层的弧形部分的上方设置有向原胞结构的竖向中轴线倾斜的二次外延p型层，两个所述二次外延p型层的中间设置有截面呈长方形的注入n层，二次外延p型层和所述注入n层的上方依次设置有呈“拱形”的栅氧化层、多晶硅层和隔离钝化层。
本发明通过刻蚀形成倾斜的台面，再通过二次外延的方法生长一层高质量的p型层，经过热氧化后在斜面部分形成MOS栅结构。导通工作情况下，栅施加电压开启，形成沟道，电子由源区经过沟道到台面顶部，再从台面顶部流经JFET区和漂移区达到漏区。可以通过刻蚀工艺控制斜面的长度和斜面与衬底基板之间的倾角。二次外延p型层的长度决定了沟道的长度，一般地控制二次外延p型层的长度为0.2-1μm之间。二次外延p型层的与衬底基板之间的角度决定了沟道平面的角度，可选择沟道电子迁移率较高的晶面作为沟道平面，一般的二次外延p型层的倾角在20-80°之间。二次外延p型层的浓度为1E15-1E18cm-3，厚度为200nm-1000nm。浓度的选择与阈值电压的设计有关。
如图5所示，为整个器件平面视图的一个示例图。整个器件结构由有源区和结终端区(包括划片槽)组成，多个原胞的简单并联形成有源区，在有源区所有的栅极区电学互联，并在有源区的一边引出栅电极压块。所有的源极区也进行电学互联，在有源区的上部，与有源区其他部分进行介质隔离引出源电极压块。器件的结终端结构可以是场限环结构或JTE结构，或者JTE结合场限环结构。
台面的宽度设计既要考虑到JFET区的电阻，同时也要考虑到p-well(p阱)区对JFET区的夹断效果，可以减少台面上部栅介质处的电场，增加栅可靠性。优选地，原胞结构的台面宽度为1.5-6μm。
本发明还提供了一种斜面沟道的SiC MOSFET器件的制备方法，具体步骤如下：
为了简化以及更清楚的示意器件结构和制作过程，结构示意图中只包含一个原胞，但同时包含了栅、源的电极压块和结终端区结构。
如图6所示，在SiC外延材料上，做上第一掩膜层，第一掩膜可以用介质，如可以选择SiO2。介质掩膜层图形可以用ICP刻蚀的方法形成，控制光刻胶的形貌以及SiO2/胶的刻蚀选择比，即可控制SiO2掩膜的形貌。外延层的掺杂浓度、厚度由器件的击穿电压设计而定。
如图7所示，用ICP的方法刻蚀SiC，通过控制SiC/SiO2选择比，可以控制SiC台面的斜面角度。刻蚀完成后，剩余的SiO2作为离子注入的掩膜，注入Al离子，同时斜面下也注入了离子，形成p-well区掺杂和结终端区的掺杂。掺杂的浓度在1E18-5E19cm-3之间，深度在0.3μm-1μm之间。掩膜层的厚度必须根据刻蚀消耗后剩余部门依旧能够阻挡p-well离子注入得到。
如图8所示，去除第一掩膜层，RCA清洗。进行牺牲氧化，并用稀释的HF或BOE去除氧化层。氧化层的厚度约在10nm-100nm之间。牺牲氧化可以去除刻蚀带来的缺陷和表面损伤层，改善表面的粗糙度。进行二次外延生长，生长一层p型层。二次外延p型层的浓度可以为 1E15-1E18cm-3之间，厚度可以为200nm-1000nm之间，厚度要考虑到后续工艺中牺牲氧化和热氧化的消耗。浓度的选择与阈值电压的设计有关。
如图9所示，做上第二掩膜层。第二掩膜层可以是介质或则光刻胶。掩膜保护表面的其他部分，露出台面的顶部。进行离子注入，注入的离子可以为N离子或者P离子，注入形成掺杂的深度和浓度都大于二次外延的p层，中和p型掺杂后形成n型掺杂，与JFET区连通。去除第二掩膜层，清洗后做上第三掩膜层，第三掩膜层可以是介质或则光刻胶，N离子或P离子注入，浓度约为1E19-3E20cm-3之间，深度约在200-1000nm，略微大于外延的p层，形成n++源区掺杂。去除第三掩膜层，清洗后做上第四掩膜层，第四掩膜层可以是介质或则光刻胶，Al离子注入，形成源区p++掺杂，p++浓度大于1E19cm-3，深度略微大于外延的p层，与p-well形成电连通。去除第四掩膜层，RCA清洗。表面淀积一薄层石墨层，进行高温激活退火，退火的温度为1700℃-1950℃之间，时间在1分钟-30分钟之间。
如图10所示，做上第五掩膜层，利用第五掩膜层刻蚀出第一JTE区。去除第五掩膜层，清洗后做上第六掩膜层，利用第六掩膜层刻蚀出第二JTE区。去除第六掩膜层，清洗后做上第七掩膜层，利用第七掩膜层刻蚀出器件隔离区域。结终端的JTE区可以为一个区或多个区，对于一般的900V-3300V SiC MOSFET比较合适的是两个区，对于更高的耐压要求可以设置多个JTE区。进行牺牲氧化，并用稀释的HF或BOE去除氧化层。氧化层的厚度约在10nm-50nm之间。牺牲氧化可以去除刻蚀带来的缺陷和表面损伤层，改善表面的粗糙度。用热氧化的方法生长50-60nm的SiO2层，热氧化温度优选在1200℃-1500℃。氧化后再进行退火(POA),退火温度在1200℃-1350℃为佳，气氛在N2O或NO为佳。POA退火可以有效钝化界面缺陷，减少界面态。
如图11所示，制作高掺杂的多晶硅层。多晶硅掺杂可以是CVD生长时临场掺杂，也可以在淀积后再进行注入退火形成掺杂，这个工艺为本领域内工程师所熟知，在此不再赘述。然后进行多晶硅的刻蚀和图形化，形成栅接触。
如图12所示，淀积第一钝化层，如200nm SiO2。背面淀积金属，进行快速热退火形成欧姆接触。源区进行光刻、刻蚀，刻蚀出介质窗口，在窗口内淀积金属并通过光刻刻蚀的方法图形化。再进行快速热退火，在源区形成欧姆接触。漏极、源极的欧姆接触也可以在依次淀积完金属后一次退火完成。淀积第二钝化层，如SiO2/SiN，厚度分别为200nm/300nm，或者可以是SiOxNy，在源区、栅电极压块金属与栅区互联的区域刻蚀出窗口。第一、第二钝化层形成源电极压块金属与原胞之间的隔离钝化层。
如图13所示，如Ti/Al或Ti/AlSi或Ti/AlSiCu或Ti/AlCu，Ti的厚度为20-200nm， Al或AlSi或AlSiCu或AlCu的厚度大概是4-8μm，刻蚀掉非电极压块处的金属。栅电极压块金属与各个原胞的栅极都是电学相连的(图中没有显示)。进行聚酰亚胺的涂布和图形化，再进行烘烤固化，形成有效的表面钝化保护层。最后淀积背面的电极金属，如可以为TiNiAg或VNiAg等。此工艺为本领域内工程师所熟知。
上面所述只是为了说明本发明，应该理解为本发明并不局限于以上实施例，符合本发明思想的各种变通形式均在本发明的保护范围之内。

Claims (11)

  1. 一种斜面沟道的SiC MOSFET器件，所述SiC MOSFET器件有源区的原胞结构从下至上依次为漏极、n++衬底、n-漂移层、左右对称设置的两个p-well层、设置在所述p-well层上的p++区和n++区、设置在所述p++区和n++区上的源电极；其特征在于，两个p-well层相对的一侧均呈向上倾斜的弧形，p-well层的弧形部分的上方设置有向原胞结构的竖向中轴线倾斜的二次外延p型层，两个所述二次外延p型层的中间设置有截面呈长方形的注入n层，二次外延p型层和所述注入n层的上方依次设置有呈“拱形”的栅氧化层、多晶硅层和隔离钝化层。
  2. 根据权利要求1所述的斜面沟道的SiC MOSFET器件，其特征在于，所述斜面上二次外延p型层的长度为0.2-1μm；二次外延p型层与衬底基板之间的夹角为20-80°。
  3. 根据权利要求1所述的斜面沟道的SiC MOSFET器件，其特征在于，所述二次外延p型层的浓度为1E15-1E18cm-3，厚度为200nm-1000nm。
  4. 根据权利要求1所述的斜面沟道的SiC MOSFET器件，其特征在于，所述原胞结构的台面顶部宽度为1.5-6μm。
  5. 根据权利要求1所述的斜面沟道的SiC MOSFET器件，其特征在于，所述SiC MOSFET器件的原胞的平面俯视结构为矩形、条形或六角形。
  6. 一种制备权利要求1-5任一所述的斜面沟道的SiC MOSFET器件的方法，其特征在于，所述方法包括如下步骤：
    1)在SiC外延材料上，做上第一掩膜层；
    2)用ICP的方法刻蚀SiC，通过控制SiC/SiO2选择比，控制SiC台面的斜面角度；刻蚀完成后，剩余的SiO2作为离子注入的掩膜，注入Al离子，同时斜面下也注入了离子，形成p-well区掺杂和结终端区的掺杂；
    3)去除第一掩膜层，RCA清洗；进行牺牲氧化，并用稀释的HF或BOE去除氧化层；然后进行二次外延生长，生长一层p型层；
    4)做上第二掩膜层，用第二掩膜层保护表面的其他部分，露出台面的顶部；进行离子注入，注入的离子可以为N离子或者P离子，注入形成掺杂的深度和浓度都大于二次外延的p层，中和p型掺杂后形成n型掺杂，与JFET区连通；去除第二掩膜层，清洗后做上第三掩膜层，之后进行N离子或P离子注入，形成n++源区掺杂；去除第三掩膜层，清洗后做上第四掩膜层，Al离子注入，形成源区p++掺杂，与p-well形成电连通；去除第四掩膜层，RCA清洗；表面淀积一层石墨层，进行高温激活退火；
    5)做上第五掩膜层，利用第五掩膜层刻蚀出第一JTE区；去除第五掩膜层，清洗后做上第六掩膜层，利用第六掩膜层刻蚀出第二JTE区；去除第六掩膜层，清洗后做上第七掩膜层，利用第七掩膜层刻蚀出器件隔离区域；进行牺牲氧化，并用稀释的HF或BOE去除氧化层；用热氧化的方法生长50-60nm的SiO2层，氧化后再进行退火；
    6)制作高掺杂的多晶硅层；然后进行多晶硅的刻蚀和图形化，形成栅接触；
    7)淀积第一钝化层，背面淀积金属，进行快速热退火形成欧姆接触；源区进行光刻、刻蚀，刻蚀出介质窗口，在窗口内淀积金属并通过光刻刻蚀的方法图形化；再进行快速热退火，在源区形成欧姆接触；漏极、源极的欧姆接触也可以在依次淀积完金属后一次退火完成；淀积第二钝化层，在源区、栅电极压块金属与栅区互联的区域刻蚀出窗口；第一、第二钝化层形成源电极压块金属与原胞之间的隔离钝化层；
    8)淀积厚电极金属，刻蚀掉非电极压块处的金属；进行聚酰亚胺的涂布和图形化，再进行烘烤固化，形成有效的表面钝化保护层；最后淀积背面的电极金属。
  7. 根据权利要求5所述的斜面沟道的SiC MOSFET器件的制备方法，其特征在于，步骤2)中的p-well区掺杂和结终端区的掺杂的浓度在1E18-5E19cm-3之间，深度在0.3μm-1μm之间。
  8. 根据权利要求6所述的斜面沟道的SiC MOSFET器件的制备方法，其特征在于，步骤3)中牺牲氧化的氧化层的厚度在10nm-100nm之间，二次外延p型层的浓度在1E15-1E18cm-3之间，厚度在200nm-1000nm之间。
  9. 根据权利要求6所述的斜面沟道的SiC MOSFET器件的制备方法，其特征在于，步骤4)中N离子或P离子注入的浓度大于1E19cm-3，深度在200-1000nm之间；高温激活退火的温度在1700℃-1950℃之间，时间在1-30分钟之间。
  10. 根据权利要求6所述的斜面沟道的SiC MOSFET器件的制备方法，其特征在于，步骤5)中牺牲氧化的氧化层的厚度在10nm-50nm之间，所述SiO2层的厚度为50-60nm，热氧化温度为1200℃-1500℃，退火温度为1200℃-1350℃，气氛在N2O或NO气氛下。
  11. 根据权利要求6所述的斜面沟道的SiC MOSFET器件的制备方法，其特征在于，步骤7)中第一钝化层为200-500nm厚的SiO2；第二钝化层为SiO2/SiN，厚度分别为200nm/300nm，或者为SiOxNy；步骤8)中厚电极金属为Ti/Al或Ti/AlSi或Ti/AlSiCu或Ti/AlCu，其中，Ti的厚度为20-200nm，Al或AlSi或AlSiCu或AlCu的厚度是4-8μm。
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