WO2018129784A1 - 一种goa电路及液晶显示器 - Google Patents

一种goa电路及液晶显示器 Download PDF

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Publication number
WO2018129784A1
WO2018129784A1 PCT/CN2017/073593 CN2017073593W WO2018129784A1 WO 2018129784 A1 WO2018129784 A1 WO 2018129784A1 CN 2017073593 W CN2017073593 W CN 2017073593W WO 2018129784 A1 WO2018129784 A1 WO 2018129784A1
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Prior art keywords
transistor
signal
gate
pull
source
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PCT/CN2017/073593
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English (en)
French (fr)
Inventor
杜鹏
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深圳市华星光电技术有限公司
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Priority to KR1020197023707A priority Critical patent/KR102253207B1/ko
Priority to JP2019538235A priority patent/JP6789400B2/ja
Priority to US15/509,499 priority patent/US10304404B2/en
Priority to EP17891237.4A priority patent/EP3570269B1/en
Publication of WO2018129784A1 publication Critical patent/WO2018129784A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the field of liquid crystals, and in particular to a GOA circuit and a liquid crystal display.
  • Existing GOA Gate driver on The array circuit includes a cascaded GOA unit and a plurality of pull-down sustain circuits, wherein one GOA unit requires one or two pull-down sustain circuits for maintaining pull-down.
  • the pull-down sustain circuit is generally composed of a plurality of transistors. Since the number of transistors is large, the pull-down sustain circuit tends to occupy a large amount of space. When the number of pull-down sustain circuits is large, the width of the wiring area of the GOA circuit is increased, thereby increasing the design difficulty of the narrow border of the liquid crystal display.
  • the technical problem to be solved by the present invention is to provide a GOA circuit and a liquid crystal display, which can reduce the width of the wiring area of the GOA circuit, thereby reducing the design difficulty of the narrow frame of the liquid crystal display.
  • a technical solution adopted by the present invention is to provide a GOA circuit for a liquid crystal display, the GOA circuit including a plurality of cascaded GOA units, wherein a plurality of cascaded GOA units are used in Controlling a plurality of clock signals to respectively output a gate drive signal of the first level signal to charge a corresponding horizontal scan line in the display area; the GOA circuit further comprising a plurality of pull-down sustain circuits, wherein each pull-down sustain circuit Corresponding to at least two GOA units, each of the pull-down maintaining circuits is configured to maintain a gate driving signal outputted by the corresponding at least two GOA units during the inactive period as a second level signal; wherein, when the number of the plurality of clock signals is N Each of the two pull-down sustain circuits corresponds to N/2 GOA units; wherein the GOA unit includes an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor,
  • the drain of the thirteenth transistor outputs a current stage enable signal, and the drain of the fourteenth transistor and the other end of the second capacitor, respectively.
  • the source of the fifteenth transistor is an output gate drive signal, and the drains of the twelfth transistor and the fifteenth transistor are connected to a constant voltage negative power supply.
  • the pull-down maintaining circuit comprises an input module and an output module
  • the input module includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and a first capacitor, wherein a gate and a source of the transistor are connected to the source of the second transistor and connected to the first input signal, and the drain of the first transistor is respectively connected to the source of the third transistor and the gate of the fourth transistor, and the second transistor
  • the gates are respectively connected to the gate of the third transistor, the source and the gate of the fifth transistor, the drain of the second transistor is connected to the source of the fourth transistor, and the drain of the fifth transistor is respectively connected to the sixth transistor a drain, a source of the seventh transistor, one end of the first capacitor, and a gate of the ninth transistor, and the gate and the source of the sixth transistor are connected to the second input signal, and the gate of the seventh transistor
  • the gate of the ten transistor is connected to the reset signal
  • the gate and the source of the eighth transistor are
  • the output module includes a plurality of transistors, the number of the plurality of transistors being equal to the number N of the plurality of clock signals, the gates of the plurality of transistors being connected to each other and being connected to the drain of the ninth transistor in the input module, the drains of the plurality of transistors being mutually connected After being connected, the fourth input signal is connected, and the sources of the plurality of transistors are respectively connected to the common signal point and the gate driving signal of the corresponding N/2 GOA units.
  • another technical solution adopted by the present invention is to provide a GOA circuit for a liquid crystal display, the GOA circuit comprising a plurality of cascaded GOA units, wherein a plurality of cascaded GOA units are used Outputting a gate drive signal of the first level signal to control a corresponding horizontal scan line in the display area under control of the plurality of clock signals; the GOA circuit further includes a plurality of pull-down sustain circuits, wherein each pull-down is maintained The circuit corresponds to at least two GOA units, and each of the pull-down maintaining circuits is configured to maintain the gate driving signal outputted by the corresponding at least two GOA units during the inactive period as the second level signal.
  • each or every two pull-down sustain circuits correspond to N/2 GOA units.
  • the pull-down maintaining circuit comprises an input module and an output module
  • the input module includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and a first capacitor, wherein a gate and a source of the transistor are connected to the source of the second transistor and connected to the first input signal, and the drain of the first transistor is respectively connected to the source of the third transistor and the gate of the fourth transistor, and the second transistor
  • the gates are respectively connected to the gate of the third transistor, the source and the gate of the fifth transistor, the drain of the second transistor is connected to the source of the fourth transistor, and the drain of the fifth transistor is respectively connected to the sixth transistor a drain, a source of the seventh transistor, one end of the first capacitor, and a gate of the ninth transistor, and the gate and the source of the sixth transistor are connected to the second input signal, and the gate of the seventh transistor
  • the gate of the ten transistor is connected to the reset signal
  • the gate and the source of the eighth transistor are
  • the output module includes a plurality of transistors, the number of the plurality of transistors being equal to the number N of the plurality of clock signals, the gates of the plurality of transistors being connected to each other and being connected to the drain of the ninth transistor in the input module, the drains of the plurality of transistors being mutually connected After being connected, the fourth input signal is connected, and the sources of the plurality of transistors are respectively connected to the common signal point and the gate driving signal of the corresponding N/2 GOA units.
  • the first input signal of the M-th stage pull-down maintaining circuit is a constant voltage positive power supply
  • the second input signal is the M-th
  • the first stage input signal is a constant voltage negative power supply
  • the drain of the ninth transistor of the Mth stage pull-down sustain circuit outputs the Mth stage level signal
  • the third input signal of the +1 stage pull-down sustain circuit is in opposite phase.
  • the first input signal of the M-th stage pull-down maintaining circuit is the first low-frequency signal
  • the second input signal is the M-2
  • the fourth input signal is a constant voltage negative power source
  • the first input signal of the M+1 stage pull-down maintaining circuit is the second low frequency signal
  • the second input signal is the M-1 level signal
  • the third The input signal is a second control signal
  • the fourth input signal is a constant voltage negative power supply
  • the Mth stage pull-down maintaining circuit is the same as the third input signal of the M+1 stage pull-down maintaining circuit, and the adjacent two The phase of the third input signal of the pull-down sustain circuit is opposite
  • the drain of the ninth transistor of the M-th stage pull-down sustain circuit outputs the M-th stage pass signal
  • the drain of the ninth transistor of the M+1 stage pull-down sustain circuit The M+1 level transmission signal is output.
  • first low frequency signal and the second low frequency signal have opposite phases.
  • the first low frequency signal and the second low frequency signal are switched once every predetermined image frame, wherein the predetermined image frame ranges from 1 to 100 frames.
  • the M-th stage pull-down maintaining circuit and the M+1-th stage pull-down maintaining circuit alternately operate under the control of the first low frequency signal and the second low frequency signal.
  • the GOA unit includes an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a second capacitor, wherein the gate of the eleventh transistor is connected to the source and the upper a first-stage enable signal connection, the drain of the eleventh transistor being respectively connected to the source of the twelfth transistor, the gate of the thirteenth transistor, the gate of the fourteenth transistor, one end of the second capacitor, and a common signal point, The gate of the twelfth transistor is connected to the gate of the fifteenth transistor, the source of the thirteenth transistor is connected to the source of the fourteenth transistor, and is connected to the clock signal, and the drain output of the thirteenth transistor is activated at the current stage.
  • the signal, the drain of the fourteenth transistor and the other end of the second capacitor, the source of the fifteenth transistor are output gate drive signals, and the drains of the twelfth transistor and the fifteenth transistor are connected to the constant voltage negative power supply .
  • a liquid crystal display including a GOA circuit, the GOA circuit including a plurality of cascaded GOA units, wherein a plurality of cascaded GOA units a gate drive signal for respectively outputting a first level signal under control of a plurality of clock signals to charge a corresponding horizontal scan line in the display area; the GOA circuit further comprising a plurality of pull-down sustain circuits, wherein each The pull-down sustain circuit corresponds to at least two GOA units, and each pull-down sustain circuit is configured to maintain the gate drive signal output by the corresponding at least two GOA units during the inactive period as the second level signal.
  • each or every two pull-down sustain circuits correspond to N/2 GOA units.
  • the pull-down maintaining circuit comprises an input module and an output module
  • the input module includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and a first capacitor, wherein a gate and a source of the transistor are connected to the source of the second transistor and connected to the first input signal, and the drain of the first transistor is respectively connected to the source of the third transistor and the gate of the fourth transistor, and the second transistor
  • the gates are respectively connected to the gate of the third transistor, the source and the gate of the fifth transistor, the drain of the second transistor is connected to the source of the fourth transistor, and the drain of the fifth transistor is respectively connected to the sixth transistor a drain, a source of the seventh transistor, one end of the first capacitor, and a gate of the ninth transistor, and the gate and the source of the sixth transistor are connected to the second input signal, and the gate of the seventh transistor
  • the gate of the ten transistor is connected to the reset signal
  • the gate and the source of the eighth transistor are
  • the output module includes a plurality of transistors, the number of the plurality of transistors being equal to the number N of the plurality of clock signals, the gates of the plurality of transistors being connected to each other and being connected to the drain of the ninth transistor in the input module, the drains of the plurality of transistors being mutually connected After being connected, the fourth input signal is connected, and the sources of the plurality of transistors are respectively connected to the common signal point and the gate driving signal of the corresponding N/2 GOA units.
  • the first input signal of the M-th stage pull-down maintaining circuit is a constant voltage positive power supply
  • the second input signal is the M-th
  • the first stage input signal is a constant voltage negative power supply
  • the drain of the ninth transistor of the Mth stage pull-down sustain circuit outputs the Mth stage level signal
  • the third input signal of the +1 stage pull-down sustain circuit is in opposite phase.
  • the first input signal of the M-th stage pull-down maintaining circuit is the first low-frequency signal
  • the second input signal is the M-2
  • the fourth input signal is a constant voltage negative power source
  • the first input signal of the M+1 stage pull-down maintaining circuit is the second low frequency signal
  • the second input signal is the M-1 level signal
  • the third The input signal is a second control signal
  • the fourth input signal is a constant voltage negative power supply
  • the Mth stage pull-down maintaining circuit is the same as the third input signal of the M+1 stage pull-down maintaining circuit, and the adjacent two The phase of the third input signal of the pull-down sustain circuit is opposite
  • the drain of the ninth transistor of the M-th stage pull-down sustain circuit outputs the M-th stage pass signal
  • the drain of the ninth transistor of the M+1 stage pull-down sustain circuit The M+1 level transmission signal is output.
  • first low frequency signal and the second low frequency signal have opposite phases.
  • the first low frequency signal and the second low frequency signal are switched once every predetermined image frame, wherein the predetermined image frame ranges from 1 to 100 frames.
  • the M-th stage pull-down maintaining circuit and the M+1-th stage pull-down maintaining circuit alternately operate under the control of the first low frequency signal and the second low frequency signal.
  • the GOA unit includes an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a second capacitor, wherein the gate of the eleventh transistor is connected to the source and the upper a first-stage enable signal connection, the drain of the eleventh transistor being respectively connected to the source of the twelfth transistor, the gate of the thirteenth transistor, the gate of the fourteenth transistor, one end of the second capacitor, and a common signal point, The gate of the twelfth transistor is connected to the gate of the fifteenth transistor, the source of the thirteenth transistor is connected to the source of the fourteenth transistor, and is connected to the clock signal, and the drain output of the thirteenth transistor is activated at the current stage.
  • the signal, the drain of the fourteenth transistor and the other end of the second capacitor, the source of the fifteenth transistor are output gate drive signals, and the drains of the twelfth transistor and the fifteenth transistor are connected to the constant voltage negative power supply .
  • the GOA circuit and the liquid crystal display of the present invention maintain a gate drive signal of a second level signal during a non-active period by a corresponding pull-down sustain circuit, thereby reducing the pull-down sustain circuit
  • the number of GOA circuit routing areas can be reduced to meet the needs of the narrow bezel design of the liquid crystal display.
  • FIG. 1 is a schematic structural view of a GOA circuit according to a first embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of a GOA circuit according to a second embodiment of the present invention.
  • FIG. 3 is a circuit schematic diagram of the GOA unit shown in Figure 2;
  • FIG. 4 is a circuit schematic diagram of the pull-down sustain circuit shown in FIG. 2;
  • Figure 5 is a timing chart showing the operation of the pull-down sustain circuit shown in Figure 4.
  • FIG. 6 is a schematic structural diagram of a GOA circuit according to a third embodiment of the present invention.
  • FIG. 7 is a circuit schematic diagram of two pull-down sustain circuits corresponding to four GOA units shown in FIG. 6;
  • Figure 8 is a timing chart showing the operation of the M-th stage pull-down maintaining circuit shown in Figure 7;
  • FIG. 9 is an operation timing chart of the M+1th stage pull-down maintaining circuit shown in FIG. 7;
  • FIG. 10 is a schematic structural view of a liquid crystal display according to an embodiment of the present invention.
  • the GOA circuit 10 includes a plurality of cascaded GOA units 11 and a plurality of pull-down sustain circuits 12.
  • the cascaded plurality of GOA units 11 are configured to respectively output gate drive signals of the first level signals under the control of the plurality of clock signals to charge corresponding horizontal scan lines in the display area.
  • the first level signal is a high level signal.
  • Each of the pull-down maintaining circuits 12 corresponds to at least two GOA units 11 , and each of the pull-down maintaining circuits is configured to maintain the gate driving signals output by the corresponding at least two GOA units 11 during the inactive period as the second level signals.
  • the second level signal is a low level signal.
  • each or every two pull-down maintaining circuits 12 correspond to N/2 GOA units 11.
  • the GOA circuit 20 includes a plurality of cascaded GOA units 21 and a plurality of pull-down sustain circuits 22.
  • the first level signal is a high level signal.
  • the connection relationship between the cascaded plurality of GOA units 21 and the eight clock signals CKn is: the first stage GOA unit 21 is connected to the clock signal CK1, the second stage GOA unit 21 is connected to the clock signal CK2, and so on.
  • the eight-stage GOA unit 21 is connected to the clock signal CK8.
  • the loop is again looped, that is, the ninth stage GOA unit 21 is connected to the clock signal CK1, the tenth stage GOA unit 21 is connected to the clock signal CK2, and so on, and the sixteenth stage GOA unit 21 is connected to the clock signal CK8.
  • the above cycle is then continued until all GOA units 21 are connected to the corresponding clock signal.
  • FIG. 3 is a circuit schematic diagram of the GOA unit shown in FIG. 2.
  • the Nth stage GOA unit 21 includes an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, and a second capacitor C2.
  • the gate of the eleventh transistor T11 is connected to the source and connected to the previous stage start signal.
  • the upper stage enable signal is the n-4th stage start signal ST(n-4).
  • the drain of the eleventh transistor T11 is respectively connected to the source of the twelfth transistor T12, the gate of the thirteenth transistor T13, the gate of the fourteenth transistor T14, one end of the second capacitor C2, and a common signal point.
  • the common signal point is the nth common signal point Q(n).
  • the gate of the twelfth transistor T12 is connected to the gate of the fifteenth transistor T15 to output a next-stage enable signal.
  • the next-stage enable signal is the n+4th start signal ST(n+4). ).
  • the source of the thirteenth transistor T13 is connected to the source of the fourteenth transistor T14 and is connected to the clock signal CKn.
  • the drain of the thirteenth transistor T13 outputs the current stage enable signal.
  • the current stage enable signal is The nth stage starts the signal ST(n).
  • the drain of the fourteenth transistor T14 is respectively connected to the other end of the second capacitor C2 and the source of the fifteenth transistor T15 to output a gate driving signal.
  • the gate driving signal is the nth gate. Drive signal G(n).
  • the drains of the twelfth transistor T12 and the fifteenth transistor T15 are connected to the constant voltage negative power source VSS.
  • the eleventh transistor T11 is used to connect the n-4th stage enable signal ST(n-4) to turn on the potential of the nth stage common signal point Q(n) after the nth stage GOA unit 21 is turned on.
  • the fourteenth transistor T14 is for outputting the nth stage gate driving signal G(n) of the high level during the action of the nth stage GOA unit 21 to charge the corresponding horizontal scanning line, and for the thirteenth transistor
  • the nth stage enable signal ST(n) is output during the inactive period of the nth stage GOA unit to turn on the next stage, that is, the n+4th stage GOA circuit, and the twelfth transistor T12 and the fifteenth transistor T15 are used.
  • the signals of the nth stage common signal point Q(n) and the nth stage gate drive signal G(n) are pulled low during the inactive period of the nth stage GOA unit.
  • each pull-down maintaining circuit 22 corresponds to four GOA units 21, and each pull-down maintaining circuit 22 is used to maintain the gate drive output of the corresponding four GOA units 21 during inactive periods.
  • the signal is a second level signal.
  • the second level signal is a low level signal.
  • FIG. 4 is a circuit schematic diagram of the pull-down sustain circuit shown in FIG. 2.
  • the pull-down maintaining circuit 22 includes an input module 221 and an output module 222.
  • the input module 221 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a Ten transistors T10 and a first capacitor C1.
  • the gate and the source of the first transistor T1 are connected to the source of the second transistor T2 and are connected to the first input signal.
  • the gate of the second transistor T2 is connected to the gate of the third transistor T3, the source and the gate of the fifth transistor T5, and the drain of the second transistor T2 is connected to the source of the fourth transistor T4.
  • the drain of the fifth transistor T5 is respectively connected to the drain of the sixth transistor T6, the source of the seventh transistor T7, one end of the first capacitor C1, the gate of the ninth transistor T9, and the gate of the sixth transistor T6.
  • the drain of the eighth transistor T8 is connected to the source of the ninth transistor T9, and the drain of the ninth transistor T9 is respectively connected to the other end of the first capacitor C1 and the source of the tenth transistor T10, and the third transistor T3, Four transistor T4, seventh transistor T7, tenth The drain of the transistor T10 is connected to the fourth input signal.
  • the output module 222 includes eight transistors TT1, wherein the number of transistors TT1 is the same as the number of clock signals.
  • the gates of the eight transistors TT1 are connected to each other and connected to the drain of the ninth transistor T9 in the input module 221, and the drains of the eight transistors TT1 are connected to each other and connected to the fourth input signal, eight
  • the sources of the transistors TT1 are respectively connected to common signal points and gate drive signals of the corresponding four GOA units.
  • the pull-down maintaining circuit 22 is an M-th stage pull-down maintaining circuit.
  • the first input signal of the M-th stage pull-down maintaining circuit 22 is a constant voltage positive power supply VDD, and the second input signal is the M-th.
  • the first level signal is the first control signal CKP, and the fourth input signal is the constant voltage negative power source VSS.
  • the drain of the ninth transistor T9 of the Mth stage pull-down maintaining circuit 22 outputs the Mth stage pass signal P(m).
  • the third input signal of the Mth stage pull-down maintaining circuit 22 and the M+1th stage pull-down maintaining circuit 22 are opposite in phase, that is, the third input signal of the M+1th stage pull-down maintaining signal 22 is The first control signal XCKP is inverted.
  • the sources of the eight transistors TT1 in the M-th stage pull-down maintaining circuit 22 are respectively associated with the Nth, N+1th, N+2, and N+3 common signal points Q ( n), Q(n+1), Q(n+2), Q(n+3), and the Nth, N+1th, N+2, and N+3 gate drive signals G (n), G(n+1), G(n+2), G(n+3) are connected.
  • FIG. 5 is an operation timing diagram of the pull-down maintaining circuit shown in FIG. 4.
  • the Mth stage level transmission signal P(m) of the Mth stage pull-down maintaining circuit 22 is always at a low potential state.
  • the Nth to N+3th GOA unit 21 normally outputs the Nth, N+1th, N+2, and N+3 gate drive signals G(n), G. (n+1), G(n+2), G(n+3).
  • the M stage pass signal P(m) is switched to a high level, which can simultaneously control the eight transistors TT1 to the Nth stage to the Nth.
  • the Nth, N+1th, N+2, and N+3 common signal points Q(n), Q(n+1), Q(n+2) of the +3 level GOA unit 21, Q(n+3) and the Nth, N+1th, N+2, and N+3 gate drive signals G(n), G(n+1), G(n+2) , G(n+3) is all pulled down to the potential of the constant voltage negative power supply VSS.
  • the M-level pass signal P(m) in the pull-down maintaining circuit 22 is maintained at a high potential state after being switched to a high potential until the next frame of the image frame is displayed.
  • the reset signal Reset signal pulls down the M-level pass signal P(m) to a low potential.
  • Fig. 6 is a block diagram showing the structure of a GOA circuit according to a third embodiment of the present invention, which is based on a GOA circuit of eight clock signals.
  • the GOA circuit 30 includes a plurality of cascaded GOA units 31 and a plurality of pull-down maintaining circuits 32.
  • each of the two pull-down maintaining circuits 32 corresponds to four GOA units 31.
  • the GOA unit 31 in this embodiment is the same as the GOA unit 21 in the second embodiment shown in FIG. 2. For the sake of brevity, details are not described herein again.
  • FIG. 7 is a circuit schematic diagram of two pull-down sustain circuits corresponding to four GOA units shown in FIG. 6.
  • the two pull-down maintaining circuits 32 include the M-th stage pull-down maintaining circuit 32 and the M+1-th stage pull-down maintaining circuit 32.
  • the pull-down maintaining circuit 32 in this embodiment is as shown in FIG.
  • the difference between the pull-down maintaining circuit 22 in the second embodiment is:
  • the first input signal of the M-th stage pull-down maintaining circuit 32 is the first low-frequency signal PLC1
  • the second input signal is the M-2 level-level signal PP(m-2)
  • the third input signal is the second control signal CKP2
  • the fourth input signal is a constant voltage negative power supply VSS
  • the first input signal of the M+1 stage pull-down maintaining circuit 32 is the second low frequency signal PLC2
  • the second input signal is the M-1 level transmission signal PP(m-1)
  • the third input signal is the second control signal CKP2, and the fourth input signal is the constant voltage negative power supply VSS.
  • the drain of the ninth transistor T9 of the Mth stage pull-down maintaining circuit 32 outputs the Mth stage pass signal PP(m), and the drain of the ninth transistor T9 of the M+1 stage pull-down sustain circuit 32 outputs the M+th.
  • the 1st level transmits the signal PP(m+1).
  • the M-th stage pull-down maintaining circuit is the same as the third input signal of the M+1-th stage pull-down maintaining circuit, and is opposite to the phase of the third input signal of the adjacent two other pull-down maintaining circuits, that is, adjacent another
  • the third input signal of the two pull-down sustain circuits is the inverted second control signal XCKP2.
  • the phase of the first low frequency signal PLC1 and the second low frequency signal PLC2 are opposite.
  • the first low frequency signal PLC1 and the second low frequency signal PLC2 are switched once every predetermined image frame, wherein the predetermined image frame ranges from 1 to 100 frames.
  • the Mth stage pull-down maintaining circuit 32 and the M+1th stage pull-down maintaining circuit 32 alternately operate under the control of the first low frequency signal PLC1 and the second low frequency signal PLC2.
  • FIG. 8 is an operation timing chart of the M-th stage pull-down maintaining circuit shown in FIG. 7
  • FIG. 9 is an operation timing chart of the M+1-stage pull-down maintaining circuit shown in FIG.
  • the Mth stage pull-down maintaining circuit 32 operates normally.
  • the second low frequency signal PLC2 is at a high level, for example, 30V
  • the first low frequency signal PLC1 is at a low level, for example, -8V
  • the M+1th stage pull-down maintaining circuit operates normally.
  • the two pull-down maintaining circuits that is, the Mth stage pull-down maintaining circuit and the M+1th stage pull-down maintaining circuit Alternate operation, thereby avoiding the problem that only one pull-down sustaining circuit in the embodiment shown in FIG. 2 causes the transistor to suffer voltage stress (Stress) and cause IV drift, thereby improving the reliability of the GOA circuit.
  • FIG. 10 is a schematic structural view of a liquid crystal display according to an embodiment of the present invention.
  • the liquid crystal display 1 includes a GOA circuit 2 in which the GOA circuit 2 is the GOA circuit 10, the GOA circuit 20, or the GOA circuit 30 described above.
  • the beneficial effects of the present invention are that the GOA circuit and the liquid crystal display of the present invention maintain the gate drive signals of the second level signals during the non-active period by the corresponding pull-down sustain circuits, thereby reducing the pull maintenance.
  • the number of circuits in turn, can reduce the width of the wiring area of the GOA circuit to meet the needs of the narrow bezel design of the liquid crystal display.

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Abstract

一种GOA电路及液晶显示器。该GOA电路包括级联的多个GOA单元（11）和多个下拉维持电路（12），其中，级联的多个GOA单元（11）用于在多个时钟信号的控制下分别输出第一电平信号的栅极驱动信号以对显示区域中对应的水平扫描线进行充电；每一个下拉维持电路（12）对应至少两个GOA单元（11），每一个下拉维持电路（12）用于维持对应的至少两个GOA单元（11）在非作用期间输出的栅极驱动信号为第二电平信号。通过上述方式，可以减少下拉维持电路的数量，进而可以减少GOA电路布线区的宽度以满足液晶显示器窄边框设计的需求。

Description

一种GOA电路及液晶显示器
【技术领域】
本发明涉及液晶领域，特别是涉及一种GOA电路及液晶显示器。
【背景技术】
现有的GOA（Gate driver on array）电路包括级联的GOA单元和多个下拉维持电路，其中，一个GOA单元需要一个或者两个用于维持下拉的下拉维持电路。在实际应用中，下拉维持电路一般由多个晶体管构成，由于晶体管的数量较多，下拉维持电路往往会占用大量的空间。当下拉维持电路的数量较多时，会增加GOA电路布线区的宽度，进而增大液晶显示器的窄边框的设计难度。
【发明内容】
本发明主要解决的技术问题是提供一种GOA电路及液晶显示器，能够减少GOA电路布线区的宽度，从而降低液晶显示器的窄边框的设计难度。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种GOA电路，用于液晶显示器，该GOA电路包括级联的多个GOA单元，其中，级联的多个GOA单元用于在多个时钟信号的控制下分别输出第一电平信号的栅极驱动信号以对显示区域中对应的水平扫描线进行充电；该GOA电路进一步包括多个下拉维持电路，其中，每一个下拉维持电路对应至少两个GOA单元，每一个下拉维持电路用于维持对应的至少两个GOA单元在非作用期间输出的栅极驱动信号为第二电平信号；其中，当多个时钟信号的数量为N时，每一个或每两个下拉维持电路对应N/2个GOA单元；其中，GOA单元包括第十一晶体管、第十二晶体管、第十三晶体管、第十四晶体管、第十五晶体管和第二电容，其中，第十一晶体管的栅极与源极连接后与上一级启动信号连接，第十一晶体管的漏极分别与第十二晶体管的源极、第十三晶体管的栅极、第十四晶体管的栅极，第二电容的一端以及公共信号点连接，第十二晶体管的栅极与第十五晶体管的栅极连接，第十三晶体管的源极与第十四晶体管的源极连接后与时钟信号连接，第十三晶体管的漏极输出当前级启动信号，第十四晶体管的漏极分别与第二电容的另一端、第十五晶体管的源极以输出栅极驱动信号，第十二晶体管、第十五晶体管的漏极与恒压负电源连接。
其中，下拉维持电路包括输入模块和输出模块；
输入模块包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管、第九晶体管、第十晶体管和第一电容，其中，第一晶体管的栅极、源极与第二晶体管的源极相连后与第一输入信号连接，第一晶体管的漏极分别与第三晶体管的源极、第四晶体管的栅极连接，第二晶体管的栅极分别与第三晶体管的栅极、第五晶体管的源极和栅极连接，第二晶体管的漏极与第四晶体管的源极连接，第五晶体管的漏极分别与第六晶体管的漏极、第七晶体管的源极、第一电容的一端、第九晶体管的栅极连接，第六晶体管的栅极和源极相连后与第二输入信号连接，第七晶体管的栅极、第十晶体管的栅极与复位信号连接，第八晶体管的栅极和源极连接后与第三输入信号连接，第八晶体管的漏极与第九晶体管的源极连接，第九晶体管的漏极分别与第一电容的另一端和第十晶体管的源极连接，第三晶体管、第四晶体管、第七晶体管、第十晶体管的漏极连接后与第四输入信号连接；
输出模块包括多个晶体管，多个晶体管的数量等于多个时钟信号的数量N，多个晶体管的栅极彼此连接后与输入模块中的第九晶体管的漏极连接，多个晶体管的漏极彼此连接后与第四输入信号连接，多个晶体管的源极分别与对应的N/2个GOA单元的公共信号点和栅极驱动信号连接。
为解决上述技术问题，本发明采用的一个另技术方案是：提供一种GOA电路，用于液晶显示器，该GOA电路包括级联的多个GOA单元，其中，级联的多个GOA单元用于在多个时钟信号的控制下分别输出第一电平信号的栅极驱动信号以对显示区域中对应的水平扫描线进行充电；该GOA电路进一步包括多个下拉维持电路，其中，每一个下拉维持电路对应至少两个GOA单元，每一个下拉维持电路用于维持对应的至少两个GOA单元在非作用期间输出的栅极驱动信号为第二电平信号。
其中，当多个时钟信号的数量为N时，每一个或每两个下拉维持电路对应N/2个GOA单元。
其中，下拉维持电路包括输入模块和输出模块；
输入模块包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管、第九晶体管、第十晶体管和第一电容，其中，第一晶体管的栅极、源极与第二晶体管的源极相连后与第一输入信号连接，第一晶体管的漏极分别与第三晶体管的源极、第四晶体管的栅极连接，第二晶体管的栅极分别与第三晶体管的栅极、第五晶体管的源极和栅极连接，第二晶体管的漏极与第四晶体管的源极连接，第五晶体管的漏极分别与第六晶体管的漏极、第七晶体管的源极、第一电容的一端、第九晶体管的栅极连接，第六晶体管的栅极和源极相连后与第二输入信号连接，第七晶体管的栅极、第十晶体管的栅极与复位信号连接，第八晶体管的栅极和源极连接后与第三输入信号连接，第八晶体管的漏极与第九晶体管的源极连接，第九晶体管的漏极分别与第一电容的另一端和第十晶体管的源极连接，第三晶体管、第四晶体管、第七晶体管、第十晶体管的漏极连接后与第四输入信号连接；
输出模块包括多个晶体管，多个晶体管的数量等于多个时钟信号的数量N，多个晶体管的栅极彼此连接后与输入模块中的第九晶体管的漏极连接，多个晶体管的漏极彼此连接后与第四输入信号连接，多个晶体管的源极分别与对应的N/2个GOA单元的公共信号点和栅极驱动信号连接。
其中，当多个时钟信号的数量为八个，每一个下拉维持电路对应四个GOA单元时，第M级下拉维持电路的第一输入信号为恒压正电源，第二输入信号为第M-1级级传信号，第四输入信号为恒压负电源；其中，第M级下拉维持电路的第九晶体管的漏极输出第M级级传信号；其中，第M级下拉维持电路和第M+1级下拉维持电路的第三输入信号相位相反。
其中，当多个时钟信号为八个，每二个下拉维持电路对应四个GOA单元时，第M级下拉维持电路的第一输入信号为第一低频信号，第二输入信号为第M-2级级传信号，第四输入信号为恒压负电源；第M+1级下拉维持电路的第一输入信号为第二低频信号，第二输入信号为第M-1级级传信号，第三输入信号为第二控制信号，第四输入信号为恒压负电源；其中，第M级下拉维持电路和第M+1级下拉维持电路的第三输入信号相同，其与相邻的另外两个下拉维持电路的第三输入信号的相位相反；其中，第M级下拉维持电路的第九晶体管的漏极输出第M级级传信号，第M+1级下拉维持电路的第九晶体管的漏极输出第M+1级级传信号。
其中，第一低频信号和第二低频信号的相位相反。
其中，第一低频信号和第二低频信号每隔预定图像帧切换一次极性，其中，预定图像帧的取值范围为1~100帧。
其中，第M级下拉维持电路和第M+1级下拉维持电路在第一低频信号和第二低频信号的控制下交替工作。
其中，GOA单元包括第十一晶体管、第十二晶体管、第十三晶体管、第十四晶体管、第十五晶体管和第二电容，其中，第十一晶体管的栅极与源极连接后与上一级启动信号连接，第十一晶体管的漏极分别与第十二晶体管的源极、第十三晶体管的栅极、第十四晶体管的栅极，第二电容的一端以及公共信号点连接，第十二晶体管的栅极与第十五晶体管的栅极连接，第十三晶体管的源极与第十四晶体管的源极连接后与时钟信号连接，第十三晶体管的漏极输出当前级启动信号，第十四晶体管的漏极分别与第二电容的另一端、第十五晶体管的源极以输出栅极驱动信号，第十二晶体管、第十五晶体管的漏极与恒压负电源连接。
为解决上述技术问题，本发明采用的再一个技术方案是：提供一种液晶显示器，该液晶显示器包括GOA电路，该GOA电路包括级联的多个GOA单元，其中，级联的多个GOA单元用于在多个时钟信号的控制下分别输出第一电平信号的栅极驱动信号以对显示区域中对应的水平扫描线进行充电；该GOA电路进一步包括多个下拉维持电路，其中，每一个下拉维持电路对应至少两个GOA单元，每一个下拉维持电路用于维持对应的至少两个GOA单元在非作用期间输出的栅极驱动信号为第二电平信号。
其中，当多个时钟信号的数量为N时，每一个或每两个下拉维持电路对应N/2个GOA单元。
其中，下拉维持电路包括输入模块和输出模块；
输入模块包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管、第九晶体管、第十晶体管和第一电容，其中，第一晶体管的栅极、源极与第二晶体管的源极相连后与第一输入信号连接，第一晶体管的漏极分别与第三晶体管的源极、第四晶体管的栅极连接，第二晶体管的栅极分别与第三晶体管的栅极、第五晶体管的源极和栅极连接，第二晶体管的漏极与第四晶体管的源极连接，第五晶体管的漏极分别与第六晶体管的漏极、第七晶体管的源极、第一电容的一端、第九晶体管的栅极连接，第六晶体管的栅极和源极相连后与第二输入信号连接，第七晶体管的栅极、第十晶体管的栅极与复位信号连接，第八晶体管的栅极和源极连接后与第三输入信号连接，第八晶体管的漏极与第九晶体管的源极连接，第九晶体管的漏极分别与第一电容的另一端和第十晶体管的源极连接，第三晶体管、第四晶体管、第七晶体管、第十晶体管的漏极连接后与第四输入信号连接；
输出模块包括多个晶体管，多个晶体管的数量等于多个时钟信号的数量N，多个晶体管的栅极彼此连接后与输入模块中的第九晶体管的漏极连接，多个晶体管的漏极彼此连接后与第四输入信号连接，多个晶体管的源极分别与对应的N/2个GOA单元的公共信号点和栅极驱动信号连接。
其中，当多个时钟信号的数量为八个，每一个下拉维持电路对应四个GOA单元时，第M级下拉维持电路的第一输入信号为恒压正电源，第二输入信号为第M-1级级传信号，第四输入信号为恒压负电源；其中，第M级下拉维持电路的第九晶体管的漏极输出第M级级传信号；其中，第M级下拉维持电路和第M+1级下拉维持电路的第三输入信号相位相反。
其中，当多个时钟信号为八个，每二个下拉维持电路对应四个GOA单元时，第M级下拉维持电路的第一输入信号为第一低频信号，第二输入信号为第M-2级级传信号，第四输入信号为恒压负电源；第M+1级下拉维持电路的第一输入信号为第二低频信号，第二输入信号为第M-1级级传信号，第三输入信号为第二控制信号，第四输入信号为恒压负电源；其中，第M级下拉维持电路和第M+1级下拉维持电路的第三输入信号相同，其与相邻的另外两个下拉维持电路的第三输入信号的相位相反；其中，第M级下拉维持电路的第九晶体管的漏极输出第M级级传信号，第M+1级下拉维持电路的第九晶体管的漏极输出第M+1级级传信号。
其中，第一低频信号和第二低频信号的相位相反。
其中，第一低频信号和第二低频信号每隔预定图像帧切换一次极性，其中，预定图像帧的取值范围为1~100帧。
其中，第M级下拉维持电路和第M+1级下拉维持电路在第一低频信号和第二低频信号的控制下交替工作。
其中，GOA单元包括第十一晶体管、第十二晶体管、第十三晶体管、第十四晶体管、第十五晶体管和第二电容，其中，第十一晶体管的栅极与源极连接后与上一级启动信号连接，第十一晶体管的漏极分别与第十二晶体管的源极、第十三晶体管的栅极、第十四晶体管的栅极，第二电容的一端以及公共信号点连接，第十二晶体管的栅极与第十五晶体管的栅极连接，第十三晶体管的源极与第十四晶体管的源极连接后与时钟信号连接，第十三晶体管的漏极输出当前级启动信号，第十四晶体管的漏极分别与第二电容的另一端、第十五晶体管的源极以输出栅极驱动信号，第十二晶体管、第十五晶体管的漏极与恒压负电源连接。
本发明的有益效果是：本发明的GOA电路及液晶显示器通过一个下拉维持电路维持对应的至少两个GOA单元在非作用期间输出第二电平信号的栅极驱动信号，从而可以减少下拉维持电路的数量，进而可以减少GOA电路布线区的宽度以满足液晶显示器窄边框设计的需求。
【附图说明】
图1是本发明第一实施例的GOA电路的结构示意图；
图2是本发明第二实施例的GOA电路的结构示意图；
图3是图2所示的GOA单元的电路原理图；
图4是图2所示的下拉维持电路的电路原理图；
图5是图4所示的下拉维持电路的工作时序图；
图6是本发明第三实施例的GOA电路的结构示意图；
图7是图6所示的对应四个GOA单元的两个下拉维持电路的电路原理图；
图8是图7所示第M级下拉维持电路的工作时序图；
图9是图7所示第M+1级下拉维持电路的工作时序图；
图10是本发明实施例的液晶显示器的结构示意图。
【具体实施方式】
在说明书及权利要求书当中使用了某些词汇来指称特定的组件，所属领域中的技术人员应可理解，制造商可能会用不同的名词来称呼同样的组件。本说明书及权利要求书并不以名称的差异来作为区分组件的方式，而是以组件在功能上的差异来作为区分的基准。下面结合附图和实施例对本发明进行详细说明。
图1是本发明第一实施例的GOA电路的结构示意图。如图1所示，GOA电路10包括级联的多个GOA单元11和多个下拉维持电路12。
其中，级联的多个GOA单元11用于在多个时钟信号的控制下分别输出第一电平信号的栅极驱动信号以对显示区域中对应的水平扫描线进行充电。其中，第一电平信号为高电平信号。其中，每一个下拉维持电路12对应至少两个GOA单元11，每一个下拉维持电路用于维持对应的至少两个GOA单元11在非作用期间输出的栅极驱动信号为第二电平信号。其中，第二电平信号为低电平信号。
优选地，当多个时钟信号的数量为N时，每一个或每两个下拉维持电路12对应N/2个GOA单元11。
图2是本发明第二实施例的GOA电路的结构示意图，本发明基于八个时钟信号的GOA电路。如图2所示，GOA电路20包括级联的多个GOA单元21和多个下拉维持电路22。
级联的多个GOA单元21用于在八个时钟信号CKn（n=1、2、…8）的控制下分别输出第一电平信号的栅极驱动信号G（n）（n=1、2、…N）以对显示区域中对应的水平扫描线进行充电。其中，第一电平信号为高电平信号。
其中，级联的多个GOA单元21和八个时钟信号CKn的连接关系为：第一级GOA单元21与时钟信号CK1连接，第二级GOA单元21与时钟信号CK2连接，…依次类推，第八级GOA单元21与时钟信号CK8连接。然后再次循环，也即第九级GOA单元21与时钟信号CK1连接，第十级GOA单元21与时钟信号CK2连接，…依次类推，第十六级GOA单元21与时钟信号CK8连接。然后继续上述的循环直至所有的GOA单元21连接上对应的时钟信号。在本实施例中，八个时钟信号CKn（n=1、2、…8）依序分时有效。
请一并参考图3，图3是图2所示的GOA单元的电路原理图。如图3所示，第N级GOA单元21包括第十一晶体管T11、第十二晶体管T12、第十三晶体管T13、第十四晶体管T14、第十五晶体管T15和第二电容C2。
其中，第十一晶体管T11的栅极与源极连接后与上一级启动信号连接，在本实施例中，上一级启动信号为第n-4级启动信号ST（n-4）。第十一晶体管T11的漏极分别与第十二晶体管T12的源极、第十三晶体管T13的栅极、第十四晶体管T14的栅极，第二电容C2的一端以及公共信号点连接，在本实施例中，公共信号点为第n级公共信号点Q(n)。第十二晶体管T12的栅极与第十五晶体管T15的栅极连接以输出下一级启动信号，在本实施例中，下一级启动信号为第n+4级启动信号ST（n+4）。第十三晶体管T13的源极与第十四晶体管T14的源极连接后与时钟信号CKn连接，第十三晶体管T13的漏极输出当前级启动信号，在本实施例中，当前级启动信号为第n级启动信号ST（n）。第十四晶体管T14的漏极分别与第二电容C2的另一端、第十五晶体管T15的源极连接以输出栅极驱动信号，在本实施例中，栅极驱动信号为第n级栅极驱动信号G（n）。第十二晶体管T12、第十五晶体管T15的漏极与恒压负电源VSS连接。
在本实施例中，第十一晶体管T11用于连接第n-4级启动信号ST（n-4）以将第n级GOA单元21打开后将第n级公共信号点Q(n)的电位拉高，第十四晶体管T14用于在第n级GOA单元21的作用期间输出高电平的第n级栅极驱动信号G（n）以对对应的水平扫描线充电，第十三晶体管用于在第n级GOA单元的非作用期间输出第n级启动信号ST（n）以将下一级也即第n+4级GOA电路打开，第十二晶体管T12和第十五晶体管T15用于在第n级GOA单元的非作用期间将第n级公共信号点Q(n)和第n级栅极驱动信号G（n）的信号拉低。
请继续参考图2，在本实施例中，每一个下拉维持电路22对应四个GOA单元21，每一个下拉维持电路22用于维持对应的四个GOA单元21在非作用期间输出的栅极驱动信号为第二电平信号。其中，第二电平信号为低电平信号。
请一并参考图4，图4是图2所示的下拉维持电路的电路原理图。如图4所示，下拉维持电路22包括输入模块221和输出模块222。
输入模块221包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、第八晶体管T8、第九晶体管T9、第十晶体管T10和第一电容C1。
其中，第一晶体管T1的栅极、源极与第二晶体管T2的源极相连后与第一输入信号连接，第一晶体管T1的漏极分别与第三晶体管T3的源极、第四晶体管T4的栅极连接，第二晶体管T2的栅极分别与第三晶体管T3的栅极、第五晶体管T5的源极和栅极连接，第二晶体管T2的漏极与第四晶体管T4的源极连接，第五晶体管T5的漏极分别与第六晶体管T6的漏极、第七晶体管T7的源极、第一电容C1的一端、第九晶体管T9的栅极连接，第六晶体管T6的栅极和源极相连后与第二输入信号连接，第七晶体管T7的栅极、第十晶体管T10的栅极与复位信号Reset连接，第八晶体管T8的栅极和源极连接后与第三输入信号连接，第八晶体管T8的漏极与第九晶体管T9的源极连接，第九晶体管T9的漏极分别与第一电容C1的另一端和第十晶体管T10的源极连接，第三晶体管T3、第四晶体管T4、第七晶体管T7、第十晶体管T10的漏极连接后与第四输入信号连接。
输出模块222包括八个晶体管TT1，其中，晶体管TT1的数量与时钟信号的数量相同。
在本实施例中，八个晶体管TT1的栅极彼此连接后与输入模块221中的第九晶体管T9的漏极连接，八个晶体管TT1的漏极彼此连接后与第四输入信号连接，八个晶体管TT1的源极分别与对应的四个GOA单元的公共信号点和栅极驱动信号连接。
在本实施例中，以下拉维持电路22为第M级下拉维持电路为例来说，第M级下拉维持电路22的第一输入信号为恒压正电源VDD，第二输入信号为第M-1级级传信号P（m-1），第三输入信号为第一控制信号CKP，第四输入信号为恒压负电源VSS。
其中，第M级下拉维持电路22的第九晶体管T9的漏极输出第M级级传信号P（m）。
另外，在本实施例中，第M级下拉维持电路22和第M+1级下拉维持电路22的第三输入信号相位相反，也即第M+1级下拉维持信号22的第三输入信号为反相第一控制信号XCKP。
在本实施例中，第M级下拉维持电路22中的八个晶体管TT1的源极分别与第N级、第N+1级、第N+2级、第N+3级公共信号点Q（n）、Q（n+1）、Q（n+2）、Q（n+3）以及第N级、第N+1级、第N+2级、第N+3级栅极驱动信号G（n）、G（n+1）、G（n+2）、G（n+3）连接。
请一并参考图5，图5是图4所示的下拉维持电路的工作时序图。如图5所示，当第N级到第N+3级GOA单元21在输出栅极驱动信号期间，第M级下拉维持电路22的第M级级传信号P（m）一直处于低电位状态，此时可以保证第N级到第N+3级GOA单元21正常输出第N级、第N+1级、第N+2级、第N+3级栅极驱动信号G（n）、G（n+1）、G（n+2）、G（n+3）。当第N级到第N+3级GOA单元21的栅极驱动信号输出完毕之后，M级级传信号P（m）切换至高电位，它可以同时控制八个晶体管TT1将第N级到第N+3级GOA单元21的第N级、第N+1级、第N+2级、第N+3级公共信号点Q（n）、Q（n+1）、Q（n+2）、Q（n+3）以及第N级、第N+1级、第N+2级、第N+3级栅极驱动信号G（n）、G（n+1）、G（n+2）、G（n+3）全部下拉至恒压负电源VSS的电位。
其中，在一帧图像帧显示的过程中，当下拉维持电路22中的M级级传信号P（m）切换为高电位之后将一直维持在高电位状态，直到下一帧图像帧显示之前由复位信号Reset信号将M级级传信号P（m）下拉为低电位。
图6是本发明第三实施例的GOA电路的结构示意图，本发明基于八个时钟信号的GOA电路。如图6所示，GOA电路30包括级联的多个GOA单元31和多个下拉维持电路32。
图6所示的GOA电路30与图2所示的GOA电路20的差别为：每两个下拉维持电路32对应四个GOA单元31。
其中，本实施例中的GOA单元31和图2所示第二实施例中的GOA单元21相同，为简约起见，在此不再赘述。
请一并参考图7，图7是图6所示的对应四个GOA单元的两个下拉维持电路的电路原理图。如图7所示，以两个下拉维持电路32包括第M级下拉维持电路32和第M+1级下拉维持电路32为例来说，本实施例中的下拉维持电路32与图2所示的第二实施例中的下拉维持电路22的区别在于：
第M级下拉维持电路32的第一输入信号为第一低频信号PLC1，第二输入信号为第M-2级级传信号PP(m-2)，第三输入信号为第二控制信号CKP2，第四输入信号为恒压负电源VSS；第M+1级下拉维持电路32的第一输入信号为第二低频信号PLC2，第二输入信号为第M-1级级传信号PP(m-1)，第三输入信号为第二控制信号CKP2，第四输入信号为恒压负电源VSS。
其中，第M级下拉维持电路32的第九晶体管T9的漏极输出第M级级传信号PP(m)，第M+1级下拉维持电路32的第九晶体管T9的漏极输出第M+1级级传信号PP(m+1)。
其中，第M级下拉维持电路和第M+1级下拉维持电路的第三输入信号相同，其与相邻的另外两个下拉维持电路的第三输入信号的相位相反，也即相邻的另外两个下拉维持电路的第三输入信号为反相第二控制信号XCKP2。
其中，第一低频信号PLC1和第二低频信号PLC2的相位相反。
其中，第一低频信号PLC1和第二低频信号PLC2每隔预定图像帧切换一次极性，其中，预定图像帧的取值范围为1~100帧。
其中，第M级下拉维持电路32和第M+1级下拉维持电路32在第一低频信号PLC1和第二低频信号PLC2的控制下交替工作。
请一并参考图8和图9，图8是图7所示第M级下拉维持电路的工作时序图，图9是图7所示第M+1级下拉维持电路的工作时序图。如图8和图9所示，当第一低频信号PLC1为高电平例如30V，第二低频信号PLC2为低电平例如-8V时，第M级下拉维持电路32正常工作。当第二低频信号PLC2为高电平例如30V，第一低频信号PLC1为低电平例如-8V时，第M+1级下拉维持电路正常工作。
在本实施例中，由于第一低频信号PLC1和第二低频信号PLC2每隔预定图像帧切换一次极性，两个下拉维持电路也即第M级下拉维持电路和第M+1级下拉维持电路交替工作，从而可以避免图2所示的实施例中只有一个下拉维持电路长时间工作造成晶体管遭受电压应力（Stress）而引起I-V漂移的问题，进而提升了GOA电路的信赖性。
图10是本发明实施例的液晶显示器的结构示意图。如图10所示，液晶显示器1包括GOA电路2，其中，GOA电路2为上述GOA电路10、GOA电路20或GOA电路30。
本发明的有益效果是：本发明的GOA电路及液晶显示器通过每一个下拉维持电路维持对应的至少两个GOA单元在非作用期间输出第二电平信号的栅极驱动信号，从而可以减少拉维持电路的数量，进而可以减少GOA电路布线区的宽度以满足液晶显示器窄边框设计的需求。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种GOA电路，用于液晶显示器，其中，所述GOA电路包括级联的多个GOA单元，其中，级联的多个所述GOA单元用于在多个时钟信号的控制下分别输出第一电平信号的栅极驱动信号以对显示区域中对应的水平扫描线进行充电；
    所述GOA电路进一步包括多个下拉维持电路，其中，每一个所述下拉维持电路对应至少两个所述GOA单元，每一个所述下拉维持电路用于维持对应的至少两个所述GOA单元在非作用期间输出的所述栅极驱动信号为第二电平信号；
    其中，当多个时钟信号的数量为N时，每一个或每两个所述下拉维持电路对应N/2个所述GOA单元；
    其中，所述GOA单元包括第十一晶体管、第十二晶体管、第十三晶体管、第十四晶体管、第十五晶体管和第二电容，其中，所述第十一晶体管的栅极与源极连接后与上一级启动信号连接，所述第十一晶体管的漏极分别与所述第十二晶体管的源极、所述第十三晶体管的栅极、所述第十四晶体管的栅极，所述第二电容的一端以及公共信号点连接，所述第十二晶体管的栅极与所述第十五晶体管的栅极连接，所述第十三晶体管的源极与所述第十四晶体管的源极连接后与所述时钟信号连接，所述第十三晶体管的漏极输出当前级启动信号，所述第十四晶体管的漏极分别与第二电容的另一端、第十五晶体管的源极以输出栅极驱动信号，所述第十二晶体管、所述第十五晶体管的漏极与恒压负电源连接。
  2. 根据权利要求1所述的GOA电路，其中，所述下拉维持电路包括输入模块和输出模块；
    所述输入模块包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管、第九晶体管、第十晶体管和第一电容，其中，所述第一晶体管的栅极、源极与所述第二晶体管的源极相连后与第一输入信号连接，所述第一晶体管的漏极分别与所述第三晶体管的源极、所述第四晶体管的栅极连接，所述第二晶体管的栅极分别与所述第三晶体管的栅极、所述第五晶体管的源极和栅极连接，所述第二晶体管的漏极与所述第四晶体管的源极连接，所述第五晶体管的漏极分别与所述第六晶体管的漏极、所述第七晶体管的源极、所述第一电容的一端、所述第九晶体管的栅极连接，所述第六晶体管的栅极和源极相连后与第二输入信号连接，所述第七晶体管的栅极、所述第十晶体管的栅极与复位信号连接，所述第八晶体管的栅极和源极连接后与第三输入信号连接，所述第八晶体管的漏极与所述第九晶体管的源极连接，所述第九晶体管的漏极分别与所述第一电容的另一端和所述第十晶体管的源极连接，所述第三晶体管、所述第四晶体管、所述第七晶体管、所述第十晶体管的漏极连接后与第四输入信号连接；
    所述输出模块包括多个晶体管，所述多个晶体管的数量等于所述多个时钟信号的数量N，所述多个晶体管的栅极彼此连接后与所述输入模块中的所述第九晶体管的漏极连接，所述多个晶体管的漏极彼此连接后与所述第四输入信号连接，所述多个晶体管的源极分别与对应的N/2个所述GOA单元的公共信号点和栅极驱动信号连接。
  3. 一种GOA电路，用于液晶显示器，其中，所述GOA电路包括级联的多个GOA单元，其中，级联的多个所述GOA单元用于在多个时钟信号的控制下分别输出第一电平信号的栅极驱动信号以对显示区域中对应的水平扫描线进行充电；
    所述GOA电路进一步包括多个下拉维持电路，其中，每一个所述下拉维持电路对应至少两个所述GOA单元，每一个所述下拉维持电路用于维持对应的至少两个所述GOA单元在非作用期间输出的所述栅极驱动信号为第二电平信号。
  4. 根据权利要求3所述的GOA电路，其中，当多个时钟信号的数量为N时，每一个或每两个所述下拉维持电路对应N/2个所述GOA单元。
  5. 根据权利要求4所述的GOA电路，其中，所述下拉维持电路包括输入模块和输出模块；
    所述输入模块包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管、第九晶体管、第十晶体管和第一电容，其中，所述第一晶体管的栅极、源极与所述第二晶体管的源极相连后与第一输入信号连接，所述第一晶体管的漏极分别与所述第三晶体管的源极、所述第四晶体管的栅极连接，所述第二晶体管的栅极分别与所述第三晶体管的栅极、所述第五晶体管的源极和栅极连接，所述第二晶体管的漏极与所述第四晶体管的源极连接，所述第五晶体管的漏极分别与所述第六晶体管的漏极、所述第七晶体管的源极、所述第一电容的一端、所述第九晶体管的栅极连接，所述第六晶体管的栅极和源极相连后与第二输入信号连接，所述第七晶体管的栅极、所述第十晶体管的栅极与复位信号连接，所述第八晶体管的栅极和源极连接后与第三输入信号连接，所述第八晶体管的漏极与所述第九晶体管的源极连接，所述第九晶体管的漏极分别与所述第一电容的另一端和所述第十晶体管的源极连接，所述第三晶体管、所述第四晶体管、所述第七晶体管、所述第十晶体管的漏极连接后与第四输入信号连接；
    所述输出模块包括多个晶体管，所述多个晶体管的数量等于所述多个时钟信号的数量N，所述多个晶体管的栅极彼此连接后与所述输入模块中的所述第九晶体管的漏极连接，所述多个晶体管的漏极彼此连接后与所述第四输入信号连接，所述多个晶体管的源极分别与对应的N/2个所述GOA单元的公共信号点和栅极驱动信号连接。
  6. 根据权利要求5所述的GOA电路，其中，当所述多个时钟信号的数量为八个，每一个所述下拉维持电路对应四个所述GOA单元时，第M级所述下拉维持电路的所述第一输入信号为恒压正电源，所述第二输入信号为第M-1级级传信号，所述第四输入信号为恒压负电源；
    其中，第M级所述下拉维持电路的所述第九晶体管的漏极输出第M级级传信号；
    其中，第M级所述下拉维持电路和第M+1级所述下拉维持电路的所述第三输入信号相位相反。
  7. 根据权利要求5所述的GOA电路，其中，当所述多个时钟信号为八个，每二个所述下拉维持电路对应四个所述GOA单元时，第M级所述下拉维持电路的所述第一输入信号为第一低频信号，所述第二输入信号为第M-2级级传信号，所述第四输入信号为恒压负电源；第M+1级所述下拉维持电路的所述第一输入信号为第二低频信号，所述第二输入信号为第M-1级级传信号，所述第三输入信号为第二控制信号，所述第四输入信号为恒压负电源；
    其中，第M级所述下拉维持电路和第M+1级所述下拉维持电路的所述第三输入信号相同，其与相邻的另外两个所述下拉维持电路的所述第三输入信号的相位相反；
    其中，第M级所述下拉维持电路的所述第九晶体管的漏极输出第M级级传信号，第M+1级所述下拉维持电路的所述第九晶体管的漏极输出第M+1级级传信号。
  8. 根据权利要求7所述的GOA电路，其中，所述第一低频信号和所述第二低频信号的相位相反。
  9. 根据权利要求7所述的GOA电路，其中，所述第一低频信号和所述第二低频信号每隔预定图像帧切换一次极性，其中，所述预定图像帧的取值范围为1~100帧。
  10. 根据权利要求7所述的GOA电路，其中，第M级所述下拉维持电路和第M+1级所述下拉维持电路在所述第一低频信号和所述第二低频信号的控制下交替工作。
  11. 根据权利要求3所述的GOA电路，其中，所述GOA单元包括第十一晶体管、第十二晶体管、第十三晶体管、第十四晶体管、第十五晶体管和第二电容，其中，所述第十一晶体管的栅极与源极连接后与上一级启动信号连接，所述第十一晶体管的漏极分别与所述第十二晶体管的源极、所述第十三晶体管的栅极、所述第十四晶体管的栅极，所述第二电容的一端以及公共信号点连接，所述第十二晶体管的栅极与所述第十五晶体管的栅极连接，所述第十三晶体管的源极与所述第十四晶体管的源极连接后与所述时钟信号连接，所述第十三晶体管的漏极输出当前级启动信号，所述第十四晶体管的漏极分别与第二电容的另一端、第十五晶体管的源极以输出栅极驱动信号，所述第十二晶体管、所述第十五晶体管的漏极与恒压负电源连接。
  12. 一种液晶显示器，其中，所述液晶显示器包括GOA电路；所述GOA电路包括级联的多个GOA单元，其中，级联的多个所述GOA单元用于在多个时钟信号的控制下分别输出第一电平信号的栅极驱动信号以对显示区域中对应的水平扫描线进行充电；
    所述GOA电路进一步包括多个下拉维持电路，其中，每一个所述下拉维持电路对应至少两个所述GOA单元，每一个所述下拉维持电路用于维持对应的至少两个所述GOA单元在非作用期间输出的所述栅极驱动信号为第二电平信号。
  13. 根据权利要求12所述的液晶显示器，其中，当多个时钟信号的数量为N时，每一个或每两个所述下拉维持电路对应N/2个所述GOA单元。
  14. 根据权利要求13所述的液晶显示器，其中，所述下拉维持电路包括输入模块和输出模块；
    所述输入模块包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管、第九晶体管、第十晶体管和第一电容，其中，所述第一晶体管的栅极、源极与所述第二晶体管的源极相连后与第一输入信号连接，所述第一晶体管的漏极分别与所述第三晶体管的源极、所述第四晶体管的栅极连接，所述第二晶体管的栅极分别与所述第三晶体管的栅极、所述第五晶体管的源极和栅极连接，所述第二晶体管的漏极与所述第四晶体管的源极连接，所述第五晶体管的漏极分别与所述第六晶体管的漏极、所述第七晶体管的源极、所述第一电容的一端、所述第九晶体管的栅极连接，所述第六晶体管的栅极和源极相连后与第二输入信号连接，所述第七晶体管的栅极、所述第十晶体管的栅极与复位信号连接，所述第八晶体管的栅极和源极连接后与第三输入信号连接，所述第八晶体管的漏极与所述第九晶体管的源极连接，所述第九晶体管的漏极分别与所述第一电容的另一端和所述第十晶体管的源极连接，所述第三晶体管、所述第四晶体管、所述第七晶体管、所述第十晶体管的漏极连接后与第四输入信号连接；
    所述输出模块包括多个晶体管，所述多个晶体管的数量等于所述多个时钟信号的数量N，所述多个晶体管的栅极彼此连接后与所述输入模块中的所述第九晶体管的漏极连接，所述多个晶体管的漏极彼此连接后与所述第四输入信号连接，所述多个晶体管的源极分别与对应的N/2个所述GOA单元的公共信号点和栅极驱动信号连接。
  15. 根据权利要求14所述的液晶显示器，其中，当所述多个时钟信号的数量为八个，每一个所述下拉维持电路对应四个所述GOA单元时，第M级所述下拉维持电路的所述第一输入信号为恒压正电源，所述第二输入信号为第M-1级级传信号，所述第四输入信号为恒压负电源；
    其中，第M级所述下拉维持电路的所述第九晶体管的漏极输出第M级级传信号；
    其中，第M级所述下拉维持电路和第M+1级所述下拉维持电路的所述第三输入信号相位相反。
  16. 根据权利要求14所述的液晶显示器，其中，当所述多个时钟信号为八个，每二个所述下拉维持电路对应四个所述GOA单元时，第M级所述下拉维持电路的所述第一输入信号为第一低频信号，所述第二输入信号为第M-2级级传信号，所述第四输入信号为恒压负电源；第M+1级所述下拉维持电路的所述第一输入信号为第二低频信号，所述第二输入信号为第M-1级级传信号，所述第三输入信号为第二控制信号，所述第四输入信号为恒压负电源；
    其中，第M级所述下拉维持电路和第M+1级所述下拉维持电路的所述第三输入信号相同，其与相邻的另外两个所述下拉维持电路的所述第三输入信号的相位相反；
    其中，第M级所述下拉维持电路的所述第九晶体管的漏极输出第M级级传信号，第M+1级所述下拉维持电路的所述第九晶体管的漏极输出第M+1级级传信号。
  17. 根据权利要求16所述的液晶显示器，其中，所述第一低频信号和所述第二低频信号的相位相反。
  18. 根据权利要求16所述的液晶显示器，其中，所述第一低频信号和所述第二低频信号每隔预定图像帧切换一次极性，其中，所述预定图像帧的取值范围为1~100帧。
  19. 根据权利要求16所述的液晶显示器，其中，第M级所述下拉维持电路和第M+1级所述下拉维持电路在所述第一低频信号和所述第二低频信号的控制下交替工作。
  20. 根据权利要求12所述的液晶显示器，其中，所述GOA单元包括第十一晶体管、第十二晶体管、第十三晶体管、第十四晶体管、第十五晶体管和第二电容，其中，所述第十一晶体管的栅极与源极连接后与上一级启动信号连接，所述第十一晶体管的漏极分别与所述第十二晶体管的源极、所述第十三晶体管的栅极、所述第十四晶体管的栅极，所述第二电容的一端以及公共信号点连接，所述第十二晶体管的栅极与所述第十五晶体管的栅极连接，所述第十三晶体管的源极与所述第十四晶体管的源极连接后与所述时钟信号连接，所述第十三晶体管的漏极输出当前级启动信号，所述第十四晶体管的漏极分别与第二电容的另一端、第十五晶体管的源极以输出栅极驱动信号，所述第十二晶体管、所述第十五晶体管的漏极与恒压负电源连接。
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