WO2018120780A1 - PCIe中断方法和*** - Google Patents
PCIe中断方法和*** Download PDFInfo
- Publication number
- WO2018120780A1 WO2018120780A1 PCT/CN2017/093470 CN2017093470W WO2018120780A1 WO 2018120780 A1 WO2018120780 A1 WO 2018120780A1 CN 2017093470 W CN2017093470 W CN 2017093470W WO 2018120780 A1 WO2018120780 A1 WO 2018120780A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- interrupt
- interface
- cfg
- signal
- type
- Prior art date
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
- G06F9/4825—Interrupt from clock, e.g. time of day
Definitions
- the embodiments of the present invention relate to the field of communications technologies, and in particular, to a PCIe interrupt method and system.
- PCIe Peripheral Component Interconnect Express
- PCIe Peripheral Component Interconnect Express
- Pin-based PCI interrupts also known as INTx interrupts
- INTx interrupts are often shared between several devices.
- the core must call every interrupt handler associated with the interrupt, which is less efficient.
- the interrupt handler When the device writes data to the memory and then initiates a pin interrupt, it is possible that the data has not yet reached the memory when the CPU receives the interrupt (the device behind the PCI-PCI bridge is more likely to do so).
- the interrupt handler must poll a register of the device that generated the interrupt, and the PCI transaction-preserving rules will ensure that the register will return a value after all data has reached memory.
- Each functional device of PCI supports only one pin-based interrupt.
- the driver often needs to query the device to determine the event that occurs, which reduces the efficiency of interrupt processing. Therefore, the MSI interrupt is used in the PCIe system.
- the MSI interrupt is not shared, so there is no shared problem in the INTx interrupt.
- the write operation that generates the interrupt cannot exceed the data write operation, so when the interrupt is generated, the driver can be sure that all data has arrived in memory.
- the MSI interrupt is implemented by writing a specific value to a specific address, and can support up to 32 interrupt vectors, but the MSI interrupt has a constraint that the interrupt vector number must be consecutive. In order to solve this problem, MSI-X has also been proposed, compared with the MSI Capability register.
- the MSI-X Capability register uses an array to hold the Message Address field and the Message Data field instead of putting these two fields into the Capability register.
- each interrupt request can use a separate Message Address field and a Message Data field.
- MSI-X does not require interrupt vector number continuation and can support up to 2048 interrupt vectors.
- Different processors have different interpretations of MSI messages sent by PCIE devices.
- the PCIe device writes the Message Data data to the address of the Message Address in the MSI/MSI-X Capability structure to form a memory write TLP, and submits an interrupt request to the processor.
- the type of interrupt supported by the driver may be one or more of a traditional INTx interrupt, an MSI interrupt, or an MSI-X interrupt.
- the hardware logic only completes some kind of interrupt that matches it, and discards the other two types of interrupts. This will result in changes in the types of interrupts that may be supported during subsequent driver platform upgrades, resulting in the underlying FPGA developers having to adapt the functions to match the software upgrades, thereby increasing project cycle and maintainability. Conducive to the platform implementation of the project.
- Embodiments of the present invention provide a PCIe interrupt method and system to extend FPGA compatibility with processor interrupts.
- an embodiment of the present invention provides a PCIe interrupt method, where data communication is implemented between a FPGA and a processor through a PCIe interface, and the method includes:
- an interrupt type configured in the FPGA, where the interrupt type includes at least one of an INTx interrupt type, an MSI interrupt type, and an MSI-X interrupt type;
- the PCIe interrupt data is transmitted through the transmission interface.
- the method further includes:
- the interrupt type of the FPGA is configured, and the PCIe interface is configured to be a full-type mode, wherein the full-type mode supports all of the interrupt types.
- the step of determining, according to the type of the interrupt, the transmission interface corresponding to the PCIe interrupt data includes:
- interrupt type MSI-X interrupt
- transmission interface is an AXI4-S interface
- the interrupt type is an MSI interrupt, it is determined that the transport interface is a CFG_INT interface;
- interrupt type is an INTx interrupt
- transport interface is a CFG_INT interface
- the processing timing of sending the PCIe interrupt data through the transmission interface includes: an INTx interrupt execution flow and an MSI interrupt execution flow;
- the INTx interrupt execution flow includes:
- the cfg_interrupt_rdy signal of the CFG_INT interface is set high by the CPU, the cfg_interrupt signal is set to a high level, and the cfg_interrupt_assert signal is set to a low level;
- the MSI interrupt execution process includes:
- the cfg_interrupt_rdy signal of the CFG_INT interface is detected to be set high by the CPU, the cfg_interrupt signal and the cfg_interrupt_di signal are set to the second flag bit as the interrupt request;
- the processing sequence of sending the PCIe interrupt data through the transmission interface includes:
- s_ais_tx_tready signal of the AXI4-S interface When the s_ais_tx_tready signal of the AXI4-S interface is detected to be set high by the CPU, it indicates that the currently transmitted data is received. When s_axis_tx_tlast is set to high level, it indicates that it is the last interrupt data transmission;
- s_ais_tx_tready signal of the AXI4-S interface is detected to be high by the CPU, indicating that the entire interrupt data transfer is completed, s_axis_tx_tvalid, s_axis_tx_tlast, s_axis_tx_tdata, s_axis_tx_tkeep are set low.
- the embodiment of the present invention further provides a PCIe interrupt system, wherein the FPGA and the processor implement data communication through a PCIe interface, and the system includes: an interrupt control module and a PCIe interface module;
- the interrupt control module is configured to receive an interrupt request, acquire an interrupt type configured in the FPGA, generate PCIe interrupt data according to the interrupt type, and determine a transmission interface on the PCIe interface module according to the interrupt type,
- the interrupt type includes at least one of an INTx interrupt type, an MSI interrupt type, and an MSI-X interrupt type;
- the interrupt control module transmits the PCIe interrupt data through the transmission interface.
- An interrupt configuration module configured to configure an interrupt type of the FPGA
- the PCIe interface module is further configured to configure the PCIe interface to be a full-type mode, wherein the full-type mode supports all of the interrupt types.
- interrupt control module is further configured to:
- the transmission interface is an AXI4-S interface
- the interrupt type is an MSI interrupt, determining that the transport interface is a CFG_INT interface;
- the transport interface is the CFG_INT interface.
- the processing timing of sending the PCIe interrupt data through the transmission interface includes: an INTx interrupt execution flow and an MSI interrupt execution flow;
- the INTx interrupt execution flow includes:
- the cfg_interrupt_rdy signal of the CFG_INT interface is set high by the CPU, the cfg_interrupt signal is set to a high level, and the cfg_interrupt_assert signal is set to a low level;
- the MSI interrupt execution process includes:
- the cfg_interrupt_rdy signal of the CFG_INT interface is detected to be set high by the CPU, the cfg_interrupt signal and the cfg_interrupt_di signal are set to the second flag bit as the interrupt request;
- the processing sequence of sending the PCIe interrupt data through the transmission interface includes:
- s_ais_tx_tready signal of the AXI4-S interface When the s_ais_tx_tready signal of the AXI4-S interface is detected to be set high by the CPU, it indicates that the currently transmitted data is received. When s_axis_tx_tlast is set to high level, it indicates that it is the last interrupt data transmission;
- s_ais_tx_tready signal of the AXI4-S interface is detected to be high by the CPU, indicating that the entire interrupt data transfer is completed, s_axis_tx_tvalid, s_axis_tx_tlast, s_axis_tx_tdata, s_axis_tx_tkeep are set low.
- the embodiment of the invention receives the interrupt request, acquires the configured interrupt type in the FPGA, generates the PCIe interrupt data according to the interrupt type, and determines the transmission interface corresponding to the PCIe interrupt data on the PCIe interface according to the interrupt type; and sends the PCIe interrupt data through the transmission interface.
- Expanded FPGA compatibility with CPU interrupts Moreover, each interrupt function can be independently developed and maintained, and has no influence on each other, which reduces the development difficulty, and helps to realize the logical platform construction of the FPGA, and also ensures the platform construction of the driver layer from the bottom layer.
- FIG. 1 is a flowchart of a PCIe interrupt method according to Embodiment 1 of the present invention.
- FIG. 2 is a schematic structural diagram of a PCIe interrupt system according to Embodiment 1 of the present invention.
- FIG. 3 is a flowchart of a PCIe interrupt method according to Embodiment 2 of the present invention.
- FIG. 5 is a timing diagram of PCIe interrupt processing in Embodiment 2 of the present invention.
- FIG. 6 is a schematic structural diagram of a PCIe interrupt data packet in Embodiment 2 of the present invention.
- FIG. 7 is a schematic structural diagram of a PCIe interrupt system according to Embodiment 3 of the present invention.
- FIG. 8 is a schematic structural diagram of a PCIe interrupt system according to another example in Embodiment 3 of the present invention.
- FIG. 1 is a flowchart of a method for interrupting a PCIe according to a first embodiment of the present invention.
- the present embodiment is applicable to a PCIe interrupt.
- the method may be implemented by a PCIe interrupt system in the embodiment of the present invention. / or hardware implementation.
- a PCIe interrupt system in the embodiment of the present invention.
- it usually includes a CPU processor, which is the core device that responds to various computing processing requirements.
- the system may also include various peripherals such as a keyboard, mouse, display, ultrasound probe or memory, and the like.
- an FPGA Field-Programmable Gate Array
- the auxiliary peripheral device initiates an interrupt request to the CPU, or
- the FPGA acquires the data in the CPU, sends an interrupt to the CPU, and asks the CPU to perform data processing for itself.
- Data communication between the FPGA and the CPU is performed through the PCIe interface.
- the method specifically includes the following steps:
- This interrupt request acts as an internal interrupt request for the FPGA and is an operation prompt to start interrupting the data transfer.
- the normal data is data that needs to be processed by a processor.
- the specific process is: the peripheral device acquires common data (if the peripheral device is an ultrasonic probe, the ordinary data can be an ultrasonic signal), and the data is transmitted to the FPGA, and the FPGA includes a data transmission module and a receiving module.
- the receiving module is configured to receive normal data transmitted by the peripheral device, and the data transmission module is configured to send the normal data acquired by the peripheral device to the memory through the AXI4-S interface.
- the memory and processor belong to the same device, the processor is responsible for computing and processing, and the memory is responsible for data exchange.
- the data transmission module After the data transmission module transmits all the data to the memory, the data transmission module sends the prompt information that the data has been completely transmitted to the memory, and the receiving module receives the prompt information.
- the interrupt request in this embodiment refers to the data transmission module transmitting data to the memory. After the data transmission is completed, the receiving module receives the prompt information that the data transmission is completed, that is, the interrupt request.
- an interrupt type configured in the FPGA, where the interrupt type includes at least one of an INTx interrupt type, an MSI interrupt type, and an MSI-X interrupt type.
- the interrupt type configured in the FPGA is that the FPGA selects an interrupt type that the processor can process according to an interrupt type that the processor can process. If there is more than one interrupt type that satisfies the interrupt type that the processor can handle, the optimal interrupt type is selected (the MSI-X interrupt type is better than the MSI interrupt type, and the MSI interrupt type is better than the INTx interrupt type).
- the interrupt type configured in the FPGA may be an INTx interrupt type and an MSI interrupt type, or may be an INTx interrupt type, an MSI interrupt type, and an MSI-X interrupt type, and may also be an INTx interrupt type and an MSI-X interrupt type. This embodiment does not limit this.
- the transmission interface is configured to transmit interrupt data, and the interrupt data is used to notify the processor that normal data transmission is completed. Because the interrupt type is different, the corresponding PCIe interrupt data is also different, so it is necessary to generate corresponding PCIe interrupt data according to the interrupt type.
- the interrupt data may be the information defined by the device memory PCIe standard, or may be the address of the interrupt vector, which is not limited in this embodiment.
- the transmission interfaces corresponding to the different types of interrupts are also different. Therefore, the transmission interface corresponding to the PCIe interrupt data on the PCIe interface needs to be determined according to the type of the interrupt. For example, if the interrupt type is INTx interrupt type, the corresponding transport interface is the CFG_INT interface; if the interrupt type For the MSI-X interrupt type, the corresponding transport interface is the AXI4-S interface.
- interrupt transmission interfaces corresponding to various interrupt types are as follows:
- the processor starts the interrupt operation after receiving the PCIe interrupt data.
- the peripheral device is an ultrasonic probe
- the ultrasonic probe acquires an ultrasonic signal that needs to be processed by the processor, and transmits the ultrasonic signal to the FPGA
- the data transmission unit in the FPGA transmits the ultrasonic signal to the AXI4-S interface.
- the data transfer unit sends a prompt message for completing the data transfer to the receiving module, that is, sends an interrupt request to the receiving module of the FPGA.
- the PCIe interrupt system includes an interrupt configuration module and an interrupt processing module.
- the driver layer acquires the type of interrupt that the processor can handle, and the interrupt configuration module configures the corresponding interrupt type, and the interrupt processing module configures the corresponding transmission interface according to the type of interrupt that the processor can handle.
- the PCIe interrupt data corresponding to the interrupt type is sent to the PCIe IP core through the corresponding transport interface, and the PCIe IP core sends the data to the PCIe root controller in the processor.
- the processor interrupt request is sent to the processor to implement the interrupt operation.
- the PCIe root controller acts as a hub for connecting CPU/memory and external devices.
- the root controller is at the core of the entire PCIe architecture.
- a root controller can support one or more PCIe ports. Each port defines a separate domain, each domain consisting of a single terminal, or a subsystem containing one or more switches and terminals. At the same time, according to the agreement, the root controller can support the function of packet routing between different domains according to specific choices.
- the technical solution of the embodiment receives the internal interrupt request through the FPGA, acquires the configured interrupt type in the FPGA, generates the PCIe interrupt data according to the interrupt type, and determines the transmission interface corresponding to the PCIe interrupt data on the PCIe interface according to the interrupt type; Send PCIe interrupt data.
- each interrupt function can be independently developed and maintained, and has no influence on each other, which reduces the development difficulty, and helps to realize the logical platform construction of the FPGA, and also ensures the platform construction of the driver layer from the bottom layer.
- the method before the step of receiving an interrupt request, the method further includes: configuring an interrupt type of the FPGA, and configuring The PCIe interface is a full type mode, wherein the full type mode supports all of the interrupt types.
- the method in this embodiment specifically includes the following steps:
- the interrupt type of the FPGA may be an INTx interrupt type, an MSI interrupt type, or an MSI-X interrupt type.
- the FPGA configures an interrupt type of the FPGA according to an interrupt type that the CPU can process.
- the interrupt type that the CPU can process is the INTx interrupt type
- the interrupt type of the FPGA is configured as the INTx interrupt type.
- the full-type mode is a data transmission that can support an INTx interrupt type, an MSI interrupt type data transmission, and an MSI-X interrupt type data transmission.
- the FPGA can provide the corresponding transmission interface as needed.
- DDR Double Data Rate, Double Rate Synchronous Dynamic Random Access Memory
- DMU Direct Memory Unit
- the configuration parameters include information such as transmission data length, destination address, channel number, and interrupt enable.
- the data transmission module in the FPGA uploads data to the CPU DDR main memory through the PCIe interface through DMA (Direct Memory Access), and the data transmission module sends the data transmission module to the receiving module in the FPGA.
- DMA Direct Memory Access
- the step of determining, according to the type of the interrupt, the transmission interface corresponding to the PCIe interrupt data includes:
- interrupt type MSI-X interrupt
- transmission interface is an AXI4-S interface
- the interrupt type is an MSI interrupt, it is determined that the transport interface is a CFG_INT interface;
- interrupt type is an INTx interrupt
- transport interface is a CFG_INT interface
- the MSI interrupt request is to write the data contained in the Message Data field to the address where the Message Address is located.
- the MSI-X interrupt mechanism stores a pointer to a set of Message Address and Message Data fields in the MSI-X Capablity structure, so that a PCIe device can support more than 32 MSI-X interrupt requests and does not require an interrupt vector. The number is continuous.
- the set of Message Address and Message Data fields used by the MSI-X mechanism are stored in the BAR space of the PCIe device, rather than in the configuration space of the PCIe device, so that the number of MSI-X interrupt requests can be determined by the user.
- the interrupt vector table corresponding to the MSI-X interrupt type exists in User Logic, and the User terminal can only be implemented by sending the MWr TLP packet containing the interrupt information, so the MSI-X interrupt must pass. Operate the AXI4-S interface implementation.
- the MSI interrupt type is stored in the PCIe Capability Structure and can be implemented by sending a MWr TLP packet or by operating the CFG_INT interface.
- the INTx interrupt type must be implemented by manipulating the CFG_INT interface.
- Interrupt The detailed processing flow of Interrupt is as follows: CPU configures the interrupt type; enables the corresponding module according to the configuration type; when the interrupt request comes, the enabled module executes the corresponding interrupt flow; the interrupt execution is completed, the idle state is returned, and the next interrupt is awaited. operating.
- the processing timing of sending the PCIe interrupt data through the transmission interface includes: an INTx interrupt execution flow and an MSI interrupt execution flow;
- the INTx interrupt execution flow includes:
- the cfg_interrupt_rdy signal of the CFG_INT interface is set high by the CPU, the cfg_interrupt signal is set to a high level, and the cfg_interrupt_assert signal is set to a low level;
- the interrupt is committed by configuring the interfaces cfg_interrupt and cfg_interrupt_assert.
- cfg_interrupt_rdy is asserted, indicating that the interrupt request is accepted.
- the position shown in 2 in the figure is that the INTx interrupt request is received, and at the rising edge of the clock output, the interrupt set signal (cfg_interrupt_assert signal), the interrupt request signal (cfg_interrupt signal), and the interrupt response signal ( The cfg_interrupt_rdy signal) is high.
- the position shown in Figure 3 is to release the INTx interrupt request.
- the interrupt request signal (cfg_interrupt signal) is high
- the interrupt set signal (cfg_interrupt_assert signal) is low
- the interrupt response signal (cfg_interrupt_rdy) The signal) is high and it is determined that the CPU responds to the INTx interrupt request.
- the MSI interrupt execution process includes:
- the cfg_interrupt signal and the cfg_interrupt_di signal of the CFG_INT interface are set to a first flag, and the cfg_interrupt signal is set high and the cfg_interrupt_di signal is set to 01h.
- the cfg_interrupt_rdy signal of the CFG_INT interface is detected to be set high by the CPU, the cfg_interrupt signal and the cfg_interrupt_di signal are set to the second flag bit as the interrupt request;
- the cfg_interrupt signal and the cfg_interrupt_di signal are set to the second flag bit to set the cfg_interrupt signal and set the cfg_interrupt_di signal to 00h.
- the position shown in FIG. 5 is that the MSI interrupt request is received.
- the interrupt request signal (cfg_interrupt signal) of the CFG_INT interface is high, and the input data signal is interrupted (cfg_interrupt_di).
- the signal) is 01h and the interrupt response signal (cfg_interrupt_rdy signal) is high.
- the position shown in Figure 4 is to release the MSI interrupt request.
- the interrupt request signal (cfg_interrupt signal) of the CFG_INT interface is high, the interrupt input data signal (cfg_interrupt_di signal) is 00h, and the interrupt response signal ( The cfg_interrupt_rdy signal) is high, and it is determined that the CPU responds to the MSI interrupt request.
- the processing sequence for sending the PCIe interrupt data by using the transmission interface includes:
- the ASI4-S complies with the standard AXI4-Stream specification, in which the interrupt address and interrupt data are included in the data packet, and are pre-RC configured to the FPGA internal module.
- the packet format needs to comply with the PCIe TLP data structure provided by Xilinx.
- s_ais_tx_tready signal of the AXI4-S interface When the s_ais_tx_tready signal of the AXI4-S interface is detected to be set high by the CPU, it indicates that the currently transmitted data is received. When s_axis_tx_tlast is set to high level, it indicates that it is the last interrupt data transmission;
- s_ais_tx_tready signal of the AXI4-S interface is detected to be high by the CPU, indicating that the entire interrupt data transfer is completed, s_axis_tx_tvalid, s_axis_tx_tlast, s_axis_tx_tdata, s_axis_tx_tkeep are set low.
- the data transmission between the PCIe core and the PCIe Root Complex is implemented through the AXI4-S interface.
- the position shown in FIG. 1 is the AXI4-S interface data transmission completion.
- s_axis_tx_tvalid, s_axis_tx_tlast, and s_axis_tx_tready are high, indicating that the transmission is completed.
- the packet format follows the PCIe TLP data structure provided by Xilinx, where the transport type field (TC field) defines the transport type of the message, the TD bit indicates whether the TLP Digest in the TLP is valid, and the EP bit indicates the current TLP. Whether the data in the message is valid, the message model field defines the message Model, the payload of the message (Length), that is, the number of double words (DW) to be read.
- the first tag consists of eight bits, which determines that the sender can temporarily store 256 TLPs of the same type. The application layer needs to be based on The payload and address of the message, and the completion message is used to return the corresponding data.
- the interrupt type of the FPGA is configured, and the PCIe interface is configured to be a full-type mode, wherein the full-type mode supports all the interrupt types. It can guarantee that no matter what type of CPU (ARM, x86, PowerPC, etc.) is used on the CPU side, no matter which type of interrupt (INTx, MSI, MSI-X) is supported, the FPGA side can support and enhance the FPGA pair.
- the compatibility of the interrupt type realizes the consistency of the interface and the standardization of the interrupt processing between the CPU and the PCIe, and at the same time, the FPGA platform construction can be improved.
- FIG. 7 is a schematic structural diagram of a PCIe interrupt system according to Embodiment 3 of the present invention, where the system is configured to execute a PCIe interrupt method. As shown in FIG. 7, the data communication is implemented between the FPGA and the processor through the PCIe interface.
- the PCIe interrupt system specifically includes an interrupt control module 310 and a PCIe interface module 320.
- the interrupt control module 310 is configured to receive an interrupt request, acquire an interrupt type configured in the FPGA, generate PCIe interrupt data according to the interrupt type, and determine the PCIe interface module 320 according to the interrupt type. Transmission interface, wherein the interrupt type includes at least one of an INTx interrupt type, an MSI interrupt type, and an MSI-X interrupt type;
- the interrupt control module 310 transmits the PCIe interrupt data through the transmission interface.
- the method further includes: an interrupt configuration module 330, configured to configure an interrupt type of the FPGA.
- the PCIe interface module is further configured to configure the PCIe interface to be a full-type mode, wherein the full-type mode supports all of the interrupt types.
- the interrupt control module is further configured to:
- the transmission interface is an AXI4-S interface
- the interrupt type is an MSI interrupt, determining that the transport interface is a CFG_INT interface;
- the transport interface is the CFG_INT interface.
- the processing timing of sending the PCIe interrupt data through the transmission interface includes: an INTx interrupt execution flow and an MSI interrupt execution flow;
- the INTx interrupt execution flow includes:
- the cfg_interrupt_rdy signal of the CFG_INT interface is set high by the CPU, the cfg_interrupt signal is set to a high level, and the cfg_interrupt_assert signal is set to a low level;
- the MSI interrupt execution process includes:
- the cfg_interrupt_rdy signal of the CFG_INT interface is detected to be set high by the CPU, the cfg_interrupt signal and the cfg_interrupt_di signal are set to the second flag bit as the interrupt request;
- the processing sequence for sending the PCIe interrupt data by using the transmission interface includes:
- s_ais_tx_tready signal of the AXI4-S interface When the s_ais_tx_tready signal of the AXI4-S interface is detected to be set high by the CPU, it indicates that the currently transmitted data is received. When s_axis_tx_tlast is set to high level, it indicates that it is the last interrupt data transmission;
- s_ais_tx_tready signal of the AXI4-S interface is detected to be high by the CPU, indicating that the entire interrupt data transfer is completed, s_axis_tx_tvalid, s_axis_tx_tlast, s_axis_tx_tdata, s_axis_tx_tkeep are set low.
- the technical solution of the embodiment receives the interrupt request, acquires the configured interrupt type in the FPGA, generates the PCIe interrupt data according to the interrupt type, and determines the transmission interface corresponding to the PCIe interrupt data on the PCIe interface according to the interrupt type; and sends the PCIe through the transmission interface.
- Interrupt data Expanded FPGA compatibility with processor interrupts. And each interrupt function can be independently developed and maintained, and each other There will be no impact between them, which will reduce the development difficulty, and help to realize the logical platform construction of FPGA, and also ensure the platform construction of the driver layer from the bottom.
- the above product can perform the method provided by any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Information Transfer Systems (AREA)
Abstract
一种PCIe中断方法和***,该方法包括:接收中断请求(S110);获取FPGA中已配置的中断类型(S120);根据中断类型生成PCIe中断数据,并根据中断类型确定PCIe接口上PCIe中断数据对应的传输接口(S130);通过传输接口发送PCIe中断数据(S140)。通过该方法,扩展了FPGA对处理器中断的兼容性。而且每种中断功能都可以独立开发和维护,且相互之间不会产生影响,降低了开发难度,且有助于实现FPGA逻辑平台化建设,也能从底层保证驱动层的平台化建设。
Description
本申请要求于2016年12月27日提交中国专利局、申请号为201611227961.1、发明名称为“PCIe中断方法和***”的中国专利申请的优先权,其全部内容通过引用结合在本申请中。
本发明实施例涉及通信技术领域,尤其涉及一种PCIe中断方法和***。
PCIe(Peripheral Component Interconnect Express,高速***组件互联)是最新的总线和接口标准,这个新标准将全面取代现行的PCI和AGP,最终实现总线标准的统一。
基于引脚的PCI中断也就是INTx中断,经常在几个设备间共享,内核必须调用与该中断相关的每一个中断处理函数,效率比较低。当设备向内存写入数据,然后发起引脚中断时,有可能在CPU接收到中断时,数据还未到达内存(在PCI-PCI桥后的设备更有可能如此)。为了保证数据已达到内存,中断处理程序必须轮询产生该中断的设备的一个寄存器,PCI事务保序规则会确保所有数据达到内存后,寄存器才会返回值。
PCI的每个功能设备只支持一个基于引脚的中断,驱动常常需要查询设备来确定发生的事件,降低了中断处理的效率,因此在PCIe***中采用了MSI中断。MSI中断不是共享的,因此不存在INTx中断中共享的问题,使用MSI时,产生中断的写操作不能超过数据写操作,因而当中断产生时,驱动可以确信所有数据已经到达内存。MSI中断是采用向特定地址写入特定数值的方式实现,而且可以支持最多32个中断向量,但MSI中断又存在中断向量号必须连续的约束。为了解决此问题,MSI-X也被提出,与MSI Capability寄存器相比,
MSI-X Capability寄存器使用一个数组存放Message Address字段和Message Data字段,而不是将这两个字段放入Capability寄存器中。从而当PCIE设备使用MSI-X机制时,每一个中断请求可以使用独立的Message Address字段和Message Data字段。MSI-X不需要中断向量号连续,而且可支持最多2048个中断向量。不同的处理器对PCIE设备发出的MSI报文的解释并不相同。但是PCIe设备在提交MSI中断请求时,都是向MSI/MSI-X Capability结构中的Message Address的地址写Message Data数据,从而组成一个存储器写TLP,向处理器提交中断请求。
在实际设计中,驱动所支持的中断类型可能是传统INTx中断、MSI中断或者是MSI-X中断中的一种或多种。基于开发简便的原因,可能硬件逻辑只完成和其匹配的某种中断,而放弃其余2种中断方式。这样就会造成在后续的驱动平台升级过程中可能支持的中断类型发生变化,从而导致底层FPGA开发人员要做相应功能适配来配合软件的升级,从而增加了项目周期和可维护性,也不利于项目的平台化实现。
发明内容
本发明实施例提供一种PCIe中断方法和***,以扩展FPGA对处理器中断的兼容性。
第一方面,本发明实施例提供了一种PCIe中断方法,FPGA与处理器之间通过PCIe接口实现数据通信,该方法包括:
接收中断请求;
获取所述FPGA中已配置的中断类型,其中,所述中断类型包括INTx中断类型、MSI中断类型和MSI-X中断类型中的至少一种;
根据所述中断类型生成PCIe中断数据,并根据所述中断类型确定所述PCIe接口上所述PCIe中断数据对应的传输接口;
通过所述传输接口发送所述PCIe中断数据。
进一步的,在所述接收中断请求的步骤之前,还包括:
配置所述FPGA的中断类型,并配置所述PCIe接口为全类型模式,其中,所述全类型模式支持所有所述中断类型。
进一步的,所述根据所述中断类型确定所述PCIe中断数据对应的传输接口的步骤包括:
若中断类型为MSI-X中断,则确定传输接口为AXI4-S接口;
若中断类型为MSI中断,则确定传输接口为CFG_INT接口;
若中断类型为INTx中断,则确定传输接口为CFG_INT接口。
进一步的,当传输接口为CFG_INT接口时,通过所述传输接口发送所述PCIe中断数据的处理时序包括:INTx中断执行流程和MSI中断执行流程;
所述INTx中断执行流程包括:
将CFG_INT接口的cfg_interrupt_assert信号和cfg_interrupt信号置为高电平;
当监测到CFG_INT接口的cfg_interrupt_rdy信号被CPU置为高电平时,将所述cfg_interrupt信号置为高电平,且将所述cfg_interrupt_assert信号置为低电平;
当所述cfg_interrupt_rdy信号被CPU置为高电平时,确定所述CPU响应所述中断;
所述MSI中断执行流程包括:
将所述CFG_INT接口的cfg_interrupt信号和cfg_interrupt_di信号置为第一标志位;
在监测到CFG_INT接口的cfg_interrupt_rdy信号被CPU置为高电平时,将所述cfg_interrupt信号和cfg_interrupt_di信号置为第二标志位,作为所述中断请求;
在所述cfg_interrupt_rdy信号被CPU置为高电平时,确定所述CPU响应所述中断请求。
进一步的,当传输接口为AXI4-S接口时,通过所述传输接口发送所述PCIe中断数据的处理时序包括:
将AXI4-S接口的s_axis_tx_tvalid信号置为高电平,s_axis_tx_tdata、s_axis_tx_tkeep、s_axis_tx_tlast信号填充适当数据;
当监测到AXI4-S接口的s_ais_tx_tready信号被CPU置为高电平时,表明当前传输的数据被接收,当s_axis_tx_tlast置为高电平时,表明是最后一笔中断数据传输;
当监测到AXI4-S接口的s_ais_tx_tready信号被CPU置为高电平时,表明整个中断数据传输完成,则将s_axis_tx_tvalid、s_axis_tx_tlast、s_axis_tx_tdata、s_axis_tx_tkeep置为低电平。
第二方面,本发明实施例还提供了一种PCIe中断***,FPGA与处理器之间通过PCIe接口实现数据通信,该***包括:中断控制模块和PCIe接口模块;
所述中断控制模块,用于接收中断请求,获取所述FPGA中已配置的中断类型,根据所述中断类型生成PCIe中断数据,并根据所述中断类型确定所述PCIe接口模块上的传输接口,其中,所述中断类型包括INTx中断类型、MSI中断类型和MSI-X中断类型中的至少一种;
所述中断控制模块通过所述传输接口发送所述PCIe中断数据。
进一步的,还包括:
中断配置模块,用于配置所述FPGA的中断类型;
所述PCIe接口模块还用于配置所述PCIe接口为全类型模式,其中,所述全类型模式支持所有所述中断类型。
进一步的,所述中断控制模块还用于:
当所述中断类型为MSI-X中断时,则确定传输接口为AXI4-S接口;
当所述中断类型为MSI中断时,则确定传输接口为CFG_INT接口;
当中断类型为INTx中断时,则确定传输接口为CFG_INT接口。
进一步的,当传输接口为CFG_INT接口时,通过所述传输接口发送所述PCIe中断数据的处理时序包括:INTx中断执行流程和MSI中断执行流程;
所述INTx中断执行流程包括:
将CFG_INT接口的cfg_interrupt_assert信号和cfg_interrupt信号置为高电平;
当监测到CFG_INT接口的cfg_interrupt_rdy信号被CPU置为高电平时,将所述cfg_interrupt信号置为高电平,且将所述cfg_interrupt_assert信号置为低电平;
当所述cfg_interrupt_rdy信号被CPU置为高电平时,确定所述CPU响应所述中断;
所述MSI中断执行流程包括:
将所述CFG_INT接口的cfg_interrupt信号和cfg_interrupt_di信号置为第一标志位;
在监测到CFG_INT接口的cfg_interrupt_rdy信号被CPU置为高电平时,将所述cfg_interrupt信号和cfg_interrupt_di信号置为第二标志位,作为所述中断请求;
在所述cfg_interrupt_rdy信号被CPU置为高电平时,确定所述CPU响应所述中断请求。
进一步的,当传输接口为AXI4-S接口时,通过所述传输接口发送所述PCIe中断数据的处理时序包括:
将AXI4-S接口的s_axis_tx_tvalid信号置为高电平,s_axis_tx_tdata、s_axis_tx_tkeep、s_axis_tx_tlast信号填充适当数据;
当监测到AXI4-S接口的s_ais_tx_tready信号被CPU置为高电平时,表明当前传输的数据被接收,当s_axis_tx_tlast置为高电平时,表明是最后一笔中断数据传输;
当监测到AXI4-S接口的s_ais_tx_tready信号被CPU置为高电平时,表明整个中断数据传输完成,则将s_axis_tx_tvalid、s_axis_tx_tlast、s_axis_tx_tdata、s_axis_tx_tkeep置为低电平。
本发明实施例通过接收中断请求;获取FPGA中已配置的中断类型;根据中断类型生成PCIe中断数据,并根据中断类型确定PCIe接口上PCIe中断数据对应的传输接口;通过传输接口发送PCIe中断数据。扩展了FPGA对CPU中断的兼容性。而且每种中断功能都可以独立开发和维护,且相互之间不会产生影响,降低了开发难度,且有助于实现FPGA逻辑平台化建设,也能从底层保证驱动层的平台化建设。
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施
例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1是本发明实施例一中的一种PCIe中断方法的流程图;
图2是本发明实施例一中的一种PCIe中断***的结构示意图;
图3是本发明实施例二中的一种PCIe中断方法的流程图;
图4是本发明实施例二中的PCIe中断处理时序图;
图5是本发明实施例二中的PCIe中断处理时序图;
图6是本发明实施例二中的PCIe中断数据包结构示意图;
图7是本发明实施例三中的一种PCIe中断***的结构示意图;
图8是本发明实施例三中的另一示例的PCIe中断***的结构示意图。
下面结合附图和实施例对本发明作进一步的详细说明。可以理解的是,此处所描述的具体实施例仅仅用于解释本发明,而非对本发明的限定。另外还需要说明的是,为了便于描述,附图中仅示出了与本发明相关的部分而非全部结构。
实施例一
图1为本发明实施例一提供的一种PCIe中断方法的流程图,本实施例可适用于PCIe中断的情况,该方法可以由本发明实施例中PCIe中断***来执行,该***可采用软件和/或硬件的方式实现。对于一个具备某种功能的***,其一般会包括CPU处理器,其是响应各种计算处理需求的核心器件。该***还可能包括各种***设备,例如键盘、鼠标、显示器、超声探头或存储器等。本发明实施例的方案中,提供了FPGA(Field-Programmable Gate Array,即现场可编程门阵列),其设置在***设备和处理器CPU之间,辅助***设备向CPU发起中断请求,也可以为FPGA获取CPU中的数据,向CPU发送中断,要求CPU为自己进行数据处理。FPGA与CPU之间通过PCIe接口实现数据通信。
如图1所示,该方法具体包括如下步骤:
S110,接收中断请求。
该中断请求作为FPGA的内部中断请求,为开始中断数据传输的操作提示。所述普通数据为需要处理器处理的数据。具体过程为:***设备获取普通数据(若***设备为超声探头,则普通数据可以为超声波信号),并将数据传输至FPGA,FPGA包括数据传输模块和接收模块。接收模块用于接收***设备传输的普通数据,数据传输模块用于通过AXI4-S接口将***设备获取的普通数据发送至内存。内存和处理器属于同一设备,处理器负责运算和处理,内存负责数据交换。在数据传输模块将数据全部传输至内存后,数据传输模块向接收模块发送数据已经全部传输至内存的提示信息,接收模块接收提示信息。本实施例中的中断请求指的是数据传输模块将数据传输至内存,数据传输完成后,接收模块接收到数据传输完成的提示信息,即中断请求。
S120,获取所述FPGA中已配置的中断类型,其中,所述中断类型包括INTx中断类型、MSI中断类型和MSI-X中断类型中的至少一种。
其中,所述FPGA中配置的中断类型为所述FPGA根据处理器能够处理的中断类型,选取处理器能够处理的中断类型。若满足处理器能够处理的中断类型的中断类型不止一个,则选取其中最优的中断类型(MSI-X中断类型优于MSI中断类型,MSI中断类型优于INTx中断类型)。其中,所述FPGA中配置的中断类型可以为INTx中断类型和MSI中断类型,也可以为INTx中断类型、MSI中断类型和MSI-X中断类型,还可以为INTx中断类型和MSI-X中断类型,本实施例对此不进行限制。
S130,根据所述中断类型生成PCIe中断数据,并根据所述中断类型确定所述PCIe接口上所述PCIe中断数据对应的传输接口。
其中,所述传输接口用于传输中断数据,所述中断数据用于通知处理器普通数据传输完成。由于中断类型不同,相应的PCIe中断数据也不相同,因此需要根据所述中断类型生成相对应的PCIe中断数据。所述中断数据可以为设备存储器PCIe标准定义的信息,也可以为中断向量的地址,本实施例对此不进行限制。不同的中断类型对应的传输接口也不相同,因此需要根据所述中断类型确定所述PCIe接口上所述PCIe中断数据对应的传输接口。例如,如果中断类型为INTx中断类型,则相应的传输接口为CFG_INT接口;如果中断类型
为MSI-X中断类型,则相应的传输接口为AXI4-S接口。
具体的,各种中断类型所对应中断传输接口如下表所示:
S140,通过所述传输接口发送所述PCIe中断数据。
处理器接收PCIe中断数据后开始进行中断操作。
在一个具体的例子中,若***设备为超声探头,超声探头获取需要处理器处理的超声波信号,将所述超声波信号传输至FPGA,FPGA中的数据传输单元通过AXI4-S接口将超声波信号传输至内存,数据传输完成之后,数据传输单元向接收模块发送数据传输完成的提示信息,也就是向FPGA的接收模块发送中断请求,如图2所示,PCIe中断***包括中断配置模块和中断处理模块,FPGA接收到超声波信号已经全部传输至内存的信息后,驱动层获取处理器能够处理的中断类型,中断配置模块配置相应的中断类型,中断处理模块根据处理器能够处理的中断类型配置相应的传输接口,将所述中断类型对应的PCIe中断数据通过相应的传输接口发送至PCIe IP核,PCIe IP核将数据发送至处理器中PCIe根控制器。进而实现将处理器中断请求发送至处理器,实现中断操作。PCIe根控制器作为连接CPU/内存和外部设备的枢纽,根控制器在整个PCIe体系结构中处于核心位置,它是I/O层次***与CPU/内存***连接的最顶层。一个根控制器可以支持一个或多个PCIe端口。每个端口定义了一个独立的域,每个域由一个单独的终端,或一个包含一个或多个交换机和终端的子***构成。同时,根据协议规定,根控制器中可以根据具体选择支持不同域间报文路由的功能。
本实施例的技术方案,通过FPGA接收内部中断请求;获取FPGA中已配置的中断类型;根据中断类型生成PCIe中断数据,并根据中断类型确定PCIe接口上PCIe中断数据对应的传输接口;通过传输接口发送PCIe中断数据。扩展了FPGA对处理器中断的兼容性。而且每种中断功能都可以独立开发和维护,且相互之间不会产生影响,降低了开发难度,且有助于实现FPGA逻辑平台化建设,也能从底层保证驱动层的平台化建设。
实施例二
图3为本发明实施例二中的一种PCIe中断方法的流程示意图,在上述实施例的基础上,在所述接收中断请求的步骤之前,还包括:配置所述FPGA的中断类型,并配置所述PCIe接口为全类型模式,其中,所述全类型模式支持所有所述中断类型。
如图3所示,本实施例的方法具体包括如下步骤:
S210,配置所述FPGA的中断类型,并配置所述PCIe接口为全类型模式,其中,所述全类型模式支持所有所述中断类型。
其中,所述FPGA的中断类型可以为INTx中断类型,也可以为MSI中断类型,还可以为MSI-X中断类型。所述FPGA根据CPU能够处理的中断类型配置所述FPGA的中断类型。例如可以是,CPU能够处理的中断类型为INTx中断类型,配置所述FPGA的中断类型为INTx中断类型。
具体的,所述全类型模式为可以支持INTx中断类型的数据传输,也可以支持MSI中断类型的数据传输,还可以为支持MSI-X中断类型的数据传输。
具体的,由于所述INTx中断类型、MSI中断类型以及MSI-X中断类型需要的传输接口不同,因此,FPGA如果需要支持所有的中断类型,则需要配置多个传输接口,在不同的中断类型的情况下使用不同的传输接口传输数据。这样就可以保证不论外接设备的中断类型为INTx中断类型、MSI中断类型还是MSI-X中断类型,FPGA都可以根据需要为其提供相应的传输接口。
S220,接收中断请求。
具体的,先阐述一下FPGA和CPU之间的数据交换过程,以最常见的FPGA上传数据至DDR(Double Data Rate,双倍速率同步动态随机存储器)为例。当FPGA端想要上传数据至CPU端的主存设备时,为了减轻CPU负担在FPGA侧通常情况下会放入DMU(Direct Memory Unit,直接内存单元)模块,最初时刻DMU处于闲置状态,等待CPU配置DMU模块,其中,配置参数有传输数据长度、目标地址、通道号以及中断使能等信息。FPGA中数据传输模块通过DMA(Direct Memory Access,存储器直接访问)的方式透过PCIe接口将数据上传至CPU端DDR主存,当数据传输模块将数据搬运完成数据传输模块向FPGA中的接收模块发送内部中断请求,FPGA中的接收模块会接收到内部中断请求。
S230,获取所述FPGA中已配置的中断类型,其中,所述中断类型包括INTx中断类型、MSI中断类型和MSI-X中断类型中的至少一种。
S240,根据所述中断类型生成PCIe中断数据,并根据所述中断类型确定所述PCIe接口上所述PCIe中断数据对应的传输接口。
可选的,所述根据所述中断类型确定所述PCIe中断数据对应的传输接口的步骤包括:
若中断类型为MSI-X中断,则确定传输接口为AXI4-S接口;
若中断类型为MSI中断,则确定传输接口为CFG_INT接口;
若中断类型为INTx中断,则确定传输接口为CFG_INT接口。
MSI中断请求是向Message Address所在的地址写Message Data字段包含的数据。MSI-X中断机制在MSI-X Capablity结构中存放了一个指向一组Message Address和Message Data字段的指针,从而一个PCIe设备可以支持的MSI-X中断请求数目大于32个,而且并不要求中断向量号连续。MSI-X机制使用的这组Message Address和Message Data字段存放在PCIe设备的BAR空间中,而不是在PCIe设备的配置空间中,从而可以由用户决定使用MSI-X中断请求的数目。
S250,通过所述传输接口发送所述PCIe中断数据。
具体的,数据搬运完成需要进行Interrupt中断请求处理,MSI-X中断类型对应的中断向量表存在于User Logic,User端只能通过发送含有中断信息的MWr TLP包实现,因此MSI-X中断必须通过操作AXI4-S接口实现。MSI中断类型存放于PCIe Capability Structure中,可以通过发送MWr TLP包或者操作CFG_INT接口来实现。INTx中断类型必须通过操作CFG_INT接口实现。其Interrupt详细处理流程如下:CPU配置中断类型;根据配置类型使能相应模块;在中断请求来到时,被使能的模块执行相应的中断流程;中断执行完成,返回空闲状态,等待下一次中断操作。
可选的,当传输接口为CFG_INT接口时,通过所述传输接口发送所述PCIe中断数据的处理时序包括:INTx中断执行流程和MSI中断执行流程;
所述INTx中断执行流程包括:
将CFG_INT接口的cfg_interrupt_assert信号和cfg_interrupt信号置
为高电平;
当监测到CFG_INT接口的cfg_interrupt_rdy信号被CPU置为高电平时,将所述cfg_interrupt信号置为高电平,且将所述cfg_interrupt_assert信号置为低电平;
当所述cfg_interrupt_rdy信号被CPU置为高电平时,确定所述CPU响应所述中断;
具体的,通过配置接口cfg_interrupt和cfg_interrupt_assert来提交中断,当接收到有效中断时将cfg_interrupt_rdy置为有效,表示中断请求被接受。
具体的,如图4所示,图中2所示位置为INTx中断请求被接收,在时钟输出的上升沿,中断置位信号(cfg_interrupt_assert信号)、中断请求信号(cfg_interrupt信号)以及中断响应信号(cfg_interrupt_rdy信号)为高电平。图中3所示的位置为释放INTx中断请求,在时钟输出的上升沿,中断请求信号(cfg_interrupt信号)为高电平,中断置位信号(cfg_interrupt_assert信号)为低电平以及中断响应信号(cfg_interrupt_rdy信号)为高电平,确定所述CPU响应INTx中断请求。
所述MSI中断执行流程包括:
将所述CFG_INT接口的cfg_interrupt信号和cfg_interrupt_di信号置为第一标志位;
其中,将所述CFG_INT接口的cfg_interrupt信号和cfg_interrupt_di信号置为第一标志位可以为置高cfg_interrupt信号和将cfg_interrupt_di信号置为01h。
在监测到CFG_INT接口的cfg_interrupt_rdy信号被CPU置为高电平时,将所述cfg_interrupt信号和cfg_interrupt_di信号置为第二标志位,作为所述中断请求;
其中,将所述cfg_interrupt信号和cfg_interrupt_di信号置为第二标志位可以为置高cfg_interrupt信号和将cfg_interrupt_di信号置为00h。
在所述cfg_interrupt_rdy信号被CPU置为高电平时,确定所述CPU响应所述中断请求。
具体的,如图4所示,图中5所示位置为MSI中断请求被接收,在时钟输出的上升沿,CFG_INT接口的中断请求信号(cfg_interrupt信号)为高电平、中断输入数据信号(cfg_interrupt_di信号)为01h以及中断响应信号(cfg_interrupt_rdy信号)为高电平。图中4所示的位置为释放MSI中断请求,在时钟输出的上升沿,CFG_INT接口的中断请求信号(cfg_interrupt信号)为高电平、中断输入数据信号(cfg_interrupt_di信号)为00h以及中断响应信号(cfg_interrupt_rdy信号)为高电平,确定所述CPU响应MSI中断请求。
可选的,当传输接口为AXI4-S接口时,通过所述传输接口发送所述PCIe中断数据的处理时序包括:
具体的,ASI4-S遵守标准AXI4-Stream规范,其中的中断地址和中断数据包含在数据包内,都是预先RC配置到FPGA内部模块的。数据包格式需要遵从Xilinx提供的PCIe TLP数据结构。
将AXI4-S接口的s_axis_tx_tvalid信号置为高电平,s_axis_tx_tdata、s_axis_tx_tkeep、s_axis_tx_tlast信号填充适当数据;
当监测到AXI4-S接口的s_ais_tx_tready信号被CPU置为高电平时,表明当前传输的数据被接收,当s_axis_tx_tlast置为高电平时,表明是最后一笔中断数据传输;
当监测到AXI4-S接口的s_ais_tx_tready信号被CPU置为高电平时,表明整个中断数据传输完成,则将s_axis_tx_tvalid、s_axis_tx_tlast、s_axis_tx_tdata、s_axis_tx_tkeep置为低电平。
具体的,通过AXI4-S接口实现PCIe核与PCIe Root Complex之间数据的传输。
具体的,如图5所示,图中1所示位置为AXI4-S接口数据传输完成,在时钟输出的上升沿,s_axis_tx_tvalid、s_axis_tx_tlast以及s_axis_tx_tready为高电平,表明传输完成。
如图6所示,数据包格式遵从Xilinx提供的PCIe TLP数据结构,其中,传送类型字段(TC字段)定义报文的传送类型,TD位表示TLP中的TLP Digest是否有效,EP位表示当前TLP中的数据是否有效,报文模型字段定义报文的
模型,报文的有效负载(Length),即需要读取的双字(DW)个数,第一标记由八位组成,决定了发送端能够暂存256个同类型的TLP,应用层需要根据报文的有效负载(Length)及地址(Address),使用完成报文返回相应的数据。
本实施例的技术方案,通过配置所述FPGA的中断类型,并配置所述PCIe接口为全类型模式,其中,所述全类型模式支持所有所述中断类型。能够保证不管CPU端采用何种类型的CPU(ARM、x86、PowerPC等),也无论其支持哪种类型的中断(INTx、MSI、MSI-X),FPGA侧均可以支持,增强了FPGA对3种中断类型的兼容性,实现了接口的一致性以及CPU和PCIe之间的中断处理标准化,同时,亦可提升FPGA平台建设。
实施例三
图7为本发明实施例三的一种PCIe中断***的结构示意图,所述***用于执行PCIe中断方法。如图7所示,FPGA与处理器之间通过PCIe接口实现数据通信,所述PCIe中断***具体包括:中断控制模块310和PCIe接口模块320。
其中,所述中断控制模块310,用于接收中断请求,获取所述FPGA中已配置的中断类型,根据所述中断类型生成PCIe中断数据,并根据所述中断类型确定所述PCIe接口模块320上的传输接口,其中,所述中断类型包括INTx中断类型、MSI中断类型和MSI-X中断类型中的至少一种;
所述中断控制模块310通过所述传输接口发送所述PCIe中断数据。
可选的,如图8所示,还包括:中断配置模块330,用于配置所述FPGA的中断类型。所述PCIe接口模块还用于配置所述PCIe接口为全类型模式,其中,所述全类型模式支持所有所述中断类型。
可选的,所述中断控制模块还用于:
当所述中断类型为MSI-X中断时,则确定传输接口为AXI4-S接口;
当所述中断类型为MSI中断时,则确定传输接口为CFG_INT接口;
当中断类型为INTx中断时,则确定传输接口为CFG_INT接口。
可选的,当传输接口为CFG_INT接口时,通过所述传输接口发送所述PCIe中断数据的处理时序包括:INTx中断执行流程和MSI中断执行流程;
所述INTx中断执行流程包括:
将CFG_INT接口的cfg_interrupt_assert信号和cfg_interrupt信号置为高电平;
当监测到CFG_INT接口的cfg_interrupt_rdy信号被CPU置为高电平时,将所述cfg_interrupt信号置为高电平,且将所述cfg_interrupt_assert信号置为低电平;
当所述cfg_interrupt_rdy信号被CPU置为高电平时,确定所述CPU响应所述中断;
所述MSI中断执行流程包括:
将所述CFG_INT接口的cfg_interrupt信号和cfg_interrupt_di信号置为第一标志位;
在监测到CFG_INT接口的cfg_interrupt_rdy信号被CPU置为高电平时,将所述cfg_interrupt信号和cfg_interrupt_di信号置为第二标志位,作为所述中断请求;
在所述cfg_interrupt_rdy信号被CPU置为高电平时,确定所述CPU响应所述中断请求。
可选的,当传输接口为AXI4-S接口时,通过所述传输接口发送所述PCIe中断数据的处理时序包括:
将AXI4-S接口的s_axis_tx_tvalid信号置为高电平,s_axis_tx_tdata、s_axis_tx_tkeep、s_axis_tx_tlast信号填充适当数据;
当监测到AXI4-S接口的s_ais_tx_tready信号被CPU置为高电平时,表明当前传输的数据被接收,当s_axis_tx_tlast置为高电平时,表明是最后一笔中断数据传输;
当监测到AXI4-S接口的s_ais_tx_tready信号被CPU置为高电平时,表明整个中断数据传输完成,则将s_axis_tx_tvalid、s_axis_tx_tlast、s_axis_tx_tdata、s_axis_tx_tkeep置为低电平。
本实施例的技术方案,通过接收中断请求;获取FPGA中已配置的中断类型;根据中断类型生成PCIe中断数据,并根据中断类型确定PCIe接口上PCIe中断数据对应的传输接口;通过传输接口发送PCIe中断数据。扩展了FPGA的对处理器中断的兼容性。而且每种中断功能都可以独立开发和维护,且相互
之间不会产生影响,降低了开发难度,且有助于实现FPGA逻辑平台化建设,也能从底层保证驱动层的平台化建设。
上述产品可执行本发明任意实施例所提供的方法,具备执行方法相应的功能模块和有益效果。
注意,上述仅为本发明的较佳实施例及所运用技术原理。本领域技术人员会理解,本发明不限于这里所述的特定实施例,对本领域技术人员来说能够进行各种明显的变化、重新调整和替代而不会脱离本发明的保护范围。因此,虽然通过以上实施例对本发明进行了较为详细的说明,但是本发明不仅仅限于以上实施例,在不脱离本发明构思的情况下,还可以包括更多其他等效实施例,而本发明的范围由所附的权利要求范围决定。
Claims (10)
- 一种PCIe中断方法,FPGA与处理器之间通过PCIe接口实现数据通信,其特征在于,包括以下步骤:接收中断请求;获取所述FPGA中已配置的中断类型,其中,所述中断类型包括INTx中断类型、MSI中断类型和MSI-X中断类型中的至少一种;根据所述中断类型生成PCIe中断数据,并根据所述中断类型确定所述PCIe接口上所述PCIe中断数据对应的传输接口;通过所述传输接口发送所述PCIe中断数据。
- 根据权利要求1所述的方法,其特征在于,在所述接收中断请求的步骤之前,还包括:配置所述FPGA的中断类型,并配置所述PCIe接口为全类型模式,其中,所述全类型模式支持所有所述中断类型。
- 根据权利要求1所述的方法,其特征在于,所述根据所述中断类型确定所述PCIe中断数据对应的传输接口的步骤包括:若中断类型为MSI-X中断,则确定传输接口为AXI4-S接口;若中断类型为MSI中断,则确定传输接口为CFG_INT接口;若中断类型为INTx中断,则确定传输接口为CFG_INT接口。
- 根据权利要求3所述的方法,其特征在于,当传输接口为CFG_INT接口时,通过所述传输接口发送所述PCIe中断数据的处理时序包括:INTx中断执行流程和MSI中断执行流程;所述INTx中断执行流程包括:将CFG_INT接口的cfg_interrupt_assert信号和cfg_interrupt信号置为高电平;当监测到CFG_INT接口的cfg_interrupt_rdy信号被CPU置为高电平时,将所述cfg_interrupt信号置为高电平,且将所述cfg_interrupt_assert信号置为低电平;当所述cfg_interrupt_rdy信号被CPU置为高电平时,确定所述CPU响应 所述中断;所述MSI中断执行流程包括:将所述CFG_INT接口的cfg_interrupt信号和cfg_interrupt_di信号置为第一标志位;在监测到CFG_INT接口的cfg_interrupt_rdy信号被CPU置为高电平时,将所述cfg_interrupt信号和cfg_interrupt_di信号置为第二标志位,作为所述中断请求;在所述cfg_interrupt_rdy信号被CPU置为高电平时,确定所述CPU响应所述中断请求。
- 根据权利要求3所述的方法,其特征在于,当传输接口为AXI4-S接口时,通过所述传输接口发送所述PCIe中断数据的处理时序包括:将AXI4-S接口的s_axis_tx_tvalid信号置为高电平,s_axis_tx_tdata、s_axis_tx_tkeep、s_axis_tx_tlast信号填充适当数据;当监测到AXI4-S接口的s_ais_tx_tready信号被CPU置为高电平时,表明当前传输的数据被接收,当s_axis_tx_tlast置为高电平时,表明是最后一笔中断数据传输;当监测到AXI4-S接口的s_ais_tx_tready信号被CPU置为高电平时,表明整个中断数据传输完成,则将s_axis_tx_tvalid、s_axis_tx_tlast、s_axis_tx_tdata、s_axis_tx_tkeep置为低电平。
- 一种PCIe中断***,FPGA与处理器之间通过PCIe接口实现数据通信,其特征在于,包括:中断控制模块和PCIe接口模块;所述中断控制模块,用于接收中断请求,获取所述FPGA中已配置的中断类型,根据所述中断类型生成PCIe中断数据,并根据所述中断类型确定所述PCIe接口模块上的传输接口,其中,所述中断类型包括INTx中断类型、MSI中断类型和MSI-X中断类型中的至少一种;所述中断控制模块通过所述传输接口发送所述PCIe中断数据。
- 根据权利要求6所述的***,其特征在于,还包括:中断配置模块,用于配置所述FPGA的中断类型;所述PCIe接口模块还用于配置所述PCIe接口为全类型模式,其中,所述全类型模式支持所有所述中断类型。
- 根据权利要求6所述的***,其特征在于,所述中断控制模块还用于:当所述中断类型为MSI-X中断时,则确定传输接口为AXI4-S接口;当所述中断类型为MSI中断时,则确定传输接口为CFG_INT接口;当中断类型为INTx中断时,则确定传输接口为CFG_INT接口。
- 根据权利要求8所述的***,其特征在于,当传输接口为CFG_INT接口时,通过所述传输接口发送所述PCIe中断数据的处理时序包括:INTx中断执行流程和MSI中断执行流程;所述INTx中断执行流程包括:将CFG_INT接口的cfg_interrupt_assert信号和cfg_interrupt信号置为高电平;当监测到CFG_INT接口的cfg_interrupt_rdy信号被CPU置为高电平时,将所述cfg_interrupt信号置为高电平,且将所述cfg_interrupt_assert信号置为低电平;当所述cfg_interrupt_rdy信号被CPU置为高电平时,确定所述CPU响应所述中断;所述MSI中断执行流程包括:将所述CFG_INT接口的cfg_interrupt信号和cfg_interrupt_di信号置为第一标志位;在监测到CFG_INT接口的cfg_interrupt_rdy信号被CPU置为高电平时,将所述cfg_interrupt信号和cfg_interrupt_di信号置为第二标志位,作为所述中断请求;在所述cfg_interrupt_rdy信号被CPU置为高电平时,确定所述CPU响应所述中断请求。
- 根据权利要求8所述的***,其特征在于,当传输接口为AXI4-S接口时,通过所述传输接口发送所述PCIe中断数据的处理时序包括:将AXI4-S接口的s_axis_tx_tvalid信号置为高电平,s_axis_tx_tdata、 s_axis_tx_tkeep、s_axis_tx_tlast信号填充适当数据;当监测到AXI4-S接口的s_ais_tx_tready信号被CPU置为高电平时,表明当前传输的数据被接收,当s_axis_tx_tlast置为高电平时,表明是最后一笔中断数据传输;当监测到AXI4-S接口的s_ais_tx_tready信号被CPU置为高电平时,表明整个中断数据传输完成,则将s_axis_tx_tvalid、s_axis_tx_tlast、s_axis_tx_tdata、s_axis_tx_tkeep置为低电平。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201611227961.1A CN106681816A (zh) | 2016-12-27 | 2016-12-27 | PCIe中断方法和*** |
CN201611227961.1 | 2016-12-27 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2018120780A1 true WO2018120780A1 (zh) | 2018-07-05 |
Family
ID=58871911
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/CN2017/093470 WO2018120780A1 (zh) | 2016-12-27 | 2017-07-19 | PCIe中断方法和*** |
Country Status (2)
Country | Link |
---|---|
CN (1) | CN106681816A (zh) |
WO (1) | WO2018120780A1 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113472964A (zh) * | 2021-06-05 | 2021-10-01 | 山东英信计算机技术有限公司 | 一种图像处理装置和*** |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106681816A (zh) * | 2016-12-27 | 2017-05-17 | 深圳开立生物医疗科技股份有限公司 | PCIe中断方法和*** |
CN108628782B (zh) * | 2018-03-27 | 2024-03-15 | 天津麒麟信息技术有限公司 | 一种基于飞腾平台的中断转换机制的实现方法 |
CN108763121B (zh) * | 2018-04-28 | 2021-07-27 | 西安电子科技大学 | TTE端***适配卡PCIe控制器的中断操作方法 |
CN109582232A (zh) * | 2018-11-21 | 2019-04-05 | 中国船舶重工集团公司第七0七研究所 | 一种基于FPGA的顺序读写多片Flash***及方法 |
CN110399324A (zh) * | 2019-06-28 | 2019-11-01 | 苏州浪潮智能科技有限公司 | 中断转换器及中断转换方法 |
CN110750472A (zh) * | 2019-09-10 | 2020-02-04 | 苏州浪潮智能科技有限公司 | 一种int中断转msi中断的转换方法、装置及存储介质 |
CN111078597B (zh) * | 2019-12-04 | 2021-07-30 | 江苏芯盛智能科技有限公司 | 一种中断消息生成装置、方法以及端设备 |
CN111427823B (zh) * | 2020-03-30 | 2023-05-02 | 天津光电通信技术有限公司 | 支持pc与fpga通过pcie通信的驱动设计方法 |
CN113138949A (zh) * | 2021-04-29 | 2021-07-20 | 上海阵量智能科技有限公司 | 中断控制器、中断控制方法、芯片、计算机设备以及介质 |
CN113282397B (zh) * | 2021-06-25 | 2022-08-30 | 厦门紫光展锐科技有限公司 | 外设的中断处理方法及设备 |
CN115221083B (zh) * | 2022-09-05 | 2023-01-24 | 浪潮电子信息产业股份有限公司 | 一种PCIe中断处理方法、装置、设备及介质 |
CN118132243B (zh) * | 2024-05-07 | 2024-07-19 | 浪潮电子信息产业股份有限公司 | 一种中断信号处理方法、装置、设备、介质、电路及*** |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101634974A (zh) * | 2009-08-26 | 2010-01-27 | 成都市华为赛门铁克科技有限公司 | 一种多中断类型的处理方法、装置和*** |
US20130198432A1 (en) * | 2011-11-30 | 2013-08-01 | Marvell World Trade Ltd. | Interrupt handling systems and methods for pcie bridges with multiple buses |
CN103559156A (zh) * | 2013-11-11 | 2014-02-05 | 北京大学 | 一种fpga与计算机之间的通信*** |
CN106681816A (zh) * | 2016-12-27 | 2017-05-17 | 深圳开立生物医疗科技股份有限公司 | PCIe中断方法和*** |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7197588B2 (en) * | 2004-03-31 | 2007-03-27 | Intel Corporation | Interrupt scheme for an Input/Output device |
US20050289271A1 (en) * | 2004-06-29 | 2005-12-29 | Martinez Alberto J | Circuitry to selectively produce MSI signals |
US7702889B2 (en) * | 2005-10-18 | 2010-04-20 | Qualcomm Incorporated | Shared interrupt control method and system for a digital signal processor |
JP5320140B2 (ja) * | 2009-04-14 | 2013-10-23 | 株式会社日立製作所 | 計算機システム、割込み中継回路及び割込み中継方法 |
US8606975B2 (en) * | 2010-05-21 | 2013-12-10 | Oracle International Corporation | Managing interrupts in a virtualized input/output device supporting multiple hosts and functions |
-
2016
- 2016-12-27 CN CN201611227961.1A patent/CN106681816A/zh active Pending
-
2017
- 2017-07-19 WO PCT/CN2017/093470 patent/WO2018120780A1/zh active Application Filing
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101634974A (zh) * | 2009-08-26 | 2010-01-27 | 成都市华为赛门铁克科技有限公司 | 一种多中断类型的处理方法、装置和*** |
US20130198432A1 (en) * | 2011-11-30 | 2013-08-01 | Marvell World Trade Ltd. | Interrupt handling systems and methods for pcie bridges with multiple buses |
CN103559156A (zh) * | 2013-11-11 | 2014-02-05 | 北京大学 | 一种fpga与计算机之间的通信*** |
CN106681816A (zh) * | 2016-12-27 | 2017-05-17 | 深圳开立生物医疗科技股份有限公司 | PCIe中断方法和*** |
Non-Patent Citations (1)
Title |
---|
SONG, ZHE: "Design of the PCIe Protocol Adaptation Layers Based on MicroBlaze", ELECTRONIC TECHNOLOGY & INFORMATION SCIENCE , CHINA MASTER'S THESES FULL-TEXT DATABASE, 15 August 2014 (2014-08-15), pages 14, ISSN: 1674-0246 * |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113472964A (zh) * | 2021-06-05 | 2021-10-01 | 山东英信计算机技术有限公司 | 一种图像处理装置和*** |
CN113472964B (zh) * | 2021-06-05 | 2024-04-16 | 山东英信计算机技术有限公司 | 一种图像处理装置和*** |
Also Published As
Publication number | Publication date |
---|---|
CN106681816A (zh) | 2017-05-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2018120780A1 (zh) | PCIe中断方法和*** | |
US5535341A (en) | Apparatus and method for determining the status of data buffers in a bridge between two buses during a flush operation | |
JP4194274B2 (ja) | クアド・ポンプ・バス・アーキテクチャおよびプロトコル | |
US5870567A (en) | Delayed transaction protocol for computer system bus | |
US6094700A (en) | Serial bus system for sending multiple frames of unique data | |
US7752374B2 (en) | Method and apparatus for host messaging unit for peripheral component interconnect busmaster devices | |
US20160117277A1 (en) | Collaborative hardware interaction by multiple entities using a shared queue | |
US7783817B2 (en) | Method and apparatus for conditional broadcast of barrier operations | |
WO1996000940A1 (en) | Pci to isa interrupt protocol converter and selection mechanism | |
US9009377B2 (en) | Edge-triggered interrupt conversion in a system employing level-sensitive interrupts | |
JPH077374B2 (ja) | インタフェース回路 | |
EP0358716A1 (en) | NODE FOR SUPPORTING INTERRUPTION REQUEST MESSAGES ON A BUS ON HOLD. | |
US6397279B1 (en) | Smart retry system that reduces wasted bus transactions associated with master retries | |
EP0358715A1 (en) | INTERRUPTION NODE FOR PROVIDING INTERRUPTION REQUESTS TO THE SYSTEM BUS. | |
US6567881B1 (en) | Method and apparatus for bridging a digital signal processor to a PCI bus | |
CN115934625B (zh) | 一种用于远程直接内存访问的敲门铃方法、设备及介质 | |
US7181559B2 (en) | Message based transport mechanism for level sensitive interrupts | |
US6693914B1 (en) | Arbitration mechanism for packet transmission | |
US6901475B2 (en) | Link bus for a hub based computer architecture | |
JP2008502977A (ja) | バス・コントローラのための割り込み方式 | |
EP3340011A1 (en) | Electronic devices and operation methods of the same | |
US8996772B1 (en) | Host communication device and method with data transfer scheduler | |
TW200304071A (en) | USB host controller | |
US7673091B2 (en) | Method to hide or reduce access latency of a slow peripheral in a pipelined direct memory access system | |
US9092581B2 (en) | Virtualized communication sockets for multi-flow access to message channel infrastructure within CPU |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 17885603 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
32PN | Ep: public notification in the ep bulletin as address of the adressee cannot be established |
Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 17.10.2019) |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 17885603 Country of ref document: EP Kind code of ref document: A1 |