WO2018120623A1 - 像素结构和显示面板 - Google Patents

像素结构和显示面板 Download PDF

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Publication number
WO2018120623A1
WO2018120623A1 PCT/CN2017/086152 CN2017086152W WO2018120623A1 WO 2018120623 A1 WO2018120623 A1 WO 2018120623A1 CN 2017086152 W CN2017086152 W CN 2017086152W WO 2018120623 A1 WO2018120623 A1 WO 2018120623A1
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Prior art keywords
conductive layer
pixel structure
line
conductive
present application
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Application number
PCT/CN2017/086152
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English (en)
French (fr)
Inventor
陈猷仁
Original Assignee
惠科股份有限公司
重庆惠科金渝光电科技有限公司
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Priority to US15/566,581 priority Critical patent/US10429707B2/en
Publication of WO2018120623A1 publication Critical patent/WO2018120623A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/13606—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit having means for reducing parasitic capacitance
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells

Definitions

  • the present application relates to the field of display technologies, and more particularly to a pixel structure and a display panel.
  • the liquid crystal display has many advantages such as thin body, power saving, no radiation, and has been widely used.
  • Most of the liquid crystal displays on the existing market are backlight type liquid crystal displays, among which, Thin Film Transistor-Liquid Crystal Display (TFT-LCD) has low power consumption, excellent picture quality, and high production. Performance such as yield has gradually occupied a dominant position in the display field.
  • TFT-LCD Thin Film Transistor-Liquid Crystal Display
  • a liquid crystal display includes a housing, a liquid crystal panel disposed in the housing, and a backlight module disposed in the housing.
  • the structure of the liquid crystal panel is mainly composed of a Thin Film Transistor Array Substrate (TFT Array Substrate), a Color Filter Substrate (CF Substrate), and a liquid crystal layer disposed between the two substrates (Liquid).
  • the crystal layer is constructed by controlling the rotation of the liquid crystal molecules of the liquid crystal layer by applying a driving voltage on the two glass substrates, and refracting the light of the backlight module to produce a picture.
  • a data signal is generally supplied through a plurality of pixel electrodes according to image information, and light transmittance of a plurality of pixel units is controlled to display a desired image.
  • each of the pixel electrodes is coupled with a data line and a scan line, and the scan line is coupled to the pixel electrode through a TFT (Thin Film Transistor).
  • the TFT is turned on by the scan line, and the data line charges the pixel electrode.
  • the data line generates a plurality of parasitic capacitances during the charging process, and the plurality of parasitic capacitances cause the voltage of the pixel electrodes to be shared (divided) due to the coupling effect (Crosstalk), resulting in insufficient voltage of the pixel electrodes to cause display color abnormality. And as the resolution is getting higher and higher, the coupling effect is more obvious.
  • the technical problem to be solved by the present application is to provide a pixel structure capable of improving the coupling effect.
  • the present application also provides a display panel employing the pixel structure.
  • the present application discloses a pixel structure, the pixel structure including:
  • a first conductive layer, the first conductive layer and a drain of the active switch are coupled;
  • the first conductive layer, the second conductive layer and the third conductive layer are stacked and spaced apart, and the first conductive layer, the second conductive layer and the third conductive layer cover each other in a vertical space.
  • the first voltage line comprises a common line.
  • the common line charges the second conductive layer such that the second conductive layer has a potential, and the structure is simple.
  • the second voltage line and the common line are overlapped in the coverage area of the first conductive layer. If two or more wires are arranged side by side, parasitic capacitances may also occur between each other, causing interference with each other, and the common line and the second voltage line of the present application are overlapped in the coverage area of the first conductive layer to prevent parasitic generation. Capacitor to improve anti-interference ability.
  • the first voltage line includes a previous scan line.
  • the charging process of the pixel structure is: controlling the active switch to be turned on by the current scan line, so that the current data line is charged for the pixel structure, and the previous scan line is in the upper row of the current scan line, and the second conductive line is previously passed through the previous scan line.
  • the layer is charged so that the second conductive layer has a voltage, which can reduce the charging time when the current data line is charged, and quickly bring the second conductive layer to a predetermined potential.
  • At least one of the first conductive layer, the second conductive layer and the third conductive layer is made of a transparent conductive material.
  • This is a specific structure of the first conductive layer, the second conductive layer and the third conductive layer.
  • the three conductive layers can all adopt transparent conductive
  • the material is made of only one or both of them made of a transparent conductive material, and the transparent conductive material not only has good electrical conductivity but also good light transmittance.
  • the transparent conductive material comprises indium tin oxide.
  • transparent conductive materials can also be used Other materials, such as: transparent conductive colloid.
  • At least one of the first conductive layer, the second conductive layer and the third conductive layer is made of a conductive metal.
  • the first conductive layer, the second conductive layer and the third conductive layer may all be made of a conductive metal, and the conductive metal has a good electrical conductivity.
  • the first conductive layer and the second conductive layer are respectively made of a conductive metal, and the third conductive layer is made of a conductive adhesive.
  • the first conductive layer and the second conductive layer are made of conductive metal, and the conductive metal has good electrical conductivity;
  • the conductive layer is made of a transparent conductive material, and the conductive effect can also be achieved.
  • the transparent conductive material of the present application can be made of a transparent conductive material such as ITO (indium tin oxide) or a transparent conductive paste, and has good light transmittance.
  • the first conductive layer is made of a conductive metal, and the second conductive layer and the third conductive layer are respectively made of a transparent conductive material.
  • the first conductive layer is made of a conductive metal, and the conductive metal has good electrical conductivity; the second conductive layer and the third conductive layer
  • the layer is made of a transparent conductive material and can also achieve the effect of conducting electricity.
  • the transparent conductive material of the present application can be made of a transparent conductive material such as ITO (indium tin oxide) or a transparent conductive paste, and has good light transmittance.
  • the first conductive layer is disposed between the second conductive layer and the third conductive layer.
  • the two storage capacitors together maintain the potential of the pixel structure voltage, and do not affect the voltage of the pixel structure due to the change of the charging voltage of the current data line during charging, and thus Improved coupling effects.
  • the second conductive layer is disposed between the first conductive layer and the third conductive layer.
  • This is another specific way of setting the third conductive layer such that a first storage capacitor is formed between the first conductive layer and the second conductive layer, and a third storage capacitor is formed between the second conductive layer and the third conductive layer. So that the two storage capacitors (the first storage capacitor and the third storage capacitor) together maintain the potential of the pixel structure voltage, The voltage of the pixel structure is not affected by the change of the charging voltage of the current data line during charging, thereby improving the coupling effect.
  • the present application further discloses a display panel including a color filter substrate and an array substrate, wherein the array substrate is provided with a common line, a data line and a scan line, wherein the The array substrate includes a pixel structure as described above, and the pixel structure is coupled to the data line and the scan line, respectively.
  • the data line generates a plurality of parasitic capacitances during charging of the pixel electrode, and the plurality of parasitic capacitances cause the voltage of the pixel electrode to be shared (divided) due to the coupling effect (Crosstalk), resulting in insufficient voltage of the pixel electrode.
  • the technical effects of the present application are:
  • the pixel structure of the present application includes three conductive layers, respectively a first conductive layer, a second conductive layer and a third conductive layer, wherein the first conductive layer is coupled to the drain of an active switch (TFT), and the active switch is respectively The current data line and the current scan line are coupled, and the control of the active switch by the current scan line causes the current data line to charge the first conductive layer.
  • TFT active switch
  • the second conductive layer is coupled to the first voltage line
  • the first voltage line charges the second conductive layer.
  • the third conductive layer is coupled to the second voltage line, and the second voltage line is charged to the third conductive layer.
  • the pixel voltage is sized to reduce the effects of multiple parasitic capacitances, thereby improving the effects of the coupling effect to enable the display panel to display properly.
  • the present application directly stacks the first conductive layer, the second conductive layer, and the third conductive layer, and the application greatly increases the capacitance of the pixel structure without increasing the planar size of each conductive layer.
  • This application is more suitable for use in a display panel with high resolution.
  • FIG. 1 is a schematic structural view of a pixel structure of the present application.
  • FIG. 2 is a schematic structural view of a pixel structure of the present application.
  • FIG. 3 is a schematic structural view of a pixel structure of the present application.
  • FIG. 4 is a schematic structural view of a pixel structure of the present application.
  • FIG. 5 is a circuit diagram of a pixel structure of the present application.
  • FIG. 6 is a circuit diagram of a pixel structure of the present application.
  • FIG. 7 is a circuit diagram of a pixel structure of the present application.
  • FIG. 8 is a circuit diagram of a pixel structure of the present application.
  • FIG. 9 is a schematic structural diagram of a pixel structure according to an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a pixel structure according to an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of a pixel structure according to an embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of a pixel structure according to an embodiment of the present application.
  • FIG. 13 is a circuit diagram of a pixel structure of an embodiment of the present application.
  • FIG. 14 is a circuit diagram of a pixel structure of an embodiment of the present application.
  • 15 is a schematic diagram of the cooperation of the first conductive layer, the second conductive layer and the third conductive layer in one embodiment of the present application;
  • FIG. 16 is a schematic diagram of the cooperation of the first conductive layer, the second conductive layer, and the third conductive layer in one embodiment of the present application.
  • first and second are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, features defining “first” and “second” may include one or more of the features either explicitly or implicitly.
  • a plurality means two or more unless otherwise stated.
  • the term “comprises” and its variations are intended to cover a non-exclusive inclusion.
  • connection In the description of the present application, it should be noted that the terms “installation”, “connected”, and “connected” are to be understood broadly, and may be fixed or detachable, for example, unless otherwise specifically defined and defined. Connected, or integrally connected; can be mechanical or electrical; can be directly connected, or indirectly connected through an intermediate medium, can be the internal communication of the two components.
  • Connected, or integrally connected can be mechanical or electrical; can be directly connected, or indirectly connected through an intermediate medium, can be the internal communication of the two components.
  • the specific meanings of the above terms in the present application can be understood in the specific circumstances for those skilled in the art.
  • a pixel structure, an array substrate, a display panel, and a display device of the present application are described below with reference to FIGS. 1 through 16.
  • the applicant Since the charging time is short in a single charging time, in order to maintain the voltage Vpixel of the pixel structure, the applicant has designed a pixel structure, as shown in FIGS. 1 to 8. Specifically, the pixel structure is respectively coupled with the current data line Data n And the current scan line Gate n, the current scan line is coupled through the active switch and the pixel structure. The active switch is opened by the current scan line, and the current data line Data n is charged by the pixel structure. Electricity.
  • the current data line Data n charges the pixel capacitance Clc and the storage capacitor Cst during charging of the pixel structure by the voltage (Vdata) of its charging, and the pixel structure maintains the voltage (Vpixel) of the pixel structure through the storage capacitor Cst to make the display
  • the panel can be displayed normally.
  • the active switch of the present application uses, for example, a thin film transistor (TFT). It should be noted that the active switch of the present application is not limited to a thin film crystal.
  • TFT thin film transistor
  • the voltage of the current data line Data n for charging the pixel structure will constantly change, so that the voltage of the pixel structure also changes, due to the charging voltage and the pixel of the current data line.
  • the structure has multiple parasitic capacitances (Cpd-L, Cgd, and Cpd-R), as shown in the dotted line in Figures 7 and 8.
  • the capacitance between the dotted lines is a plurality of parasitic capacitances, and multiple parasitic capacitances (Cpd-L, Cgd) And Cpd-R) will cause the voltage of the pixel structure to be divided due to the coupling effect (Crosstalk), resulting in insufficient voltage of the pixel structure and causing abnormal color display.
  • One is to set the data line away from the pixel structure, thereby reducing the generation of parasitic capacitance, thereby making the influence of the coupling effect smaller, but this increases the planar space of the display panel, and is not easily used in a display panel with high resolution. .
  • the second is to increase the storage capacitor Cst, which is much larger than the parasitic capacitance (Cpd-L, Cgd, and Cpd-R), which makes the influence of the coupling effect smaller, but it is necessary to increase the size of the conductive layer in the storage capacitor.
  • the planar space of the pixel structure is increased. As the resolution becomes higher and higher, the pixel electrode space becomes smaller and smaller, and the storage capacitor setting is also smaller, so that the storage capacitor is also less likely to be used in the display panel with higher resolution, due to the storage capacitor plane space.
  • the size limit, and thus the effect of improving the coupling effect by increasing the storage capacitance, is also reduced.
  • an embodiment of the present application discloses a pixel structure.
  • the pixel structure of the embodiment may be multiple, and multiple pixel structures may be separately applied to different display devices, for example,
  • the pixel structure of the present application is applied to the following display devices: Twisted Nematic (TN) or Super Twisted Nematic (STN) type, In-Plane Switching (IPS) type, vertical Vertical Alignment (VA) type, and High Vertical Alignment (HVA) type, curved type panel.
  • TN Twisted Nematic
  • STN Super Twisted Nematic
  • IPS In-Plane Switching
  • VA vertical Vertical Alignment
  • HVA High Vertical Alignment
  • the pixel structure of the embodiment of the present application may be four different pixel structures as shown in FIG. 9 to FIG. 12 .
  • FIG. 9 to FIG. 12 are only a few examples of the pixel structure in the embodiment of the present application.
  • the pixel structure of the embodiment of the present application is not limited to the four structures.
  • the pixel structure of the embodiment of the present application includes a pixel electrode, wherein FIG. 9 illustrates a pixel structure of the present application, the pixel structure includes a first pixel electrode 110; and FIG. 10 illustrates another pixel structure of the present application.
  • the pixel structure includes a second pixel electrode 120; FIG. 11 shows another pixel structure of the present application, the pixel structure includes a third pixel electrode 130; FIG. 12 shows a pixel structure of the embodiment of the present application.
  • the pixel structure includes a fourth pixel electrode 140.
  • the pixel structure of the embodiment of the present application includes a first conductive layer 11, a second conductive layer 12, and a third conductive layer 13, as shown in FIGS. 15 and 16, the first conductive layer 11 and an active switch (for example, a thin film transistor, but not limited to a drain transistor of the thin film transistor, the second conductive layer 12 is coupled to a first voltage line, the third conductive layer 13 and the second voltage line are coupled; the first conductive layer 11
  • the second conductive layer 12 and the third conductive layer 13 are stacked and spaced apart, and the first conductive layer 11, the second conductive layer 12, and the third conductive layer 13 are covered with each other in a vertical space.
  • the three conductive layers of the pixel structure of the embodiment of the present application can be energized, and the three can form two storage capacitors, and the two storage capacitors simultaneously maintain the pixel voltage of the pixel structure to reduce multiple The effect of parasitic capacitance, thereby improving the effects of the coupling effect, so that the display panel can be displayed normally.
  • the embodiment of the present application maintains the voltage level of the pixel structure by two storage capacitors. Compared with the pixel structure in FIG. 1 to FIG. 8 , the voltage level of the pixel structure is maintained by a storage capacitor, and the voltage level of the pixel structure is maintained. The effect is better, making the voltage structure of the pixel structure more stable.
  • the first conductive layer, the second conductive layer, and the third conductive layer are directly stacked, and It is not necessary to increase the plane size of each conductive layer, so that the embodiment of the present application greatly increases the capacitance of the pixel structure without increasing the plane size of each conductive layer, and better maintains the voltage level of the pixel structure, thereby making the application more Suitable for use in high resolution display panels.
  • FIG. 16 is a specific manner of stacking a first conductive layer, a second conductive layer, and a third conductive layer according to an embodiment of the present application.
  • the first conductive layer 11 is disposed between the second conductive layer 12 and the third conductive layer 13 such that a first storage capacitor 14 is formed between the first conductive layer 11 and the second conductive layer 12.
  • the first storage capacitor 14 is a storage capacitor Cst.
  • the storage capacitor Cst is defined as the first storage capacitor 14.
  • a second storage capacitor 16 is formed between the first conductive layer and the third conductive layer 13, and the second storage capacitor 16 is a storage capacitor Cnew, and the storage capacitor Cnew is defined as the second storage capacitor 16. Therefore, the two storage capacitors (the first storage capacitor 11 and the second storage capacitor 16) jointly maintain the potential of the pixel structure voltage without affecting the voltage of the pixel structure due to the change of the charging voltage of the current data line during charging. In turn, the coupling effect phenomenon is improved.
  • FIG. 16 is only a distribution of a specific conductive layer structure according to an embodiment of the present application, and may also be other structural distributions, for example, as shown in FIG. 15 , FIG. 16 is an embodiment of the present application.
  • the same storage capacitor as that of FIG. 16 is formed between the first conductive layer 11 and the second conductive layer 12, that is, the first storage capacitor 14, as shown in FIG. 13 and FIG. 14, the first storage capacitor 14 is the storage capacitor Cst.
  • the storage capacitor Cst is defined herein as the first storage capacitor 14.
  • a third storage capacitor 15 is formed between the second conductive layer 12 and the third conductive layer 13. As shown in FIG. 13 and FIG. 14, the third storage capacitor 15 is also illustrated as a storage capacitor Cnew (however, it should be noted that Since only one new storage capacitor, that is, the second storage capacitor or the third storage capacitor, can be illustrated in FIGS. 13 and 14, Cnew in FIGS. 13 and 14 is merely for explaining the second storage capacitor or the first Three storage capacitors, where the second storage capacitor and the third storage capacitor are not the same one.), when the pixel structure adopts the structure in FIG. 15, the storage capacitor Cnew is defined as the third storage capacitor. 15.
  • Such two storage capacitors (first storage battery
  • the capacitance and the third storage capacitor jointly maintain the potential of the pixel structure voltage, and do not affect the voltage of the pixel structure due to the change of the charging voltage of the current data line during charging, thereby improving the coupling effect phenomenon.
  • this embodiment replaces the second storage capacitor or the third storage capacitor with Cnew.
  • the first conductive layer 11 is coupled to the drain of the active switch, one end of the pixel capacitor Clc is coupled to the common line Vcom, and the pixel capacitor Clc is coupled to the active switch.
  • the active switch is coupled with the current data line Data n and the current scan line Gate n.
  • the current scan line controls the active switch to be turned on
  • the current data line charges the pixel structure through the active switch, specifically charging the pixel capacitor Clc and two storages.
  • Capacitors (Cst and Cnew, specifically in FIG. 16, are the first storage capacitor and the second storage capacitor; or specifically in FIG. 15, which are the first storage capacitor and the third storage capacitor).
  • the first voltage line includes a previous scan line Gate n-1, as shown in FIG. 14, that is, the second conductive layer 12 is coupled with the previous scan line, and the charging process of the pixel structure is through the current scan.
  • the line Gate n controls the active switch to be turned on, so that the current data line Data n is charged for the pixel structure, and the previous scan line is in the upper row of the current scan line, and the second conductive layer 12 is precharged by the previous scan line, so that The two conductive layers 12 have a voltage, which can reduce the charging time when the current data line is charged, and quickly bring the second conductive layer 12 to a predetermined potential. This is a specific manner in which the second conductive layer is coupled to the first voltage line.
  • the second conductive layer may also be coupled to other first voltage lines, for example, as shown in FIG.
  • the first voltage line includes a common line Vcom, that is, the second conductive layer 12 and the common line Vcom are coupled, and the common line Vcom charges the second conductive layer, which is simple in structure.
  • the third conductive layer 13 and the second voltage line are coupled.
  • the second voltage line Vdc of the embodiment of the present application is coupled to the DC voltage and the second conductive.
  • the voltage range of the common line of the layer connection is, for example, 7.5V or 0V; the voltage range of the data line is -5 to 15V; the voltage range of the scan line is -6 to 35V; due to the third conductive layer connected to the second voltage line and The voltages of the first conductive layer and the second conductive layer are all different, so a storage capacitor can be formed between the third conductive layer and the first conductive layer or the second conductive layer.
  • three conductive layers are used in a single pixel structure to form a plurality of storage capacitors. It should be noted that the embodiment of the present application is not limited thereto, for example, more conductive layers (greater than or equal to four conductive layers) may be formed in the pixel structure, and more storage capacitors are formed in the pixel structure. Four storage capacitors, fifth storage capacitors, etc.).
  • the first conductive layer 11, the second conductive layer 12, and the third conductive layer 13 are respectively made of a conductive metal, which is a first conductive layer and a second conductive layer. And a specific structure of the third conductive layer, the three conductive layers (the first conductive layer 11, the second conductive layer 12 and the third conductive layer 13) are all made of a conductive metal, and the conductive metal has a good conductive effect.
  • the conductive metal of an embodiment of the present application may be: aluminum, molybdenum, copper, titanium, silver or an alloy thereof.
  • the three conductive layers are all made of a conductive metal, which is a specific mode of the embodiment of the present application.
  • Other ways can be used:
  • the first conductive layer 11 and the second conductive layer 12 are respectively made of a conductive metal
  • the third conductive layer 13 is made of a transparent conductive material.
  • the first conductive layer 11 and the second conductive layer 12 are both made of conductive metal and are electrically conductive.
  • the metal conductive effect is good;
  • the third conductive layer 13 is made of a transparent conductive material, and the conductive effect can also be achieved, and the transparent conductive material of the embodiment of the present application can use indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide. It is made of transparent conductive material such as tin-zinc (ITZO) and has good light transmittance.
  • the first conductive layer 11 is made of a conductive metal
  • the second conductive layer 12 and the third conductive layer 13 are respectively made of a transparent conductive material.
  • the first conductive layer 11 is made of conductive metal, and the conductive metal has good electrical conduction effect;
  • the conductive layer 12 and the third conductive layer 13 are made of a transparent conductive material, and the conductive effect can also be achieved, and the transparent conductive material of the present application can use indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO). It is made of a transparent conductive material and has good light transmittance.
  • the first conductive layer 11 is made of a transparent conductive material
  • the second conductive layer 12 and the third conductive layer 13 are respectively made of a transparent conductive material.
  • the first conductive layer 11 and the second conductive layer 12 are disposed.
  • a specific structure of the third conductive layer 13, the first conductive layer 11, the second conductive layer 12 and the third conductive layer 13 are all made of a transparent conductive material, not only can achieve the effect of conduction, but also transparent
  • the conductive material can be made of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO), and has good light transmittance.
  • the second voltage line Vdc and the common line Vcom partially overlap in space, specifically, the second voltage line and the common line are covered by the first conductive layer. Overlap settings in the area. If two or more wires are arranged side by side, parasitic capacitances are generated between each other, and mutual interference occurs. However, in the embodiment of the present application, the common line Vcom and the second voltage line Vdc are partially overlapped in space to prevent parasitic capacitance from being generated. Improve anti-interference ability.
  • the three conductive layers (the first conductive layer 11, the second conductive layer 12, and the third conductive layer 13) of one embodiment of the present application are parallel to each other, so that the space occupied by the three in the plane space is further Small, the effect of applying the pixel structure of the embodiment of the present application to the display panel is better.
  • an embodiment of the present application further discloses an array substrate, wherein the array substrate is provided with a common line, a data line, and a scan line, and the array substrate further includes a pixel structure,
  • the pixel structures are coupled to the data lines and the scan lines, respectively.
  • the common line, the data line, the scan line, and the pixel structure on the array substrate of the embodiment refer to the common line, the data line, the scan line, and the pixel structure in the above embodiment, or the common line on the array substrate in this embodiment.
  • the data lines, the scan lines, and the pixel structure reference may be made to the common lines, the data lines, the scan lines, the pixel structures, and the mutual cooperation and connection relationship in FIG. 9 to FIG.
  • the array substrate of the present embodiment has a plurality of pixel structures. For each pixel structure, reference may be made to FIG. 9 to FIG. 16. The pixel structure, the common lines, the data lines, the scan lines, and the like are not described in detail herein.
  • the embodiment of the present application further discloses a display panel, where the display panel includes a color filter substrate and an array substrate, and the array substrate is provided with a common line, a data line, and a scan line.
  • the array substrate further includes a pixel structure, and the pixel structure is coupled to the data line and the scan line, respectively.
  • the data line, the scan line, and the pixel structure in the display panel of the embodiment refer to the common line, the data line, the scan line, and the pixel structure in the above embodiment, or
  • the common lines, data lines, scan lines, and pixel structures in the display panel of the embodiment reference may be made to the common lines, the data lines, the scan lines, the pixel structures, and the mutual cooperation and connection relationship in FIG. 9 to FIG.
  • the array substrate of the present embodiment has a plurality of pixel structures. For each pixel structure, reference may be made to FIG. 9 to FIG. 16.
  • the pixel structure, the common lines, the data lines, the scan lines, and the like are not described in detail herein.
  • the embodiment of the present application further discloses a display device including a display panel and a backlight module, wherein the display panel includes a color film substrate and an array substrate, and the array substrate A common line, a data line and a scan line are disposed on the array substrate, and the array substrate further includes a pixel structure, and the pixel structure is coupled to the data line and the scan line, respectively.
  • the common line, the data line, the scan line, and the pixel structure in the display panel of the present embodiment refer to the common line, the data line, the scan line, and the pixel structure in the above embodiment, or the common line in the display panel of this embodiment.
  • the array substrate of the present embodiment has a plurality of pixel structures. For each pixel structure, reference may be made to FIG. 9 to FIG. 16.
  • the pixel structure, the common lines, the data lines, the scan lines, and the like are not described in detail herein.
  • the display device of the embodiment may be a liquid crystal display or other display device.
  • the backlight module can be used as a light source for supplying sufficient light source with uniform brightness and distribution.
  • the backlight module of this embodiment The group may be of the front light type or the backlight type. It should be noted that the backlight module of the embodiment is not limited thereto.

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Abstract

一种像素结构和显示面板，其中，像素结构包括第一导电层(11)、第二导电层(12)和第三导电层(13)，第一导电层(11)和主动开关的漏极耦合，第二导电层(12)和第一电压线耦合，第三导电层(13)和第二电压线(Vdc)耦合；第一导电层(11)、第二导电层(12)和第三导电层(13)三者叠放且间隔设置，第一导电层(11)、第二导电层(12)和第三导电层(13)三者在垂直空间上相互覆盖。

Description

像素结构和显示面板 【技术领域】
本申请涉及显示技术领域，更具体的说，涉及一种像素结构和显示面板。
【背景技术】
液晶显示器具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。现有市场上的液晶显示器大部分为背光型液晶显示器，其中，薄膜晶体管液晶显示器(Thin Film Transistor-Liquid Crystal Display，TFT-LCD)由于具有低的功耗、优异的画面品质以及较高的生产良率等性能，目前已经逐渐占据了显示领域的主导地位。
通常液晶显示器包括壳体、设于壳体内的液晶面板及设于壳体内的背光模组(Backlight module)。其中，液晶面板的结构主要是由一薄膜晶体管阵列基板(Thin Film Transistor Array Substrate，TFT Array Substrate)、一彩膜基板(Color Filter Substrate，CF Substrate)、以及配置于两基板间的液晶层(Liquid Crystal Layer)所构成，其工作原理是通过在两片玻璃基板上施加驱动电压来控制液晶层的液晶分子的旋转，将背光模组的光线折射出来产生画面。
现有的液晶显示器，通常是根据图像信息通过多个像素(pixel)电极分别提供数据信号，并且控制多个像素单元的透光率来显示所需图像。具体的是，每一个像素电极都分别耦合有数据线和扫描线，扫描线通过TFT(Thin Film Transistor，薄膜晶体管)和像素电极耦合。通过扫描线控制TFT打开，数据线为像素电极充电。但是，数据线在充电过程中产生多个寄生电容，多个寄生电容会因为耦合效应(Crosstalk)使像素电极的电压被share(分压)，导致像素电极的电压不足进而造成显示产色异常。而且随着解析度越来越高，耦合效应更加明显。
【发明内容】
本申请所要解决的技术问题是提供一种能够改善耦合效应的像素结构。
此外，本申请还提供一种采用所述像素结构的显示面板。
本申请的目的是通过以下技术方案来实现的：
根据本申请的一个方面，本申请公开了一种像素结构，所述像素结构包括：
第一导电层，所述第一导电层和主动开关的漏极耦合；
第二导电层，所述第二导电层和第一电压线耦合；
第三导电层，所述第三导电层和第二电压线耦合；
所述第一导电层、第二导电层和第三导电层三者叠放且间隔设置，所述第一导电层、第二导电层和第三导电层三者在垂直空间上相互覆盖。
其中，所述第一电压线包括共通线。所述共通线为第二导电层充电，使得第二导电层具有电位，这种结构简单。
其中，所述第二电压线和共通线在在第一导电层覆盖区域内重叠设置。若两个或多个导线之间并列设置，相互之间也会产生寄生电容，相互产生干扰，而本申请共通线和第二电压线在第一导电层覆盖区域内重叠设置就可以防止产生寄生电容，提高抗干扰能力。
其中，所述第一电压线包括上一扫描线。像素结构的充电过程是，通过当前扫描线控制主动开关导通，使得当前数据线为像素结构充电，而上一扫描线是在当前扫描线的上一行，通过上一扫描线预先为第二导电层充电，使第二导电层具有电压，在当前数据线充电时可减少充电时间，快速将第二导电层达到预定的电位。
其中，所述第一导电层、第二导电层及第三导电层的其中至少一者采用透明导电材料制成。这是本申请设置第一导电层、第二导电层及第三导电层的一种具体结构，三个导电层(第一导电层、第二导电层及第三导电层)可以都采用透明导电材料制成，也可以仅其中一者或两者采用透明导电材料制成，透明导电材料不仅导电效果好，而且透光性好。
其中，所述透明导电材料包括氧化铟锡。然而，透明导电材料也可以采用 其他材料，比如：透明导电胶体。
其中，所述第一导电层、第二导电层和第三导电层的其中至少一者采用导电金属制成。第一导电层、第二导电层和第三导电层三者可以都采用导电金属制成，导电金属导电效果好。
其中，所述第一导电层和第二导电层分别采用导电金属制成，所述第三导电层采用导电胶制成。这是本申请设置第一导电层、第二导电层及第三导电层的另一种具体结构，第一导电层和第二导电层都采用导电金属制成，导电金属导电效果好；第三导电层采用透明导电材料制成同样可以实现导电的效果，且本申请透明导电材料可以使用ITO(氧化铟锡)、透明导电胶体等透明导电材料制成，其透光性好。
其中，所述第一导电层采用导电金属制成，所述第二导电层和第三导电层分别采用透明导电材料制成。这是本申请设置第一导电层、第二导电层及第三导电层的又一种具体结构，第一导电层采用导电金属制成，导电金属导电效果好；第二导电层和第三导电层采用透明导电材料制成同样可以实现导电的效果，且本申请透明导电材料可以使用ITO(氧化铟锡)、透明导电胶体等透明导电材料制成，其透光性好。
其中，所述第一导电层设置在所述第二导电层和第三导电层之间。这是设置第三导电层的一种具体方式，从而第一导电层和第二导电层之间形成一个第一存储电容，第一导电层和第三导电层之间形成一个第二存储电容，这样两个存储电容(第一存储电容、第二存储电容)共同保持像素结构电压的电位，而不会因为当前数据线在充电过程中的充电电压的变化而影响到像素结构的电压，进而就改善了耦合效应现象。
其中，所述第二导电层设置在所述第一导电层和第三导电层之间。这是设置第三导电层的另一种具体方式，从而第一导电层和第二导电层之间形成一个第一存储电容，第二导电层和第三导电层之间形成一个第三存储电容，这样两个存储电容(第一存储电容、第三存储电容)共同保持像素结构电压的电位， 而不会因为当前数据线在充电过程中的充电电压的变化而影响到像素结构的电压，进而就改善了耦合效应现象。
根据本申请的另一个方面，本申请还公开了一种显示面板，所述显示面板包括彩膜基板和阵列基板，所述阵列基板上设置有共通线、数据线和扫描线，其中，所述阵列基板包括如上所述的像素结构，所述像素结构分别与所述数据线、扫描线耦合。
现有技术中数据线在给像素电极充电过程中会产生多个寄生电容，多个寄生电容会因为耦合效应(Crosstalk)使像素电极的电压被share(分压)，导致像素电极的电压不足进而造成显示产色异常。与现有技术相比，本申请的技术效果是：
本申请像素结构包括有三个导电层，分别为第一导电层、第二导电层及第三导电层，其中，第一导电层耦合到一主动开关(TFT)的漏极，主动开关又分别和当前数据线、当前扫描线耦合，通过当前扫描线对主动开关的控制使得当前数据线为第一导电层充电。其中，第二导电层耦合到第一电压线，第一电压线为第二导电层充电。其中，第三导电层耦合到第二电压线，第二电压线为第三导电层充电。从而三个导电层都可以通电，将第一导电层、第二导电层和第三导电层三者叠放间隔设置，这样三者就可以形成两个存储电容，两个存储电容同时保持像素结构的像素电压大小，以减小多个寄生电容的影响，从而改善耦合效应的影响，以使得显示面板能够正常显示。
另外，本申请直接将第一导电层、第二导电层和第三导电层三者叠放设置，本申请在不增大各个导电层平面大小的情况下就大大提高了像素结构的电容，从而本申请更加适用于解析度高的显示面板中。
【附图说明】
所包括的附图用来提供对本申请实施例的进一步的理解，其构成了说明书 的一部分，用于例示本申请的实施方式，并与文字描述一起来阐释本申请的原理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1是本申请一种像素结构的结构示意图；
图2是本申请一种像素结构的结构示意图；
图3是本申请一种像素结构的结构示意图；
图4是本申请一种像素结构的结构示意图；
图5是本申请一种像素结构的电路示意图；
图6是本申请一种像素结构的电路示意图；
图7是本申请一种像素结构的电路示意图；
图8是本申请一种像素结构的电路示意图；
图9是本申请一个实施例像素结构的结构示意图；
图10是本申请一个实施例像素结构的结构示意图；
图11是本申请一个实施例像素结构的结构示意图；
图12是本申请一个实施例像素结构的结构示意图；
图13是本申请一个实施例像素结构的电路示意图；
图14是本申请一个实施例像素结构的电路示意图；
图15是本申请一个实施例第一导电层、第二导电层和第三导电层三者配合的示意图；
图16是本申请一个实施例第一导电层、第二导电层和第三导电层三者配合的示意图。
【具体实施方式】
这里所公开的具体结构和功能细节仅仅是代表性的，并且是用于描述本申请的示例性实施例的目的。但是本申请可以通过许多替换形式来具体实现，并 且不应当被解释成仅仅受限于这里所阐述的实施例。
在本申请的描述中，需要理解的是，术语“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。另外，术语“包括”及其任何变形，意图在于覆盖不排他的包含。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
这里所使用的术语仅仅是为了描述具体实施例而不意图限制示例性实施例。除非上下文明确地另有所指，否则这里所使用的单数形式“一个”、“一项”还意图包括复数。还应当理解的是，这里所使用的术语“包括”和/或“包含”规定所陈述的特征、整数、步骤、操作、单元和/或组件的存在，而不排除存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
下面参考图1至图16描述本申请的像素结构、阵列基板、显示面板及显示装置。
由于单个充电时间内的充电时间较短，为了保持像素结构的电压Vpixel，申请人设计了一种像素结构，如图1至图8所示，具体的，像素结构分别耦合有当前数据线Data n和当前扫描线Gate n，当前扫描线通过主动开关和像素结构耦合。通过当前扫描线控制主动开关打开，当前数据线Data n为像素结构充 电。当前数据线Data n通过其充电的电压(Vdata)在为像素结构充电过程中为像素电容Clc和存储电容Cst充电，像素结构通过存储电容Cst来保持像素结构的电压(Vpixel)大小，以使得显示面板能够正常显示。
本申请的主动开关例如采用薄膜晶体管(TFT)，需要说明的是，本申请的主动开关并不限于薄膜晶体。
但是，在显示面板显示过程中，会显示不同灰阶，当前数据线Data n为像素结构充电的电压会不断变化，从而使得像素结构的电压也随之变化，由于当前数据线的充电电压和像素结构存在多个寄生电容(Cpd-L、Cgd和Cpd-R)，如图7和8中的虚线部分，虚线部分之间的电容为多个寄生电容，多个寄生电容(Cpd-L、Cgd和Cpd-R)会因为耦合效应(Crosstalk)使像素结构的电压被分压，导致像素结构的电压不足进而造成显示产色异常。
为减少多个寄生电容的影响，改善耦合效应的影响，申请人进一步采用以下两种方法：
其一是将数据线设置远离像素结构，从而减小寄生电容的产生，进而使得耦合效应的影响变小，但是这样就增加了显示面板的平面空间，不易用于解析度较高的显示面板中。
其二是加大存储电容Cst，使其远大于寄生电容(Cpd-L、Cgd和Cpd-R)，进而使得耦合效应的影响变小，但是这样就需要加大了存储电容中导电层的大小，进而就增加了像素结构的平面空间。随着解析度越来越高，像素电极空间越来越小，也会将存储电容设置变小，从而加大存储电容也不易用于解析度较高的显示面板中，由于受到存储电容平面空间大小的限制，从而通过加大存储电容来改善耦合效应的效果也因此而降低。
为此，申请人又设计了另外的技术方案，以解决以上技术问题，具体如下：
下面结合附图9至16和较佳的实施例对本申请作进一步详细说明。
如图9至16所示，本申请一实施例公开了一种像素结构，本实施例的像素结构可以为多种，多种像素结构可以分别应用于不同的显示装置中，比如，将 本申请的像素结构应用到以下几种显示装置中：扭曲向列(Twisted Nematic，TN)或超扭曲向列(Super Twisted Nematic，STN)型，平面转换(In-Plane Switching，IPS)型、垂直配向(Vertical Alignment，VA)型、及高垂直配向(High Vertical Alignment，HVA)型、曲面型面板。
具体的，本申请实施例的像素结构可以为如图9至图12所示的4种不同的像素结构，需要说明的是，图9至图12仅仅是本申请实施例对像素结构的几种具体举例说明，本申请实施例的像素结构并不限于这四种结构。本申请实施例像素结构包括有像素电极，其中，图9示出了本申请一种像素结构，该像素结构包括有第一像素电极110；图10示出了本申请另一种像素结构，该像素结构包括有第二像素电极120；图11示出了本申请又一种像素结构，该像素结构包括有第三像素电极130；图12示出了本申请实施例还一种像素结构，该像素结构包括有第四像素电极140。
进一步的，本申请实施例的像素结构包括有第一导电层11、第二导电层12和第三导电层13，如图15和16所示，所述第一导电层11和主动开关(例如薄膜晶体管，但并不限于薄膜晶体管)的漏极耦合，所述第二导电层12和第一电压线耦合，所述第三导电层13和第二电压线耦合；所述第一导电层11、第二导电层12和第三导电层13三者叠放且间隔设置，所述第一导电层11、第二导电层12和第三导电层13三者在垂直空间上相互覆盖。
相比现有技术，本申请实施例的像素结构的三个导电层都可以通电，三者就可以形成两个存储电容，两个存储电容同时保持像素结构的像素电压大小，以减小多个寄生电容的影响，从而改善耦合效应的影响，以使得显示面板能够正常显示。
另外，本申请实施例通过两个存储电容来保持像素结构的电压大小，相比图1至图8中的像素结构，通过一个存储电容来保持像素结构的电压大小，对像素结构的电压大小保持效果更好，使得像素结构的电压大小更加稳定。同时，本申请实施例直接将第一导电层、第二导电层和第三导电层三者叠放设置，就 不必增加各个导电层的平面大小，这样本申请实施例在不增大各个导电层平面大小的情况下就大大提高了像素结构的电容，更好的保持了像素结构的电压大小，从而本申请更加适用于解析度高的显示面板中。
在本申请一本实施例中，如图16所示，图16为本申请一实施例第一导电、第二导电层和第三导电层三者叠放的一种具体方式，具体的是，第一导电层11设置在第二导电层12和第三导电层13之间，这样第一导电层11和第二导电层12之间形成第一存储电容14。结合图13和图14所示，第一存储电容14为存储电容Cst，当像素结构采用图16中的结构时，在此将存储电容Cst定义为第一存储电容14。第一导电层和第三导电层13之间形成第二存储电容16，第二存储电容16为存储电容Cnew，在此将存储电容Cnew定义为第二存储电容16。从而两个存储电容(第一存储电容11、第二存储电容16)共同保持像素结构电压的电位，而不会因为当前数据线在充电过程中的充电电压的变化而影响到像素结构的电压，进而就改善了耦合效应现象。
然而，需要说明的是，图16为仅为本申请一实施例的一种具体导电层结构的分布，也可以为其他结构分布，比如：如图15所示，图16为本申请一实施例第一导电、第二导电层和第三导电层三者叠放的另一种具体方式，具体的是，所述第二导电层12设置在所述第一导电层11和第三导电层13之间。这样第一导电层11和第二导电层12之间形成与图16相同的存储电容，即第一存储电容14，同样结合图13和图14所示，第一存储电容14为存储电容Cst，在此将存储电容Cst定义为第一存储电容14。第二导电层12和第三导电层13之间形成一个第三存储电容15，同样结合图13和图14所示中，第三存储电容15也示意为存储电容Cnew(然而，需要说明的是，由于在图13及图14中仅能够示意出一个新的存储电容，即第二存储电容或第三存储电容，因此，图13和图14中的Cnew仅仅是为了说明第二存储电容或第三存储电容，在此，第二存储电容和第三存储电容并不是同一个。)，在此当像素结构采用图15中的结构时，此时就将将存储电容Cnew定义为第三存储电容15。这样两个存储电容(第一存储电 容、第三存储电容)共同保持像素结构电压的电位，而不会因为当前数据线在充电过程中的充电电压的变化而影响到像素结构的电压，进而就改善了耦合效应现象。
在以下叙述中，本实施例将第二存储电容或第三存储电容用Cnew代替。
如图13和图14所示，第一导电层11和主动开关的漏极耦合，像素电容Clc一端和共通线Vcom耦合，像素电容Clc和主动开关耦合。主动开关分别和当前数据线Data n耦合、当前扫描线Gate n耦合，当前扫描线控制主动开关打开时，当前数据线通过主动开关为像素结构充电，具体是为像素电容Clc充电、以及两个存储电容(Cst和Cnew，具体在图16中，即是第一存储电容和第二存储电容；或者具体在图15中，即是第一存储电容和第三存储电容)。
进一步的，所述第一电压线包括上一扫描线Gate n-1，如图14所示，也就是说第二导电层12和上一扫描线耦合，像素结构的充电过程是，通过当前扫描线Gate n控制主动开关导通，使得当前数据线Data n为像素结构充电，而上一扫描线是在当前扫描线的上一行，通过上一扫描线预先为第二导电层12充电，使第二导电层12具有电压，在当前数据线充电时可减少充电时间，快速将第二导电层12达到预定的电位。这是第二导电层与第一电压线耦合的一种具体方式，当然，需要说明的是，第二导电层也可以耦合到其他的第一电压线，比如：如图13所示，所述第一电压线包括共通线Vcom，也就是说第二导电层12和共通线Vcom耦合，所述共通线Vcom为第二导电层充电，这种方式结构简单。
在本申请一实施例中，第三导电层13和第二电压线耦合，如图9至图14所示，本申请一实施例的第二电压线Vdc耦合到一直流电压，与第二导电层连接的共通线的电压范围例如为7.5V或0V；数据线的电压范围为-5～15V；扫描线的电压范围为-6～35V；由于与第二电压线连接的第三导电层和第一导电层和、第二导电层的电压均不相同，所以第三导电层与第一导电层或第二导电层之间就可以形成存储电容。
在本申请实施例中，单个像素结构中采用三个导电层以形成多个存储电容， 需要说明的是，本申请实施例并不限于此，比如：可在像素结构中形成更多堆栈的导电层(大于或等于四个导电层)，在像素结构中形成更多的存储电容(第四存储电容、第五存储电容等)。
在本申请一实施例中，其中，所述第一导电层11、第二导电层12及第三导电层13分别采用导电金属制成，这是本申请设置第一导电层、第二导电层及第三导电层的一种具体结构，三个导电层(第一导电层11、第二导电层12及第三导电层13)都采用导电金属制成，导电金属导电效果好。其中，本申请一实施例的导电金属可以是：铝、钼、铜、钛、银或其合金。
需要说明的是，三个导电层(第一导电层11、第二导电层12及第三导电层13)都采用导电金属制成是本申请实施例的一种具体方式，本申请实施例还可以采用其他方式：
例如1：所述第一导电层11和第二导电层12分别采用导电金属制成，所述第三导电层13采用透明导电材料制成。这是本申请实施例设置第一导电层11、第二导电层12及第三导电层13的另一种具体结构，第一导电层11和第二导电层12都采用导电金属制成，导电金属导电效果好；第三导电层13采用透明导电材料制成同样可以实现导电的效果，且本申请实施例的透明导电材料可以使用氧化铟锡(ITO)、氧化铟锌(IZO)、氧化铟锡锌(ITZO)等透明导电材料制成，其透光性好。
例如2：所述第一导电层11采用导电金属制成，所述第二导电层12和第三导电层13分别采用透明导电材料制成。这是本申请实施例设置第一导电层11、第二导电层12及第三导电层13的又一种具体结构，第一导电层11采用导电金属制成，导电金属导电效果好；第二导电层12和第三导电层13采用透明导电材料制成同样可以实现导电的效果，且本申请透明导电材料可以使用氧化铟锡(ITO)、氧化铟锌(IZO)、氧化铟锡锌(ITZO)等透明导电材料制成，其透光性好。
例如3：所述第一导电层11采用导、第二导电层12和第三导电层13分别采用透明导电材料制成。这是本申请实施例设置第一导电层11、第二导电层12 及第三导电层13的还一种具体结构，第一导电层11、第二导电层12和第三导电层13三者都采用透明导电材料制成不仅可以实现导电的效果，而且本申请透明导电材料可以使用氧化铟锡(ITO)、氧化铟锌(IZO)、氧化铟锡锌(ITZO)等透明导电材料制成，其透光性好。
在本申请一实施例中，如图9至图12所示，所述第二电压线Vdc和共通线Vcom在空间上部分重叠，具体的是第二电压线和共通线在第一导电层覆盖区域内重叠设置。若两个或多个导线之间并列设置，相互之间也会产生寄生电容，相互产生干扰，而本申请实施例共通线Vcom和第二电压线Vdc在空间上部分重叠就可以防止产生寄生电容，提高抗干扰能力。
更进一步的，本申请一实施例的三个导电层(第一导电层11、第二导电层12、第三导电层13)相互平行，从而就使得三者在平面空间上所占用的空间更小，使得本申请实施例的像素结构应用到显示面板中的效果更佳。
在本申请的另一个实施例中，本申请实施例还公开了一种阵列基板，所述阵列基板上设置有共通线、数据线和扫描线，所述阵列基板还包括有像素结构，所述像素结构分别与所述数据线、扫描线耦合。其中，本实施例阵列基板上的共通线、数据线、扫描线、像素结构可以参见以上实施例中的共通线、数据线、扫描线、像素结构，或者说本实施例阵列基板上的共通线、数据线、扫描线、像素结构可以参见图9至图16中的共通线、数据线、扫描线、像素结构，以及相互的配合、连接关系。本实施例的阵列基板上具有多个像素结构，每个像素结构可参见图9至图16，在此不再对像素结构、共通线、数据线、扫描线等进行一一详述。
在本申请的又一个实施例中，本申请实施例还公开了一种显示面板，所述显示面板包括彩膜基板和阵列基板，所述阵列基板上设置有共通线、数据线和扫描线，所述阵列基板还包括有像素结构，所述像素结构分别与所述数据线、扫描线耦合。其中，本实施例显示面板中的共通线、数据线、扫描线、像素结构可以参见以上实施例中的共通线、数据线、扫描线、像素结构，或者说本实 施例显示面板中的共通线、数据线、扫描线、像素结构可以参见图9至图16中的共通线、数据线、扫描线、像素结构，以及相互的配合、连接关系。本实施例的阵列基板上具有多个像素结构，每个像素结构可参见图9至图16，在此不再对像素结构、共通线、数据线、扫描线等进行一一详述。
在本申请的再一个实施例中，本申请实施例还公开了一种显示装置，显示装置包括显示面板和背光模组，其中，所述显示面板包括彩膜基板和阵列基板，所述阵列基板上设置有共通线、数据线和扫描线，所述阵列基板还包括有像素结构，所述像素结构分别与所述数据线、扫描线耦合。其中，本实施例显示面板中的共通线、数据线、扫描线、像素结构可以参见以上实施例中的共通线、数据线、扫描线、像素结构，或者说本实施例显示面板中的共通线、数据线、扫描线、像素结构可以参见图9至图16中的共通线、数据线、扫描线、像素结构，以及相互的配合、连接关系。本实施例的阵列基板上具有多个像素结构，每个像素结构可参见图9至图16，在此不再对像素结构、共通线、数据线、扫描线等进行一一详述。其中，本实施例的显示装置可以为液晶显示器或其他显示装置，当显示装置为液晶显示器时，背光模组可作为光源，用于供应充足的亮度与分布均匀的光源，本实施例的背光模组可以为前光式，也可以为背光式，需要说明的是，本实施例的背光模组并不限于此。
以上内容是结合具体的优选实施方式对本申请所作的进一步详细说明，不能认定本申请的具体实施只局限于这些说明。对于本申请所属技术领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本申请的保护范围。

Claims (20)

  1. 一种像素结构，所述像素结构包括：
    第一导电层，所述第一导电层和主动开关的漏极耦合；
    第二导电层，所述第二导电层和第一电压线耦合；
    第三导电层，所述第三导电层和第二电压线耦合；
    所述第一导电层、第二导电层和第三导电层三者叠放且间隔设置，所述第一导电层、第二导电层和第三导电层三者在垂直空间上相互覆盖；
    所述第一电压线包括共通线；所述第二电压线和共通线在第一导电层覆盖区域内重叠设置；所述第一电压线包括上一扫描线；所述第一导电层、第二导电层及第三导电层的其中至少一者采用透明导电材料制成；所述透明导电材料包括氧化铟锡；
    所述第一导电层、第二导电层和第三导电层的其中至少一者采用导电金属制成；所述第一导电层设置在所述第二导电层和第三导电层之间。
  2. 一种像素结构，所述像素结构包括：
    第一导电层，所述第一导电层和主动开关的漏极耦合；
    第二导电层，所述第二导电层和第一电压线耦合；
    第三导电层，所述第三导电层和第二电压线耦合；
    所述第一导电层、第二导电层和第三导电层三者叠放且间隔设置，所述第一导电层、第二导电层和第三导电层三者在垂直空间上相互覆盖。
  3. 如权利要求2所述的像素结构，其中所述第一电压线包括共通线。
  4. 如权利要求3所述的像素结构，其中所述第二电压线和共通线在第一导电层覆盖区域内重叠设置。
  5. 如权利要求2所述的像素结构，其中所述第一电压线包括上一扫描线。
  6. 如权利要求2所述的像素结构，其中所述第一导电层、第二导电层及第三导电层的其中至少一者采用透明导电材料制成。
  7. 如权利要求6所述的像素结构，其中所述透明导电材料包括氧化铟锡。
  8. 如权利要求2所述的像素结构，其中所述第一导电层、第二导电层和第三导电层的其中至少一者采用导电金属制成。
  9. 如权利要求2所述的像素结构，其中所述第一导电层设置在所述第二导电层和第三导电层之间。
  10. 如权利要求2所述的像素结构，其中所述第二导电层设置在所述第一导电层和第三导电层之间。
  11. 如权利要求8所述的像素结构，其中所述第二导电层设置在所述第一导电层和第三导电层之间。
  12. 一种显示面板，包括彩膜基板和阵列基板，所述阵列基板上设置有共通线、数据线和扫描线，其中所述阵列基板包括像素结构，所述像素结构分别与所述数据线、扫描线耦合，所述像素结构包括：
    第一导电层，所述第一导电层和主动开关的漏极耦合；
    第二导电层，所述第二导电层和第一电压线耦合；
    第三导电层，所述第三导电层和第二电压线耦合；
    所述第一导电层、第二导电层和第三导电层三者叠放且间隔设置，所述第一导电层、第二导电层和第三导电层三者在垂直空间上相互覆盖。
  13. 如权利要求12所述的显示面板，其中所述第一电压线包括共通线。
  14. 如权利要求13所述的像素结构，其中所述第二电压线和共通线在第一导电层覆盖区域内重叠设置。
  15. 如权利要求12所述的显示面板，其中所述第一电压线包括上一扫描线。
  16. 如权利要求12所述的显示面板，其中所述第一导电层、第二导电层及第三导电层的其中至少一者采用透明导电材料制成。
  17. 如权利要求16所述的显示面板，其中所述透明导电材料包括氧化铟锡。
  18. 如权利要求12所述的显示面板，其中所述第一导电层、第二导电层和第三导电层的其中至少一者采用导电金属制成；所述第二导电层设置在所述第 一导电层和第三导电层之间。
  19. 如权利要求12所述的显示面板，其中所述第一导电层设置在所述第二导电层和第三导电层之间。
  20. 如权利要求12所述的显示面板，其中所述第二导电层设置在所述第一导电层和第三导电层之间。
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