WO2018101956A1

WO2018101956A1 - Self-aligned electrode nano-contacts for non-volatile random access memory (ram) bit cells

Info

Publication number: WO2018101956A1
Application number: PCT/US2016/064644
Authority: WO
Inventors: Sarah E. ATANASOV; Satyarth Suri; Brian S. Doyle; Kevin P. O'brien; Kaan OGUZ; Mark L. Doczy; Charles C. Kuo
Original assignee: Intel Corporation
Priority date: 2016-12-02
Filing date: 2016-12-02
Publication date: 2018-06-07

Abstract

Self-aligned electrode nano-contacts for non-volatile random access memory (RAM) bit cells, and methods of fabricating electrode nano-contacts for non-volatile random access memory (RAM) bit cells, are described. In an example, semiconductor structure includes a conductive electrode disposed above a substrate. A non-volatile random access memory (RAM) element is disposed above the conductive electrode. The non-volatile RAM element has an uppermost surface with a surface area. A conductive contact is disposed on and is electrically connected to the uppermost surface of the non-volatile RAM element. The conductive contact has a surface area less than the surface area of the uppermost surface of the non-volatile RAM element at an interface of the conductive contact and the uppermost surface of the non-volatile RAM element.

Description

SELF-ALIGNED ELECTRODE NA O-CONTACTS FOR NON- VOLATILE RANDOM ACCESS

TECHNICAL FIELD

[0001] Embodiments of the invention are in the field of integrated circuit fabrication and, in particular, self-aligned electrode nano-contacts for non-volatile random access memory (RAM) bit cells.

BACKGROUND

[0002 ] For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of

semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. The necessity to optimize the performance of each device becomes increasingly significant.

[0003] Embedded SRAM and DRAM have problems with non-volatility and soft error rates, while embedded FLASH memories require additional masking layers or processing steps during manufacture, require high-voltage for programming, and have issues with endurance and reliability. Nonvolatile memory based on magnetic state change or resistance change is commonly anticipated as a replacement technology for flash memory. However, the processing of the material layers needed to fabricate devices based on magnetic state change or resistance change has proven problematic. Also, for low voltage non-volatile embedded applications, operating voltages less than IV and compatible with CMDS logic processes may be desirable but challenging to achieve.

[0004] Thus, significant improvements are still needed in the area of nonvolatile memory device manufacture,

BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figures 1 A-1E illustrate cross-sectional views representing various operations in a method of fabricating a self-aligned top electrode nano-contact for a non-volatile random access memory (RAM) bit cell, in accordance with an embodiment of the present invention.

[0006] Figures 2A-2E illustrate cross-sectional views representing various operations in a method of fabricating a self-aligned bottom electrode nano-contact for a non-volatile random access memory (RAM) bit cell, in accordance with an embodiment of the present invention. [0007] Figures 3A-3E illustrate cross-sectional views representing various operations in another method of fabricating a self-aligned bottom electrode nano-contact for a non-volatile random access memory (RAM ) bit cell, in accordance with an embodiment of the present invention.

[0008] Figure 4A illustrates a cross-sectional view and corresponding plan view of a nonvolatile random access memory (RAM) bit cell having a top electrode nano-contact, in accordance with an embodiment of the present invention.

[0009] Figure 4B illustrates a cross-sectional view and corresponding plan view of a nonvolatile random access memory (RAM) bit cell having a bottom electrode nano-contact, in accordance with an embodiment of the present invention,

[0010] Figure 4C illustrates a cross-sectional view and corresponding plan view of a nonvolatile random access memory (RAM) bit cell having another bottom electrode nano-contact, in accordance with an embodiment of the present invention.

[0011] Figure 5 illustrates a cross-sectional view of two RAM devices, each having an electrode nano-contact, in accordance with an embodiment of the present invention.

[0012] Figure 6 illustrates a cross-sectional view of a random access memory (RAM) element coupled to a drain side of a transistor selector, in accordance with an embodiment of the present invention.

[0013] Figures 7A-7E illustrate schematic views of several options for positioning an RAM element in an integrated circuit, in accordance with embodiments of the present invention.

[0014] Figure 8 illustrates a cross-sectional view of a logic region together with a random access memory (RAM) memory array integrated on a common substrate, in accordance with an embodiment of the present invention.

[0015] Figure 9 illustrates a schematic of a memory bit cell which includes an RAM memory element, in accordance with an embodiment of the present invention.

[0016] Figure 10 illustrates a block diagram of an electronic system, in accordance with an embodiment of the present invention.

[0017] Figure 11 illustrates a computing device in accordance with one embodiment of the invention.

[0018] Figure 12 illustrates an interposer that includes one or more embodiments of the invention.

DESCRIPTION OF THE EMBODIMENTS

[0019] Self-aligned electrode nano-contacts for non-volatile random access memory (RAM) bit cells, and methods of fabricating electrode nano-contacts for non-volatile random access memory (RAM) bit cells, are described. In the following description, numerous specific details are set forth, such as specific random access memory (RAM) material regimes and structure architectures, in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that embodiments of the present invention may be practiced without these specific details. In other instances, well-known features, such as operations associated with embedded memory, are not described in detail in order to not unnecessarily obscure embodiments of the present invention. Furthermore, it is to be appreciated that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.

[0020] Certain terminology may also be used in the following description for the purpose of reference only, and thus are not intended to be limiting. For example, terms such as "upper," "lower," "above," "below," "bottom," and "top" refer to directions in the drawings to which reference is made. Terms such as "front," "back," "rear," and "side" describe the orientation and/or location of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.

[0021] One or more embodiments described herein are directed to the fabrication of self- aligned top-electrode nano-contacts or self-aligned bottom-electrode nano-contacts for non- volatile memory bit cells. For example, embodiments may be implemented to provide a method for fabricating a self-aligned contact for a magnetic tunnel junction (MTJ) device structure and may be applicable for one of or both top and bottom electrodes for the MTJ device structure.

[0022] To provide context, traditional interconnects for MTJ devices are typically fabricated using dual damascene processes for both the top and bottom electrodes. Such an approach may result in contact areas approximately equal to device cross-sectional area.

Contacts which have cross-sectional areas smaller than the MTJ device may be of interest for increasing current density and efficiency of the MTJ device while avoiding edge-damaged regions as a result of etching MTJ material layers to form the MTJ device. Additionally, realization of self-aligned interconnects may enable precise patterning at smaller dimensions while reducing the number of lithography operations required to fabri cate such interconnects. State-of-the-art approaches to interconnect fabrication for MTJ devices have not addressed self- aligned interconnects or smaller dimension contact fabrication.

[0023] In accordance with an embodiment of the present invention, a single crystalline film (e.g., monocrystalline film) have crystal faces or planes that etch at different relative rates is used as either a template for creating self-aligned contacts to MTJ or other non-volatile memory devices, or as the interconnect itself (e.g., in the case of conductive monocrystalline films). As the crystal faces of the film are etched at different rates, it may be possible to fabricate very precise geometries for use as an interconnect. In a specific exemplary embodiment, fabrication of a self-aligned contact of relatively small dimension for a top or bottom MTJ electrode is described.

[0024] It is to be appreciated that the illustrated particular patterning layers or stacks described below in association with Figures 1A-1E, Figures 2A-2E or Figures 3A-3E, such particular material or layer compositions, are provided as exemplary embodiments. One of skill in the art will appreciate that other compositions or specific material stacks may be implemented within the spirit and scope of embodiments of the present invention.

[0025] In a first aspect, in the case of fabricating a top electrode nano-contact, a process sequence may involve first deposition of a single crystalline film on top of a blanket memory material stack. The memory material stack and the single crystalline film may then be etched to fabricate a non-volatile memory device, and a sidewall spacer may subsequently be formed, Metal fill and the fabrication of a self-aligned, relatively small, top contact may then be performed. As an example, Figures 1 A-1E illustrate cross-sectional views representing various operations in a method of fabricating a self-aligned top electrode nano-contact for a non-volatile random access memory (RAM) bit ceil, in accordance with an embodiment of the present invention.

[0026] Referring to Figure 1 A, a monocrystalline cap layer may be formed on a memory stack. For example, a starting structure 100 includes a substrate 102, a bottom electrode 104, a bottom conductive contact layer 106 (e.g., a monocrystalline or amorphous layer of a metal or semiconductor metal), a memory material stack 108, and a monocrystalline film 1 10. In an embodiment, the monocrystalline film 1 10 is composed of a semiconductor or insulating material having facets or planes with differing etch rates, such as a (100) monocrystalline silicon layer. In an embodiment, the memory material stack 108 represents a single material or multiple material layers, depending on the type of non-volatile memory. For example, the memory material stack 108 may include at least three layers (fixed layer, tunneling oxide, and free layer) suitable for fabricating a spin torque transfer memory (STTM). In another example, the memory material stack 108 may include one or more layers suitable for fabricating a resistive random access memory (RRAM) or a conductive bridge random access memory (CBRAM).

[0027] Referring to Figure I B, the memory stack may be etched and a sidewall spacer may be formed. For example, the memory material stack 108 is etched to form a patterned memory stack 112. Additionally, the monocrystalline film 110 is etched to form a

monocrystalline cap 1 14 on the patterned memory stack 112. In one embodiment, the monocrystalline film 110 and the memory material stack 108 are etched using a physical or dry or plasma etching process, A dielectric sidewail spacer 1 16 is then formed along the sidewalls of the monocrystalline cap 1 14 and the patterned memory stack 112. In one embodiment, the dielectric sidewail spacer 1 16 is fabricated using a blanket deposition and anisotropic etch process following the etching of the monocrystalline film 1 10 and the memory material stack 108. In an embodiment, the lateral dimension of the monocrystalline cap 114 and the patterned memory stack 1 12 is approximately the same in the X-dimension as in the Y -dimension. The patterned memory stack 112 may be referred to as a dot, and may have a round/circular shape or a square-like shape from a plan perspective (top-down along the Z -dimension).

[0028] Referring to Figure 1C, an opening for a nano-contact may then be etched. For example, the monocrystalline cap 1 14 is etched using a facet- or plane-dependent wet etch process, such as a hydroxide based wet etch process used for a monocrystalline silicon film. The etching provides a faceted cap layer 118 having an opening 120 therein exposing a small portion 122 (e.g., 10% or less of surface area) of the top surface of patterned memory stack 112.

[0029] Referring to Figure ID, nano-contact material may then be formed on the structure of Figure 1 C. For example, a metal fill process is performed by depositing conductive layer 124, e.g., by a chemical vapor deposition process, a physical vapor deposition process, or an electrochemical plating process. The conductive layer 124 is formed in opening 120 and is formed in electrical contact with the exposed small portion 122 of the top surface of the patterned memory stack 112.

[0030] Referring to Figure IE, a planarization process may then be performed. For example, planarization of the conductive layer 124 forms top electrode nano-contact 126 and confines the top electrode nano-contact 126 to a location above and in electrical contact with the exposed small portion 122 of the top surface of the patterned memory stack 112. In an embodiment, the conductive layer 124 is planarized using a chemical mechanical planarization (CMP) process. The planarization process may leave remaining polished metal portions 128. Additionally, in an embodiment, the faceted cap 1 8 is recessed during the planarization to form recessed faceted cap 130. Likewise, the dielectric spacer 1 16 is recessed to form recessed dielectric spacer 132, as is depicted in Figure IE.

[0031] It is to be appreciated that subsequent processing of the structure of Figure IE may involve formation of an upper electrode on the stack of Figure IE or may involve first removal of portions 128, replacement with an inter-layer dielectric (ILD) material and then formation of a top electrode thereon. In either case, in an embodiment, a top electrode is subsequently formed in electrical contact with the top electrode nano-contact 126. Exemplary structures including such a top electrode nano-contact 126 are described below. [0032] In another aspect, in a case of fabricating a bottom electrode nano-contact, a process sequence may involve first deposition of a conductive, monocrystalline film as a bottom electrode contact having crystal planes or facets with differing etch rates. A memory material stack may then be deposited and etched to provide a memory device. The monocrystalline film may then be etched to create a contact. The crystalline face which has the lower etch rate may naturally create the contact. A resulting void may then be filled with an oxide or other insulating material. As an example, Figures 2A-2E illustrate cross-sectional views representing various operations in a method of fabricating a self-aligned bottom electrode nano-contact for a nonvolatile random access memory (RAM) bit cell, in accordance with an embodiment of the present invention.

[0033] Referring to Figure 2A, a process may begin with deposition of a conductive monocrystalline film, followed by deposition and etching of a memory material stack. For example, a starting structure 200 includes a substrate 102, a bottom electrode 104, and a bottom conductive contact layer 202 (e.g., a monocrystalline metal or semiconductor material layer, such as a (100) silicon layer). A patterned memory material stack 1 12 is then fabricated on the bottom conductive contact layer 202, e.g., using a physical or dry or plasma etching process. In an embodiment, the lateral dimension of the patterned memory stack 112 is approximately the same in the X-dimension as in the Y-dimension. The patterned memory stack 112 may be referred to as a dot, and may have a round/circular shape or a square-like shape from a plan perspective (top- down along the Z-dimension).

[0034] Referring to Figure 2B, a monocrystalline film may be deposited for use as a mask. For example, a monocrystalline mask layer 204 is formed on the bottom conductive contact layer 202 and on either side of the patterned memory stack 112. In an embodiment, since the monocrystalline mask layer 204 is a mask layer, it need not be a conductive layer. In one embodiment, facets 206 are formed as the monocrystalline mask layer 204 is grown or deposited.

[0035] Referring to Figure 2C, the conductive crystalline film 202 may then be etched.

For example, the conductive crystalline film 202 is etched to form a patterned conductive crystalline film 208 with faceted recesses 210. In one such embodiment, the conductive crystalline film 202 is a doped (100) silicon film and faceted recesses 210 expose (111) surfaces of the doped (100) silicon film. In an embodiment, the etch process also thins and widens openings in the monocrystalline mask layer 204 forming monocrystalline mask layer 204'. In an embodiment, the conductive crystalline film 202 is etched to an extent that the patterned conductive crystalline film 208 exposes bottom portions 212 of the patterned memory stack 1 12. In a particular embodiment, the openings 210 expose a portion of the bottom electrode 104 to leave confined portion 214 which is a bottom nan o-con tact with a point or narrow portion 215 formed as a portion of the patterned conductive crystalline film 208,

[0036] Referring to Figure 2D, an oxide or other insulating film may be deposited to fill openings 210. For example, a dielectric layer 214 (e.g., oxide or ILD layer) is formed over the structure of Figure 2Cand beneath bottom portions 212 of the patterned memory stack 1 12. In an embodiment, the dielectric layer 214 is formed using a spin-on or chemical vapor deposition, either of which m ay be followed by a planarization process.

[0037] Referring to Figure 2E, a planarization process may be performed to re-expose an uppermost surface of the patterned memory stack 1 12. For example, the dielectric layer 214 is planarized to form planarized dielectric layer 216', e.g., by a chemical mechanical planarization process.

[0038] It is to be appreciated that subsequent processing of the structure of Figure 2E may involve formation of a contact layer and/or an upper electrode on the stack of Figure 2E. Exemplar}' structures including such a bottom electrode nano-contact 214 are described below.

[0039] In another aspect, in another case of fabricating a bottom electrode nano-contact, a process sequence may involve first deposition of an amorphous film on top of a bottom electrode. A memory material stack may then be deposited and etched to form a memory device, and a sidewalls spacer may be formed. A monocrystalline film having crystal planes or facets that etch at different rates may then be deposited and then etched for nano-contact fabrication. The amorphous film may etch faster than the crystal "mask." A resulting void may then be filled with a contact metal material. As an example, Figures 3A-3E illustrate cross-sectional views representing various operations in another method of fabricating a self-aligned bottom electrode nano-contact for a non-volatile random access memory (RAM) bit cell, in accordance with an embodiment of the present invention.

[0040] Referring to Figure 3A, an amorphous film deposition may be followed by memory material stack formation and etch process, and possible sidewall spacer formation. For example, a starting structure 300 includes a substrate 102, a bottom electrode 104, and a bottom amorphous layer 302, In an embodiment, the bottom amorphous layer 302 is an insulating material. A patterned memory material stack 112 is then fabricated on the bottom amorphous layer 302, e.g., using a physical or dry or plasma etching process. In an embodiment, the lateral dimension of the patterned memory stack 12 is approximately the same in the X-dimension as in the Y-dimension. The patterned memory stack 112 may be referred to as a dot, and may have a round/circular shape or a square-like shape from a plan perspective (top-down along the Z- dimension). A dielectric sidewall spacer 1 16 is then formed along the sidewalls of the patterned memory stack 1 12. A mask layer or patterned dielectric layer 304 is formed to cover a portion of bottom amorphous layer 302 on one side of the patterned memory stack 1 12 and, in an embodiment, further covers the patterned memory stack 112 and dielectric spacer 1 16, as is depicted.

[0041] Referring to Figure 3B, a monocrystailine film may then be deposited. For example, a monocrystailine mask layer 306 is formed on the bottom amorphous layer 302 and on the side of the patterned memory stack 1 12 opposite the side where the mask layer or patterned dielectric layer 304 is formed. In an embodiment, since the monocrystailine mask layer 306 is a mask layer, it need not be a conductive layer. In one embodiment, facets 308 are formed as the monocrystailine mask layer 306 is grown or deposited.

[0042] Referring to Figure 3C, the amorphous film may then be etched to form an opening for forming a nano-contact. For example, the bottom amorphous layer 302 is etched to form a patterned amorphous layer 310 with an opening 31 1. The etching may also laterally recess, and possibly thin, the monocrystailine mask layer 306 forming monocrystailine mask layer 306' . The opening 311 exposes a bottom portion 312 of the patterned memory stack 1 12. The opening 311 also exposes a portion of the bottom electrode 104.

[0043] Referring to Figure 3D, a metal fill of the opening 31 1 may then be performed.

For example, a metal fill layer 314 is deposited in opening 311 to provide electrical contact between the patterned memory stack 112 and the bottom electrode 104. The metal fill layer may be formed using a deposition such as, but not limited to, chemical vapor deposition, atomic layer deposition, or electroplating deposition.

[0044] Referring Figure 3E, the metal fill layer 314 may then be planarized. For example, the metal fill layer 314 is planarized, e.g., using a chemical mechanical planarization process, to expose an uppermost surface of the patterned memory stack 112. In an embodiment, the planarization of metal fill layer 314 forms a bottom electrode nano-contact 316 below and in electrical contact with the exposed bottom portion 312 of the patterned memory stack 112. A remaining planarized metal portion 318 is coupled to the bottom electrode nano-contact 316 and may be retained to provide access to contacting bottom electrode nano-contact 316. In an embodiment, the planarization process further provides a planarized mask or dielectric layer 320 from the mask layer or patterned dielectric layer 304. The planarized mask or dielectric layer 320 is laterally adjacent to and on a side of the patterned memory stack 112 opposite the side adjacent to the planarized metal portion 318.

[0045] It is to be appreciated that subsequent processing of the structure of Figure 3E may involve formation of a contact layer and/or an upper electrode on the stack of Figure 3E, e.g., on the upper surface of patterned memory stack 1 12 but not in contact with the planarized metal portion 318. Exemplar)' structures including such a bottom electrode nano-contact 316 are described below.

[0046] hi another aspect, a non-volatile memory device includes a top nano-contact, a bottom nano-contact, or both a top nano-contact and a bottom nano-contact, such as one or more of the nano-contacts 126, 214 or 316 described above. It is to be appreciated, however, that inclusion of both a top nano-contact and a bottom nano-contact may be too electrically resistive for some applications. Exemplary embodiments described below include either a top nano- contact or a bottom nano-contact.

[0047] In a first example, Figure 4A illustrates a cross-sectional view and corresponding plan view of a non-volatile random access memory (RAM) bit cell having a top electrode nano- contact, in accordance with an embodiment of the present invention,

[0048] Referring to Figure 4A, a semiconductor structure includes a conductive electrode

104 disposed above a substrate 102. A bottom conductive contact layer 106 is optionally included on the conductive electrode 104. A non-volatile random access memory (RAM) element 1 12 is disposed on the conductive electrode 104 or on the bottom conductive contact layer 106. The non-volatile RAM element 1 12 has an uppermost surface with a surface area, e.g., the area in the X-Y plane. A conductive contact 126 is disposed on and is electrically connected to the uppermost surface of the non-volatile RAM element 112. The conductive contact 126 has a surface area less than the surface area of the uppermost surface of the non- volatile RAM element 112 at an interface of the conductive contact 126 and the uppermost surface of the non-volatile RAM element 1 12, as is depicted.

[0049] In an embodiment, the conductive contact 126 is laterally surrounded by and in contact with a faceted material 130 disposed on the uppermost surface of the non-volatile RAM element 1 12. In an embodiment, the surface area of the uppermost surface of the non-volatile RAM element 1 12 is approximately in the range of 4-100 square nanometers (e.g., having a dimension of approximately 2 nanometers - 10 nanometers in the X-direction and a dimension of approximately 2 nanometers - 10 nanometers in the Y-direction), and the surface area of the conductive contact 126 at the interface of the conductive contact 126 and the uppermost surface of the non-volatile RAM element 1 12 is approximately 1 square nanometer (e.g., having a dimension of approximately I nanometer in the X-direction and a dimension of approximately 1 nanometer in the Y-direction). In an embodiment, a dielectric sidewail spacer 1 6 is laterally surrounding the non-volatile RAM element 1 12 and the conductive contact 126. In an embodiment, a second conductive electrode 400 is disposed on and is electrically coupled to the conductive contact 126. [0050] In a second example, Figure 4B illustrates a cross-sectional view and corresponding plan view of a non-volatile random access memory (RAM) bit ceil having a bottom electrode nano-contact, in accordance with an embodiment of the present invention.

[0051] Referring to Figure 4B, a semiconductor structure includes a conductive electrode 104 disposed above a substrate 102. A conductive contact 214 is disposed on and is electrically connected to the conductive electrode 104. A non-volatile random access memory (RAM) element 112 is disposed on and is electrically connected to the conductive contact 214. The nonvolatile RAM element 1 12 has a lowermost surface with a surface area, e.g., the area in the X-Y plane. The conductive contact 214 has a surface area less than the surface area of the lowermost surface of the non-volatile RAM element 112 at an interface of the conductive contact 214 and the lowermost surface of the non-volatile RAM element 1 12, as is depicted.

[0052] In an embodiment, the conductive contact 214 is laterally surrounded by but not in contact with a faceted material 208 disposed on the conductive electrode 104, as is depicted. In one such embodiment, a monocrystalline mask layer 204' is disposed on the faceted material 208, as is also depicted. In an embodiment, the surface area of the lowermost surface of the nonvolatile RAM element 112 is approximately in the range of 4-100 square nanometers (e.g., having a dimension of approximately 2 nanometers - 10 nanometers in the X-direction and a dimension of approximately 2 nanometers - 10 nanometers in the Y-direction), and the surface area of the conductive contact 214 at the interface of the conductive contact 214 and the lowermost surface of the non-volatile RAM element 1 12 is approximately 1 square nanometer (e.g., having a dimension of approximately 1 nanometer in the X-direction and a dimension of approximately 1 nanometer in the Y-direction). In an embodiment, a dielectric sidewall spacer 1 16 is laterally surrounding the non-volatile RAM element 1 12 but is not laterally surrounding the conductive contact 2 4, In an embodiment, a second conductive electrode 402 is disposed on and is electrically coupled to an uppermost surface of the non-volatile RAM element 1 12.

[0053] In a third example, Figure 4C illustrates a cross-sectional view and corresponding plan view of a non-volatile random access memory (RAM) bit cell having another bottom electrode nano-contact, in accordance with an embodiment of the present invention.

[0054] Referring to Figure 4C, a semiconductor structure includes a conductive electrode 104 disposed above a substrate 02. A conductive contact 316 is disposed on and is electrically connected to the conductive electrode 104, A non-volatile random access memory (RAM) element 112 is disposed on and is electrically connected to the conductive contact 316. The nonvolatile A : element 112 has a lowermost surface with a surface area, e.g., the area in the X-Y plane, surrounded by a perimeter, A portion of the conductive contact 316 is within the perimeter and a portion of the conductive contact 316 is outside of the perimeter at an interface of the conductive contact 316 and the lowermost surface of the non-volatile RAM element 1 12. The portion of the conductive contact 316 within the perimeter, i.e., the portion of the contact 316 in contact with exposed bottom portion 312 of the non-volatile RAM element 112, has a surface area less than the surface area of the lowermost surface of the non-volatile KAM element 112 at the interface of the conductive contact 316 and the lowerm ost surface of the non-volatile RAM element 112.

[0055] In an embodiment, the conductive contact 316 is laterally surrounded by and in contact with an insulating material 310 disposed on the conductive electrode 104. In an embodiment, the surface area of the lowermost surface of the non-volatile RAM element 1 12 is approximately in the range of 4-100 square nanometers (e.g., having a dimension of

approximately 2 nanometers - 10 nanometers in the X-direction and a dimension of

approximately 2 nanometers - 10 nanometers in the Y -directi on), and the surface area of the portion of the conductive contact 316 within the perimeter at the interface of the conductive contact 316 and the lowermost surface of the non-volatile RAM element 1 12 is approximately 1 square nanometer (e.g., having a dimension of approximately I nanometer in the X-direction and a dimension of approximately 1 nanometer in the Y-direction). In an embodiment, a dielectric sidewall spacer 116 is laterally surrounding the non-volatile RA : element 112 but is not laterally surrounding the conductive contact 316. In an embodiment, a second conductive electrode 404 is disposed on and is electrically coupled to an uppermost surface of the non- volati le RAM element 1 12.

[0056] For all cases of Figures 4A-4C, in an embodiment, the non-volatile RAM element

1 12 is a spin torque transfer random access memory (STTRAM) element. In another

embodiment, the non-volatile RAM element 1 12 is a resistive random access memory (RRAM) element. In another embodiment, the non-volatile RAM element 112 is a conductive bridge random access memory (CBRAM) element.

[0057] More generally, one or more embodiments of the present invention are directed to methods for integrating RAM memory arrays into a logic processor, such as spin torque transfer random access memory (STTRAM) arrays, resistive random access memory (RRAM) arrays, or conductive bridge random access memory (CBRAM) memory arrays. Particular embodiments may be suitable for fabricating embedded non-volatile memory (e-NVM). Approaches described herein may provide a fabrication pathway for high performance RAM cells and increase the potential of using scaled RAM cells for future e-NVM needs, such as for integration in system on chip (SoC) products.

[0058] It is to be appreciated that an array of A : elements may be fabricated on an array of conductive interconnect formed in an inter-layer dielectric (ELD) layer. As an example, Figure 5 illustrates a cross-sectional view of two RAM devices, each having an electrode nano- contact, in accordance with an embodiment of the present inventi on.

[0059] Referring to Figure 5, each of the RAM devices includes a conductive

interconnect 506 disposed in an inter-layer dielectric (ILD) layer 504 disposed above a substrate 502. The ILD layer 506 may have an uppermost surface substantially co-planar with an uppermost surface of the conductive interconnect 506. An RAM element 570 is disposed on each of the conductive interconnects 506. Each RAM element 570 may include a lower electrode 572, a switching layer (or stack of layers including a switching layer) 112, and a top nano-contact 126, which may be laterally surrounded by a faceted material 130, as is depicted in Figure 5 and as is described in association with Figures 1 A-1E and Figure 4A. In an embodiment, in addition to, or in place of, the top nano-contact 126, a bottom nano-contact may be included at location 214, an example of which is described in association with Figures 2A-2E and Figure 4B. In another embodiment, in addition to, or in place of, the top nano-contact 126, a bottom nano- contact may be included at location 316, an example of which is described in association with Figures 3 A-3E and Figure 4C.

[0060] In an embodiment, the conductive interconnect 506 includes a conductive line portion 508 and an underlying via portion 510, as is depicted in Figure 5. In another

embodiment, the conductive interconnect is a conductive via. In one embodiment, the conductive interconnect includes a conductive fill material 514 surrounded by a barrier layer 512, which may include an upper barrier layer 516, as is depicted in Figure 5, In a specific such embodiment, the conductive fill material 5 14 but not the barrier layer 512 is recessed to form an opening in which the upper barrier layer 516 is then formed. In an embodiment, although depicted using different shading, the upper barrier layer 516 is composed of substantially the same material as barrier layer. In one such embodiment, the material includes tantalum nitride.

[0061] In an embodiment, with reference to Figure 5, the RAM bit cell or element 570 is a spin torque transfer random access memory (STTRAM) bit cell or element. In one such embodiment, the switching layer (or stack of layers including a switching layer) 1 12 is a stack of layers 112A/112B/112C that is referred to as a magnetic tunnel junction (MTJ). In a specific such embodiment, the MTJ includes a fixed magnetic layer 112A, a tunneling barrier layer 112B, and a free magnetic layer 1 12C. In another specific such embodiment, the MTJ includes a free magnetic layer 112 A, a tunneling barrier layer 1 12B, and a fixed magnetic layer 1 12C. The MTJ may utilize a phenomenon known as tunneling magnetoresistance (TMR).

[0062] For such a structure 112A/112B/1 12C including two ferromagnetic layers separated by a thin insulating tunnel layer, it is more likely that electrons will tunnel through the tunnel material layer when magnetizations of the two magnetic layers are in a parallel orientati on than if they are not (non-parallel or antiparallel orientation). As such, the MTJ can be switched between two states of electrical resi stance, one state having a low resi stance and one state with a high resistance. The greater the differential in resistance, the higher the TMR ratio. The higher the TMR ratio, the more readily a bit can be reliably stored in association with the MTJ resistive state, MTJs with magneti c electrodes having a perpendicular (out of plane of substrate) magnetic easy axis have a potential for realizing higher density memory than in-plane variants, and may be referred to a pMTJ. In some embodiments, then, the MTJ is a perpendicular system, where spins of the magnetic layers are perpendicular to the plane of the material layers (e.g., the magnetic easy axis is in the z-direction out of the plane of substrate).

[0063] Referring to Figure 5, fixed magnetic layer 112A (or 1 12C in the case that 1 12A is a free layer) may be composed of a material or stack of materials suitable for maintaining a fixed magnetization direction while a free magnetic material layer is magnetically softer (e.g., magnetization can easily rotate to parallel and antiparallel state with respect to fixed layer). In an embodiment, the fixed magnetic layer 1 2A (or 1 12C) is composed of a material or stack of materials suitable for maintaining a fixed majority spin. Thus, the fixed magnetic layer 112A (or 1 12C) may be referred to as a ferromagnetic layer. In one embodiment, the fixed magnetic layer 112A (or 1 12C) is composed of a single layer of cobalt iron boron (CoFeB). However, in another embodiment, the fixed magnetic layer 112A (or 1 12C) is composed of a cobalt iron boron (CoFeB) layer, ruthenium (Ru) layer, cobalt iron boron (CoFeB) layer stack. In an embodiment, although not depicted, a synthetic antiferromagnet (SAF) is disposed on or adjacent the fixed magnetic layer 112A (or 112C).

[0064] Referring again to Figure 5, in an embodiment, the dielectric or tunneling layer

1 12B is composed of a material suitable for allowing current of a majority spin to pass through the layer, while impeding at least to some extent current of a minority spin to pass through the layer. Thus, the dielectric or tunneling layer 112B (or spin filter layer) may be referred to as a tunneling layer. In one embodiment, the dielectric layer is composed of a material such as, but not limited to, magnesium oxide (MgO) or aluminum oxide (A1₂0₃). In one embodiment, the dielectric layer has a thickness of approximately 1 nanometer.

[0065] Referring again to Figure 5, in an embodiment, the free magnetic layer 112C (or 1 12 A in the case that 1 12C is a fixed layer) is composed of a material suitable for transitioning between a majority spin and a minority spin, depending on the application. Thus, the free magnetic layer (or memory layer) may be referred to as a ferromagnetic memory layer. In one embodiment, the free magnetic layer is composed of a layer of cobalt iron (CoFe) or cobalt iron boron (CoFeB). [0066] In an embodiment, the MTJ functions essentially as a resistor, where the resistance of an electrical path through the MTJ may exist in two resistive states, either "high" or "low," depending on the direction or orientation of magnetization in the free magnetic layer and in the fixed magnetic layer. In the case that the spin direction is of minority in the free magnetic layer, a high resistive state exists, where direction of magnetization in the free magnetic layer and the fixed magnetic layer are substantially opposed or anti-parallel with one another. In the case that the spin direction is of majority in the free magnetic layer, a low resistive state exists, where the direction of magnetization in the free magnetic layer and the fixed magnetic layer is substantially aligned or parallel with one another. It is to be appreciated that the terms "low" and "high" with regard to the resistive state of the MTJ are relative to one another. In other words, the high resistive state is merely a detectibly higher resistance than the low resistive state, and vice versa. Thus, with a detectible difference in resistance, the low and high resistive states can represent different bits of information (i.e. a "0" or a " 1").

[0067] Thus, the MTJ may store a single bit of information ("0" or "1") by its state of magnetization. The information stored in the MTJ is sensed by driving a current through the MTJ. The free magnetic layer does not require power to retain its magnetic orientations. As such, the state of the MTJ is preserved when power to the device is removed. Therefore, a memory bit cell 570 is, in an embodiment, non-volatile. In accordance with an embodiment of the present invention, each bit of data is stored in a separate magnetic tunnel junction (MTJ). To write information in a STT-MRAM device, the spin transfer torque effect is used to switch the free layer from the parallel to anti-parallel state and vice versa. The passing of current through the MTJ produces spin polarized current, which results in a torque being applied to the magnetization of the free layer. When the spin polarized current is sufficiently strong, enough torque is applied to the free layer to cause its magnetic orientation to change, thus allowing for bits to be written. To read the stored bit, sensing circuitry measures the resistance of the MTJ.

[0068] Referring again to Figure 5, in an embodiment in which the RAM bit cell or element 570 is a spin torque transfer random access memory (STTRAM) bit cell or element, the lower electrode 572 includes a metal alloy layer, such as a titanium nitride (TiN) layer or a tantalum nitride (TaN) layer. In an embodiment, the top nano-contact 126 is a topographically smooth electrode. In one such embodiment, the top nano-contact 126 has a thickness suitable for good conductivity but has little to no columnar structure formation that would otherwise lead to a rough top surface. Such a topographically smooth feature may be referred to as amorphous in structure. In a specific embodiment, the top nano-contact 126 is composed of Ru layers interleaved with Ta layers. In alternative embodiments, however, the top nano-contact 126 is a conventional single metal electrode, such as a Ta, Pt or Ru electrode. [0069] In another embodiment, with reference to Figure 5, the RAM bit cell or element

570 is a resistive random access memory (RRAM) bit cell or element. Nonvolatile memory based on resistance change is known as RRAM. In an embodiment, the switching layer 112 is an anionic-based conductive oxide layer. In one such embodiment, one electrode (lower electrode 572 or top nano-contact 126) in a memory element including the anionic-based conductive oxide layer 1 12 is a noble metal based electrode, while the other electrode (top nano-contact 126 or lower electrode 572, respectively) is a transition metal for which some of the lower valence oxides are conductive (e.g., to act as an oxygen reservoir). That is, when oxygen atoms migrate to the transition metal oxide, the resulting interfacial transition metal oxide formed remains conductive. Examples of suitable transition metals which form conductive oxides include but are not limited to, W, V, Cr, or Ir. In an embodiment, examples of suitable noble metals include, but are not limited to Pd or Pt. In other embodiments, one or both of the bottom electrode 572 and/or the top nan-contact 126 is fabricated from an electro-chromic material. In other embodiments, one or both of the bottom electrode 572 and/or the top nano-contact 126 is fabricated from a second, different conductive oxide material.

[0070] In an embodiment, for an RRAM bit cell or element, examples of suitable conductive oxides for switching layer 1 12 include, but are not limited to I lf(X or TaO_x. In another embodiment, the conductive oxide layer is composed of a material with two or more metal elements (e.g., as contrasted to common RRAM memories using one metal such as found in binary oxides, such as Hf(3_x or TaO_x). For example, in an embodiment, the switching layer 112 includes a material such as, but not limited to, ITO (In₂0₃-_xSn0₂-x), IniCb-x, sub- stoichiometric yttria doped zirconia (Y₂0₃-_xZr02-_x), or

In such ternary, quaternary, etc. alloys, the metals used are from adjacent columns of the periodic table. Specific examples of suitable such conductive oxides include, but are not limited to: Y and Zr in Y₂0₃-xZr0₂-x, In and Sn in In₂0₃-_xSn0₂-_x, or Sr and La in Lat-xSrxGai-yMgyCb. Such materials may be viewed as compositions selected to have aliovalent substitution to significantly increase the number of oxygen vacancies.

[0071] In an embodiment, with reference to Figure 5, the RAM bit ceil or element 570 is a conductive bridge random access memory (CBRAM) bit ceil or element. It is to be appreciated that CBRAM may be viewed as a specific type of resistive random access memory (RR AM). In a CBRAM device, a filament may be formed based on metallic migration into an electrolyte material which is the switching layer of the CBRAM device. By contrast, in conventional RRAM, a filament may be created based on oxygen vacancies.

[0072] In an embodiment, for a CBRAM) bit cell or element, the resistance switching layer 1 12 is composed of a solid electrolyte material. An electrolyte or solid electrolyte, as used herein, refers to solid electrolyte material which is a solid substance that receives ions, provides ions, or can transport ions. In an exemplary embodiment, the solid electrolyte material i s a chalcogenide material. In another embodiment, the resistance switching layer 112 is composed of a metal oxide, such as hafnium oxide.

[0073] In an embodiment, in the case of a CBRAM bit cell or element, the lower electrode 572 (or, alternatively, the top nano-contact 126) is an active electrode layer. The active electrode layer may be a source of cations for filament formation or resistance change in the switching layer 112. In an embodiment, the active electrode layer includes a metal species such as, but not limited to, copper, silver, nickel, or lithium. In an embodiment, the top nano-contact 126 (or, alternatively, the lower electrode 572 in the case that the top nano-contact 126 is an active electrode) is a passive electrode layer. The passive electrode layer may not be a source of cations for filament formation or resistance change in the switching layer 1 12. In an

embodiment, the passive electrode layer includes a metal species such as, but not limited to, tungsten or platinum. In one embodiment, a metal nitride, such as a titanium nitride or a tantalum nitride layer, is used as the material for the passive electrode layer. In another embodiment, the passive electrode layer is composed of a noble metal such as, but not limited to Pd or Pt.

[0074] As described in association with Figures 1 A-1E, Figures 2A-2E or Figures 3A-3E, in an embodiment, the materials of the RAM bit cell or elements 570 are patterned using a subtractive etching process. As depicted in Figure 5, in an embodiment, a dielectric sidewall spacer 1 16 is formed laterally adjacent to and in contact with sidewails of the patterned material layers of the RAM bit cell or elements 570, In one embodiment, the dielectric sidewall spacer 1 16 is formed using a conformal deposition of a dielectric material, such as a silicon nitride layer, and subsequent anisotropic etching to form the dielectric sidewall spacer 116.

[0075] As used throughout the present disclosure, in an embodiment, a substrate such as substrate 102, 502, 606 or 4060 is a semiconductor substrate. In one implementation, the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon- on-insulator substructure. In other implementations, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antirnonide, lead tellunde, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antirnonide, or other combinations of group III-V or group IV materials. Although a few examples of materials from which the substrate may^¬ be formed are described here, any material that may serve as a foundation upon which a semiconductor device may be built falls within the spirit and scope of the present invention. [0076] Thus, it is to be appreciated that the layers and materials described herein and as used throughout the present disclosure are typically formed on or above an underlying

semiconductor substrate or structure, such as underlying device layer(s) of an integrated circuit. In an embodiment, an underlying semiconductor substrate such as substrate 102, 502, 606 or 4060 represents a general workpiece object used to manufacture integrated circuits. The semiconductor substrate often includes a wafer or other piece of silicon or another semiconductor material. Suitable semiconductor substrates include, but are not limited to, single crystal silicon, poiycrystalline silicon and silicon on insulator (SOI), as well as similar substrates formed of other semiconductor materials. The semiconductor substrate, depending on the stage of manufacture, often inciudes transistors, integrated circuitry, and the like. The substrate may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates. In one embodiment, the illustrated structures depicted in Figures 1A-1E, Figures 2A-2E, Figures 3A-3E, Figures 4A-4C, Figure 5, Figure 6, Figures 7A- 7E or Figure 8 are fabricated on underlying transistor or other semiconductor device layer(s) formed in or above the substrate 102, 502, 606 or 4060. In another embodiment, the illustrated structures depicted in 1A-1E, Figures 2A-2E, Figures 3A-3E, Figures 4A-4C, Figure 5, Figure 6, Figures 7A-7E or Figure 8 are fabricated on underlying lower level interconnect layers formed above the substrate 102, 502, 606 or 4060,

[0077] In an embodiment, as used throughout the present description, interlay er dielectric ILD) material is composed of or includes a layer of a dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (Si0₂)), doped oxides of silicon, fluorinated oxides of silicon, carbon doped oxides of silicon, various low-k dielectric materials known in the arts, and combinations thereof. The interlayer dielectric material may be formed by conventional techniques, such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods.

[0078] In an embodiment, as is also used throughout the present description, metal lines or interconnect line material (and via material) is composed of one or more metal or other conductive structures. A common example is the use of copper lines and structures that may or may not include barrier layers between the copper and surrounding DLD material. As used herein, the term metal inciudes alloys, stacks, and other combinations of multiple metals. For example, the metal interconnect lines may include barrier layers (e.g., layers including one or more of Ta, TaN, Ti or TiN), stacks of different metals or alloys, etc. Thus, the interconnect lines may be a single material layer, or may be formed from several layers, including conductive liner layers and fill layers. Any suitable deposition process, such as electroplating, chemical vapor deposition or physical vapor deposition, may be used to form interconnect lines. In an embodiment, the interconnect lines are composed of a conductive material such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au or alloys thereof. The interconnect lines are also sometimes referred to in the art as traces, wires, lines, metal, or simply interconnect.

[0079] In an embodiment, as is also used throughout the present description, hardmask materials are composed of dielectric materials different from the interlayer dielectric material . In one embodiment, different hardmask materials may be used in different regions so as to provide different growth or etch selectivity to each other and to the underlying dielectric and metal layers. In some embodiments, a hardmask layer includes a layer of a nitride of silicon (e.g., silicon nitride) or a layer of an oxide of silicon, or both, or a combination thereof. Other suitable materials may include carbon-based materials. In another embodiment, a hardmask material includes a metal species. For example, a hardmask or other overlying material may include a layer of a nitride of titanium or another metal (e.g., titanium nitride). Potentially lesser amounts of other materials, such as oxygen, may be included in one or more of these layers.

Alternatively, other hardmask layers known in the arts may be used depending upon the particular implementation. The hardmask layers maybe formed by CVD, PVD, or by other deposition methods.

[0080] In an embodiment, as is also used throughout the present description, lithographic- operations are performed using 193nm immersion litho (1193), EUV and/or EBDW lithography, or the like. A positive tone or a negative tone resist may be used. In one embodiment, a lithographic mask is a trilayer mask composed of a topographic masking portion, an anti- reflective coating (ARC) layer, and a photoresist layer. In a particular such embodiment, the topographic masking portion is a carbon hardmask (CHM) layer and the anti -reflective coating layer is a silicon ARC layer.

[0081] In another aspect, a conductive interconnect of an associated RAM element stack may be coupled to a drain region of an underlying select transistor disposed on a substrate. As an example. Figure 6 illustrates a cross-sectional view of a random access memory (RAM) element coupled to a drain side of a transistor selector, in accordance with an embodiment of the present invention.

[0082] Referring to Figure 6, a memory structure 600 includes a transistor 602 disposed in or above an active region 604 of a semiconductor substrate 606. The transistor 602 includes a gate electrode 608 with source/drain regions 610 on either side of the gate electrode 608, and in active region 604 of substrate 606. In an embodiment, the source/drain region 610 on the left- hand side of Figure 6 is a source region, and the source/drain region 610 on the right-hand side of Figure 6 is a drain region. An RAM element 570 is coupled to the drain region of the transistor 602, but not to the source region of the transistor 602, The arrangement enables driving of the RAM element 570 by the drain side only. The RAM element 570 and portions of the transistor 602 may be included in an inter-layer dielectric (HJD) layer 650, as is depicted in Figure 6.

[0083] The RAM element 570 of Figure 6 includes a lower electrode 572, a switching layer (or stack of layers including a switching layer) 112, and a top nano-contact 126, which may be laterally surrounded by a faceted material 130, as is depicted in Figure 6 and as is described in association with Figures 1A-1E and Figure 4A. In an embodiment, in addition to, or in place of, the top nano-contact 126, a bottom nano-contact may be included at location 214, an example of which is described in association with Figures 2A-2E and Figure 4B. In another embodiment, in addition to, or in place of, the top nano-contact 126, a bottom nano-contact may be included at location 316, an example of which is described in association with Figures 3A-3E and Figure 4C.

[0084] In an embodiment, the RAM element 570 is, in an embodiment, included as an interrupting feature along a conductive drain contact 630, as is depicted. In one such

embodiment, corresponding gate contact 634 and source contact 632 are not coupled to, or interrupted by the RAM element 570, as is depicted in Figure 6. It is to be appreciated that although the RAM element 570 is shown generically along the drain contact 630 without a lateral reference, the actual layer in which the RAM element 570 is included may be viewed as an interconnect layer (e.g., Ml, M2, M3, M4, etc) corresponding to a logic region in another area of the substrate 606. It is also to be appreciated that additional interconnect layer(s) may be formed on top of the structure 600 shown in Figure 6, e.g., using standard dual damascene process techniques that are well-known in the art.

[0085] In an embodiment, transistor 602 is a metal-oxide-semiconductor field-effect transistor (MOSFET or simply MOS transistor), fabricated on a substrate. In various

implementations of the invention, the MOS transistors described herein may be planar transistors, nonplanar transistors, or a combination of both. Nonplanar transistors include

FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors,

[0086] In an embodiment, each MOS transistor includes a gate stack formed of at least two layers, a gate dielectric layer and a gate electrode layer. The gate dielectric layer may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide (Si0₂) and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used.

[0087] The gate electrode layer of each MOS transistor is formed on the gate dielectric- layer and may consist of at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a fill metal layer.

[0088] For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3 ,9 eV and about 4.2 eV.

[0089] In some implementations, the gate electrode may consist of a "LP'-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the invention, the gate electrode may consist of a combination of U- shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

[0090] In some implementations of the invention, a pair of sidewall spacers 652 may be formed on opposing sides of the gate stack that bracket the gate stack. The sidewall spacers may^¬ be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack,

[0091] As is well known in the art, source and drain regions are formed within the substrate adjacent to the gate stack of each MOS transistor. The source and drain regions are generally formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source and drain regions. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source and drain regions. In some implementations, the source and drain regions may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations the epitaxiaily deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the source and drain regions may be formed using one or more alternate semiconductor materials such as germanium or a group HI-V material or alloy. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the source and drain regions.

[0092] To provide further context, integrating memory directly onto a microprocessor chip would be advantageous since it enables higher operation speeds compared to having physically separate logic and memory chips. Unfortunately, traditional charge-based memory technologies such as DRAM and NAND Flash are now facing severe scal bility issues related to increasingly precise charge placement and sensing requirements. As such, embedding charge- based memory directly onto a high performance logic chip is not very attractive for future technology nodes. However, a memory technology that does have the potential to scale to much smaller geometries compared to traditional charge-based memories includes one of STTRAM, RRAM, or CBRAM, since it relies on magnetic state or on resistivity rather than charge as the information carrier. However, in order to exploit the potential benefits of a high performance logic chip with embedded STTRAM memory, RRAM memory, or CBRAM memory, an appropriate integrated logic plus RAM structure and fabrication method is needed.

Embodim ents of the present invention include such structures and fabrication processes.

[0093] Relating to one or more embodiments described herein, it is to be appreciated that traditional DRAM: memon,' is facing severe scaling issues and, so, other types of memory devices are being actively explored in the electronics industry. Future contenders include STTRAM devices, RRAM devices, or CBRAM devices. Embodiments described herein include a fabrication method for embedding such RAM: bit cell arrays into a logic process technology. Embodiments described may be advantageous for processing schemes involving the fabrication of logic processors with embedded memory arrays.

[0094] In another aspect, an RAM element may be included in an integrated circuit in regions typically referred to as back end or back end of line (BEOL) layers of the integrated circuit. As examples, Figures 7A-7E illustrate schematic views of several options for positioning an RAM element in an integrated circuit, in accordance with embodim ents of the present invention.

[0095] Referring to all Figures 7A-7E, in each case, a memory region 700 and a logic region 702 of an integrated circuit are depicted schematically. Each memory region 700 includes a select transistor 704 and overlying alternating metal lines and vias. Each logic region includes a plurality of transistors 706 and overlying alternating metal lines and vias which can be used to connect the plurality of transistors 706 into functional circuits, as is well known in the art. Each of the RAM: devices 720, 730, 740, 750 or 760 may be a device such as described above for RAM memory element 170, which includes a lower electrode 172, a switching layer 174 (or stack of layers including a switching layer), and an upper electrode 176, as described in association with Figures 2 and 5. In an embodiment, each RAM device is an STTRAM device, an R AM device, or a CBRAM device.

[0096] Referring to Figure 7A, an RAM: device 720 is disposed between a lower conductive via 722 and an upper conductive line 724. In one embodiment, the lower conductive via 722 is in electrical contact with a lower electrode of the RAM device 720, and the upper conductive line 724 is in electrical contact with an upper electrode of the RAM device 720. In a specific embodiment, the lower conductive via 722 is in direct contact with a lower electrode of the RAM device 720, and the upper conductive line 724 is in direct contact with an upper electrode of the R AM device 720.

[0097] Referring to Figure 7B, an RAM device 730 is disposed between a lower conductive line 732 and an upper conductive via 734. In one embodiment, the lower conductive line 732 is in electrical contact with a lower electrode of the RAM device 730, and the upper conductive via 734 is in electrical contact with an upper electrode of the RAM: device 730. In a specific embodiment, the lower conductive line 732 is in direct contact with a lower electrode of the RAM device 730, and the upper conductive via 834 is in direct contact with an upper electrode of the R AM: device 730.

[0098] Referring to Figure 7C, an RAM device 740 is disposed between a lower conductive line 742 and an upper conductive line 744 without an intervening conductive via. In one embodiment, the lower conductive line 742 is in electrical contact with a lower electrode of the RAM device 740, and the upper conductive line 744 is in electrical contact with an upper electrode of the RAM device 740. In a specific embodiment, the lower conductive line 742 is in direct contact with a lower electrode of the RAM device 740, and the upper conductive line 744 is in direct contact with an upper electrode of the RAM device 740.

[0099] Referring to Figure 7D, an RAM device 750 is disposed between a lower conductive via 752 and an upper conductive via 754 without an intervening conductive line. In one embodiment, the lower conductive via 752 is in electrical contact with a lower electrode of the RAM device 750, and the upper conductive via 754 is in electrical contact with an upper electrode of the A : device 750. In a specific embodiment, the lower conductive via 752 is in direct contact with a bottom electrode of the RAM device 750, and the upper conductive via 754 is in direct contact with an upper electrode of the RAM device 750.

[00100] Referring to Figure 7E, an RAM device 760 is disposed between a lower conductive line 762 and an upper conductive via 764 in place of an intervening conductive line and conductive via pairing. In one embodiment, the lower conductive line 762 is in electrical contact with a bottom electrode of the RAM device 760, and the upper conductive via 764 is in electrical contact with a lower electrode of the RAM device 760. In a specific embodiment, the lower conductive line 762 is in direct contact with a lower electrode of the RAM device 760, and the upper conductive via 764 is in direct contact with an upper electrode of the RAM device 760.

[00101] An RAM array may be embedded in a logic chip. As an example, Figure 8 illustrates a cross-sectional view of a logic region together with a random access memory (RAM) memory array integrated on a common substrate, in accordance with an embodiment of the present invention. Referring to Figure 8, a structure 4000 includes a logic region 4020 and an RAM array region 4040.

[00102] Referring to the RAM array region 4040 of Figure 8, in a first layer, metal 2 (M2) 4080 and via 1 (VI) 4100 structures are formed above a substrate 4060. The M2 4080 and VI 4100 structures are formed in an inter-layer dielectric layer 4120 disposed over an etch stop layer 4140.

[00103] Referring again to the RAM array region 4040 of Figure 8, in a second layer, a plurality of R AM stacks 570 is formed in the inter-layer dielectric layer 4200 disposed over the etch stop layer 4220. The plurality of RAM stacks 570 may be coupled to corresponding ones of the M2 4080 structures by a conductive layer 4240, as is depicted in Figure 8, A dielectric spacer layer 1 16 m ay be formed on sidewalls of portions of the R AM: stacks, as is also depicted in Figure 8. Each of the RAM stacks 570 includes a lower electrode 572, a switching layer (or stack of layers including a switching layer) 1 12, and a top nano-contact 126, which may be laterally surrounded by a faceted material, as is depicted in Figure 8 and as is described in association with Figures 1 A-1E and Figure 4A. In an embodiment, in addition to, or in place of, the top nano-contact 126, a bottom nano-contact may be included at location 214, an example of which is described in association with Figures 2A-2E and Figure 4B. In another embodiment, in addition to, or in place of, the top nano-contact 126, a bottom nano-contact may be included at location 316, an example of which is described in association with Figures 3A-3E and Figure 4C. It is to be appreciated that each RAM stack 570 may include one of combinations of material layers of RAM element 570 described in association with Figure 5. In an embodiment, the RAM stack 570 is an STTRAM stack, an RRAM stack, or a CBRAM stack. In an embodiment, a top electrode or conductive hardmask 4340 may also be included, as is depicted in Figure 8.

[00104] Referring again to the RAM array region 4040 of Figure 8, in a third layer, an etch stop layer 4360 is disposed on the inter-layer dielectric layer 4200. Metal 4 (M4) 4380 and via to memory 4400 structures are formed in the inter-layer dielectric layer 4420 disposed over the etch stop layer 4360. It is to be appreciated that additional interconnect layer(s) may be formed on top of the M4/via to memory layers of the RAM array region 4040 of Figure 8, e.g., using standard dual damascene process techniques that are well-known in the art.

[00105] It is to be appreciated that although the RAM stacks may actually include numerous layers of very thin films, for the sake of simplicity the RAM stacks 570 are depi cted as describe above. It is also to be appreciated that although in the illustrations the RAM stacks are shown embedded into a corresponding logic metal 3 (M3) layer, they may instead be embedded into some other interconnect layer (e.g., Ml, M2, M4, etc.)

[00106] Referring again to Figure 8, in an embodiment, the conductive metal layer 4240 is a tantalum nitride (TaN) layer. In one embodiment, the conductive metal layer 4240 is referred to as a "thin via" layer. In an embodiment, the top electrode 4340 is composed of a material or stack of materials suitable for electrically contacting the RAM stack 170. in an embodiment, the top electrode 4340 i s a topographically smooth electrode. In one such embodiment, the top electrode 4340 has a thickness suitable for good conductivity but has little to no columnar structure formation that would otherwise lead to a rough top surface. Such a topographically smooth electrode may be referred to as amorphous in structure. In an embodiment, the top electrode 4340 begins as a hardmask layer, such as a titanium nitride hardmask layer, used for patterning the RAM stack and is ultimately retained as a conductive contact.

[00107] Referring now to the logic region 4020 of Figure 8, in the first layer, metal 2 (M2)

4500 and via 1 (VI ) 4520 structures are formed in the inter-layer dielectric layer 4120 disposed over the etch stop layer 4140. In the second layer, the etch stop layer 4220 is disposed on the inter-layer dielectric layer 4120. Metal 3 (M3) 4540 and via 2 (V2) 4560 structures are formed in the inter-layer dielectric layer 4200 disposed over the etch stop layer 4220. In the third layer, the etch stop layer 4360 is disposed on the inter-layer dielectric layer 4200. Metal 4 (M4) 4580 and via 3 (V3) 4600 structures are formed in the inter-layer dielectric layer 4420 disposed over the etch stop layer 4360. It is to be appreciated that additional interconnect iayer(s) may be formed on top of the M4/V3 layers of the logic region 4020 of Figure 8, e.g., using standard dual damascene process techniques that are well-known in the art.

[00108] It is to be appreciated that an RAM material stack may be used to fabricate a memoiy bit cell. For example, Figure 9 illustrates a schematic of a memoiy bit cell 900 which includes a random access memory (RAM) memory element 570, in accordance with an embodiment of the present invention. Such an RAM memory element may be suitable for manufacture on a substrate in common with logic regions of the substrate.

[00109] Referring to Figure 9, the RAM memory element 570 includes a lower electrode

572 with a switching layer 1 12 (or stack of layers including a switching layer) above the lower electrode 572. A top nano-contact 26 is above the switching layer 1 2 (or stack of layers including a switching layer), and may be laterally surrounded by a faceted material 130, It is to be appreciated that the RAM element 570 may include the material layers described in association with RAM element 570 described in association with Figure 5. In an embodiment, in addition to, or in place of, the top nano-contact 126, a bottom nano-contact may be included at location 214, an example of which is described in association with Figures 2A-2E and Figure 4B. In another embodiment, in addition to, or in place of, the top nano-contact 126, a bottom nano- contact may be included at location 316, an example of which is described in association with Figures 3 A-3E and Figure 4C. In an embodiment, the RAM memory element 570 is an

STTRAM element, an RRAM^ element, or a CBRAM element.

[00110] The top nano-contact 126 may be electrically connected to a bit line 932. The lower electrode 572 may be coupled with a transistor 934, The transistor 934 may be coupled with a wordline 936 and a source line 938 in a manner that will be appreciated by those skilled in the art. The memoiy bit cell 900 may further include additional read and write circuitry (not shown), a sense amplifier (not shown), a bit line reference (not shown), and the like, as will be appreciated by those skilled in the art, for the operation of the memory bit cell 900. It is to be appreciated that a plurality of the memoiy bit cells 900 may be operably connected to one another to form a memory array, where the memory array can be incorporated into a non-volatile memory region of a substrate in common with a logic region. It is to be appreciated that the transistor 934 may be connected to the top nano-contact 126 or the lower electrode 572, although only the latter is shown. Likewise, bit line 932 may be connected to the lower electrode 572 or the top nano- contact 126, although only the latter is shown. [00111] Embodiments disclosed herein may be used to manufacture a wide variety of different types of integrated circuits and/or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, micro-controllers, and the like. In other embodiments, semiconductor memory may be manufactured. Moreover, the integrated circuits or other microelectronic devices may be used in a wide variety of electronic devices known in the arts. For example, in computer systems (e.g., desktop, laptop, server), cellular phones, personal electronics, etc. The integrated circuits may be coupled with a bus and other components in the systems. For example, a processor may be coupled by one or more buses to a memory, a chipset, etc. Each of the processor, the memory, and the chipset, may potentially be manufactured using the approaches disclosed herein.

[00112] Figure 10 illustrates a block diagram of an electronic system 1000, in accordance with an embodiment of the present invention. The electronic system 000 can correspond to, for example, a portable system, a computer system, a process control system, or any other system that utilizes a processor and an associated memory. The electronic system 1000 may include a microprocessor 1002 (having a processor 1004 and control unit 1006), a memory device 1008, and an input/output device 1010 (it is to be appreciated that the electronic system 1000 may have a plurality of processors, control units, memory device units and/or input/output devices in various embodiments). In one embodiment, the electronic system 1000 has a set of instructions that define operations which are to be performed on data by the processor 1004, as well as, other transactions between the processor 1004, the memory device 1008, and the input/output device 1010, The control unit 1006 coordinates the operations of the processor 1004, the memory device 1008 and the input/output device 1010 by cycling through a set of operations that cause instructions to be retrieved from the memory device 1008 and executed. The memory device 1008 can include a memory element as described in the present description, in an embodiment, the memory device 1008 is embedded in the microprocessor 1002, as depicted in Figure 10. In an embodiment, the processor 1004, or another component of electronic system 1000, includes an array of random access memory (RAM) devices, such as those described herein.

[00113] Figure 11 illustrates a computing device 1100 in accordance with one

embodiment of the invention. The computing device 1 100 houses a board 1 102. The board

1102 may include a number of components, including but not limited to a processor 1104 and at least one communication chip 1106. The processor 1104 is physically and electrically coupled to the board 1102. In some implementations the at least one communication chip 1 106 is also physically and electrically coupled to the board 1 102. In further implementations, the communication chip 1 106 is part of the processsor 1104. [00114] Depending on its applications, computing device 1 100 may include other components that may or may not be physically and electrically coupled to the board 1102. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

[00115] The communication chip 1106 enables wireless communications for the transfer of data to and from the computing device 1100. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc, that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 1 06 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.1 1 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, 1 1 Si . P · . EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 1100 may include a plurality of communication chips 1 106, For instance, a first communication chip 1 106 may be dedicated to shorter range wireless

communications such as Wi-Fi and Bluetooth and a second communication chip 1 106 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0011.6] The processor 1 104 of the computing device 1 100 includes an integrated circuit die packaged within the processor 1 104. In some implementations of embodiments of the invention, the integrated circuit die of the processor includes one or more arrays, such as random access memory (RAM) bit cells fabricated with a top or bottom electrode nano-contact, built in accordance with embodiments of the present invention. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

[00117] The com muni cation chip 1106 also includes an integrated circuit die packaged within the communication chip 1106. In accordance with another implementation of an embodiment of the invention, the integrated circuit die of the communication chip includes

?7 random access memory (RAM) bit cell s fabricated with a top or bottom electrode nano-contact, built in accordance with embodiments of the present inventi on.

[00118] hi further implementations, another component housed within the computing device 1 100 may contain a stand-alone integrated circuit memory die that includes one or more arrays, such as random access memory (RAM) bit cells fabricated with a top or bottom electrode nano-contact, built in accordance with embodiments of the present invention.

[00119] Ei various implementations, the computing device 1 100 may be a laptop, a netbook, a notebook, an ultrabook, a smariphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 1 100 may be any other electronic device that processes data.

[00120J Accordingly, one or more embodiments of the present invention relate generally to the fabrication of embedded microelectronic memory. The microelectronic memory may be non-volatile, where the memory can retain stored information even when not powered. One or more embodiments of the present invention relate to the fabrication of spin torque transfer random access memory (STTRAM), resistive random access memory (RRAM), or conductive bridge random access memory (CBRAM) memory arrays integrated into a logic processor. Such arrays may be used in an embedded non-volatile memory, either for its non-volatility, or as a replacement for embedded dynamic random access memory (eDRAM). For example, such an array may be used for I T- I X memory or 2T-1 X memory (X =^;: magneto-based switching device or resi stor-based switching device) at competitive cell sizes within a given technology node, [00121 ] Figure 12 illustrates an interposer 200 that includes one or more embodiments of the invention. The interposer 1200 is an intervening substrate used to bridge a first substrate 1202 to a second substrate 1204. The first substrate 1202 may be, for instance, an integrated circuit die. The second substrate 1204 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of an interposer 1200 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer 1200 may couple an integrated circuit die to a bail grid array (BGA) 1206 that can subsequently be coupled to the second substrate 1204. In some embodiments, the first and second substrates 1202/1204 are attached to opposing sides of the interposer 1200. In other embodiments, the first and second substrates 1202/1204 are attached to the same side of the interposer 1200. And in further embodiments, three or more substrates are interconnected by way of the interposer 1200. [00122] The interposer 1200 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as poiyimide. In further

implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group M-V and group IV materials.

[00123] The interposer may include metal interconnects 1208 and vias 1210, including but not limited to through-silicon vias (TSVs) 1212. The interposer 1200 may further include embedded devices 121.4, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 1200. In accordance with embodiments of the invention, apparatuses or processes disclosed herein may be used in the fabrication of interposer 1200.

[00124] Thus, embodiments of the present invention include self-aligned electrode nano- contacts for non-volatile random access memory (RAM) bit cells, and methods of fabricating electrode nano-contacts for non-volatile random access memory (RAM) bit cells.

[00125] Example embodiment 1 : A semiconductor structure includes a conductive electrode disposed above a substrate. A non-volatile random access memory (RAM) element is disposed above the conductive electrode. The non-volatile RAM element has an uppermost surface with a surface area. A conductive contact is disposed on and is electrically connected to the uppermost surface of the non-volatile RAM element. The conductive contact has a surface area less than the surface area of the uppermost surface of the non-volatile RAM element at an interface of the conductive contact and the uppermost surface of the non-volatile RAM element.

[00126] Example embodiment 2: The semiconductor substrate of example embodiment 1, wherein the conductive contact is laterally surrounded by and in contact with a faceted material disposed on the uppermost surface of the non-volatile RAM element.

[00127] Example embodiment 3 : The semiconductor structure of example embodiment 1 or 2, wherein the surface area of the uppermost surface of the non-volatile RAM element is approximately in the range of 4-100 square nanometers, and wherein the surface area of the conductive contact at the interface of the conductive contact and the uppermost surface of the non-volatile RAM element is approximately 1 square nanometer.

[00128] Example embodiment 4: The semiconductor structure of example embodiment 1, 2 or 3, further including a dielectric sidewall spacer laterally surrounding the non-volatile RAM element and the conductive contact, [00129] Example embodiment 5: The semiconductor structure of example embodiment 1, 2, 3 or 4, further including a second conductive electrode disposed on and electrically coupled to the conductive contact.

[00130] Example embodiment 6: The semiconductor structure of example embodiment 1, 2, 3, 4 or 5, further including a conductive contact layer disposed between the conductive electrode and the non-volatile RAM element.

[00131] Example embodiment 7: The semiconductor structure of example embodiment 1,

2, 3, 4, 5 or 6, wherein the non-volatile RAM element is a spin torque transfer random access memory (STTRAM) element.

[00132] Example embodiment 8: The semiconductor structure of example embodiment 1, 2, 3, 4, 5 or 6, wherein the non-volatile RAM element is a resistive random access memory (RRAM) element.

[00133] Example embodiment 9: The semiconductor structure of example embodiment 1,

2, 3, 4, 5 or 6, wherein the non-volatile RAM element is a conductive bridge random access memory (CBRAM) element.

[00134] Example embodiment 10: A semiconductor structure includes a conductive electrode disposed above a substrate. A conductive contact is disposed on and is electrically connected to the conductive electrode. A non-volatile random access memory (RAM) element is disposed on and is electrically connected to the conductive contact. The non-volatile RAM element has a lowermost surface with a surface area. The conductive contact has a surface area less than the surface area of the lowermost surface of the non-voiatiie RAM element at an interface of the conductive contact and the lowermost surface of the non-volatile RAM element.

[00135] Example embodiment 11 : The semiconductor substrate of example embodiment

10, wherein the conductive contact is laterally surrounded by but not in contact with a faceted material disposed on the conductive electrode.

[00136] Example embodiment 12: The semiconductor substrate of example embodiment 10 or 1 1, wherein the surface area of the lowennost surface of the non-volatile RAM element is approximately in the range of 4-100 square nanometers, and wherein the surface area of the conductive contact at the interface of the conductive contact and the lowermost surface of the non-volatile RAM element is approximately 1 square nanometer.

[00137] Example embodiment 13 : The semiconductor substrate of example embodiment 10, 1 1 or 12, further including a dielectric sidewall spacer laterally surrounding the non-volatile RAM element but not laterally surrounding the conductive contact. [00138] Example embodiment 14: The semiconductor substrate of example embodiment 10, 11, 12 or 13, further including a second conductive electrode disposed on and electrically coupled to an uppermost surface of the non-volatile RAM element.

[00139] Example embodiment 15: The semiconductor substrate of example embodiment 10, 1 1 , 12, 13 or 14, wherein the non-volatile RAM element is a spin torque transfer random access memory (STTRAM) element.

[00140] Example embodiment 16: The semiconductor substrate of example embodiment

10, 1 1, 12, 13 or 14, wherein the non-volatile RAM element is a resistive random access memory (RRAM) element.

[00141] Example embodiment 17: The semiconductor substrate of example embodiment 10, 11, 12, 13 or 14, wherein the non-volatile RAM element is a conductive bridge random access memory (CBRAM) element.

[00142] Example embodiment 18: A semiconductor structure includes a conductive electrode disposed above a substrate. A conductive contact is disposed on and is electrically connected to the conductive electrode. A non-volatile random access memory (RAM) element is disposed on and is electrically connected to the conductive contact. The non-volatile RAM element has a lowermost surface with a surface area surrounded by a perimeter. A portion of the conductive contact is within the perimeter and a portion of the conductive contact is outside of the perimeter at an interface of the conductive contact and the lowermost surface of the non- volatile AM: element. The portion of the conductive contact within the perimeter has a surface area less than the surface area of the lowermost surface of the non-volatile RAM element at the interface of the conductive contact and the lowermost surface of the non-volatile RAM element.

[00143] Example embodiment 19: The semiconductor substrate of example embodiment 18, wherein the conductive contact is laterally surrounded by and in contact with an insulating material disposed on the conductive electrode.

[00144] Example embodiment 20: The semiconductor substrate of example embodiment 18 or 19, wherein the surface area of the lowermost surface of the non-volatile RAM element is approximately in the range of 4-100 square nanometers, and wherein the surface area of the portion of the conductive contact within the perimeter at the interface of the conductive contact and the lowermost surface of the non-volatile RAM element is approximately I square nanometer.

[00145] Example embodiment 21 : The semiconductor substrate of example embodiment 18, 19 or 20, further including a dielectric sidewall spacer laterally surrounding the non-volatile RAM element but not laterally surrounding the conductive contact. [00146] Example embodiment 22: The semiconductor substrate of example embodiment 18, 19, 20 or 21, further including a second conductive electrode disposed on and electrically coupled to an uppermost surface of the non-volatile RAM element.

[00147] Example embodiment 23 : The semiconductor substrate of example embodiment

18, 19, 20, 21 or 22, wherein the non-volatile RAM element is a spin torque transfer random access memory (STTRAM) element,

[00148] Example embodiment 24: The semiconductor substrate of example embodiment

18, 19, 20, 21 or 22, wherein the non-volatile RAM element is a resistive random access memory (REAM) element.

[00149] Example embodiment 25: The semiconductor substrate of example embodiment 18, 19, 20, 21 or 22, wherein the non-volatile RAM element is a conductive bridge random access memory (CBRAM) element.

Claims

■LAIMS What is claimed

1. A semiconductor structure, comprising:

a conductive electrode disposed above a substrate;

a non-volatile random access memory (RAM) element disposed above the conductive

electrode, the non-volatile RAM element having an uppermost surface with a surface area; and

a conductive contact disposed on and electrically connected to the uppermost surface of the non-volatile RAM element, the conductive contact having a surface area less than the surface area of the uppermost surface of the non-volatile RAM element at an interface of the conductive contact and the uppermost surface of the non-volatile RAM element.

2. The semiconductor substrate of claim 1, wherein the conductive contact is laterally- surrounded by and in contact with a faceted material disposed on the uppermost surface of the non-volatile RAM element.

3. The semiconductor structure of claim 1 , wherein the surface area of the uppermost surface of the non-volatile RAM element is approximately in the range of 4-100 square nanometers, and wherein the surface area of the conductive contact at the interface of the conductive contact and the uppermost surface of the non-volatile RAM element is approximately 1 square nanometer.

4. The semiconductor structure of claim 1, further comprising:

a dielectric sidewall spacer laterally surrounding the non-volatile RAM element and the

conductive contact.

5. The semiconductor structure of claim 1 , further comprising:

a second conductive electrode disposed on and electrically coupled to the conductive contact.

6. The semiconductor structure of claim 1, further comprising:

a conductive contact layer disposed between the conductive electrode and the non-volatile RAM element.

7. The semiconductor structure of claim 1 , wherein the non-volatile RAM element is a spin torque transfer random access memory (STTRAM) element.

8. The semiconductor structure of claim 1 , wherein the non-volatile RAM element is a resistive random access memory (RRAM) element.

9. The semiconductor structure of claim 1 , wherein the non-volatile RAM element is a conductive bridge random access memory (CBRAM) element.

10. A semiconductor structure, comprising:

a conductive electrode disposed above a substrate;

a conductive contact disposed on and electrically connected to the conductive electrode; and a non-volatile random access memory (RAM) element disposed on and electrically connected to the conductive contact, the non-volatile AM: element having a lowermost surface with a surface area, wherein the conductive contact has a surface area less than the surface area of the lowermost surface of the non-volatile RAM element at an interface of the conductive contact and the lowermost surface of the non-volatile RAM element.

11. The semiconductor substrate of claim 10, wherein the conductive contact is laterally surrounded by but not in contact with a faceted material disposed on the conductive electrode.

12. The semiconductor structure of claim 10, wherein the surface area of the lowermost surface of the non-volatile RAM element is approximately in the range of 4-100 square nanometers, and wherein the surface area of the conductive contact at the interface of the conductive contact and the lowermost surface of the non-volatile RAM element is approximately 1 square nanometer.

13. The semiconductor structure of claim 10, further comprising:

a dielectric sidewall spacer laterally surrounding the non-volatile RAM element but not laterally surrounding the conductive contact.

14. The semiconductor structure of claim 10, further comprising:

a second conductive electrode disposed on and electrically coupled to an uppermost surface of the non-volatile RAM element.

15. The semiconductor structure of claim 10, wherein the non-volatile RAM element is a spin torque transfer random access memory (STTRAM) element.

16. The semiconductor structure of claim 10, wherein the non-volatile RAM element is a resistive random access memory (RRAM) element.

17. The semiconductor structure of claim 10, wherein the non-volatile RAM: element is a conductive bridge random access memory (CBRAM) element.

18. A semiconductor structure, comprising:

a conductive electrode disposed above a substrate;

a conductive contact disposed on and electrically connected to the conductive electrode; and a non-volatile random access memory (RAM) element disposed on and electrically connected to the conductive contact, the non-volatile RAM element having a lowermost surface with a surface area surrounded by a perimeter, wherein a portion of the conductive contact is within the perimeter and a portion of the conductive contact is outside of the perimeter at an interface of the conductive contact and the lowermost surface of the non- volatile RAM element, and wherein the portion of the conductive contact within the perimeter has a surface area less than the surface area of the lowermost surface of the non-volatile RAM element at the interface of the conductive contact and the lowermost surface of the non-voiatiie RAM element,

19. The semiconductor substrate of claim 18, wherein the conductive contact is laterally surrounded by and in contact with an insulating material disposed on the conductive electrode.

20. The semiconductor structure of claim 18, wherein the surface area of the lowermost surface of the non-volatile RAM element is approximately in the range of 4-100 square nanometers, and wherein the surface area of the portion of the conductive contact within the perimeter at the interface of the conductive contact and the lowermost surface of the non-volatile RAM element is approximately J square nanometer.

21. The semiconductor structure of claim 18, further comprising;

a dielectric sidewail spacer laterally surrounding the non-volatile RAM element but not laterally surrounding the conductive contact.

22. The semiconductor structure of claim 18, further comprising:

23. The semiconductor structure of claim 18, wherein the non-volatile RAM element is a spin torque transfer random access memory (STTRAM) element.

24. The semiconductor structure of claim 18, wherein the non-volatile RAM element is a resistive random access memory (RRAM) element.

25. The semiconductor structure of claim 18, wherein the non-volatile RAM element is a conductive bridge random access memory (CBRAM) element.