WO2018099079A1 - 阵列基板和显示装置 - Google Patents
阵列基板和显示装置 Download PDFInfo
- Publication number
- WO2018099079A1 WO2018099079A1 PCT/CN2017/091984 CN2017091984W WO2018099079A1 WO 2018099079 A1 WO2018099079 A1 WO 2018099079A1 CN 2017091984 W CN2017091984 W CN 2017091984W WO 2018099079 A1 WO2018099079 A1 WO 2018099079A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- conductive layer
- conductive
- passivation
- array substrate
- Prior art date
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 114
- 238000002161 passivation Methods 0.000 claims abstract description 124
- 239000000463 material Substances 0.000 claims description 28
- 229910004205 SiNX Inorganic materials 0.000 claims description 17
- 230000002093 peripheral effect Effects 0.000 claims description 16
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 11
- 125000006850 spacer group Chemical group 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 229910020286 SiOxNy Inorganic materials 0.000 claims description 7
- 230000000149 penetrating effect Effects 0.000 claims description 6
- 238000009751 slip forming Methods 0.000 abstract description 13
- 239000000853 adhesive Substances 0.000 abstract description 5
- 230000001070 adhesive effect Effects 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 240
- 238000000034 method Methods 0.000 description 16
- 239000011347 resin Substances 0.000 description 9
- 229920005989 resin Polymers 0.000 description 9
- 239000010408 film Substances 0.000 description 6
- 239000003292 glue Substances 0.000 description 6
- 239000004973 liquid crystal related substance Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 239000000203 mixture Substances 0.000 description 5
- 238000000059 patterning Methods 0.000 description 5
- 238000004544 sputter deposition Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 229910052750 molybdenum Inorganic materials 0.000 description 4
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910004140 HfO Inorganic materials 0.000 description 1
- 229910021193 La 2 O 3 Inorganic materials 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 229910010413 TiO 2 Inorganic materials 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 239000003570 air Substances 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009194 climbing Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- JAONJTDQXUSBGG-UHFFFAOYSA-N dialuminum;dizinc;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Al+3].[Al+3].[Zn+2].[Zn+2] JAONJTDQXUSBGG-UHFFFAOYSA-N 0.000 description 1
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 description 1
- 238000005363 electrowinning Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910001195 gallium oxide Inorganic materials 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 238000007641 inkjet printing Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- KYKLWYKWCAYAJY-UHFFFAOYSA-N oxotin;zinc Chemical compound [Zn].[Sn]=O KYKLWYKWCAYAJY-UHFFFAOYSA-N 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000002294 plasma sputter deposition Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229920001169 thermoplastic Polymers 0.000 description 1
- 239000004416 thermosoftening plastic Substances 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
- TYHJXGDMRRJCRY-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) tin(4+) Chemical compound [O-2].[Zn+2].[Sn+4].[In+3] TYHJXGDMRRJCRY-UHFFFAOYSA-N 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13452—Conductors connecting driver circuitry and terminals of panels
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136204—Arrangements to prevent high voltage or static electricity failures
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
- H01L21/441—Deposition of conductive or insulating materials for electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3192—Multilayer coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/124—Insulating layers formed between TFT elements and OLED elements
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/136295—Materials; Compositions; Manufacture processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Definitions
- At least one embodiment of the present disclosure is directed to an array substrate and a display device.
- the large-size oxide array substrate is currently in the stage of mass production and performance improvement, and the mass-produced oxide array substrate is basically an Etching Stop Layer (ESL) structure.
- ESL Etching Stop Layer
- the technical level of the etch barrier oxide array substrate has been mass-produced, due to the device reliability and reliability problems of the oxide array substrate, the current product has a complicated and complicated compensation method (for example, using optical compensation, internal electrical compensation, External electrical compensation, etc.) and life expectancy issues, and performance needs to be improved for harsh environments such as military products, high temperature, and humid environments.
- At least one embodiment of the present disclosure is directed to an array substrate and a display device to improve stability, reliability, and reliability of the array substrate.
- At least one embodiment of the present disclosure provides an array substrate including a substrate substrate and a first conductive layer and a second conductive layer sequentially disposed on the substrate, wherein the first conductive layer and the first conductive layer At least two passivation layers disposed continuously in a direction perpendicular to the substrate are disposed between the second conductive layers.
- An array substrate further includes a third conductive layer disposed between the base substrate and the first conductive layer, and the first conductive layer and The second conductive layer is electrically insulated.
- the first conductive layer includes a plurality of first conductive structures insulated from each other
- the second conductive layer includes a plurality of second conductive structures insulated from each other.
- the plurality of first conductive structures and the plurality of second conductive structures are in one-to-one correspondence, and the second conductive structures are electrically connected to the first conductive structures through via holes penetrating the at least two passivation layers.
- An array substrate further including a groove penetrating through at least one passivation layer of the at least two passivation layers adjacent to the plurality of second conductive structures, and at least one a passivation layer in contact with the plurality of first conductive structures is not penetrated by the recess, the recess including at least a spacer, the spacer being located adjacent in a direction parallel to the base substrate Between two second conductive structures.
- the groove further includes at least a connecting portion connecting the two adjacent spacers.
- a material of the passivation layer adjacent to the second conductive layer includes SiNx.
- three passivation layers are disposed between the first conductive layer and the second conductive layer, and the three passivation layers are sequentially disposed on the base substrate.
- a first passivation layer, a second passivation layer and a third passivation layer the first passivation layer material comprises SiOx
- the second passivation layer material comprises SiOxNy
- the third passivation layer material comprises SiNx.
- the array substrate includes a display area and a peripheral area disposed on at least one side of the display area, the first conductive layer, the at least two passivation layers, and the A second conductive layer is disposed in the peripheral region.
- an array substrate further includes a first electrode disposed in the same layer as the first conductive layer, and a second electrode disposed in the same layer as the second conductive layer.
- the at least two passivation layers are disposed between the first electrode and the second electrode, the first electrode includes a source and a drain, and the second electrode includes a pixel electrode or a common electrode.
- the array substrate includes a display area and a peripheral area disposed on at least one side of the display area, the first conductive layer, the at least two passivation layers, and the A second conductive layer is disposed in the display area.
- a material of the passivation layer adjacent to the second conductive layer includes SiNx.
- three passivation layers are disposed between the first conductive layer and the second conductive layer, and the three passivation layers are sequentially disposed on the base substrate.
- a first passivation layer, a second passivation layer and a third passivation layer the first passivation layer material comprising SiOx
- the second passivation layer material comprises SiOxNy
- the third passivation layer material comprises SiNx.
- At least one embodiment of the present disclosure also provides a display device including any of the array substrates described in the embodiments of the present disclosure.
- a display device further comprising a circuit board, wherein the circuit board is provided with a connection electrode layer, the connection electrode layer includes a plurality of connection electrodes insulated from each other, the plurality of connection electrodes and the The plurality of second conductive structures are in one-to-one correspondence, and the connection electrode is electrically connected to the second conductive structure through an anisotropic conductive paste.
- a portion of the anisotropic conductive paste located in the recess has a crack.
- Figure 1 is a scanning electron microscope (SEM) photograph of poor contact between ITO and resin
- FIG. 2 is a schematic diagram of breakdown of a bonding region
- FIG. 3 is a top plan view of an array substrate according to an embodiment of the present disclosure.
- Figure 4 is a cross-sectional view taken along line A-B of Figure 3;
- FIG. 5a is a top view of the bonding zone of FIG. 3 according to an embodiment of the present disclosure
- FIG. 5b is another top view of the bonding zone of FIG. 3 according to an embodiment of the present disclosure.
- 6a is a third conductive layer formed on a substrate according to an embodiment of the present disclosure.
- FIG. 6b is a schematic diagram of forming a gate insulating layer and an active layer on a third conductive layer according to an embodiment of the present disclosure
- FIG. 6c is an embodiment of the present disclosure, forming an etch stop layer on an active layer
- FIG. 6 is a first conductive layer formed on an etch barrier layer according to an embodiment of the present disclosure
- 6e is a schematic diagram of forming at least two passivation layers continuously formed in a direction perpendicular to a substrate substrate on a first conductive layer according to an embodiment of the present disclosure
- 6f is a second conductive layer formed on at least two passivation layers continuously formed in a direction perpendicular to a substrate substrate according to an embodiment of the present disclosure
- FIG. 7 is a schematic diagram of a display device (before bonding) according to an embodiment of the present disclosure.
- FIG. 8a is a cross-sectional view of a bonding area of a display device according to an embodiment of the present disclosure
- ACF adhesive has cracks
- FIG. 9 is a cross-sectional view of a display device (including a display area and a peripheral area) according to an embodiment of the present disclosure.
- a typical array substrate includes a display area and a peripheral area disposed on at least one side of the display area.
- indium tin oxide (ITO) as a pixel electrode can be electrically connected to the drain of the thin film transistor through a via penetrating through the resin layer, and the pixel electrode is provided on the resin layer to be in contact with the resin layer.
- ITO indium tin oxide
- the adhesion between the ITO and the resin layer is not good, and the problem of poor contact between the ITO and the resin layer is liable to occur.
- the adhesion between the ITO layer 01102 and the resin layer 0789 in Fig. 1 is not good.
- the connection between the connection electrode of the Chip On Film (COF) (driver IC) and the bonding area of the display panel passes through an anisotropic conductive film (ACF).
- ACF anisotropic conductive film
- At least one embodiment of the present disclosure provides an array substrate including a substrate substrate and a first conductive layer and a second conductive layer sequentially disposed on the base substrate, and at least two are disposed between the first conductive layer and the second conductive layer Passivation layers are continuously disposed (continuously formed) in a direction perpendicular to the substrate.
- the array substrate has the beneficial effects of at least one of the following.
- the stability, reliability, and reliability of the array substrate can be improved. It can extend the life of array substrates and broaden the field of use of array substrates. For example, the life and application range of the array substrate under severe conditions such as high temperature and high humidity can be improved.
- the present embodiment provides an array substrate 10, as shown in FIG. 3, including a display area 01 and a peripheral area 02 disposed on at least one side of the display area 01.
- FIG. 3 also shows a bonding area located in the peripheral area 02 ( Bonding region)021.
- the bonding zone 021 can be configured to connect to an external circuit.
- the bonding zone 021 can be configured to be coupled to a driver IC, for example, as a flexible circuit board lead-out zone.
- the array substrate includes a base substrate 101 and a first conductive layer 106 and a second conductive layer 110 sequentially disposed on the base substrate 101 between the first conductive layer 106 and the second conductive layer 110.
- At least two passivation layers continuously formed in a direction perpendicular to the base substrate 101 are provided.
- the first conductive layer 106, the at least two passivation layers, and the second conductive layer 110 are disposed in the peripheral region 02.
- three passivation layers continuously formed in the direction perpendicular to the base substrate 101 are disposed between the first conductive layer 106 and the second conductive layer 110 as an example.
- the three passivation layers include a first passivation layer 107, a second passivation layer 108, and a third passivation layer 109 which are sequentially disposed on the base substrate 101.
- the array substrate 10 provided in this embodiment has at least the following beneficial effects: by providing a continuously formed passivation layer, it is convenient to adjust the composition of the passivation layer so that the second conductive layer and the passivation layer in contact therewith are better. The adhesion can make the connection performance between the layers more stable.
- the first conductive layer 106 includes a plurality of first conductive structures 1060 insulated from each other
- the second conductive layer 110 includes a plurality of second conductive structures 1101 insulated from each other, a plurality of first conductive structures 1060 and
- the plurality of second conductive structures 1101 are in one-to-one correspondence, and the second conductive structures 1101 pass through vias 789 extending through at least two passivation layers (not shown in FIG. 4, see FIG. 5a, FIG. 5b, FIG. 6f, and/or 9) Electrically coupled to the first conductive structure 1060 (not shown in FIG. 4, see the peripheral region 02 of FIG. 6f and/or FIG. 9).
- the array substrate further includes a third conductive layer 102 disposed between the base substrate 101 and the first conductive layer 106, and with the first conductive layer 106 and The two conductive layers 110 are electrically insulated.
- the array substrate 10 provided in this embodiment has at least the following beneficial effects: by providing a continuously formed passivation layer, it is also convenient to form a groove in the passivation layer to improve the height difference of the non-electrical connection region of the ACF glue, so that The anisotropic conductive paste in the groove deforms or breaks, thereby increasing the anisotropic conductivity of the anisotropic conductive paste to reduce short circuit and/or open circuit of the display screen.
- the array substrate further includes a groove 115 penetrating at least one passivation layer of the at least two passivation layers adjacent to the plurality of second conductive structures 1101, and at least The passivation layer in contact with the plurality of first conductive structures 1060 is not penetrated by the recess 115, and the recess 115 includes at least the spacer 1151, and in the direction parallel to the base substrate 101, the spacer 1151 is located adjacent to the second two Between the conductive structures 1101.
- the groove 115 includes a spacer 1151 as an example for description.
- the arrangement of the grooves 115 can improve the height difference of the COF non-electrical connection region, so that The anisotropic conductive paste in the groove is broken to increase the anisotropic conductivity of the anisotropic conductive paste to reduce short circuit and/or open circuit of the display. Thereby, the stability, reliability, and reliability of the array substrate can be improved. It can extend the life of array substrates and broaden the field of use of array substrates.
- the groove 115 may further include at least a connecting portion 1152 connecting the adjacent two spaced portions 1151.
- the connection portion 1152 is disposed such that the ACF glue has a height difference in more groove regions, so that the ACF glue can be deformed or broken at the groove so that the adjacent two second conductive structures 1101 can be better. They are insulated from each other (not electrically connected) to avoid short circuits.
- the material of the passivation layer adjacent to the second conductive layer 110 includes SiNx.
- the SiNx has good adhesion, increases the adhesion of the passivation layer and the material of the second conductive layer 110, thereby improving the connection performance of the conductive material and the connection thereof, and improving the stability, reliability and reliability of the array substrate. .
- the first passivation layer 107 material comprises SiOx
- the second passivation layer 108 material comprises SiOxNy
- the third passivation layer 109 material comprises SiNx.
- the above description is made by taking the first conductive layer 106, at least two passivation layers, and the second conductive layer 110 in the peripheral region 02 as an example.
- the embodiment is not limited to this.
- the display area 01 further includes a first electrode disposed in the same layer as the first conductive layer 106, and a second electrode 1102 disposed in the same layer as the second conductive layer 110, the first electrode and the second electrode.
- At least two passivation layers are disposed between the electrodes
- the first electrode includes a source 1062 and a drain 1061
- the second electrode may be a pixel electrode 1102 or a common electrode.
- the pixel electrode 1102 can be electrically connected to the drain 1061 through at least two passivation layers disposed between the first conductive layer 106 and the second conductive layer 110.
- the display area 01 further includes a gate 1021 disposed in the same layer as the third conductive layer 102.
- the third conductive layer 102 is a gate layer
- the gate layer of the display region includes a gate electrode 1021
- the third conductive structure 1020 of the peripheral region may be formed in the same layer as the gate electrode 1021.
- a gate insulating layer 103 is formed over the third conductive layer 102.
- an active layer 104 and an etch stop layer 105 disposed on the active layer 104.
- An additional number of at least two passivation layers may be disposed between the first conductive layer 106 and the second conductive layer 110, which is not limited in this embodiment.
- the embodiment further provides a method for manufacturing an array substrate, and the method for manufacturing the array substrate includes the following steps.
- Step 1 Form a third conductive layer 102 on the base substrate.
- forming the third conductive layer 102 on the base substrate includes: depositing a metal layer on a base substrate of glass, plastic (polyimide), silicon, or the like by using a sputtering method, for example, the metal layer material may be Mo, a metal or an alloy such as Al/N d , Al/N d /Mo, Mo/Al/N d /Mo, Au/Ti, Pt/Ti, and photolithographically etched to pattern the metal layer to obtain a third conductive layer 102.
- the third conductive layer 102 includes a gate 1021 (third conductive structure) of the display region 01 and a third conductive structure 1020 of the peripheral region 02, as shown in FIG. 6a.
- Step 2 Form the gate insulating layer 103 and the active layer 104 as shown in FIG. 6b.
- the gate insulating layer 103 may be deposited by atmospheric pressure chemical vapor deposition, low pressure chemical vapor deposition, plasma assisted chemical vapor deposition, sputtering, or the like to deposit SiOx, SiNx, SiON, Al 2 O 3 , HfO 2 , A single or multiple gate insulating layer such as ZrO 2 , TiO 2 , , Y 2 O 3 , La 2 O 3 , Ta 2 O 5 or the like.
- the active layer 104 can be prepared by sputtering, sol-gel, vacuum evaporation, spray coating, inkjet printing, etc., such as indium gallium zinc oxide (IGZO), zinc oxynitride (ZnON), indium tin zinc oxide ( ITZO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium gallium oxide (IGO), aluminum zinc oxide (AZTO), and the like.
- IGZO indium gallium zinc oxide
- ZnON zinc oxynitride
- ITZO indium tin zinc oxide
- ZTO zinc tin oxide
- ZIO zinc indium oxide
- IGO indium gallium oxide
- AZTO aluminum zinc oxide
- Step 3 Form an etch stop layer 105 as shown in FIG. 6c.
- atomic layer deposition, atmospheric pressure chemical vapor deposition, low pressure chemical vapor deposition, plasma assisted chemical vapor deposition, sputtering, sol-gel, etc. deposition of SiOx, SiNx, SiON, Al 2 O 3 , A single layer or a multilayer structure such as TEOS is patterned and an etch stop layer 105 is obtained.
- Step 4 forming a first conductive layer 106, as shown in Figure 6d.
- a metal or alloy layer such as Mo, AlN d , AlN d /Mo, Mo/AlN d /Mo, Au/Ti, Pt/Ti may be deposited by sputtering, and photolithographically etched to pattern the thin film layer.
- a first conductive layer 106 is obtained.
- the first conductive layer 106 can include a source 10662 and a drain 1061 and a first conductive structure 1060 of the perimeter region 02.
- Step 5 Form at least two passivation layers continuously formed in a direction perpendicular to the substrate, as shown in FIG. 6e.
- the passivation layer can be grown by thermal growth, atmospheric pressure chemical vapor deposition, low pressure chemical vapor deposition, plasma assisted chemical vapor deposition, sputtering, spin coating, and the like.
- a multilayer passivation layer composed of one or more materials of SiOx, SiNx, SiOxNy, Al 2 O 3 , a resin, or a different composition may be prepared.
- Step 6 Form a contact hole and/or a recess and form a second conductive layer as shown in FIG. 6f.
- the passivation layer can be patterned, the contact holes and/or the grooves can be etched, and a transparent conductive material, such as ITO, can be sputtered for electro-extraction to form a second conductive layer, and the material of the second conductive layer is not limited to ITO. .
- Step 7 Annealing treatment.
- the product may be annealed in a vacuum, nitrogen, air or oxygen atmosphere at an annealing temperature between 120 and 450 ° C and an annealing time of between 0.5 and 3 hours.
- the first conductive layer 106, the at least two passivation layers, and the second conductive layer 110 are disposed only in the display region 01. Reference may be made to the display area 01 on the left side of Fig. 6f.
- the first conductive layer 106 includes a plurality of first conductive structures 1060 insulated from each other, and the first conductive structures 1060 may be the source 1062 or the drain 1061.
- the second conductive layer 110 includes a plurality of second conductive structures 1102 insulated from each other, and the second conductive structures 1102 may be pixel electrodes.
- the second conductive structure 1102 can be electrically connected to the first conductive structure 1060 (eg, to the drain 1061) through vias penetrating through the at least two passivation layers.
- the second conductive structure 1102 can also be a common electrode.
- the second conductive structure 1102 is electrically insulated from the first conductive structure.
- the material of the passivation layer adjacent to the second conductive layer 110 includes SiNx.
- SiNx has good adhesion, thereby improving the connection performance of the conductive material and its connection, and improving the stability, reliability and reliability of the array substrate.
- three passivation layers are disposed between the first conductive layer 106 and the second conductive layer 110, and the passivation layer adjacent to the second conductive layer 110 refers to the third passivation layer 109.
- the three passivation layers include a first passivation layer 107, a second passivation layer 108, and a third passivation layer 109, which are sequentially disposed on the base substrate 101, and the first passivation
- the layer 107 material comprises SiOx
- the second passivation layer 108 material comprises SiOxNy
- the third passivation layer 109 material comprises SiNx.
- the embodiment provides a display device including any of the array substrates described in Embodiments 1 to 2.
- the display device includes a liquid crystal display device or an organic light emitting diode display device, but is not limited thereto.
- the display device may include a television, a digital camera, a mobile phone, a watch, a tablet, a note This computer, navigation device and other display devices.
- ADS Advanced Super Dimension Switching
- HADS High aperture Advanced super Dimensional Switching
- Twisted twisted nematic display
- Various modes, such as Nematic, TN) and Vertical Alignment (VA) are not limited in this embodiment.
- the array substrate 10 and the opposite substrate 20 may be paired with a liquid crystal layer (a liquid crystal layer is not shown) formed therebetween to expose the bonding region 021.
- the display device further includes a circuit board 201.
- the circuit board 201 is provided with a connection electrode layer 202.
- the connection electrode layer 202 includes a plurality of connection electrodes 2020 insulated from each other, and a plurality of connection electrodes 2020 and a plurality of The two conductive structures 1101 are in one-to-one correspondence, and the connection electrode 2020 is electrically connected to the second conductive structure 1101 through the anisotropic conductive paste 301.
- the circuit board 201 can be a flexible circuit board on which a chip can be mounted, that is, a COF is formed, but is not limited thereto.
- the portion of the anisotropic conductive paste 301 between the connection electrode 2020 and the second conductive structure 1101 corresponding to the connection electrode 2020 is an electrical connection region 3011, and the anisotropic conductive paste 301 is adjacent to each other.
- a portion between the two connection electrodes 2020 is a non-electrical connection region 3012.
- the anisotropic conductive paste 301 is provided with a plurality of conductive particles, and each of the conductive particles may be wrapped with an insulating layer, so that the electrical connection region 3011 and the non-electrical connection region 3012 may be formed after the heat pressing.
- the anisotropic conductive paste 301 of the electrical connection region 3011 is electrically conductive in its thickness direction and non-conductive in a direction parallel to its surface.
- At least two passivation layers continuously formed in a direction perpendicular to the substrate 101 are disposed between the first conductive layer 106 and the second conductive layer 110, thereby improving the non-electrical connection of the second conductive layer 110 with the COF.
- the height difference of the regions, the arrangement of the grooves 115 forms a large slope angle at a position where electrical connection is not required, and thus, as shown in FIG. 8b, the portion of the anisotropic conductive paste 301 located in the groove 115 can be made. Break to increase the resistance of the non-contact zone. That is, the anisotropic conductive paste 301 has a crack 0301 in a portion located inside the groove 115. For example, as shown in FIG.
- a crack 0301 may be formed at the edge of the groove, for example, the crack 0301 may be at the climbing position of the groove 115 (the first passivation layer 107 in the groove is adjacent to the second passivation layer 108) The position is formed, but is not limited to this.
- a crack 0301 may also be formed at the second passivation layer 108 and the third passivation layer 109 of the recess 115.
- thermoplastic for example, a thermocompression temperature of 230 degrees or less
- suitable ductility in the concave Deformation or fracture at the groove (step) improves the anisotropic conductivity of the ACF glue non-electrical connection region 3012, improves the electrical connection of the COF, and reduces short circuit and open circuit of the display screen.
- the array substrate can be fabricated without a new mask, which is advantageous for cost control.
- Fig. 9 is a schematic view showing a display device formed using the display substrate shown in Fig. 6f.
- the embodiment of the present disclosure is described by taking the electrical connection of the COF and the bonding area as an example.
- the driving IC is not limited to the COF, and may be in other forms, which is not limited by the embodiment of the present disclosure.
- “same layer” refers to a layer structure formed by forming a film layer for forming a specific pattern by the same film forming process, and then forming the pattern by one patterning process using the same mask.
- a patterning process may include multiple exposure, development, or etching processes, and the particular pattern in the resulting layer structure may be continuous or discontinuous, and these particular patterns may also be at different heights. Or have different thicknesses.
- the patterning or patterning process may include only a photolithography process, or a photolithography process and an etching process, or may include other processes for forming a predetermined pattern, such as printing, inkjet, and the like.
- the photolithography process refers to a process including film formation, exposure, development, and the like, and forms a pattern by using a photoresist, a mask, an exposure machine, or the like.
- the corresponding patterning process can be selected in accordance with the structure formed in the embodiments of the present disclosure.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Nonlinear Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Mathematical Physics (AREA)
- Manufacturing & Machinery (AREA)
- Optics & Photonics (AREA)
- Ceramic Engineering (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Electroluminescent Light Sources (AREA)
Abstract
Description
Claims (15)
- 一种阵列基板,包括衬底基板和依次设置在所述衬底基板上的第一导电层和第二导电层,其中,在所述第一导电层和所述第二导电层之间设置至少两个在垂直于所述衬底基板的方向上连续设置的钝化层。
- 根据权利要求1所述的阵列基板,还包括第三导电层,其中,所述第三导电层设置在所述衬底基板和所述第一导电层之间,并与所述第一导电层和所述第二导电层电绝缘。
- 根据权利要求1或2所述的阵列基板,其中,所述第一导电层包括多个彼此绝缘的第一导电结构,所述第二导电层包括多个彼此绝缘的第二导电结构,所述多个第一导电结构和所述多个第二导电结构一一对应,所述第二导电结构通过贯穿所述至少两个钝化层的过孔与所述第一导电结构电连接。
- 根据权利要求3所述的阵列基板,还包括凹槽,其中,所述凹槽贯穿所述至少两个钝化层中靠近所述多个第二导电结构的至少一个钝化层,并且,至少一个与所述多个第一导电结构接触的钝化层未被所述凹槽贯穿,所述凹槽至少包括间隔部,在平行于所述衬底基板的方向上,所述间隔部位于相邻两个第二导电结构之间。
- 根据权利要求4所述的阵列基板,其中,所述凹槽至少还包括连接部,所述连接部连接相邻两个所述间隔部。
- 根据权利要求1-5任一项所述的阵列基板,其中,靠近所述第二导电层的钝化层的材质包括SiNx。
- 根据权利要求1-6任一项所述的阵列基板,其中,所述第一导电层和所述第二导电层之间设置三个钝化层,所述三个钝化层包括依次设置在所述衬底基板上的第一钝化层、第二钝化层和第三钝化层,所述第一钝化层材质包括SiOx,所述第二钝化层材质包括SiOxNy,所述第三钝化层材质包括SiNx。
- 根据权利要求1-7任一项所述的阵列基板,其中,所述阵列基板包括显示区和设置在所述显示区至少一侧的周边区,所述第一导电层、所述至少两个钝化层和所述第二导电层设置在所述周边区。
- 根据权利要求8所述的阵列基板,其中,在所述显示区还包括与所述 第一导电层同层设置的第一电极,以及与所述第二导电层同层设置的第二电极,所述第一电极和所述第二电极之间设置所述至少两个钝化层,所述第一电极包括源极和漏极,所述第二电极包括像素电极或公共电极。
- 根据权利要求1所述的阵列基板,其中,所述阵列基板包括显示区和设置在所述显示区至少一侧的周边区,所述第一导电层、所述至少两个钝化层和所述第二导电层设置在所述显示区。
- 根据权利要求10所述的阵列基板,其中,靠近所述第二导电层的钝化层的材质包括SiNx。
- 根据权利要求10所述的阵列基板,其中,所述第一导电层和所述第二导电层之间设置三个钝化层,所述三个钝化层包括依次设置在所述衬底基板上的第一钝化层、第二钝化层和第三钝化层,所述第一钝化层材质包括SiOx,所述第二钝化层材质包括SiOxNy,所述第三钝化层材质包括SiNx。
- 一种显示装置,包括权利要求1-12任一项所述的阵列基板。
- 根据权利要求13所述的显示装置,还包括电路板,其中,所述电路板上设置有连接电极层,所述连接电极层包括多个彼此绝缘的连接电极,所述多个连接电极与所述多个第二导电结构一一对应,所述连接电极通过各向异性导电胶与所述第二导电结构电连接。
- 根据权利要求14所述的显示装置,其中,所述各向异性导电胶位于所述凹槽内的部分具有裂纹。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/743,597 US20190027509A1 (en) | 2016-12-02 | 2017-07-06 | Array Substrate and Display Device |
US16/721,109 US10804298B2 (en) | 2016-12-02 | 2019-12-19 | Array substrate and display device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201611095901.9 | 2016-12-02 | ||
CN201611095901.9A CN106449666B (zh) | 2016-12-02 | 2016-12-02 | 阵列基板和显示装置 |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/743,597 A-371-Of-International US20190027509A1 (en) | 2016-12-02 | 2017-07-06 | Array Substrate and Display Device |
US16/721,109 Division US10804298B2 (en) | 2016-12-02 | 2019-12-19 | Array substrate and display device |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2018099079A1 true WO2018099079A1 (zh) | 2018-06-07 |
Family
ID=58223719
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/CN2017/091984 WO2018099079A1 (zh) | 2016-12-02 | 2017-07-06 | 阵列基板和显示装置 |
Country Status (3)
Country | Link |
---|---|
US (2) | US20190027509A1 (zh) |
CN (1) | CN106449666B (zh) |
WO (1) | WO2018099079A1 (zh) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106449666B (zh) | 2016-12-02 | 2018-04-03 | 京东方科技集团股份有限公司 | 阵列基板和显示装置 |
CN108389868A (zh) * | 2018-02-26 | 2018-08-10 | 武汉华星光电技术有限公司 | 阵列基板及显示面板 |
CN108732813A (zh) * | 2018-05-29 | 2018-11-02 | 深圳市华星光电技术有限公司 | 液晶面板、液晶显示器及电子设备 |
CN108987439A (zh) * | 2018-06-21 | 2018-12-11 | 武汉华星光电半导体显示技术有限公司 | 显示面板和显示装置 |
CN108549505A (zh) * | 2018-07-18 | 2018-09-18 | 业成科技(成都)有限公司 | 电子***及其超声波触控装置 |
CN110854171B (zh) * | 2019-11-21 | 2022-09-13 | 京东方科技集团股份有限公司 | 一种显示基板及其制备方法、显示装置 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102629588A (zh) * | 2011-12-13 | 2012-08-08 | 京东方科技集团股份有限公司 | 阵列基板的制造方法 |
CN103809340A (zh) * | 2012-11-13 | 2014-05-21 | 乐金显示有限公司 | 边缘场切换模式液晶显示装置的阵列基板及其制造方法 |
CN105097548A (zh) * | 2015-06-23 | 2015-11-25 | 京东方科技集团股份有限公司 | 氧化物薄膜晶体管、阵列基板及各自制备方法、显示装置 |
CN106449666A (zh) * | 2016-12-02 | 2017-02-22 | 京东方科技集团股份有限公司 | 阵列基板和显示装置 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3139549B2 (ja) * | 1999-01-29 | 2001-03-05 | 日本電気株式会社 | アクティブマトリクス型液晶表示装置 |
JP3511172B2 (ja) * | 2001-03-30 | 2004-03-29 | 富士通カンタムデバイス株式会社 | 高周波半導体装置 |
KR100551046B1 (ko) * | 2003-08-28 | 2006-02-09 | 삼성에스디아이 주식회사 | 유기 이엘 소자 |
KR102004398B1 (ko) * | 2012-07-24 | 2019-07-29 | 삼성디스플레이 주식회사 | 표시 장치 및 그 제조 방법 |
WO2014054569A1 (ja) * | 2012-10-03 | 2014-04-10 | シャープ株式会社 | 半導体装置及び表示装置 |
KR101853032B1 (ko) * | 2016-07-21 | 2018-06-05 | 엘지디스플레이 주식회사 | 표시장치 |
KR101951939B1 (ko) * | 2016-08-26 | 2019-02-25 | 엘지디스플레이 주식회사 | 표시장치 |
-
2016
- 2016-12-02 CN CN201611095901.9A patent/CN106449666B/zh active Active
-
2017
- 2017-07-06 WO PCT/CN2017/091984 patent/WO2018099079A1/zh active Application Filing
- 2017-07-06 US US15/743,597 patent/US20190027509A1/en not_active Abandoned
-
2019
- 2019-12-19 US US16/721,109 patent/US10804298B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102629588A (zh) * | 2011-12-13 | 2012-08-08 | 京东方科技集团股份有限公司 | 阵列基板的制造方法 |
CN103809340A (zh) * | 2012-11-13 | 2014-05-21 | 乐金显示有限公司 | 边缘场切换模式液晶显示装置的阵列基板及其制造方法 |
CN105097548A (zh) * | 2015-06-23 | 2015-11-25 | 京东方科技集团股份有限公司 | 氧化物薄膜晶体管、阵列基板及各自制备方法、显示装置 |
CN106449666A (zh) * | 2016-12-02 | 2017-02-22 | 京东方科技集团股份有限公司 | 阵列基板和显示装置 |
Also Published As
Publication number | Publication date |
---|---|
US20190027509A1 (en) | 2019-01-24 |
CN106449666A (zh) | 2017-02-22 |
US10804298B2 (en) | 2020-10-13 |
US20200127018A1 (en) | 2020-04-23 |
CN106449666B (zh) | 2018-04-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2018099079A1 (zh) | 阵列基板和显示装置 | |
US11251410B2 (en) | Flexible display substrate and method for manufacturing the same | |
US12010881B2 (en) | Display device | |
WO2019148909A1 (zh) | 柔性显示面板及其制备方法、显示装置 | |
TWI576749B (zh) | 可撓性顯示裝置、感測其撓曲之方法及其操作方法 | |
WO2018214727A1 (zh) | 柔性显示基板及其制作方法、显示装置 | |
US9899428B2 (en) | Display device having terminal electrode including stepped surface | |
WO2016176886A1 (zh) | 柔性oled及其制作方法 | |
CN102881839B (zh) | 有机发光二极管、触摸显示装置及其制造方法 | |
US11251257B2 (en) | Manufacturing method of display panel having pad comprising embedded part and protruded part | |
WO2015027569A1 (zh) | 阵列基板及其制作方法、显示装置 | |
WO2016150073A1 (zh) | 薄膜晶体管和阵列基板及其制作方法、显示装置 | |
US9496284B2 (en) | Display panel and display apparatus including the same | |
US10347660B2 (en) | Array substrate and manufacturing method thereof | |
WO2018171268A1 (zh) | 基板及其制备方法、显示面板和显示装置 | |
WO2015062265A1 (zh) | 像素结构、阵列基板、显示装置及像素结构的制造方法 | |
WO2020088368A1 (zh) | 薄膜晶体管及其制作方法、阵列基板、显示装置 | |
US9165954B2 (en) | Array substrate and method for manufacturing the same, and display device | |
US20220238819A1 (en) | Display Substrate, Preparation Method thereof, and Display Apparatus | |
WO2015192538A1 (zh) | 基板及其制作方法、显示装置 | |
CN106128960B (zh) | 薄膜晶体管、阵列基板及各自制备方法、显示装置 | |
CN110690256A (zh) | 一种柔性tft基板及其制造方法 | |
US9691836B2 (en) | Pixel unit, array substrate, display device and method for manufacturing the same including MoW/Cu/MoW conductive line | |
WO2019041934A1 (zh) | 电极结构及其制作方法、薄膜晶体管和阵列基板 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 17875813 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 17875813 Country of ref document: EP Kind code of ref document: A1 |
|
32PN | Ep: public notification in the ep bulletin as address of the adressee cannot be established |
Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 09.12.2019) |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 17875813 Country of ref document: EP Kind code of ref document: A1 |