WO2018077233A1 - Procédé et dispositif de transmission de code de contrôle de parité à faible densité - Google Patents

Procédé et dispositif de transmission de code de contrôle de parité à faible densité Download PDF

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Publication number
WO2018077233A1
WO2018077233A1 PCT/CN2017/108005 CN2017108005W WO2018077233A1 WO 2018077233 A1 WO2018077233 A1 WO 2018077233A1 CN 2017108005 W CN2017108005 W CN 2017108005W WO 2018077233 A1 WO2018077233 A1 WO 2018077233A1
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ldpc
bit
interleaver
sequence
order
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PCT/CN2017/108005
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English (en)
Chinese (zh)
Inventor
穆锡金
王加庆
白宝明
孙韶辉
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电信科学技术研究院
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Priority claimed from CN201710015031.8A external-priority patent/CN108011691B/zh
Application filed by 电信科学技术研究院 filed Critical 电信科学技术研究院
Priority to US16/345,626 priority Critical patent/US10833803B2/en
Priority to EP17864561.0A priority patent/EP3534554A4/fr
Publication of WO2018077233A1 publication Critical patent/WO2018077233A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received

Definitions

  • the present application relates to the field of communications technologies, and in particular, to a method and an apparatus for transmitting a low density parity check code.
  • the current channel coding parameters of the 3rd Generation Partnership Project (3GPP) for the 5G Mobile Broadband Enhanced (eMBB) scenario are:
  • Incremental Redundancy Low Density Parity Check Code has the advantages of excellent performance, wide code rate coverage, high multiplexing, easy hardware implementation, and direct coding with a check matrix. It is one of the 5G candidate codes and has been discussed and studied in depth in the 3GPP standardization conference.
  • the check matrix structure of the incremental redundant LDPC is as shown in FIG. 1. Cyclic replacement of small matrices And unit matrix
  • the highest code rate (such as the highest code rate R1 portion in FIG. 1) is a quasi-cyclic irregular repeat-accumulate LDPC codes (QC-IRA LDPC codes) having a double diagonal structure.
  • the parity bit is increased by increasing the redundancy, and then the low code rate LDPC can be obtained (such as the low code rate R2, R3, R4, and R5 parts in FIG. 1).
  • the transmission scheme of the incremental redundant LDPC is as shown in FIG. 2.
  • the information sequence input by the encoder is encoded by an incremental redundancy LDPC encoder, and then the LDPC codeword is output, and then modulated, channel-transmitted, and demodulated.
  • the demodulated result is decoded by the decoder for incremental redundant LDPC decoding. After the output.
  • the incremental redundancy LDPC has the advantages of excellent performance, wide code length code coverage, high multiplexing degree, easy hardware implementation, and can be directly encoded by the check matrix. It is one of the candidate codes of 5G. According to the above incremental redundant LDPC check matrix structure, it can be seen that the code belongs to the system code, and the information bits and the check bits are separated. This structure is susceptible to burst errors (such as the continuous fading of multiple symbols in the associated fading channel) and is less resistant to burst errors.
  • the embodiment of the present application provides a method and a device for transmitting a low-density parity check code, which are used to improve the anti-burst error capability of the LDPC transmission.
  • the interleaver changes the bit stream order of the LDPC according to a preset rule, and outputs the LDPC after changing the order of the bit stream to the modulator;
  • the modulator modulates the LDPC after changing the bit stream order and transmits it to the receiving end through the channel.
  • the interleaver changes the bit stream order of the LDPC according to a preset rule, and outputs the LDPC after changing the order of the bit stream to the modulator; the modulator modulates the LDPC after changing the order of the bit stream and transmits it to the channel through the channel.
  • the receiving end can reduce the probability of burst errors in consecutive bit streams during LDPC transmission, thereby improving the anti-burst error capability of LDPC transmission.
  • the method further includes: the encoder encodes the LDPC, and the encoded LDPC is input. Out to the interleaver;
  • the interleaver changes the bitstream order of the LDPC according to a preset rule, and outputs the LDPC after changing the sequence of the bitstream to the modulator, specifically:
  • the interleaver changes the bit stream order of the encoded LDPC according to a preset rule, and outputs the LDPC after changing the order of the bit stream to the modulator.
  • the LDPC is specifically an incremental redundancy LDPC.
  • the interleaver comprises an N/C row block interleaver, each row comprising a C column block interleaver, wherein the N is a total codeword number of the LDPC, and the LDPC comprises an N/C group codeword, each The group code word includes C bit code words;
  • the interleaver changes the bitstream sequence of the LDPC according to a preset rule, and outputs the LDPC after changing the sequence of the bitstream to the modulator, specifically including:
  • the interleaver sequentially receives each group of codewords of the LDPC in the order of rows, and sequentially outputs the codewords in the order of the columns, and obtains the LDPCs after changing the order of the bitstreams and outputs them to the modulator.
  • the interleaver is configured to change a bitstream order of an LDPC.
  • the code check matrix of the LDPC has one of the following structures or a deformed structure based on one of the following structures: a lower triangle, a lower triangular, an upper triangular, and a quasi-upper triangular.
  • the interleaver changes the bitstream sequence of the LDPC according to a preset rule, and specifically includes:
  • the interleaver changes a codeword of a first partial bit in the LDPC to a preset bit position, and performs a random bit position change on a codeword of a second partial bit in the LDPC; wherein the preset bit position It is the bit position agreed with the receiving end in advance.
  • the codeword of the first partial bit includes a codeword of a punctured bit.
  • the demodulator receives the LDPC through the channel, and demodulates the LDPC, where the LDPC is an LDPC after the bitstream sequence is changed according to a preset rule by the interleaver;
  • the deinterleaver restores the bit stream order to the demodulated LDPC according to a preset rule.
  • the method further includes: the decoder decoding the LDPC after the bit stream sequence is restored.
  • the LDPC is specifically an incremental redundancy LDPC.
  • the deinterleaver comprises an N/C row block deinterleaver, each row comprising a C column block deinterleaver, wherein the N is a total codeword number of the LDPC, and the LDPC comprises an N/C group code Word, each group of code words includes C bit code words;
  • the deinterleaver restores the bitstream sequence to the demodulated LDPC according to a preset rule, and specifically includes:
  • the deinterleaver sequentially receives each set of codewords of the demodulated LDPC in the order of the columns, and sequentially outputs the codewords in the order of the rows, and obtains the LDPCs after the order of the restored bitstreams and outputs them to the decoder.
  • the deinterleaver is configured to recover a bitstream sequence of a demodulated LDPC.
  • the code check matrix of the LDPC has one of the following structures or a deformed structure based on one of the following structures: a lower triangle, a lower triangular, an upper triangular, and a quasi-upper triangular.
  • the deinterleaver restores the bitstream sequence to the demodulated LDPC according to a preset rule, and specifically includes:
  • the deinterleaver restores the codeword of the first partial bit in the LDPC to a preset bit position, and recovers the codeword of the second partial bit in the LDPC by using a random bit position; wherein the preset bit The location is a bit position that is pre-agreed with the sender.
  • the codeword of the first partial bit includes a codeword of a punctured bit.
  • An interleaver configured to change an LDPC bitstream sequence according to a preset rule, and output the LDPC after changing the bitstream sequence to the modulator;
  • the modulator is configured to modulate the LDPC after changing the order of the bit stream, and then send the channel to the receiving end through the channel.
  • the method further includes: an encoder, configured to: before the interleaver changes the bitstream sequence of the LDPC according to a preset rule, and output the LDPC to the modulator, and output the encoded LDPC to the interleaver ;
  • the interleaver is specifically configured to: change a bit stream order of the encoded LDPC according to a preset rule, The LDPC after changing the order of the bit stream is output to the modulator.
  • the LDPC is specifically an incremental redundancy LDPC.
  • the interleaver comprises an N/C row block interleaver, each row comprising a C column block interleaver, wherein the N is a total codeword number of the LDPC, and the LDPC comprises an N/C group codeword, each The group code word includes C bit code words;
  • the interleaver is specifically configured to: sequentially receive each group of codewords of the LDPC in the order of rows, and sequentially output the codewords in the order of the columns, obtain an LDPC after changing the order of the bitstreams, and output the LDPCs to the modulator.
  • the interleaver is configured to change a bitstream order of an LDPC.
  • the code check matrix of the LDPC has one of the following structures or a deformed structure based on one of the following structures: a lower triangle, a lower triangular, an upper triangular, and a quasi-upper triangular.
  • the interleaver changes the bitstream sequence of the LDPC according to a preset rule, and specifically includes:
  • the interleaver changes a codeword of a first partial bit in the LDPC to a preset bit position, and performs a random bit position change on a codeword of a second partial bit in the LDPC; wherein the preset bit position It is the bit position agreed with the receiving end in advance.
  • the codeword of the first partial bit includes a codeword of a punctured bit.
  • a demodulator configured to receive an LDPC through a channel, and demodulate the LDPC, where the LDPC is an LDPC after the bitstream sequence is changed according to a preset rule by an interleaver;
  • the deinterleaver is configured to restore the bitstream sequence to the demodulated LDPC according to a preset rule.
  • the method further includes: a decoder, configured to: after the deinterleaver restores the bitstream sequence to the demodulated LDPC according to a preset rule, decode the LDPC after the bitstream sequence is restored.
  • a decoder configured to: after the deinterleaver restores the bitstream sequence to the demodulated LDPC according to a preset rule, decode the LDPC after the bitstream sequence is restored.
  • the LDPC is specifically an incremental redundancy LDPC.
  • the deinterleaver comprises an N/C row block deinterleaver, each row comprising a C column block deinterleaver, wherein the N is a total codeword number of the LDPC, and the LDPC comprises an N/C group code Word, each group of code words includes C bit code words;
  • the deinterleaver is specifically configured to: sequentially receive each of the demodulated LDPCs in the order of columns
  • the code words are grouped, and the code words are sequentially output in the order of the lines, and the LDPC after the order of the bit stream is restored is output to the decoder.
  • the deinterleaver is configured to recover a bitstream sequence of a demodulated LDPC.
  • the code check matrix of the LDPC has one of the following structures or a deformed structure based on one of the following structures: a lower triangle, a lower triangular, an upper triangular, and a quasi-upper triangular.
  • the deinterleaver restores the bitstream sequence to the demodulated LDPC according to a preset rule, and specifically includes:
  • the deinterleaver restores the codeword of the first partial bit in the LDPC to a preset bit position, and recovers the codeword of the second partial bit in the LDPC by using a random bit position; wherein the preset bit The location is a bit position that is pre-agreed with the sender.
  • the codeword of the first partial bit includes a codeword of a punctured bit.
  • FIG. 1 is a schematic structural diagram of a check matrix of an incremental redundant LDPC in the background art
  • FIG. 2 is a schematic diagram of a transmission scheme of an incremental redundant LDPC in the background art
  • FIG. 3 is a schematic diagram of a transmission scheme of an incremental redundant LDPC according to an embodiment of the present disclosure
  • FIG. 4 is a schematic diagram of an incremental redundant LDPC codeword grouping according to an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a block interleaver of an N/C row and a C column according to an embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of an LDPC codeword after interleaving according to an embodiment of the present disclosure
  • FIG. 7 is a schematic flowchart of a method for transmitting an LDPC on a sending end according to an embodiment of the present disclosure
  • FIG. 8 is a schematic structural diagram of an LDPC of a lower triangular matrix structure according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of an LDPC of a quasi-lower triangular matrix structure according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of an LDPC of an upper triangular matrix structure according to an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of an LDPC of a quasi-upper triangular matrix structure according to an embodiment of the present disclosure
  • FIG. 12 is a schematic structural diagram of an LDPC of a structure that is determined based on an LDPC code of a lower triangular matrix structure according to an embodiment of the present disclosure
  • FIG. 13 is a schematic diagram of a sequence of changing a bit stream of an LDPC according to an embodiment of the present disclosure
  • FIG. 14 is a schematic flowchart of a method for transmitting an LDPC at a receiving end according to an embodiment of the present disclosure
  • 15 is a schematic diagram of comparison of simulation results of an LDPC transmission scheme and an LDPC transmission scheme in other schemes according to an embodiment of the present disclosure
  • FIG. 16 is a schematic structural diagram of an LDPC transmission apparatus at a transmitting end according to an embodiment of the present disclosure
  • FIG. 17 is a schematic structural diagram of an LDPC transmission apparatus at a receiving end according to an embodiment of the present disclosure.
  • the embodiment of the present application provides a method and a device for transmitting a low-density parity check code, which are used to improve the anti-burst error capability of the LDPC transmission.
  • the embodiment of the present application is described by taking the transmission of the incremental LDPC as an example.
  • the technical solution provided by the embodiment of the present application is not limited to the transmission of the incremental redundant LDPC, and may be applied to the transmission of all types of LDPC.
  • the embodiment of the present application proposes an incremental redundancy LDPC transmission scheme against burst errors, which can improve the burst error resistance of the incremental redundant LDPC on the basis of maintaining the original function of the incremental redundancy LDPC.
  • the “burst error” refers to “continuous error”, that is, consecutive multiple codewords of the incremental redundant LDPC generate transmission errors.
  • anti-burst error capability can be understood as "the ability to correct continuous errors", that is, to avoid transmission errors caused by successive multiple codewords of the incremental redundant LDPC.
  • the embodiment of the present application further provides an interleaver structure for an LDPC transmission scheme, which can be adapted to the code length variation of the incremental redundant LDPC, so that the incremental redundancy against burst errors
  • the LDPC transmission scheme can be implemented.
  • the "interleaver” is a proper noun. The interleaver changes the order of the elements in the input sequence according to certain rules, and then outputs the sequence in a new order.
  • the incremental redundancy LDPC transmission scheme against burst errors proposed in the embodiment of the present application is as shown in FIG. 3.
  • At least one difference from the incremental redundancy LDPC transmission scheme in other modes is that an interleaver and a deinterleaver are introduced in the transmission of the incremental redundant LDPC.
  • the information sequence input by the encoder is encoded by an incremental redundant LDPC encoder and then outputs an incremental redundant LDPC codeword.
  • the incremental redundant LDPC codeword is interleaved by an interleaver, and then modulated, channel transmitted, and demodulated.
  • the adjusted result is deinterleaved by the deinterleaver.
  • the incremental LDPC decoding is decoded to obtain the decoder output.
  • the "interleaving operation” is to change the order of the elements in the input sequence (that is, the code words of the LDPC described in the embodiment of the present application) according to a certain rule, and then output the sequence in a new order.
  • the object of the interleaving operation ie, the input sequence
  • the embodiment of the present application designs an interleaving manner for incrementally redundant LDPC (ie, a rule for changing the bit stream order of the LDPC).
  • an interleaver is involved.
  • the interleaver is designed based on a matrix structure of incremental redundancy LDPC.
  • the codewords can be divided into N/C groups, each group including C bits, as shown in FIG. .
  • the interleaver designed for the LDPC is a block interleaver of N/C rows and C columns, and its interleaving strategy is "line-in list", as shown in FIG.
  • the "block interleaver” is an interleaver of a specific interleaving strategy, and the interleaving strategy is "line-in list".
  • the specific interleaving process includes:
  • the incremental redundant LDPC codeword sequentially enters each row block interleaver of the interleaver shown in FIG. 5 in sequence, wherein a group of codewords of the LDPC codeword can fill a row block interleaver of the interleaver; when the LDPC codeword After filling the entire interleaver, output by bit by bit, and finally get the result shown in Figure 6.
  • the LDPC codeword after interleaving that is, the LDPC in which the bit stream order is changed.
  • an LDPC transmission method provided by the embodiment of the present application includes:
  • the interleaver changes the bitstream sequence of the LDPC according to a preset rule, and outputs the LDPC after changing the sequence of the bitstream to the modulator.
  • the modulator modulates the LDPC after changing the bit stream order, and then sends the LDPC to the receiving end through the channel.
  • the interleaver changes the bit stream order of the LDPC according to a preset rule (for example, the above-mentioned line entry, or may also be included in the line-out rule, etc.), and outputs the LDPC after changing the order of the bit stream to the modulation.
  • the modulator modulates the LDPC after changing the order of the bit stream and transmits it to the receiving end through the channel, thereby reducing the probability of burst errors in successive bit streams during LDPC transmission, thereby improving the anti-burst of LDPC transmission. Error ability.
  • the method further includes: the encoder encodes the LDPC, and outputs the encoded LDPC to the interleaver;
  • the interleaver changes the bitstream order of the LDPC according to a preset rule, and outputs the LDPC after changing the sequence of the bitstream to the modulator, specifically:
  • the interleaver changes the bit stream order of the encoded LDPC according to a preset rule, and outputs the LDPC after changing the order of the bit stream to the modulator.
  • the LDPC is specifically an incremental redundancy LDPC.
  • the code check matrix of the incremental redundancy LDPC described in the embodiment of the present application has a partial deterministic structure, for example, a lower triangle, a lower triangle, an upper triangle, a quasi-up triangle, and on the basis of these structures. Make some deterministic modifications to the resulting graphical structure.
  • the LDPC of the lower triangular matrix structure is as shown in FIG. 8, the LDPC of the quasi-lower triangular matrix structure is as shown in FIG. 9, the LDPC of the upper triangular matrix structure is as shown in FIG. 10, and the LDPC of the quasi-upper triangular matrix structure is as shown in FIG.
  • FIG. 12 an LDPC of a structure which is determined based on the LDPC code of the lower triangular matrix structure is shown.
  • One embodiment of the LDPC of the sub-triangular or lower triangular structure is the LDPC of the highest code rate incremental redundancy structure.
  • the other embodiment may also be that the mother code structure is as shown in FIG. 1 , and the highest bit rate in the figure.
  • the code word has a double diagonal structure as an example, and may also be a single diagonal structure, and of course other structures are not excluded.
  • the interleaver comprises an N/C row block interleaver, each row comprising a C column block interleaver, wherein the N is a total codeword number of the LDPC, and the LDPC comprises an N/C group codeword, each The group code word includes C bit code words;
  • the interleaver changes the bitstream sequence of the LDPC according to a preset rule, and outputs the LDPC after changing the sequence of the bitstream to the modulator, specifically including:
  • the interleaver sequentially receives each group of codewords of the LDPC in the order of rows (for example, in a top-to-bottom order of rows, and of course other preset orders), and in the order of columns (eg, according to The order of the columns from left to right, of course, may be other preset sequences.
  • the codewords are sequentially outputted, and the LDPC after changing the order of the bitstreams is obtained and output to the modulator.
  • the interleaver is configured to change a bitstream order of an LDPC.
  • the interleaver can also be designed to perform the interleaving operation on the received bit streams of multiple LDPCs, that is, one interleaver can change the bit stream order of multiple LDPCs at the same time.
  • the interleaver is only used to change the bitstream order of an LDPC, which can reduce the transmission processing delay of the LDPC.
  • FIG. 8 to FIG. 11 are respectively a lower triangle, a sub-triangular triangle, an upper triangle, and a quasi-upper triangle matrix.
  • the specific embodiment does not exclude other situations, such as a combination thereof, for example, a quasi-lower triangular matrix.
  • a quasi-lower triangular matrix for example, a quasi-lower triangular matrix.
  • a lower triangular matrix below is a lower triangular matrix.
  • the check matrices shown in Figures 8 through 11 always have code bits corresponding to certain fixed columns deleted (or called punctured bits, such bits can be called punctured bits), that is, although encoding
  • the coded bits corresponding to some columns in the matrix are not sent to the channel and do not occupy the transmission time-frequency resources; although the punctured bits are coded bits, they are always one-to-one correspondence with the columns of the check matrix, so it can be called These are listed as fixed perforated columns of the check matrix.
  • the number and position of the fixed perforated columns of the check matrix are fixed.
  • the positions of these columns may be located at the forefront of the matrix, or some positions in the middle, may be continuous or discontinuous, and another
  • the scheme may also be that the punctured bits correspond to the fixed puncturing column of the check matrix, and the base station and the terminal (or both the transmitting end and the receiving end) are known, and of course, the possibility of signaling indication is not excluded;
  • the coded bits corresponding to the fixed puncture column encoded by the check matrix may be replaced by a deterministic position, and the remaining coded bits may be randomly replaced. Specifically, as shown in Figure 13.
  • the number of information bits is K bits
  • a codeword of length N bits is obtained by LDPC coding
  • the first L bits of the K bits are punctured bits, so that the first L columns of the check matrix are fixed Punch column
  • the position of the punctured bits in FIG. 13 is only an example, and the L bits may be located at any position including the code word check bit; in the process of replacing the code words, deterministic permutation is used for the punctured bits.
  • the method is such that the position after the replacement is at a fixed position. For convenience of expression in FIG.
  • the bits after the deterministic replacement are successively placed at the end of the new sequence, but other deterministic positions are not excluded, the above deterministic position, and the other
  • An implementation may also be that the base station and the terminal agree in advance; and the coded bits other than the punctured bits are randomly replaced to obtain the codeword to be transmitted and sent to the channel.
  • the object determining the replacement part in this example is a puncturing bit, and it is not excluded that other bits, such as zero padding bits, "shortened bits", etc., are not sent to the channel, but the code words are The interleaving within is always divided into two parts: deterministic position permutation and random position permutation.
  • the shortening bit is actually 0 bits, and the difference from the zero padding bit is that the columns of the check matrix corresponding to the zero padding during decoding participate in the decoding complexity, and the columns of the check matrix corresponding to the shortened bits are not Participating in decoding, low complexity but poor performance, these bits that are not sent to the channel are known in advance by the base station and the terminal.
  • the interleaver changes the bitstream sequence of the LDPC according to a preset rule, and specifically includes:
  • the interleaver changes a codeword of a first partial bit in the LDPC to a preset bit position, and performs a random bit position change on a codeword of a second partial bit in the LDPC; wherein the preset bit position It is the bit position agreed with the receiving end in advance.
  • the codeword of the first partial bit includes a codeword of a punctured bit.
  • an LDPC transmission provided by an embodiment of the present application is provided. Methods, including:
  • the demodulator receives the LDPC through the channel, and demodulates the LDPC, where the LDPC is an LDPC after the bitstream sequence is changed according to a preset rule by the interleaver;
  • the deinterleaver restores the bitstream sequence to the demodulated LDPC according to a preset rule.
  • the deinterleave rule of the deinterleaver at the receiving end is corresponding to the interleaving rule of the interleaver at the transmitting end, or may be understood as the operation of the deinterleaver to restore the bit stream sequence of the demodulated LDPC according to a preset rule.
  • the interleaver changes the inverse operation of the bitstream order of the LDPC according to a preset rule.
  • the method further includes: the decoder decoding the LDPC after the bit stream sequence is restored.
  • the LDPC is specifically an incremental redundancy LDPC.
  • the deinterleaver comprises an N/C row block deinterleaver, each row comprising a C column block deinterleaver, wherein the N is a total codeword number of the LDPC, and the LDPC comprises an N/C group code Word, each group of code words includes C bit code words;
  • the deinterleaver restores the bitstream sequence to the demodulated LDPC according to a preset rule, and specifically includes:
  • the deinterleaver sequentially receives each set of codewords of the demodulated LDPC in the order of the columns, and sequentially outputs the codewords in the order of the rows, and obtains the LDPCs after the order of the restored bitstreams and outputs them to the decoder.
  • the deinterleaver receives the codeword and the output codeword in a specific order, depending on the specific interleaving rules of the interleaver at the transmitting end, as long as the order of the LDPC bitstream can be restored to normal, that is, the bitstream sequence of the LDPC is restored to The original continuous bit stream order.
  • the deinterleaver is configured to recover a bitstream sequence of a demodulated LDPC.
  • FIG. 15 is a simulation result. It can be seen from the simulation result curve of FIG. 15 that the transmission scheme of the LDPC against burst error provided by the embodiment of the present application is compared with the transmission scheme of the LDPC in other manners, and the packet error probability block rate (BLock Error Rate) When the BLER is 10 -4 , the transmission scheme of the LDPC against burst error provided by the embodiment of the present application can obtain a performance gain of nearly 1 dB.
  • BLER Packe Rate
  • an incremental redundancy LDPC transmission mode with strong burst error resistance is introduced.
  • an interleaver and a deinterleaver are needed to enhance the burst capability. .
  • the interleaver design for the incremental redundant LDPC is also introduced.
  • the codewords can be divided into N/C groups, and each group includes C. Bit.
  • the interleaver designed for the LDPC is a block interleaver of N/C rows and C columns, and the interleaving strategy is "line-in list”.
  • the deinterleaving strategy is the corresponding "listing out”.
  • the embodiment of the present application proposes an incremental redundancy LDPC transmission scheme against burst errors, which can improve the burst error resistance of the incremental redundant LDPC on the basis of maintaining the original function of the incremental redundant LDPC.
  • the present application also provides a special interleaver structure, which can be effectively adapted to the incremental redundancy LDPC code length variation, so that the incremental redundancy LDPC transmission scheme against burst errors can be efficiently implemented.
  • an LDPC transmission apparatus provided by the embodiment of the present application includes:
  • the interleaver 12 is configured to change the bitstream sequence of the LDPC according to a preset rule, and output the LDPC after changing the sequence of the bitstream to the modulator;
  • the modulator 13 is configured to modulate the LDPC after changing the order of the bit stream, and then transmit the LDPC to the receiving end through the channel.
  • the method further includes: an encoder 11 configured to: before the interleaver changes the bitstream sequence of the LDPC according to a preset rule, and output the LDPC to the modulator, and output the encoded LDPC to the interlace Device
  • the interleaver is specifically configured to: change the bitstream sequence of the encoded LDPC according to a preset rule, and output the LDPC after changing the sequence of the bitstream to the modulator.
  • the LDPC is specifically an incremental redundancy LDPC.
  • the interleaver comprises an N/C row block interleaver, each row comprising a C column block interleaver, wherein the N is a total codeword number of the LDPC, and the LDPC comprises an N/C group codeword, each The group code word includes C bit code words;
  • the interleaver is specifically configured to: sequentially receive each group of codewords of the LDPC in the order of rows, and sequentially output the codewords in the order of the columns, obtain an LDPC after changing the order of the bitstreams, and output the LDPCs to the modulator.
  • the interleaver is configured to change a bitstream order of an LDPC.
  • an apparatus for transmitting an LDPC includes:
  • a demodulator 21 configured to receive an LDPC through a channel, and perform demodulation on the LDPC, where the LDPC is an LDPC after the bitstream sequence is changed according to a preset rule by an interleaver;
  • the deinterleaver 22 is configured to restore the bitstream sequence to the demodulated LDPC according to a preset rule.
  • the method further includes: a decoder 23, configured to: after the deinterleaver restores the bitstream sequence to the demodulated LDPC according to a preset rule, decode the LDPC after the bitstream sequence is restored.
  • a decoder 23 configured to: after the deinterleaver restores the bitstream sequence to the demodulated LDPC according to a preset rule, decode the LDPC after the bitstream sequence is restored.
  • the LDPC is specifically an incremental redundancy LDPC.
  • the deinterleaver comprises an N/C row block deinterleaver, each row comprising a C column block deinterleaver, wherein the N is a total codeword number of the LDPC, and the LDPC comprises an N/C group code Word, each group The codeword includes C bit code words;
  • the deinterleaver is specifically configured to: sequentially receive each group of codewords of the demodulated LDPC according to the order of the columns, and sequentially output the codewords in the order of the rows, obtain an LDPC after recovering the sequence of the bitstreams, and output the signals to the decoding.
  • Device configured to: sequentially receive each group of codewords of the demodulated LDPC according to the order of the columns, and sequentially output the codewords in the order of the rows, obtain an LDPC after recovering the sequence of the bitstreams, and output the signals to the decoding.
  • the deinterleaver is configured to recover a bitstream sequence of a demodulated LDPC.
  • the embodiment of the present application proposes an incremental redundancy LDPC transmission scheme against burst errors.
  • an incremental redundancy LDPC is used, an interleaver is used between the encoder and the modulator, and the demodulator and the translator are used.
  • the deinterleaver is used between the encoders. Therefore, the scheme can improve the burst error resistance of the incremental redundant LDPC while maintaining the original functions of the incremental redundant LDPC.
  • the present application also designs a special interleaver structure based on the scheme, that is, the block interleaver structure shown in FIG. 5, and because of the selection of row parameters and column parameters in the block interleaver structure of FIG. 5, the interleaver structure can It is effectively adapted to the incremental redundancy LDPC code length variation, so that the transmission scheme of the incremental redundancy LDPC against burst errors can be efficiently implemented.
  • embodiments of the present application can be provided as a method, system, or computer program product.
  • the present application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment in combination of software and hardware.
  • the application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.
  • These computer program instructions can also be stored in a bootable computer or other programmable data processing device.
  • a computer readable memory that operates in a particular manner, causing instructions stored in the computer readable memory to produce an article of manufacture comprising an instruction device implemented in one or more flows and/or block diagrams of the flowchart The function specified in the box or in multiple boxes.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

L'invention concerne un procédé et un dispositif de transmission de code de contrôle de parité à faible densité qui permettent d'améliorer la capacité d'erreur anti-rafale d'un code de contrôle de parité à faible densité. Le procédé selon la présente invention comprend : la modification par un entrelaceur de la séquence de flux binaires d'un code de contrôle de parité à faible densité selon une règle préétablie et l'émission vers un modulateur du code de contrôle de parité à faible densité dont la séquence de flux binaires est modifiée ; la modulation par le modulateur du code de contrôle de parité à faible densité dont la séquence de flux binaires est modifiée, puis l'envoi du code de contrôle de parité à faible densité modulé à une extrémité de réception à l'aide d'un canal.
PCT/CN2017/108005 2016-10-27 2017-10-27 Procédé et dispositif de transmission de code de contrôle de parité à faible densité WO2018077233A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US16/345,626 US10833803B2 (en) 2016-10-27 2017-10-27 Low density parity check code transmission method and device
EP17864561.0A EP3534554A4 (fr) 2016-10-27 2017-10-27 Procédé et dispositif de transmission de code de contrôle de parité à faible densité

Applications Claiming Priority (4)

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CN201610959949.3 2016-10-27
CN201610959949 2016-10-27
CN201710015031.8 2017-01-09
CN201710015031.8A CN108011691B (zh) 2016-10-27 2017-01-09 一种低密度奇偶校验码的传输方法及装置

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101150378A (zh) * 2006-09-18 2008-03-26 国家广播电影电视总局广播科学研究院 低密度奇偶校验编码的32apsk***的交织方案
US20150082131A1 (en) * 2013-09-17 2015-03-19 Samsung Electronics Co., Ltd. Transmitting apparatus and signal processing method thereof
WO2015178694A1 (fr) * 2014-05-21 2015-11-26 Samsung Electronics Co., Ltd. Appareil émetteur et son procédé d'entrelacement

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Publication number Priority date Publication date Assignee Title
CN101150378A (zh) * 2006-09-18 2008-03-26 国家广播电影电视总局广播科学研究院 低密度奇偶校验编码的32apsk***的交织方案
US20150082131A1 (en) * 2013-09-17 2015-03-19 Samsung Electronics Co., Ltd. Transmitting apparatus and signal processing method thereof
WO2015178694A1 (fr) * 2014-05-21 2015-11-26 Samsung Electronics Co., Ltd. Appareil émetteur et son procédé d'entrelacement

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