WO2018077233A1

WO2018077233A1 - Low density parity check code transmission method and device

Info

Publication number: WO2018077233A1
Application number: PCT/CN2017/108005
Authority: WO
Inventors: 穆锡金; 王加庆; 白宝明; 孙韶辉
Original assignee: 电信科学技术研究院
Priority date: 2016-10-27
Filing date: 2017-10-27
Publication date: 2018-05-03

Abstract

A low density parity check code transmission method and device, for use in improving the anti-burst-error capability of a low density parity check code. The method provided by the present application comprises: an interleaver changes the sequence of bit streams of a low density parity check code according to a preset rule, and outputs to a modulator the low density parity check code the sequence of bit streams of which is changed; the modulator modulates the low density parity check code the sequence of bit streams of which is changed and then sends the modulated low density parity check code to a receive end by using a channel.

Description

一种低密度奇偶校验码的传输方法及装置Method and device for transmitting low density parity check code

本申请要求在2016年10月27日提交中国专利局、申请号为201610959949.3、发明名称为“一种低密度奇偶校验码的传输方法及装置”、在2017年1月9日提交中国专利局、申请号为201710015031.8、发明名称为“一种低密度奇偶校验码的传输方法及装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。This application is required to be submitted to the China Patent Office on October 27, 2016, the application number is 201610959949.3, and the invention name is “a transmission method and device for low-density parity check code”, which was submitted to the Chinese Patent Office on January 9, 2017. The priority of the Chinese Patent Application No. 201710015031.8, entitled "Transmission Method and Apparatus for a Low-Density Parity Check Code", the entire contents of which are incorporated herein by reference.

技术领域Technical field

本申请涉及通信技术领域，尤其涉及一种低密度奇偶校验码的传输方法及装置。The present application relates to the field of communications technologies, and in particular, to a method and an apparatus for transmitting a low density parity check code.

背景技术Background technique

随着4G进入大规模商用阶段，面向未来的第五代移动通信(5G)已成为全球研发热点。当前第三代合作伙伴计划(3GPP)针对5G中移动宽带增强(Enhanced Mobile Broadband，eMBB)场景的信道编码参数为：As 4G enters the large-scale commercial phase, the future-oriented fifth-generation mobile communication (5G) has become a global research and development hotspot. The current channel coding parameters of the 3rd Generation Partnership Project (3GPP) for the 5G Mobile Broadband Enhanced (eMBB) scenario are:

表1.eMBB场景的信道编码参数Table 1. Channel coding parameters for eMBB scenarios

递增冗余低密度奇偶校验码(Low Density Parity Check Code，LDPC)具有性能优异、码长码率覆盖范围广、复用度高、易于硬件实现、可以直接用校验矩阵进行编码等优点，是5G的候选码之一，已经在3GPP标准化会议中深入的讨论和研究。Incremental Redundancy Low Density Parity Check Code (LDPC) has the advantages of excellent performance, wide code rate coverage, high multiplexing, easy hardware implementation, and direct coding with a check matrix. It is one of the 5G candidate codes and has been discussed and studied in depth in the 3GPP standardization conference.

在一种方案中，递增冗余LDPC的校验矩阵结构如图1所示。整个矩阵由循环置换小矩阵

和单位矩阵

构成，其中最高码率(如图1中最高码率R1部分)为具有双对角结构的准循环非规则重复累加LDPC(Quasi-cyclic irregular repeat-accumulate LDPC codes，QC-IRA LDPC codes)。基于最高码率的QC-IRA LDPC，通过递增冗余的方式增加校验位，进而可以得到低码率的LDPC(如图1中低码率R2，R3，R4，R5部分)。In one scheme, the check matrix structure of the incremental redundant LDPC is as shown in FIG. 1. Cyclic replacement of small matrices

And unit matrix

The composition, wherein the highest code rate (such as the highest code rate R1 portion in FIG. 1) is a quasi-cyclic irregular repeat-accumulate LDPC codes (QC-IRA LDPC codes) having a double diagonal structure. Based on the QC-IRA LDPC with the highest bit rate, the parity bit is increased by increasing the redundancy, and then the low code rate LDPC can be obtained (such as the low code rate R2, R3, R4, and R5 parts in FIG. 1).

在一种方案中，递增冗余LDPC的传输方案如图2所示。其中编码器输入的信息序列经过递增冗余LDPC编码器进行编码后输出LDPC码字，然后调制、信道传输和解调，解调后的结果经过译码器对递增冗余LDPC译码进行译码后输出。In one scheme, the transmission scheme of the incremental redundant LDPC is as shown in FIG. 2. The information sequence input by the encoder is encoded by an incremental redundancy LDPC encoder, and then the LDPC codeword is output, and then modulated, channel-transmitted, and demodulated. The demodulated result is decoded by the decoder for incremental redundant LDPC decoding. After the output.

递增冗余LDPC具有性能优异、码长码率覆盖范围广、复用度高、易于硬件实现、可以直接用校验矩阵进行编码等优点，是5G的候选码之一。根据上述递增冗余LDPC校验矩阵结构可以看出，该码属于***码，其信息比特和校验比特是分开的。这种结构易受突发错误(如相关衰落信道中多个符号连续衰落)的影响，抗突发错误能力较弱。The incremental redundancy LDPC has the advantages of excellent performance, wide code length code coverage, high multiplexing degree, easy hardware implementation, and can be directly encoded by the check matrix. It is one of the candidate codes of 5G. According to the above incremental redundant LDPC check matrix structure, it can be seen that the code belongs to the system code, and the information bits and the check bits are separated. This structure is susceptible to burst errors (such as the continuous fading of multiple symbols in the associated fading channel) and is less resistant to burst errors.

发明内容Summary of the invention

本申请实施例提供了一种低密度奇偶校验码的传输方法及装置，用以提高LDPC传输的抗突发错误能力。The embodiment of the present application provides a method and a device for transmitting a low-density parity check code, which are used to improve the anti-burst error capability of the LDPC transmission.

本申请实施例提供的一种LDPC的传输方法，包括：An LDPC transmission method provided by the embodiment of the present application includes:

交织器按照预设规则变更LDPC的比特流顺序，并将变更比特流顺序后的LDPC输出给调制器；The interleaver changes the bit stream order of the LDPC according to a preset rule, and outputs the LDPC after changing the order of the bit stream to the modulator;

所述调制器将变更比特流顺序后的LDPC进行调制后通过信道发送给接收端。The modulator modulates the LDPC after changing the bit stream order and transmits it to the receiving end through the channel.

通过该方法，交织器按照预设规则变更LDPC的比特流顺序，并将变更比特流顺序后的LDPC输出给调制器；所述调制器将变更比特流顺序后的LDPC进行调制后通过信道发送给接收端，从而可以降低LDPC传输过程中连续的比特流发生突发错误的概率，进而提高LDPC传输的抗突发错误能力。According to this method, the interleaver changes the bit stream order of the LDPC according to a preset rule, and outputs the LDPC after changing the order of the bit stream to the modulator; the modulator modulates the LDPC after changing the order of the bit stream and transmits it to the channel through the channel. The receiving end can reduce the probability of burst errors in consecutive bit streams during LDPC transmission, thereby improving the anti-burst error capability of LDPC transmission.

可选地，交织器按照预设规则变更LDPC的比特流顺序，并输出给调制器之前，该方法还包括：编码器对LDPC进行编码，并将编码后的LDPC输出给交织器；Optionally, before the interleaver changes the bitstream sequence of the LDPC according to a preset rule, and outputs the sequence to the modulator, the method further includes: the encoder encodes the LDPC, and the encoded LDPC is input. Out to the interleaver;

所述交织器按照预设规则变更LDPC的比特流顺序，并将变更比特流顺序后的LDPC输出给调制器，具体为：The interleaver changes the bitstream order of the LDPC according to a preset rule, and outputs the LDPC after changing the sequence of the bitstream to the modulator, specifically:

所述交织器按照预设规则变更编码后的LDPC的比特流顺序，并将变更比特流顺序后的LDPC输出给调制器。The interleaver changes the bit stream order of the encoded LDPC according to a preset rule, and outputs the LDPC after changing the order of the bit stream to the modulator.

可选地，所述LDPC具体为递增冗余LDPC。Optionally, the LDPC is specifically an incremental redundancy LDPC.

可选地，所述交织器包括N/C行块交织器，每行包括C列块交织器，其中，所述N为LDPC的总码字数，所述LDPC包括N/C组码字，每组码字包括C个比特码字；Optionally, the interleaver comprises an N/C row block interleaver, each row comprising a C column block interleaver, wherein the N is a total codeword number of the LDPC, and the LDPC comprises an N/C group codeword, each The group code word includes C bit code words;

所述交织器按照预设规则变更LDPC的比特流顺序，并将变更比特流顺序后的LDPC输出给调制器，具体包括：The interleaver changes the bitstream sequence of the LDPC according to a preset rule, and outputs the LDPC after changing the sequence of the bitstream to the modulator, specifically including:

所述交织器按照行的顺序依次接收所述LDPC的每一组码字，并且按照列的顺序依次输出码字，得到变更比特流顺序后的LDPC并输出给调制器。The interleaver sequentially receives each group of codewords of the LDPC in the order of rows, and sequentially outputs the codewords in the order of the columns, and obtains the LDPCs after changing the order of the bitstreams and outputs them to the modulator.

可选地，所述交织器用于变更一个LDPC的比特流顺序。Optionally, the interleaver is configured to change a bitstream order of an LDPC.

可选地，所述LDPC的码校验矩阵具有如下结构之一或者具有以如下结构之一为基础的变形结构：下三角、准下三角、上三角、准上三角。Optionally, the code check matrix of the LDPC has one of the following structures or a deformed structure based on one of the following structures: a lower triangle, a lower triangular, an upper triangular, and a quasi-upper triangular.

可选地，所述交织器按照预设规则变更LDPC的比特流顺序，具体包括：Optionally, the interleaver changes the bitstream sequence of the LDPC according to a preset rule, and specifically includes:

所述交织器将LDPC中的第一部分比特的码字，变更到预设比特位置，将所述LDPC中的第二部分比特的码字，进行随机比特位置变更；其中，所述预设比特位置是预先与接收端约定的比特位置。The interleaver changes a codeword of a first partial bit in the LDPC to a preset bit position, and performs a random bit position change on a codeword of a second partial bit in the LDPC; wherein the preset bit position It is the bit position agreed with the receiving end in advance.

可选地，所述第一部分比特的码字，包括打孔比特的码字。Optionally, the codeword of the first partial bit includes a codeword of a punctured bit.

解调器通过信道接收LDPC，并对所述LDPC进行解调，所述LDPC是经过交织器按照预设规则变更比特流顺序后的LDPC；The demodulator receives the LDPC through the channel, and demodulates the LDPC, where the LDPC is an LDPC after the bitstream sequence is changed according to a preset rule by the interleaver;

解交织器按照预设规则对解调后的LDPC恢复比特流顺序。The deinterleaver restores the bit stream order to the demodulated LDPC according to a preset rule.

可选地，所述解交织器按照预设规则对解调后的LDPC恢复比特流顺序之后，该方法还包括：译码器对恢复比特流顺序后的LDPC进行译码。 Optionally, after the deinterleaver restores the bit stream sequence to the demodulated LDPC according to a preset rule, the method further includes: the decoder decoding the LDPC after the bit stream sequence is restored.

可选地，所述解交织器包括N/C行块解交织器，每行包括C列块解交织器，其中，所述N为LDPC的总码字数，所述LDPC包括N/C组码字，每组码字包括C个比特码字；Optionally, the deinterleaver comprises an N/C row block deinterleaver, each row comprising a C column block deinterleaver, wherein the N is a total codeword number of the LDPC, and the LDPC comprises an N/C group code Word, each group of code words includes C bit code words;

所述解交织器按照预设规则对解调后的LDPC恢复比特流顺序，具体包括：The deinterleaver restores the bitstream sequence to the demodulated LDPC according to a preset rule, and specifically includes:

所述解交织器按照列的顺序依次接收解调后的LDPC的每一组码字，并且按照行的顺序依次输出码字，得到恢复比特流顺序后的LDPC并输出给译码器。The deinterleaver sequentially receives each set of codewords of the demodulated LDPC in the order of the columns, and sequentially outputs the codewords in the order of the rows, and obtains the LDPCs after the order of the restored bitstreams and outputs them to the decoder.

可选地，所述解交织器用于恢复一个解调后的LDPC的比特流顺序。Optionally, the deinterleaver is configured to recover a bitstream sequence of a demodulated LDPC.

可选地，所述解交织器按照预设规则对解调后的LDPC恢复比特流顺序，具体包括：Optionally, the deinterleaver restores the bitstream sequence to the demodulated LDPC according to a preset rule, and specifically includes:

所述解交织器将LDPC中的第一部分比特的码字，恢复到预设比特位置，将所述LDPC中的第二部分比特的码字，进行随机比特位置恢复；其中，所述预设比特位置是预先与发送端约定的比特位置。The deinterleaver restores the codeword of the first partial bit in the LDPC to a preset bit position, and recovers the codeword of the second partial bit in the LDPC by using a random bit position; wherein the preset bit The location is a bit position that is pre-agreed with the sender.

本申请实施例提供的一种LDPC的传输装置，包括：An apparatus for transmitting an LDPC according to an embodiment of the present application includes:

交织器，用于按照预设规则变更LDPC的比特流顺序，并将变更比特流顺序后的LDPC输出给调制器；An interleaver, configured to change an LDPC bitstream sequence according to a preset rule, and output the LDPC after changing the bitstream sequence to the modulator;

所述调制器，用于将变更比特流顺序后的LDPC进行调制后通过信道发送给接收端。The modulator is configured to modulate the LDPC after changing the order of the bit stream, and then send the channel to the receiving end through the channel.

可选地，还包括：编码器，用于在所述交织器按照预设规则变更LDPC的比特流顺序，并输出给调制器之前，对LDPC进行编码，并将编码后的LDPC输出给交织器；Optionally, the method further includes: an encoder, configured to: before the interleaver changes the bitstream sequence of the LDPC according to a preset rule, and output the LDPC to the modulator, and output the encoded LDPC to the interleaver ;

所述交织器具体用于：按照预设规则变更编码后的LDPC的比特流顺序，并将变更比特流顺序后的LDPC输出给调制器。The interleaver is specifically configured to: change a bit stream order of the encoded LDPC according to a preset rule, The LDPC after changing the order of the bit stream is output to the modulator.

所述交织器具体用于：按照行的顺序依次接收所述LDPC的每一组码字，并且按照列的顺序依次输出码字，得到变更比特流顺序后的LDPC并输出给调制器。The interleaver is specifically configured to: sequentially receive each group of codewords of the LDPC in the order of rows, and sequentially output the codewords in the order of the columns, obtain an LDPC after changing the order of the bitstreams, and output the LDPCs to the modulator.

解调器，用于通过信道接收LDPC，并对所述LDPC进行解调，所述LDPC是经过交织器按照预设规则变更比特流顺序后的LDPC；a demodulator, configured to receive an LDPC through a channel, and demodulate the LDPC, where the LDPC is an LDPC after the bitstream sequence is changed according to a preset rule by an interleaver;

解交织器，用于按照预设规则对解调后的LDPC恢复比特流顺序。The deinterleaver is configured to restore the bitstream sequence to the demodulated LDPC according to a preset rule.

可选地，还包括：译码器，用于在所述解交织器按照预设规则对解调后的LDPC恢复比特流顺序之后，对恢复比特流顺序后的LDPC进行译码。Optionally, the method further includes: a decoder, configured to: after the deinterleaver restores the bitstream sequence to the demodulated LDPC according to a preset rule, decode the LDPC after the bitstream sequence is restored.

所述解交织器具体用于：按照列的顺序依次接收解调后的LDPC的每一组码字，并且按照行的顺序依次输出码字，得到恢复比特流顺序后的LDPC并输出给译码器。The deinterleaver is specifically configured to: sequentially receive each of the demodulated LDPCs in the order of columns The code words are grouped, and the code words are sequentially output in the order of the lines, and the LDPC after the order of the bit stream is restored is output to the decoder.

附图说明DRAWINGS

为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简要介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域的普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following drawings will be briefly described in the description of the embodiments. It is obvious that the drawings in the following description are only some embodiments of the present application, Those skilled in the art can also obtain other drawings based on these drawings without paying any creative work.

图1为背景技术中递增冗余LDPC的校验矩阵结构示意图；1 is a schematic structural diagram of a check matrix of an incremental redundant LDPC in the background art;

图2为背景技术中递增冗余LDPC的传输方案示意图；2 is a schematic diagram of a transmission scheme of an incremental redundant LDPC in the background art;

图3为本申请实施例提供的递增冗余LDPC的传输方案示意图；FIG. 3 is a schematic diagram of a transmission scheme of an incremental redundant LDPC according to an embodiment of the present disclosure;

图4为本申请实施例提供的递增冗余LDPC码字分组示意图；4 is a schematic diagram of an incremental redundant LDPC codeword grouping according to an embodiment of the present application;

图5为本申请实施例提供的N/C行C列的块交织器结构示意图；FIG. 5 is a schematic structural diagram of a block interleaver of an N/C row and a C column according to an embodiment of the present disclosure;

图6为本申请实施例提供的交织后的LDPC码字示意图；FIG. 6 is a schematic diagram of an LDPC codeword after interleaving according to an embodiment of the present disclosure;

图7为本申请实施例提供的发送端的一种LDPC的传输方法的流程示意图；FIG. 7 is a schematic flowchart of a method for transmitting an LDPC on a sending end according to an embodiment of the present disclosure;

图8为本申请实施例提供的下三角矩阵结构的LDPC的结构示意图；FIG. 8 is a schematic structural diagram of an LDPC of a lower triangular matrix structure according to an embodiment of the present disclosure;

图9为本申请实施例提供的准下三角矩阵结构的LDPC的结构示意图； FIG. 9 is a schematic structural diagram of an LDPC of a quasi-lower triangular matrix structure according to an embodiment of the present disclosure;

图10为本申请实施例提供的上三角矩阵结构的LDPC的结构示意图；FIG. 10 is a schematic structural diagram of an LDPC of an upper triangular matrix structure according to an embodiment of the present disclosure;

图11为本申请实施例提供的准上三角矩阵结构的LDPC的结构示意图；FIG. 11 is a schematic structural diagram of an LDPC of a quasi-upper triangular matrix structure according to an embodiment of the present disclosure;

图12为本申请实施例提供的在下三角矩阵结构的LDPC码基础上进行确定的修改的一种结构的LDPC的结构示意图；FIG. 12 is a schematic structural diagram of an LDPC of a structure that is determined based on an LDPC code of a lower triangular matrix structure according to an embodiment of the present disclosure;

图13为本申请实施例提供的一种变更LDPC的比特流顺序的示意图；FIG. 13 is a schematic diagram of a sequence of changing a bit stream of an LDPC according to an embodiment of the present disclosure;

图14为本申请实施例提供的接收端的一种LDPC的传输方法的流程示意图；FIG. 14 is a schematic flowchart of a method for transmitting an LDPC at a receiving end according to an embodiment of the present disclosure;

图15为本申请实施例提供的LDPC的传输方案与其他方案中的LDPC的传输方案的仿真结果对比示意图；15 is a schematic diagram of comparison of simulation results of an LDPC transmission scheme and an LDPC transmission scheme in other schemes according to an embodiment of the present disclosure;

图16为本申请实施例提供的发送端的一种LDPC的传输装置的结构示意图；FIG. 16 is a schematic structural diagram of an LDPC transmission apparatus at a transmitting end according to an embodiment of the present disclosure;

图17为本申请实施例提供的接收端的一种LDPC的传输装置的结构示意图。FIG. 17 is a schematic structural diagram of an LDPC transmission apparatus at a receiving end according to an embodiment of the present disclosure.

具体实施方式detailed description

本申请实施例以递增冗余LDPC的传输为例进行说明，但本申请实施例提供的技术方案并不限于递增冗余LDPC的传输，可以应用到所有类型的LDPC的传输。The embodiment of the present application is described by taking the transmission of the incremental LDPC as an example. However, the technical solution provided by the embodiment of the present application is not limited to the transmission of the incremental redundant LDPC, and may be applied to the transmission of all types of LDPC.

本申请实施例提出抗突发错误的递增冗余LDPC传输方案，该方案能够在保持递增冗余LDPC原有功能的基础上，提高递增冗余LDPC的抗突发错误能力。其中，所述的“突发错误”是指“连续的错误”，即递增冗余LDPC的连续多个码字产生传输错误。那么，“抗突发错误能力”可以理解为“纠正连续错误的能力”，即避免递增冗余LDPC的连续多个码字产生传输错误。与此同时，本申请实施例还提供了用于LDPC传输方案的交织器结构，该交织器结构能够适应于递增冗余LDPC的码长变化，使得抗突发错误的递增冗余 LDPC传输方案能够实现。其中，所述的“交织器”为专有名词。所述交织器按照一定规则改变输入序列中元素的顺序，然后按照新的顺序输出序列。The embodiment of the present application proposes an incremental redundancy LDPC transmission scheme against burst errors, which can improve the burst error resistance of the incremental redundant LDPC on the basis of maintaining the original function of the incremental redundancy LDPC. The “burst error” refers to “continuous error”, that is, consecutive multiple codewords of the incremental redundant LDPC generate transmission errors. Then, "anti-burst error capability" can be understood as "the ability to correct continuous errors", that is, to avoid transmission errors caused by successive multiple codewords of the incremental redundant LDPC. At the same time, the embodiment of the present application further provides an interleaver structure for an LDPC transmission scheme, which can be adapted to the code length variation of the incremental redundant LDPC, so that the incremental redundancy against burst errors The LDPC transmission scheme can be implemented. Wherein, the "interleaver" is a proper noun. The interleaver changes the order of the elements in the input sequence according to certain rules, and then outputs the sequence in a new order.

下面介绍一下本申请实施例提供的抗突发错误能力强的递增冗余LDPC传输方式。The following describes the incremental redundant LDPC transmission mode with strong burst error resistance provided by the embodiment of the present application.

在本申请实施例所提出的抗突发错误的递增冗余LDPC传输方案如图3所示。与其他方式中的递增冗余LDPC传输方案的至少一个区别在于，在递增冗余LDPC的传输过程中引入了交织器和解交织器。其中，编码器输入的信息序列经过递增冗余LDPC编码器进行编码后输出递增冗余LDPC码字，该递增冗余LDPC码字经过交织器进行交织操作，然后调制、信道传输和解调，解调后的结果经过解交织器进行解交织操作，最后，递增冗余LDPC译码进行译码后得到译码器输出结果。其中，所述“交织操作”是按照一定规则改变输入序列中元素(即本申请实施例中所述的LDPC的码字)的顺序，然后按照新的顺序输出序列。所述交织操作的对象(即输入序列)为递增冗余LDPC，本申请实施例设计了针对递增冗余LDPC的交织方式(即改变LDPC的比特流顺序的规则)。The incremental redundancy LDPC transmission scheme against burst errors proposed in the embodiment of the present application is as shown in FIG. 3. At least one difference from the incremental redundancy LDPC transmission scheme in other modes is that an interleaver and a deinterleaver are introduced in the transmission of the incremental redundant LDPC. The information sequence input by the encoder is encoded by an incremental redundant LDPC encoder and then outputs an incremental redundant LDPC codeword. The incremental redundant LDPC codeword is interleaved by an interleaver, and then modulated, channel transmitted, and demodulated. The adjusted result is deinterleaved by the deinterleaver. Finally, the incremental LDPC decoding is decoded to obtain the decoder output. The "interleaving operation" is to change the order of the elements in the input sequence (that is, the code words of the LDPC described in the embodiment of the present application) according to a certain rule, and then output the sequence in a new order. The object of the interleaving operation (ie, the input sequence) is an incremental redundancy LDPC. The embodiment of the present application designs an interleaving manner for incrementally redundant LDPC (ie, a rule for changing the bit stream order of the LDPC).

针对递增冗余LDPC的交织器设计介绍如下：The design of the interleaver for incremental redundant LDPC is as follows:

在本申请实施例所提出的抗突发错误的递增冗余LDPC传输方案中，涉及到了交织器，本申请实施例中基于递增冗余LDPC的矩阵结构设计该交织器。In the incremental redundancy LDPC transmission scheme against the burst error proposed in the embodiment of the present application, an interleaver is involved. In the embodiment of the present application, the interleaver is designed based on a matrix structure of incremental redundancy LDPC.

对于码率为R，码长为N，循环置换小矩阵和单位矩阵大小为C的递增冗余LDPC，其码字可以分为N/C组，每组包括C个比特，如图4所示。针对该LDPC设计的交织器是N/C行、C列的块交织器，其交织策略为“行入列出”，如图5所示。所述“块交织器”为一种特定交织策略的交织器，其交织策略为“行入列出”，参见图5和图6，其具体的交织流程包括：For an incremental redundancy LDPC with a code rate R, a code length of N, a cyclic permutation small matrix, and an identity matrix size C, the codewords can be divided into N/C groups, each group including C bits, as shown in FIG. . The interleaver designed for the LDPC is a block interleaver of N/C rows and C columns, and its interleaving strategy is "line-in list", as shown in FIG. The "block interleaver" is an interleaver of a specific interleaving strategy, and the interleaving strategy is "line-in list". Referring to FIG. 5 and FIG. 6, the specific interleaving process includes:

首先递增冗余LDPC码字按照顺序依次进入图5所示的交织器的每一行块交织器，其中LDPC码字的一组码字正好能填满交织器的一行块交织器；当LDPC码字填充满整个交织器后，按列逐比特输出，最终得到图6所示的交织后的LDPC码字，即比特流顺序发生变更的LDPC。First, the incremental redundant LDPC codeword sequentially enters each row block interleaver of the interleaver shown in FIG. 5 in sequence, wherein a group of codewords of the LDPC codeword can fill a row block interleaver of the interleaver; when the LDPC codeword After filling the entire interleaver, output by bit by bit, and finally get the result shown in Figure 6. The LDPC codeword after interleaving, that is, the LDPC in which the bit stream order is changed.

由此可见，参见图7，在发送端，本申请实施例提供的一种LDPC的传输方法，包括：Therefore, referring to FIG. 7, at the transmitting end, an LDPC transmission method provided by the embodiment of the present application includes:

S101、交织器按照预设规则变更LDPC的比特流顺序，并将变更比特流顺序后的LDPC输出给调制器；S101. The interleaver changes the bitstream sequence of the LDPC according to a preset rule, and outputs the LDPC after changing the sequence of the bitstream to the modulator.

S102、所述调制器将变更比特流顺序后的LDPC进行调制后通过信道发送给接收端。S102. The modulator modulates the LDPC after changing the bit stream order, and then sends the LDPC to the receiving end through the channel.

通过该方法，交织器按照预设规则(例如上述的行入列出，或者也可以是列入行出等等规则)变更LDPC的比特流顺序，并将变更比特流顺序后的LDPC输出给调制器；所述调制器将变更比特流顺序后的LDPC进行调制后通过信道发送给接收端，从而可以降低LDPC传输过程中连续的比特流发生突发错误的概率，进而提高LDPC传输的抗突发错误能力。By this method, the interleaver changes the bit stream order of the LDPC according to a preset rule (for example, the above-mentioned line entry, or may also be included in the line-out rule, etc.), and outputs the LDPC after changing the order of the bit stream to the modulation. The modulator modulates the LDPC after changing the order of the bit stream and transmits it to the receiving end through the channel, thereby reducing the probability of burst errors in successive bit streams during LDPC transmission, thereby improving the anti-burst of LDPC transmission. Error ability.

可选地，交织器按照预设规则变更LDPC的比特流顺序，并输出给调制器之前，该方法还包括：编码器对LDPC进行编码，并将编码后的LDPC输出给交织器；Optionally, before the interleaver changes the bitstream sequence of the LDPC according to a preset rule, and outputs the sequence to the modulator, the method further includes: the encoder encodes the LDPC, and outputs the encoded LDPC to the interleaver;

并且，进一步地，本申请实施例中所述的递增冗余LDPC的码校验矩阵具有部分确定性结构，例如：下三角、准下三角、上三角、准上三角及其在这些结构基础上做某些确定性的修改得到的图形结构。其中，下三角矩阵结构的LDPC如图8所示，准下三角矩阵结构的LDPC如图9所示，上三角矩阵结构的LDPC如图10所示，准上三角矩阵结构的LDPC如图11所示，在下三角矩阵结构的LDPC码基础上进行确定的修改的一种结构的LDPC如图12所示。 Moreover, further, the code check matrix of the incremental redundancy LDPC described in the embodiment of the present application has a partial deterministic structure, for example, a lower triangle, a lower triangle, an upper triangle, a quasi-up triangle, and on the basis of these structures. Make some deterministic modifications to the resulting graphical structure. The LDPC of the lower triangular matrix structure is as shown in FIG. 8, the LDPC of the quasi-lower triangular matrix structure is as shown in FIG. 9, the LDPC of the upper triangular matrix structure is as shown in FIG. 10, and the LDPC of the quasi-upper triangular matrix structure is as shown in FIG. As shown in FIG. 12, an LDPC of a structure which is determined based on the LDPC code of the lower triangular matrix structure is shown.

准下三角或者下三角结构的LDPC的一个实施例为最高码率的递增冗余结构的LDPC，另一种实施方案还可以是，其母码结构如图1所示，该图中最高码率码字为双对角结构只是一个示例，也可以是单对角结构，当然也不排除其他结构。One embodiment of the LDPC of the sub-triangular or lower triangular structure is the LDPC of the highest code rate incremental redundancy structure. The other embodiment may also be that the mother code structure is as shown in FIG. 1 , and the highest bit rate in the figure. The code word has a double diagonal structure as an example, and may also be a single diagonal structure, and of course other structures are not excluded.

所述交织器按照行的顺序(例如按照行的从上到下的顺序，当然也可以是别的预设顺序)依次接收所述LDPC的每一组码字，并且按照列的顺序(例如按照列的从左到右的顺序，当然也可以是别的预设顺序)依次输出码字，得到变更比特流顺序后的LDPC并输出给调制器。The interleaver sequentially receives each group of codewords of the LDPC in the order of rows (for example, in a top-to-bottom order of rows, and of course other preset orders), and in the order of columns (eg, according to The order of the columns from left to right, of course, may be other preset sequences. The codewords are sequentially outputted, and the LDPC after changing the order of the bitstreams is obtained and output to the modulator.

可选地，所述交织器用于变更一个LDPC的比特流顺序。当然，也可以设计交织器用于对接收到的多个LDPC的比特流顺序进行交织操作，即一个交织器可以同时变更多个LDPC的比特流顺序。而交织器仅用于变更一个LDPC的比特流顺序，可以减少LDPC的传输处理时延。Optionally, the interleaver is configured to change a bitstream order of an LDPC. Of course, the interleaver can also be designed to perform the interleaving operation on the received bit streams of multiple LDPCs, that is, one interleaver can change the bit stream order of multiple LDPCs at the same time. The interleaver is only used to change the bitstream order of an LDPC, which can reduce the transmission processing delay of the LDPC.

上述图8至图11所示，分别是下三角、准下三角、上三角、准上三角矩阵，只是具体实施例，不排除其他情形，例如其组合方式，例如上面是一个准下三角矩阵，下面是一个下三角矩阵。The above-mentioned FIG. 8 to FIG. 11 are respectively a lower triangle, a sub-triangular triangle, an upper triangle, and a quasi-upper triangle matrix. However, the specific embodiment does not exclude other situations, such as a combination thereof, for example, a quasi-lower triangular matrix. Below is a lower triangular matrix.

图8至图11所示的这些校验矩阵总是有某些位置固定的列对应的编码比特被删除(或称为被打孔掉，这样的比特可以称为打孔比特)，即虽然编码，但是矩阵中某些列对应的编码比特，不送入信道，不占用传输时频资源；打孔比特虽然是编码比特，但是由于其与校验矩阵的列总是一一对应，故可以称这些列为校验矩阵的固定打孔列。The check matrices shown in Figures 8 through 11 always have code bits corresponding to certain fixed columns deleted (or called punctured bits, such bits can be called punctured bits), that is, although encoding However, the coded bits corresponding to some columns in the matrix are not sent to the channel and do not occupy the transmission time-frequency resources; although the punctured bits are coded bits, they are always one-to-one correspondence with the columns of the check matrix, so it can be called These are listed as fixed perforated columns of the check matrix.

校验矩阵的固定打孔列的数目与位置都是固定的，这些列的位置可以位于矩阵的最前面，或者中间某些位置，可以连续，也可以不连续，另一种实施方案还可以是，打孔比特对应校验矩阵的固定打孔列，基站与终端(或者称为发送端与接收端)都是已知的，当然并不排除信令指示的可能；此情形下，作为所述的LDPC校验矩阵块内交织的一种特例，可以将校验矩阵编码后的固定打孔列对应的编码比特置换到确定性的位置，而将其余的编码比特进行随机置换，具体如图13所示。不失一般性，假定信息比特个数为K比特，经过LDPC编码得到长为N比特的码字；这K个比特的前L个比特为打孔比特，这样校验矩阵的前L列为固定打孔列，图13中打孔比特的位置仅仅是一个示例，这L个比特可能位于码字校验比特在内的任何位置；在码字内置换过程中，对打孔比特采用确定性置换方法，使得其置换后的位置位于固定的位置，图13中为了表达方便，将确定性置换后的比特连续放置在新序列的最后，但并不排除其他确定性位置，上述确定性位置，另一种实施方案还可以是，可以是基站与终端提前约定；而打孔比特以外的编码比特采用随机置换的方式得到待传输的码字，送入信道。The number and position of the fixed perforated columns of the check matrix are fixed. The positions of these columns may be located at the forefront of the matrix, or some positions in the middle, may be continuous or discontinuous, and another The scheme may also be that the punctured bits correspond to the fixed puncturing column of the check matrix, and the base station and the terminal (or both the transmitting end and the receiving end) are known, and of course, the possibility of signaling indication is not excluded; In the following, as a special example of the inter-layer interleaving in the LDPC check matrix, the coded bits corresponding to the fixed puncture column encoded by the check matrix may be replaced by a deterministic position, and the remaining coded bits may be randomly replaced. Specifically, as shown in Figure 13. Without loss of generality, assuming that the number of information bits is K bits, a codeword of length N bits is obtained by LDPC coding; the first L bits of the K bits are punctured bits, so that the first L columns of the check matrix are fixed Punch column, the position of the punctured bits in FIG. 13 is only an example, and the L bits may be located at any position including the code word check bit; in the process of replacing the code words, deterministic permutation is used for the punctured bits. The method is such that the position after the replacement is at a fixed position. For convenience of expression in FIG. 13, the bits after the deterministic replacement are successively placed at the end of the new sequence, but other deterministic positions are not excluded, the above deterministic position, and the other An implementation may also be that the base station and the terminal agree in advance; and the coded bits other than the punctured bits are randomly replaced to obtain the codeword to be transmitted and sent to the channel.

需要说明的是，该例子中确定置换部分的对象是打孔比特，不排除还可以是其他比特，例如补零(zero padding)比特、“缩短比特”等不送入信道的比特，但是码字内的交织总是分为确定性位置置换与随机位置置换两部分。其中，所述缩短比特事实上也是0比特，与zero padding比特区别在于，译码时zero padding对应的那些校验矩阵的列参与译码复杂度高，缩短比特对应的那些校验矩阵的列不参与译码，复杂度低但是性能差，这些不送入信道的比特都是基站与终端预先知道的。It should be noted that the object determining the replacement part in this example is a puncturing bit, and it is not excluded that other bits, such as zero padding bits, "shortened bits", etc., are not sent to the channel, but the code words are The interleaving within is always divided into two parts: deterministic position permutation and random position permutation. The shortening bit is actually 0 bits, and the difference from the zero padding bit is that the columns of the check matrix corresponding to the zero padding during decoding participate in the decoding complexity, and the columns of the check matrix corresponding to the shortened bits are not Participating in decoding, low complexity but poor performance, these bits that are not sent to the channel are known in advance by the base station and the terminal.

因此，可选地，所述交织器按照预设规则变更LDPC的比特流顺序，具体包括：Therefore, optionally, the interleaver changes the bitstream sequence of the LDPC according to a preset rule, and specifically includes:

相应地，参见图14，在接收端，本申请实施例提供的一种LDPC的传输方法，包括：Correspondingly, referring to FIG. 14, at the receiving end, an LDPC transmission provided by an embodiment of the present application is provided. Methods, including:

S201、解调器通过信道接收LDPC，并对所述LDPC进行解调，所述LDPC是经过交织器按照预设规则变更比特流顺序后的LDPC；S201, the demodulator receives the LDPC through the channel, and demodulates the LDPC, where the LDPC is an LDPC after the bitstream sequence is changed according to a preset rule by the interleaver;

S202、解交织器按照预设规则对解调后的LDPC恢复比特流顺序。S202. The deinterleaver restores the bitstream sequence to the demodulated LDPC according to a preset rule.

其中，接收端的解交织器的解交织规则，与发送端的交织器的交织规则，是相应的，或者可以理解为解交织器按照预设规则对解调后的LDPC恢复比特流顺序的操作，是交织器按照预设规则变更LDPC的比特流顺序的逆操作。The deinterleave rule of the deinterleaver at the receiving end is corresponding to the interleaving rule of the interleaver at the transmitting end, or may be understood as the operation of the deinterleaver to restore the bit stream sequence of the demodulated LDPC according to a preset rule. The interleaver changes the inverse operation of the bitstream order of the LDPC according to a preset rule.

可选地，所述解交织器按照预设规则对解调后的LDPC恢复比特流顺序之后，该方法还包括：译码器对恢复比特流顺序后的LDPC进行译码。Optionally, after the deinterleaver restores the bit stream sequence to the demodulated LDPC according to a preset rule, the method further includes: the decoder decoding the LDPC after the bit stream sequence is restored.

当然，解交织器具体按照怎样的顺序接收码字以及输出码字，取决于发送端交织器具体的交织规则，只要能将LDPC的比特流顺序恢复正常即可，即将LDPC的比特流顺序恢复为原有的连续的比特流顺序。Of course, the deinterleaver receives the codeword and the output codeword in a specific order, depending on the specific interleaving rules of the interleaver at the transmitting end, as long as the order of the LDPC bitstream can be restored to normal, that is, the bitstream sequence of the LDPC is restored to The original continuous bit stream order.

以下仿真实例可以说明本申请实施例提供的传输方案的有效性，表2为仿真参数，图15为仿真结果。由图15的仿真结果曲线可以看出：本申请实施例提供的抗突发错误的LDPC的传输方案，与其他方式中的LDPC的传输方案相比，在分组错误概率误块率(BLock Error Rate，BLER)为10^-4时，本申请实施例提供的抗突发错误的LDPC的传输方案能获得接近1dB的性能增益。The following simulation examples can illustrate the effectiveness of the transmission scheme provided by the embodiment of the present application, Table 2 is a simulation parameter, and FIG. 15 is a simulation result. It can be seen from the simulation result curve of FIG. 15 that the transmission scheme of the LDPC against burst error provided by the embodiment of the present application is compared with the transmission scheme of the LDPC in other manners, and the packet error probability block rate (BLock Error Rate) When the BLER is 10 ^-4 , the transmission scheme of the LDPC against burst error provided by the embodiment of the present application can obtain a performance gain of nearly 1 dB.

表2.仿真参数Table 2. Simulation parameters

上述本申请实施例提供的技术方案中，先介绍了抗突发错误能力强的递增冗余LDPC传输方式，当使用递增冗余LDPC时，需要引入了交织器和解交织器来增强抗突发能力。In the technical solution provided by the foregoing embodiment of the present application, an incremental redundancy LDPC transmission mode with strong burst error resistance is introduced. When an incremental redundancy LDPC is used, an interleaver and a deinterleaver are needed to enhance the burst capability. .

另外，上述本申请实施例提供的技术方案中，还介绍了针对递增冗余LDPC的交织器设计，当使用递增冗余LDPC时，其码字可以分为N/C组，每组包括C个比特。针对该LDPC设计的交织器是N/C行、C列的块交织器，其交织策略为“行入列出”。相应地，在接收端的解交织器，其解交织策略为相应的“列入行出”。In addition, in the technical solution provided by the foregoing application, the interleaver design for the incremental redundant LDPC is also introduced. When the incremental redundancy LDPC is used, the codewords can be divided into N/C groups, and each group includes C. Bit. The interleaver designed for the LDPC is a block interleaver of N/C rows and C columns, and the interleaving strategy is "line-in list". Correspondingly, at the deinterleaver of the receiving end, the deinterleaving strategy is the corresponding "listing out".

因此，本申请实施例提出一种抗突发错误的递增冗余LDPC传输方案，该方案能够在保持递增冗余LDPC原有功能的基础上，提高递增冗余LDPC的抗突发错误能力。与此同时，本申请还给出了特殊的交织器结构，该交织器结构能够有效地适应于递增冗余LDPC码长变化，使得抗突发错误的递增冗余LDPC传输方案能够高效实现。Therefore, the embodiment of the present application proposes an incremental redundancy LDPC transmission scheme against burst errors, which can improve the burst error resistance of the incremental redundant LDPC on the basis of maintaining the original function of the incremental redundant LDPC. At the same time, the present application also provides a special interleaver structure, which can be effectively adapted to the incremental redundancy LDPC code length variation, so that the incremental redundancy LDPC transmission scheme against burst errors can be efficiently implemented.

基于与上述发送端方法的同一发明构思，参见图16，在发送端，本申请实施例提供的一种LDPC的传输装置，包括： Based on the same inventive concept as the above-mentioned method of the transmitting end, referring to FIG. 16, at the transmitting end, an LDPC transmission apparatus provided by the embodiment of the present application includes:

交织器12，用于按照预设规则变更LDPC的比特流顺序，并将变更比特流顺序后的LDPC输出给调制器；The interleaver 12 is configured to change the bitstream sequence of the LDPC according to a preset rule, and output the LDPC after changing the sequence of the bitstream to the modulator;

所述调制器13，用于将变更比特流顺序后的LDPC进行调制后通过信道发送给接收端。The modulator 13 is configured to modulate the LDPC after changing the order of the bit stream, and then transmit the LDPC to the receiving end through the channel.

可选地，还包括：编码器11，用于在所述交织器按照预设规则变更LDPC的比特流顺序，并输出给调制器之前，对LDPC进行编码，并将编码后的LDPC输出给交织器；Optionally, the method further includes: an encoder 11 configured to: before the interleaver changes the bitstream sequence of the LDPC according to a preset rule, and output the LDPC to the modulator, and output the encoded LDPC to the interlace Device

所述交织器具体用于：按照预设规则变更编码后的LDPC的比特流顺序，并将变更比特流顺序后的LDPC输出给调制器。The interleaver is specifically configured to: change the bitstream sequence of the encoded LDPC according to a preset rule, and output the LDPC after changing the sequence of the bitstream to the modulator.

相应地，在接收端，参见图17，本申请实施例提供的一种LDPC的传输装置，包括：Correspondingly, at the receiving end, referring to FIG. 17, an apparatus for transmitting an LDPC according to an embodiment of the present application includes:

解调器21，用于通过信道接收LDPC，并对所述LDPC进行解调，所述LDPC是经过交织器按照预设规则变更比特流顺序后的LDPC；a demodulator 21, configured to receive an LDPC through a channel, and perform demodulation on the LDPC, where the LDPC is an LDPC after the bitstream sequence is changed according to a preset rule by an interleaver;

解交织器22，用于按照预设规则对解调后的LDPC恢复比特流顺序。The deinterleaver 22 is configured to restore the bitstream sequence to the demodulated LDPC according to a preset rule.

可选地，还包括：译码器23，用于在所述解交织器按照预设规则对解调后的LDPC恢复比特流顺序之后，对恢复比特流顺序后的LDPC进行译码。Optionally, the method further includes: a decoder 23, configured to: after the deinterleaver restores the bitstream sequence to the demodulated LDPC according to a preset rule, decode the LDPC after the bitstream sequence is restored.

可选地，所述解交织器包括N/C行块解交织器，每行包括C列块解交织器，其中，所述N为LDPC的总码字数，所述LDPC包括N/C组码字，每组码字包括C个比特码字；Optionally, the deinterleaver comprises an N/C row block deinterleaver, each row comprising a C column block deinterleaver, wherein the N is a total codeword number of the LDPC, and the LDPC comprises an N/C group code Word, each group The codeword includes C bit code words;

所述解交织器具体用于：按照列的顺序依次接收解调后的LDPC的每一组码字，并且按照行的顺序依次输出码字，得到恢复比特流顺序后的LDPC并输出给译码器。The deinterleaver is specifically configured to: sequentially receive each group of codewords of the demodulated LDPC according to the order of the columns, and sequentially output the codewords in the order of the rows, obtain an LDPC after recovering the sequence of the bitstreams, and output the signals to the decoding. Device.

综上所述，本申请实施例提出一种抗突发错误的递增冗余LDPC传输方案，当采用递增冗余LDPC时，在编码器和调制器之间使用交织器，在解调器和译码器之间使用解交织器，因此，该方案能够在保持递增冗余LDPC原有功能的基础上，提高递增冗余LDPC的抗突发错误能力。In summary, the embodiment of the present application proposes an incremental redundancy LDPC transmission scheme against burst errors. When an incremental redundancy LDPC is used, an interleaver is used between the encoder and the modulator, and the demodulator and the translator are used. The deinterleaver is used between the encoders. Therefore, the scheme can improve the burst error resistance of the incremental redundant LDPC while maintaining the original functions of the incremental redundant LDPC.

与此同时，本申请还基于方案设计了特殊的交织器结构，即图5所示的块交织器结构，并且由于图5中块交织器结构中行参数和列参数的选择，该交织器结构能够有效地适应于递增冗余LDPC码长变化，使得抗突发错误的递增冗余LDPC的传输方案能够高效实现。At the same time, the present application also designs a special interleaver structure based on the scheme, that is, the block interleaver structure shown in FIG. 5, and because of the selection of row parameters and column parameters in the block interleaver structure of FIG. 5, the interleaver structure can It is effectively adapted to the incremental redundancy LDPC code length variation, so that the transmission scheme of the incremental redundancy LDPC against burst errors can be efficiently implemented.

本领域内的技术人员应明白，本申请的实施例可提供为方法、***、或计算机程序产品。因此，本申请可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本申请可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器和光学存储器等)上实施的计算机程序产品的形式。Those skilled in the art will appreciate that embodiments of the present application can be provided as a method, system, or computer program product. Thus, the present application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment in combination of software and hardware. Moreover, the application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.

本申请是参照根据本申请实施例的方法、设备(***)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (system), and computer program products according to embodiments of the present application. It will be understood that each flow and/or block of the flowchart illustrations and/or FIG. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing device to produce a machine for the execution of instructions for execution by a processor of a computer or other programmable data processing device. Means for implementing the functions specified in one or more of the flow or in a block or blocks of the flow chart.

这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。These computer program instructions can also be stored in a bootable computer or other programmable data processing device. In a computer readable memory that operates in a particular manner, causing instructions stored in the computer readable memory to produce an article of manufacture comprising an instruction device implemented in one or more flows and/or block diagrams of the flowchart The function specified in the box or in multiple boxes.

这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device. The instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。 It will be apparent to those skilled in the art that various modifications and changes can be made in the present application without departing from the spirit and scope of the application. Thus, it is intended that the present invention cover the modifications and variations of the present invention.

Claims

一种低密度奇偶校验码LDPC的传输方法，其特征在于，包括：A method for transmitting a low density parity check code LDPC, comprising:

交织器按照预设规则变更LDPC的比特流顺序，并将变更比特流顺序后的LDPC输出给调制器；The interleaver changes the bit stream order of the LDPC according to a preset rule, and outputs the LDPC after changing the order of the bit stream to the modulator;

所述调制器将变更比特流顺序后的LDPC进行调制后通过信道发送给接收端。The modulator modulates the LDPC after changing the bit stream order and transmits it to the receiving end through the channel.
根据权利要求1所述的方法，其特征在于，交织器按照预设规则变更LDPC的比特流顺序，并输出给调制器之前，该方法还包括：编码器对LDPC进行编码，并将编码后的LDPC输出给交织器；The method according to claim 1, wherein the interleaver changes the bitstream order of the LDPC according to a preset rule and outputs the sequence to the modulator, the method further comprises: the encoder encoding the LDPC, and encoding the coded LDPC output to the interleaver;

所述交织器按照预设规则变更LDPC的比特流顺序，并将变更比特流顺序后的LDPC输出给调制器，具体为：The interleaver changes the bitstream order of the LDPC according to a preset rule, and outputs the LDPC after changing the sequence of the bitstream to the modulator, specifically:

所述交织器按照预设规则变更编码后的LDPC的比特流顺序，并将变更比特流顺序后的LDPC输出给调制器。The interleaver changes the bit stream order of the encoded LDPC according to a preset rule, and outputs the LDPC after changing the order of the bit stream to the modulator.
根据权利要求1所述的方法，其特征在于，所述LDPC具体为递增冗余LDPC。The method according to claim 1, wherein the LDPC is specifically an incremental redundancy LDPC.
根据权利要求1所述的方法，其特征在于，所述交织器包括N/C行块交织器，每行包括C列块交织器，其中，所述N为LDPC的总码字数，所述LDPC包括N/C组码字，每组码字包括C个比特码字；The method of claim 1 wherein said interleaver comprises an N/C row block interleaver, each row comprising a C column block interleaver, wherein said N is a total number of codewords of LDPC, said LDPC Including N/C group code words, each group of code words includes C bit code words;

所述交织器按照预设规则变更LDPC的比特流顺序，并将变更比特流顺序后的LDPC输出给调制器，具体包括：The interleaver changes the bitstream sequence of the LDPC according to a preset rule, and outputs the LDPC after changing the sequence of the bitstream to the modulator, specifically including:

所述交织器按照行的顺序依次接收所述LDPC的每一组码字，并且按照列的顺序依次输出码字，得到变更比特流顺序后的LDPC并输出给调制器。The interleaver sequentially receives each group of codewords of the LDPC in the order of rows, and sequentially outputs the codewords in the order of the columns, and obtains the LDPCs after changing the order of the bitstreams and outputs them to the modulator.
根据权利要求1所述的方法，其特征在于，所述交织器用于变更一个LDPC的比特流顺序。The method of claim 1 wherein said interleaver is operative to change the bitstream order of an LDPC.
根据权利要求1所述的方法，其特征在于，所述LDPC的码校验矩阵具有如下结构之一或者具有以如下结构之一为基础的变形结构：下三角、准下三角、上三角、准上三角。The method according to claim 1, wherein the code check matrix of the LDPC has one of the following structures or a deformed structure based on one of the following structures: a lower triangle, a standard The lower triangle, the upper triangle, and the upper triangle.
根据权利要求1所述的方法，其特征在于，所述交织器按照预设规则变更LDPC的比特流顺序，具体包括：The method according to claim 1, wherein the interleaver changes the bit stream order of the LDPC according to a preset rule, and specifically includes:

所述交织器将LDPC中的第一部分比特的码字，变更到预设比特位置，将所述LDPC中的第二部分比特的码字，进行随机比特位置变更；其中，所述预设比特位置是预先与接收端约定的比特位置。The interleaver changes a codeword of a first partial bit in the LDPC to a preset bit position, and performs a random bit position change on a codeword of a second partial bit in the LDPC; wherein the preset bit position It is the bit position agreed with the receiving end in advance.
根据权利要求7所述的方法，其特征在于，所述第一部分比特的码字，包括打孔比特的码字。The method of claim 7 wherein the codeword of the first partial bit comprises a codeword of a punctured bit.
一种LDPC的传输方法，其特征在于，包括：A method for transmitting an LDPC, comprising:

解调器通过信道接收LDPC，并对所述LDPC进行解调，所述LDPC是经过交织器按照预设规则变更比特流顺序后的LDPC；The demodulator receives the LDPC through the channel, and demodulates the LDPC, where the LDPC is an LDPC after the bitstream sequence is changed according to a preset rule by the interleaver;

解交织器按照预设规则对解调后的LDPC恢复比特流顺序。The deinterleaver restores the bit stream order to the demodulated LDPC according to a preset rule.
根据权利要求9所述的方法，其特征在于，所述解交织器按照预设规则对解调后的LDPC恢复比特流顺序之后，该方法还包括：译码器对恢复比特流顺序后的LDPC进行译码。The method according to claim 9, wherein after the deinterleaver restores the bit stream sequence to the demodulated LDPC according to a preset rule, the method further comprises: decoding the LDPC after the bit stream sequence is restored by the decoder Perform decoding.
根据权利要求9所述的方法，其特征在于，所述LDPC具体为递增冗余LDPC。The method according to claim 9, wherein the LDPC is specifically an incremental redundancy LDPC.
根据权利要求9所述的方法，其特征在于，所述解交织器包括N/C行块解交织器，每行包括C列块解交织器，其中，所述N为LDPC的总码字数，所述LDPC包括N/C组码字，每组码字包括C个比特码字；The method according to claim 9, wherein said deinterleaver comprises an N/C block deinterleaver, each row comprising a C column block deinterleaver, wherein said N is a total number of codewords of LDPC, The LDPC includes N/C group codewords, and each group of codewords includes C bit codewords;

所述解交织器按照预设规则对解调后的LDPC恢复比特流顺序，具体包括：The deinterleaver restores the bitstream sequence to the demodulated LDPC according to a preset rule, and specifically includes:

所述解交织器按照列的顺序依次接收解调后的LDPC的每一组码字，并且按照行的顺序依次输出码字，得到恢复比特流顺序后的LDPC并输出给译码器。The deinterleaver sequentially receives each set of codewords of the demodulated LDPC in the order of the columns, and sequentially outputs the codewords in the order of the rows, and obtains the LDPCs after the order of the restored bitstreams and outputs them to the decoder.
根据权利要求9所述的方法，其特征在于，所述解交织器用于恢复一个解调后的LDPC的比特流顺序。 The method of claim 9 wherein said deinterleaver is operative to recover a sequence of bitstreams of a demodulated LDPC.
根据权利要求9所述的方法，其特征在于，所述LDPC的码校验矩阵具有如下结构之一或者具有以如下结构之一为基础的变形结构：下三角、准下三角、上三角、准上三角。The method according to claim 9, wherein the code check matrix of the LDPC has one of the following structures or a deformed structure based on one of the following structures: a lower triangle, a lower triangular, an upper triangular, a quasi Upper triangle.
根据权利要求9所述的方法，其特征在于，所述解交织器按照预设规则对解调后的LDPC恢复比特流顺序，具体包括：The method according to claim 9, wherein the deinterleaver restores the sequence of the bit stream to the demodulated LDPC according to a preset rule, and specifically includes:

所述解交织器将LDPC中的第一部分比特的码字，恢复到预设比特位置，将所述LDPC中的第二部分比特的码字，进行随机比特位置恢复；其中，所述预设比特位置是预先与发送端约定的比特位置。The deinterleaver restores the codeword of the first partial bit in the LDPC to a preset bit position, and recovers the codeword of the second partial bit in the LDPC by using a random bit position; wherein the preset bit The location is a bit position that is pre-agreed with the sender.
根据权利要求15所述的方法，其特征在于，所述第一部分比特的码字，包括打孔比特的码字。The method of claim 15 wherein the codeword of the first partial bit comprises a codeword of a punctured bit.
一种LDPC的传输装置，其特征在于，包括：An LDPC transmission device, comprising:

交织器，用于按照预设规则变更LDPC的比特流顺序，并将变更比特流顺序后的LDPC输出给调制器；An interleaver, configured to change an LDPC bitstream sequence according to a preset rule, and output the LDPC after changing the bitstream sequence to the modulator;

所述调制器，用于将变更比特流顺序后的LDPC进行调制后通过信道发送给接收端。The modulator is configured to modulate the LDPC after changing the order of the bit stream, and then send the channel to the receiving end through the channel.
根据权利要求17所述的装置，其特征在于，还包括：编码器，用于在所述交织器按照预设规则变更LDPC的比特流顺序，并输出给调制器之前，对LDPC进行编码，并将编码后的LDPC输出给交织器；The apparatus according to claim 17, further comprising: an encoder, configured to encode the LDPC before the interleaver changes the bitstream order of the LDPC according to a preset rule and outputs the same to the modulator, and Outputting the encoded LDPC to the interleaver;

所述交织器具体用于：按照预设规则变更编码后的LDPC的比特流顺序，并将变更比特流顺序后的LDPC输出给调制器。The interleaver is specifically configured to: change the bitstream sequence of the encoded LDPC according to a preset rule, and output the LDPC after changing the sequence of the bitstream to the modulator.
根据权利要求17所述的装置，其特征在于，所述LDPC具体为递增冗余LDPC。The apparatus according to claim 17, wherein the LDPC is specifically an incremental redundancy LDPC.
根据权利要求17所述的装置，其特征在于，所述交织器包括N/C行块交织器，每行包括C列块交织器，其中，所述N为LDPC的总码字数，所述LDPC包括N/C组码字，每组码字包括C个比特码字；The apparatus according to claim 17, wherein said interleaver comprises an N/C row block interleaver, each row comprising a C column block interleaver, wherein said N is a total codeword number of LDPC, said LDPC Including N/C group code words, each group of code words includes C bit code words;

所述交织器具体用于：按照行的顺序依次接收所述LDPC的每一组码字，并且按照列的顺序依次输出码字，得到变更比特流顺序后的LDPC并输出给调制器。The interleaver is specifically configured to: sequentially receive each group of codewords of the LDPC in the order of rows, and sequentially output the codewords in the order of columns, obtain an LDPC after changing the order of the bitstreams, and output the LDPCs to Modulator.
根据权利要求17所述的装置，其特征在于，所述交织器用于变更一个LDPC的比特流顺序。The apparatus according to claim 17, wherein said interleaver is adapted to change a bitstream order of an LDPC.
根据权利要求17所述的装置，其特征在于，所述LDPC的码校验矩阵具有如下结构之一或者具有以如下结构之一为基础的变形结构：下三角、准下三角、上三角、准上三角。The apparatus according to claim 17, wherein the code check matrix of the LDPC has one of the following structures or a deformed structure based on one of the following structures: a lower triangle, a lower triangular, an upper triangular, a quasi Upper triangle.
根据权利要求17所述的装置，其特征在于，所述交织器按照预设规则变更LDPC的比特流顺序，具体包括：The device according to claim 17, wherein the interleaver changes the bitstream sequence of the LDPC according to a preset rule, and specifically includes:

所述交织器将LDPC中的第一部分比特的码字，变更到预设比特位置，将所述LDPC中的第二部分比特的码字，进行随机比特位置变更；其中，所述预设比特位置是预先与接收端约定的比特位置。The interleaver changes a codeword of a first partial bit in the LDPC to a preset bit position, and performs a random bit position change on a codeword of a second partial bit in the LDPC; wherein the preset bit position It is the bit position agreed with the receiving end in advance.
根据权利要求23所述的装置，其特征在于，所述第一部分比特的码字，包括打孔比特的码字。The apparatus of claim 23 wherein said first partial bit of codeword comprises a codeword of a punctured bit.
一种LDPC的传输装置，其特征在于，包括：An LDPC transmission device, comprising:

解调器，用于通过信道接收LDPC，并对所述LDPC进行解调，所述LDPC是经过交织器按照预设规则变更比特流顺序后的LDPC；a demodulator, configured to receive an LDPC through a channel, and demodulate the LDPC, where the LDPC is an LDPC after the bitstream sequence is changed according to a preset rule by an interleaver;

解交织器，用于按照预设规则对解调后的LDPC恢复比特流顺序。The deinterleaver is configured to restore the bitstream sequence to the demodulated LDPC according to a preset rule.
根据权利要求25所述的装置，其特征在于，还包括：译码器，用于在所述解交织器按照预设规则对解调后的LDPC恢复比特流顺序之后，对恢复比特流顺序后的LDPC进行译码。The apparatus according to claim 25, further comprising: a decoder, configured to restore the bit stream sequence after the deinterleaver restores the bit stream sequence to the demodulated LDPC according to a preset rule The LDPC is decoded.
根据权利要求25所述的装置，其特征在于，所述LDPC具体为递增冗余LDPC。The apparatus according to claim 25, wherein the LDPC is specifically an incremental redundancy LDPC.
根据权利要求25所述的装置，其特征在于，所述解交织器包括N/C行块解交织器，每行包括C列块解交织器，其中，所述N为LDPC的总码字数，所述LDPC包括N/C组码字，每组码字包括C个比特码字；The apparatus according to claim 25, wherein said deinterleaver comprises an N/C row block deinterleaver, each row comprising a C column block deinterleaver, wherein said N is a total number of code words of LDPC, The LDPC includes N/C group codewords, and each group of codewords includes C bit codewords;

所述解交织器具体用于：按照列的顺序依次接收解调后的LDPC的每一组码字，并且按照行的顺序依次输出码字，得到恢复比特流顺序后的LDPC 并输出给译码器。The deinterleaver is specifically configured to: sequentially receive each group of codewords of the demodulated LDPC in the order of columns, and sequentially output the codewords in the order of rows, to obtain an LDPC after recovering the sequence of bitstreams. And output to the decoder.
根据权利要求25所述的装置，其特征在于，所述解交织器用于恢复一个解调后的LDPC的比特流顺序。The apparatus of claim 25 wherein said deinterleaver is operative to recover a sequence of bitstreams of a demodulated LDPC.
根据权利要求25所述的装置，其特征在于，所述LDPC的码校验矩阵具有如下结构之一或者具有以如下结构之一为基础的变形结构：下三角、准下三角、上三角、准上三角。The apparatus according to claim 25, wherein the code check matrix of the LDPC has one of the following structures or a deformed structure based on one of the following structures: a lower triangle, a lower triangular, an upper triangular, a quasi Upper triangle.
根据权利要求25所述的装置，其特征在于，所述解交织器按照预设规则对解调后的LDPC恢复比特流顺序，具体包括：The apparatus according to claim 25, wherein the deinterleaver restores the sequence of the bit stream to the demodulated LDPC according to a preset rule, and specifically includes:

所述解交织器将LDPC中的第一部分比特的码字，恢复到预设比特位置，将所述LDPC中的第二部分比特的码字，进行随机比特位置恢复；其中，所述预设比特位置是预先与发送端约定的比特位置。The deinterleaver restores the codeword of the first partial bit in the LDPC to a preset bit position, and recovers the codeword of the second partial bit in the LDPC by using a random bit position; wherein the preset bit The location is a bit position that is pre-agreed with the sender.
根据权利要求31所述的装置，其特征在于，所述第一部分比特的码字，包括打孔比特的码字。 The apparatus of claim 31, wherein the codeword of the first partial bit comprises a codeword of a punctured bit.