WO2018068544A1 - High-voltage interlock detection circuit - Google Patents

High-voltage interlock detection circuit Download PDF

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Publication number
WO2018068544A1
WO2018068544A1 PCT/CN2017/093114 CN2017093114W WO2018068544A1 WO 2018068544 A1 WO2018068544 A1 WO 2018068544A1 CN 2017093114 W CN2017093114 W CN 2017093114W WO 2018068544 A1 WO2018068544 A1 WO 2018068544A1
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WIPO (PCT)
Prior art keywords
high voltage
loop
voltage interlock
limiting resistor
current limiting
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PCT/CN2017/093114
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French (fr)
Chinese (zh)
Inventor
敖翔
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宁德时代新能源科技股份有限公司
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Publication of WO2018068544A1 publication Critical patent/WO2018068544A1/en

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/40—Testing power supplies

Definitions

  • the present application relates to the field of circuit protection technologies, and in particular, to a high voltage interlock detection circuit.
  • the integrity of the high-voltage power supply circuit is the basis of the high-voltage circuit. If the high-voltage circuit is incomplete, if the connector is not connected, the circuit will not work properly, and even if it is serious, it will cause component damage.
  • a high voltage interlock circuit is generally used for detecting the integrity of the high voltage loop, and the high voltage interlock circuit generally adopts an analog type and a digital type.
  • the analog type refers to a type in which the potential of the circuit is stable after the high-voltage connection relationship is determined, for example, a simple resistor-divided type, an optocoupler-conducting type, etc., but its anti-interference ability is relatively poor.
  • the digital type refers to the type in which the potential of the circuit changes periodically after the high-voltage connection relationship is determined, such as the PWM output type and the communication network loop type.
  • the communication network loop type if the communication network is only used for high-voltage interlock detection, the circuit is complicated and expensive, and if the communication network also serves as another important communication channel, the high-voltage interlock and other communication functions are mutually accustomed. Miscellaneous, it is easy to have mutual influence. At the same time, in practical applications, it also faces difficulties in wiring and interference, so the PWM output type is often used in related technologies.
  • the embodiment of the present application provides a high voltage interlock detection circuit, which aims to solve the technical problem of how to reduce the complexity of the high voltage interlock detection circuit, and can simplify the high voltage interlock detection circuit, thereby reducing the test cost.
  • the embodiment of the present application provides a high voltage interlock detection circuit, including: high voltage interlock a loop, the high voltage interlocking loop has a loop input end and a loop output end; a high voltage interlock circuit having a PWM signal output end and a signal check input end, the PWM signal output end
  • the first current limiting resistor is connected to the loop input end, and the loop output end is connected to the signal check input terminal via a second current limiting resistor
  • the high voltage interlock circuit includes a monitoring chip and filtering Capacitor, the monitoring chip and the filter capacitor are connected to the signal check input end, and the PWM signal outputted by the PWM signal output end is returned to the signal check input end via the high voltage interlock loop, and
  • the filter capacitor is filtered and then enters the monitoring chip.
  • the high voltage interlock circuit further includes: an inverter between the PWM signal output end and the first current limiting resistor.
  • the high voltage interlock circuit further includes: a transmission gate located between the PWM signal output end and the first current limiting resistor.
  • the high voltage interlock circuit further includes: a first checkback module, one end of the first checkback module is connected between the first current limiting resistor and the loop input end The other end is connected to the signal check input.
  • the first checkback module further includes a third current limiting resistor.
  • the resistances of the first current limiting resistor, the second current limiting resistor, and the third current limiting resistor are greater than or equal to 100 ohms.
  • the high voltage interlock circuit further includes: a second checkback module, one end of the second checkback module is connected to the output end of the second current limiting resistor, and the other end is connected to the The signal check input is connected in parallel with the monitoring chip.
  • the second checkback module includes: a first comparator, a non-inverting input end of the first comparator is connected to an output end of the second current limiting resistor; and a second comparator In parallel with the first comparator, an inverting input of the second comparator is coupled to an output of the second current limiting resistor; and an outer port connection of the second current limiting resistor is shorted to ground or Short circuit to the positive supply.
  • the first back check module and/or the second check module further includes Includes clamp diodes.
  • the clamping diode is a Schottky diode.
  • the monitoring chip (watchdog chip) can be added to the signal return input end of the high voltage interlock circuit.
  • the PWM (Pulse Width Modulation) signal output by the MCU (micro control unit) in the high voltage interlock circuit passes through the first current limiting resistor to the high voltage interlocking loop.
  • the circuit then returns to the second current limiting resistor of the circuit, which is filtered by the filter capacitor and then sent to the monitoring chip.
  • the maximum voltage value of the waveform filtered by the filter capacitor is higher than the high level threshold of the input signal of the monitoring chip, and the waveform is minimum.
  • the voltage value is lower than the low level decision threshold of the monitor chip input signal.
  • the filtered waveform satisfies the dog feed timing requirement of the monitoring chip, and its Reset output is an inactive level.
  • the MCU detects the state of the Reset signal to know that the high voltage loop is well connected and can work normally.
  • the MCU When the high voltage loop is disconnected, the high voltage interlock loop is high impedance, and the MCU outputs the PWM signal through the first current limiting resistor to the high voltage interlock loop, but because the loop is high impedance, the signal cannot return to the loop.
  • Two current limiting resistors The waveform filtered by the filter capacitor is a DC voltage, which cannot meet the timing requirement of the monitoring chip.
  • the Reset output is an active level, and the MCU detects the state of the Reset signal to know that there is a problem with the connection of the high voltage loop, and thus can be taken. Measures such as alarming and cutting off the output.
  • a single PWM output and monitoring chip is used to simplify the high voltage interlock detection circuit, the MCU only detects the level signal of the watchdog output, reduces the occupation of the MCU computing resources, and the MCU detection output uses only the general number.
  • the input port can be used, which reduces the requirements for the MCU hardware port resources.
  • FIG. 1 shows a circuit diagram of a high voltage interlock detection circuit in accordance with one embodiment of the present application
  • FIG. 2 shows a circuit diagram of a high voltage interlock detection circuit in accordance with another embodiment of the present application
  • FIG. 3 shows a circuit diagram of a high voltage interlock detection circuit in accordance with still another embodiment of the present application.
  • FIG. 4 shows a circuit diagram of a high voltage interlock detection circuit in accordance with yet another embodiment of the present application.
  • FIG. 5 shows a circuit diagram of a high voltage interlock detection circuit in accordance with yet another embodiment of the present application.
  • the high voltage interlock detection circuit includes a high voltage interlock loop and a high voltage interlock circuit.
  • the high voltage interlock loop has a loop input end and a loop output end
  • the high voltage interlock circuit has a PWM signal output end and a signal.
  • the PWM signal output end is connected to the loop input end via a first current limiting resistor, and the loop output end is connected to the signal check input end via a second current limiting resistor, wherein the high voltage interlock circuit includes a monitoring chip and The filter capacitor, the monitor chip and the filter capacitor are connected with the signal check input terminal, and the PWM signal outputted from the PWM signal output terminal is returned to the signal detection input terminal through the high voltage interlock loop, and filtered by the filter capacitor to enter the monitor chip.
  • the monitoring chip (watchdog chip) can be added to the signal return input end of the high voltage interlock circuit.
  • FIG. 1 shows a circuit diagram of a high voltage interlock detection circuit in accordance with one embodiment of the present application.
  • the MCU when the high voltage loop is well connected, that is, when the high voltage interlock loop is low impedance, the MCU outputs the PWM signal through the resistor R11 to the high voltage interlock loop, and then returns to the R12 of the circuit, and is filtered by the C11. The wave is given to the watchdog chip.
  • the maximum voltage value of the waveform filtered by C11 is higher than the high-level determination threshold VOH of the input signal of the watchdog chip, and the minimum voltage value of the waveform is lower than the low-level determination threshold VOL of the input signal of the watchdog chip.
  • the filtered waveform satisfies the dog timing requirement of the watchdog chip U11, and its Reset output is an inactive level.
  • the MCU detects the state of the Reset signal to know that the high voltage loop is well connected and can work normally.
  • the high voltage interlock loop When the high voltage loop is disconnected, the high voltage interlock loop also exhibits high impedance.
  • the MCU outputs a PWM signal through the resistor R11 to the high voltage interlock loop, but because the loop is high impedance, the signal cannot return to the R12 of the loop.
  • the waveform after C11 filtering is a DC voltage, which cannot meet the dog timing requirement of the watchdog chip U11.
  • the Reset output is an active level, and the MCU detects the state of the Reset signal to know that there is a problem in the connection of the high voltage loop, and then takes Measures such as alarming and cutting off the output.
  • a single PWM output and monitoring chip is used to simplify the high voltage interlock detection circuit, the MCU only detects the level signal of the watchdog output, reduces the occupation of the MCU computing resources, and the MCU detection output uses only the general number.
  • the input port can be used, which reduces the requirements for the MCU hardware port resources.
  • the value of the capacitor C11 should be selected in combination with the RC time constant to be close to half of the period of the MCU output PWM, so as to maximize the filtering of the enhanced immunity and facilitate the support of the high voltage interlock interface. Short circuit to ground, short circuit to power supply, etc.
  • the MCU when the high-voltage loop is well connected, that is, when the high-voltage interlock loop is low impedance, the MCU outputs a PWM signal, which is amplified by the inverter U21, and then returns to the high-voltage interlock loop through the resistor R22.
  • the R23 of the circuit is filtered by the capacitor C21 and supplied to the watchdog chip U22.
  • the inverter U21 is located between the PWM signal output terminal and R22 for amplifying the driving capability, so that the circuit can have a stronger PWM output capability, and is convenient for completing the PWM output circuit diagnosis.
  • the maximum voltage value of the waveform filtered by the capacitor C21 is higher than the high-level determination threshold VOH of the input signal of the watchdog chip, and the minimum voltage value of the waveform is lower than the low-level determination valve of the input signal of the watchdog chip. Value VOL.
  • the filtered waveform satisfies the dog timing requirement of the watchdog chip U22, and its Reset output is an inactive level.
  • the MCU detects the state of the Reset signal to know that the high voltage loop is well connected and can work normally.
  • the high voltage interlock loop When the high voltage loop is disconnected, the high voltage interlock loop also exhibits high impedance.
  • the MCU outputs a PWM signal, which is amplified by the inverter U21 and then passed through the resistor R22 to the high voltage interlock loop, but because the loop is high impedance. The signal cannot return to R23 of this circuit.
  • the waveform filtered by the capacitor C21 is a DC voltage, which cannot meet the dog timing requirement of the watchdog chip U22, and the Reset output is an active level, and the MCU detects the state of the Reset signal to know that there is a problem in the connection of the high voltage loop. In addition, measures such as alarming and cutting off the output are taken.
  • the value of the capacitor C21 should be selected in combination with the RC time constant to be close to half of the period of the MCU output PWM, so as to maximize the filtering of the enhanced immunity and facilitate the support of the high voltage interlock interface. Short circuit to ground, short circuit to power supply, etc.
  • the MCU when the high-voltage circuit is well connected, that is, when the high-voltage interlocking loop is low impedance, the MCU outputs a PWM signal, and after amplifying the driving capability through the transmission gate U31, it returns to the circuit through the resistor R32 to the high-voltage interlocking loop.
  • the resistor R33 is filtered by the capacitor C31 and supplied to the watchdog chip U32.
  • the transmission gate U31 is located between the PWM signal output end and R22 for amplifying the driving capability, so that the circuit can have a stronger PWM output capability, and is convenient for completing the PWM output circuit diagnosis.
  • the maximum voltage value of the waveform filtered by the capacitor C31 is higher than the high-level determination threshold VOH of the input signal of the watchdog chip, and the minimum voltage value of the waveform is lower than the low-level determination threshold VOL of the input signal of the watchdog chip.
  • the filtered waveform satisfies the dog feed timing requirement of the watchdog chip U32, and its Reset output is an inactive level.
  • the MCU detects the state of the Reset signal to know that the high voltage loop is well connected and can work normally.
  • the high-voltage interlocking loop When the high-voltage circuit is connected to open circuit, the high-voltage interlocking loop is also embodied as high impedance.
  • the MCU outputs a PWM signal, which is amplified by the transmission gate U31 and then passed through the resistor R32 to the high-voltage interlocking loop, but because of the high impedance of the loop, The signal cannot return to R33 of this circuit.
  • the waveform filtered by capacitor C31 is A DC voltage cannot meet the dog timing requirement of the watchdog chip U32, and its Reset output is an active level.
  • the MCU detects the state of the Reset signal to know that there is a problem with the connection of the high voltage circuit, and then takes measures such as alarming and cutting off the output. .
  • the value of the capacitor C31 should be selected in combination with the RC time constant to be close to half of the period of the MCU output PWM, so as to maximize the filtering of the enhanced immunity and facilitate the support of the high voltage interlock interface. Short circuit to ground, short circuit to power supply, etc.
  • the first checkback module may be further included in the high voltage interlock detection circuit, and one end of the first checkback module is connected between the first current limiting resistor and the loop input end, and the other end is connected. To the signal check input.
  • the resistance of R21, R22 and R23 is greater than or equal to 100 ohms, so that the output current can be limited to a small range to prevent the output power from being too large to damage the circuit, or to limit the input when there is an abnormality such as short circuit to power supply. The current thus protects the circuit from damage.
  • resistance values of R31, R32 and R33 are greater than or equal to 100 ohms, so that the output current can be limited to a small range to prevent the output power from being too large to damage the circuit, or to disconnect the short circuit to the power supply.
  • the input current is limited to protect the circuit from damage.
  • the high voltage interlock detection circuit may further include a second checkback module, one end of the second checkback module is connected to the output end of the second current limiting resistor, and the other end is connected to the signal check input. End, in parallel with the monitoring chip. In this way, it can have stronger PWM output capability, and can complete PWM output circuit diagnosis, port short circuit to power supply diagnosis, port short circuit to ground diagnosis and so on.
  • the MCU when the high-voltage circuit is well connected, that is, when the high-voltage interlocking loop is low impedance, the MCU outputs a PWM signal, and after amplifying the driving capability through the transmission gate U51, it returns to the circuit through the resistor R52 to the high-voltage interlocking loop.
  • the resistor R53 is filtered by the capacitor C51 and supplied to the watchdog chip U52.
  • the maximum voltage value of the waveform filtered by the capacitor C51 is higher than the high-level determination threshold VOH of the input signal of the watchdog chip, and the minimum voltage value of the waveform is lower than the low-level determination threshold VOL of the input signal of the watchdog chip.
  • the filtered waveform satisfies the dog timing requirement of the watchdog chip U52, and its Reset output is an inactive level.
  • the MCU detects the state of the Reset signal to know that the high voltage loop is well connected and can work normally.
  • the high-voltage interlocking loop When the high-voltage loop is connected, the high-voltage interlocking loop is also reflected as high impedance.
  • the MCU outputs a PWM signal, which is amplified by the transmission gate U51 and then passed through the resistor R52 to the high-voltage interlocking loop, but because the loop is high impedance, The signal cannot return to the R53 of the loop.
  • the waveform filtered by the capacitor C51 is a DC voltage, which cannot meet the dog timing requirement of the watchdog chip U52.
  • the Reset output is an active level, and the MCU detects the state of the Reset signal. It can be known that there is a problem with the connection of the high-voltage circuit, and then measures such as alarming and cutting off the output are taken.
  • the voltage of the input terminal of the watchdog U52 is close to 0.
  • the voltage is simultaneously supplied to the MCU for detection.
  • the MCU detects that the signal continues to approach 0, it is determined that the R43 outer port connection line is short-circuited to ground. .
  • the R43 outer port connection line is short-circuited to the positive supply terminal, for example, 12V or 24V
  • the input voltage of the watchdog U52 is close to VCC, and the voltage is simultaneously supplied to the MCU for detection.
  • the MCU detects that the signal continues to approach VCC, it determines that the R43 is connected outside. The line is shorted to the positive supply.
  • the second checkback module includes a first comparator and a second comparator, the non-inverting input of the first comparator is connected to the output of the second current limiting resistor, and the second comparator and the second comparator A comparator is connected in parallel, and an inverting input terminal of the second comparator is connected to an output terminal of the second current limiting resistor, and an outer port connection line of the second current limiting resistor is short-circuited to ground or short-circuited to the positive terminal of the power supply.
  • the MCU when the high-voltage circuit is well connected, that is, when the high-voltage interlocking loop is low impedance, the MCU outputs a PWM signal, and after amplifying the driving capability through the transmission gate U41, the resistor R42 is connected to the high-voltage interlocking loop, and then returned.
  • the resistor R43 to the circuit is filtered by the capacitor C41 and supplied to the watchdog chip U42.
  • the maximum voltage value of the waveform filtered by the capacitor C41 is higher than the high-level determination threshold VOH of the input signal of the watchdog chip, and the minimum voltage value of the waveform is lower than the low-level determination threshold VOL of the input signal of the watchdog chip.
  • the filtered waveform satisfies the dog timing requirement of the watchdog chip U42, and its Reset output is an inactive level.
  • the MCU detects the state of the Reset signal to know that the high voltage loop is well connected and can work normally.
  • the high-voltage interlocking loop When the high-voltage circuit is disconnected, the high-voltage interlocking loop also exhibits high impedance.
  • the MCU outputs a PWM signal, which is amplified by the transmission gate U41, and then passes through the resistor R42 to the high-voltage interlocking loop, but because the loop is high impedance, The signal cannot be returned to R43 of this circuit.
  • the waveform filtered by the capacitor C41 is a DC voltage, which cannot meet the dog timing requirement of the watchdog chip U42.
  • the Reset output is an active level, and the MCU detects the state of the Reset signal to know that there is a problem with the high voltage loop connection. In addition, measures such as alarming and cutting off the output are taken.
  • the comparator U43 When the R43 outer port connection line is short-circuited to ground, the voltage of the non-inverting input terminal of the comparator U43 is close to 0, lower than the set voltage V1, the comparator U43 outputs a pull-down alarm signal to the MCU, and the MCU detects the alarm signal and determines that it is outside the R43.
  • the port cable is shorted to ground.
  • the comparator U44 When the R43 outer port connection line is short-circuited to the power supply positive terminal, for example, 12V or 24V, the voltage of the inverting input terminal of the comparator U44 is close to VCC, which is higher than the set voltage V2, and the comparator U44 outputs a pull-down alarm signal to the MCU, and the MCU detects the alarm. The signal is determined to be shorted to the positive supply of R43.
  • the first check module and/or the second check module also includes a clamping diode, which is preferably a Schottky diode with a lower forward voltage drop for greater clamping protection.
  • the word “if” as used herein may be interpreted as “when” or “when” or “in response to a determination” or “in response to Detection”.
  • the phrase “if determined” or “if detected (conditions or events stated)” may be interpreted as “when determined” or “in response to determination” or “when detected (stated condition or event) “Time” or “in response to a test (condition or event stated)”.
  • the functional modules in the various embodiments of the present application may be integrated into one processing module, or each module may exist physically separately, or two or more modules may be integrated into one module.
  • the above integrated modules can be implemented in the form of hardware or in the form of hardware plus software function modules.

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  • General Physics & Mathematics (AREA)
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Abstract

A high-voltage interlock detection circuit, comprising: a high-voltage interlock loop having a loop input terminal and a loop output terminal; and a high-voltage interlock circuit, comprising a monitoring chip (U11) and a filter capacitor (C11) and having a pulse width modulation (PWM) signal output terminal and a signal back-check input terminal, the PWM signal output terminal being connected to the loop input terminal by means of a first current-limiting resistor (R11), and the loop output terminal being connected to the signal back-check input terminal by means of a second current-limiting resistor (R12). A PWM signal output from the PWM signal output terminal is returned back to the signal back-check input terminal by means of the high-voltage interlock loop, and is filtered by the filter capacitor (C11), and thereafter enters the monitoring chip (U11). Simplifying the high-voltage interlock detection circuit reduces occupation of MCU computing resources and reduces the requirements for MCU hardware port resources.

Description

高压互锁检测电路High voltage interlock detection circuit 技术领域Technical field
本申请涉及电路保护技术领域，尤其涉及一种高压互锁检测电路。The present application relates to the field of circuit protection technologies, and in particular, to a high voltage interlock detection circuit.
背景技术Background technique
高压供电电路的完整性是高压回路工作的基础，若高压回路不完整，如连接器未连接等，则回路无法正常工作，严重时甚至会造成部件损坏。The integrity of the high-voltage power supply circuit is the basis of the high-voltage circuit. If the high-voltage circuit is incomplete, if the connector is not connected, the circuit will not work properly, and even if it is serious, it will cause component damage.
相关技术中一般采用高压互锁电路来进行高压回路完整性的检测，高压互锁电路一般采用模拟型和数字型。模拟型指高压连接关系确定后，电路工作时的电位稳定不变的类型，例如，单纯的电阻分压型、光耦导通型等，但是，其抗干扰能力相对较差。In the related art, a high voltage interlock circuit is generally used for detecting the integrity of the high voltage loop, and the high voltage interlock circuit generally adopts an analog type and a digital type. The analog type refers to a type in which the potential of the circuit is stable after the high-voltage connection relationship is determined, for example, a simple resistor-divided type, an optocoupler-conducting type, etc., but its anti-interference ability is relatively poor.
数字型指高压连接关系确定后，电路工作时电位会周期性变化的类型，例如PWM输出型、通信网络回路型等。其中，对于通信网络回路型，若该通信网络仅用于高压互锁检测，则电路复杂成本高，若该通信网络同时也作为其他重要通信通道，则会使高压互锁和其他通信功能相互参杂，易产生相互影响，同时，实际应用时也会面临布线困难、干扰大等问题，故相关技术中采用PWM输出型的情况较多。The digital type refers to the type in which the potential of the circuit changes periodically after the high-voltage connection relationship is determined, such as the PWM output type and the communication network loop type. Among them, for the communication network loop type, if the communication network is only used for high-voltage interlock detection, the circuit is complicated and expensive, and if the communication network also serves as another important communication channel, the high-voltage interlock and other communication functions are mutually accustomed. Miscellaneous, it is easy to have mutual influence. At the same time, in practical applications, it also faces difficulties in wiring and interference, so the PWM output type is often used in related technologies.
因此，如何降低高压互锁检测电路的复杂度，减少测试成本，成为目前亟待解决的技术问题。Therefore, how to reduce the complexity of the high voltage interlock detection circuit and reduce the test cost has become a technical problem to be solved.
发明内容Summary of the invention
本申请实施例提供了一种高压互锁检测电路，旨在解决如何降低高压互锁检测电路的复杂度的技术问题，能够简化高压互锁检测电路，从而减少测试成本。The embodiment of the present application provides a high voltage interlock detection circuit, which aims to solve the technical problem of how to reduce the complexity of the high voltage interlock detection circuit, and can simplify the high voltage interlock detection circuit, thereby reducing the test cost.
一方面，本申请实施例提供了一种高压互锁检测电路，包括：高压互锁 环路，所述高压互锁环路具有环路输入端和环路输出端；高压互锁电路，所述高压互锁电路具有PWM信号输出端和信号回检输入端，所述PWM信号输出端经第一限流电阻与所述环路输入端连通，所述环路输出端经第二限流电阻与所述信号回检输入端连通，其中，所述高压互锁电路包括监控芯片和滤波电容，所述监控芯片和所述滤波电容与所述信号回检输入端连通，所述PWM信号输出端输出的PWM信号经所述高压互锁环路返回所述信号回检输入端，并经所述滤波电容滤波后进入所述监控芯片。In one aspect, the embodiment of the present application provides a high voltage interlock detection circuit, including: high voltage interlock a loop, the high voltage interlocking loop has a loop input end and a loop output end; a high voltage interlock circuit having a PWM signal output end and a signal check input end, the PWM signal output end The first current limiting resistor is connected to the loop input end, and the loop output end is connected to the signal check input terminal via a second current limiting resistor, wherein the high voltage interlock circuit includes a monitoring chip and filtering Capacitor, the monitoring chip and the filter capacitor are connected to the signal check input end, and the PWM signal outputted by the PWM signal output end is returned to the signal check input end via the high voltage interlock loop, and The filter capacitor is filtered and then enters the monitoring chip.
在本申请上述实施例中，所述高压互锁电路还包括：反相器，位于所述PWM信号输出端和所述第一限流电阻之间。In the above embodiment of the present application, the high voltage interlock circuit further includes: an inverter between the PWM signal output end and the first current limiting resistor.
在本申请上述实施例中，所述高压互锁电路还包括：传输门，位于所述PWM信号输出端和所述第一限流电阻之间。In the above embodiment of the present application, the high voltage interlock circuit further includes: a transmission gate located between the PWM signal output end and the first current limiting resistor.
在本申请上述实施例中，所述高压互锁电路还包括：第一回检模块，所述第一回检模块的一端连接在所述第一限流电阻与所述环路输入端之间，另一端连接至所述信号回检输入端。In the above embodiment of the present application, the high voltage interlock circuit further includes: a first checkback module, one end of the first checkback module is connected between the first current limiting resistor and the loop input end The other end is connected to the signal check input.
在本申请上述实施例中，所述第一回检模块还包括第三限流电阻。In the above embodiment of the present application, the first checkback module further includes a third current limiting resistor.
在本申请上述实施例中，所述第一限流电阻、所述第二限流电阻和所述第三限流电阻的阻值大于或等于100欧姆。In the above embodiment of the present application, the resistances of the first current limiting resistor, the second current limiting resistor, and the third current limiting resistor are greater than or equal to 100 ohms.
在本申请上述实施例中，所述高压互锁电路还包括：第二回检模块，所述第二回检模块的一端连接至所述第二限流电阻的输出端，另一端连接至所述信号回检输入端，与所述监控芯片并联。In the above embodiment of the present application, the high voltage interlock circuit further includes: a second checkback module, one end of the second checkback module is connected to the output end of the second current limiting resistor, and the other end is connected to the The signal check input is connected in parallel with the monitoring chip.
在本申请上述实施例中，所述第二回检模块包括：第一比较器，所述第一比较器的同相输入端连接至所述第二限流电阻的输出端；第二比较器，与所述第一比较器并联，所述第二比较器的反相输入端连接至所述第二限流电阻的输出端；以及所述第二限流电阻的外侧端口连接线短路到地或短路到供电正极。In the above embodiment of the present application, the second checkback module includes: a first comparator, a non-inverting input end of the first comparator is connected to an output end of the second current limiting resistor; and a second comparator In parallel with the first comparator, an inverting input of the second comparator is coupled to an output of the second current limiting resistor; and an outer port connection of the second current limiting resistor is shorted to ground or Short circuit to the positive supply.
在本申请上述实施例中，所述第一回检模块和/或所述第二回检模块还包 括箝位二极管。In the foregoing embodiment of the present application, the first back check module and/or the second check module further includes Includes clamp diodes.
在本申请上述实施例中，所述箝位二极管为肖特基二极管。In the above embodiment of the present application, the clamping diode is a Schottky diode.
针对相关技术中的高压互锁检测电路的复杂度较高等问题，可在高压互锁电路的信号回检输入端增加监控芯片(看门狗芯片)。In view of the high complexity of the high voltage interlock detection circuit in the related art, the monitoring chip (watchdog chip) can be added to the signal return input end of the high voltage interlock circuit.
具体来说，高压回路连接良好即高压互锁环路为低阻抗时，高压互锁电路中MCU(微控制单元)输出的PWM(脉冲宽度调制)信号经第一限流电阻至高压互锁环路，再回到本电路的第二限流电阻，经滤波电容滤波后给到监控芯片，经滤波电容滤波后的波形最大电压值高于监控芯片输入信号的高电平判定阀值，波形最小电压值低于监控芯片输入信号的低电平判定阀值。经滤波后的波形满足监控芯片的喂狗时序要求，其Reset(复位)输出为无效电平，MCU检测该Reset信号的状态即可得知高压回路连接良好，可以正常工作。Specifically, when the high voltage loop is well connected, that is, when the high voltage interlock loop is low impedance, the PWM (Pulse Width Modulation) signal output by the MCU (micro control unit) in the high voltage interlock circuit passes through the first current limiting resistor to the high voltage interlocking loop. The circuit then returns to the second current limiting resistor of the circuit, which is filtered by the filter capacitor and then sent to the monitoring chip. The maximum voltage value of the waveform filtered by the filter capacitor is higher than the high level threshold of the input signal of the monitoring chip, and the waveform is minimum. The voltage value is lower than the low level decision threshold of the monitor chip input signal. The filtered waveform satisfies the dog feed timing requirement of the monitoring chip, and its Reset output is an inactive level. The MCU detects the state of the Reset signal to know that the high voltage loop is well connected and can work normally.
而高压回路连接断路时，高压互锁环路为高阻抗，MCU输出PWM信号经第一限流电阻至高压互锁环路，但因为该环路为高阻抗，信号无法回到本回路的第二限流电阻。经滤波电容滤波后的波形为某直流电压，无法满足监控芯片的喂狗时序要求，其Reset输出为有效电平，MCU检测该Reset信号的状态即可得知高压回路连接出现问题，进而可以采取报警、切断输出等措施。When the high voltage loop is disconnected, the high voltage interlock loop is high impedance, and the MCU outputs the PWM signal through the first current limiting resistor to the high voltage interlock loop, but because the loop is high impedance, the signal cannot return to the loop. Two current limiting resistors. The waveform filtered by the filter capacitor is a DC voltage, which cannot meet the timing requirement of the monitoring chip. The Reset output is an active level, and the MCU detects the state of the Reset signal to know that there is a problem with the connection of the high voltage loop, and thus can be taken. Measures such as alarming and cutting off the output.
通过以上技术方案，采用单路PWM输出和监控芯片，以简化高压互锁检测电路，MCU仅检测看门狗输出的电平信号，减少了MCU运算资源占用，并且，MCU检测输出仅使用通用数字输入口即可，降低了对MCU硬件端口资源的要求。Through the above technical solution, a single PWM output and monitoring chip is used to simplify the high voltage interlock detection circuit, the MCU only detects the level signal of the watchdog output, reduces the occupation of the MCU computing resources, and the MCU detection output uses only the general number. The input port can be used, which reduces the requirements for the MCU hardware port resources.
附图说明DRAWINGS
为了更清楚地说明本申请实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的 一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其它的附图。In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings to be used in the embodiments will be briefly described below. It is obvious that the drawings in the following description are only the present application. For some embodiments, other drawings may be obtained from those skilled in the art without departing from the drawings.
图1示出了根据本申请的一个实施例的高压互锁检测电路的电路图；1 shows a circuit diagram of a high voltage interlock detection circuit in accordance with one embodiment of the present application;
图2示出了根据本申请的另一个实施例的高压互锁检测电路的电路图；2 shows a circuit diagram of a high voltage interlock detection circuit in accordance with another embodiment of the present application;
图3示出了根据本申请的再一个实施例的高压互锁检测电路的电路图；3 shows a circuit diagram of a high voltage interlock detection circuit in accordance with still another embodiment of the present application;
图4示出了根据本申请的还一个实施例的高压互锁检测电路的电路图；4 shows a circuit diagram of a high voltage interlock detection circuit in accordance with yet another embodiment of the present application;
图5示出了根据本申请的又一个实施例的高压互锁检测电路的电路图。FIG. 5 shows a circuit diagram of a high voltage interlock detection circuit in accordance with yet another embodiment of the present application.
具体实施方式detailed description
为了更好的理解本申请的技术方案，下面结合附图对本申请实施例进行详细描述。For a better understanding of the technical solutions of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.
应当明确，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其它实施例，都属于本申请保护的范围。It should be understood that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present application without departing from the inventive scope are the scope of the present application.
本申请实施例提供的高压互锁检测电路包括高压互锁环路和高压互锁电路，高压互锁环路具有环路输入端和环路输出端，高压互锁电路具有PWM信号输出端和信号回检输入端，PWM信号输出端经第一限流电阻与环路输入端连通，环路输出端经第二限流电阻与信号回检输入端连通，其中，高压互锁电路包括监控芯片和滤波电容，监控芯片和滤波电容与信号回检输入端连通，PWM信号输出端输出的PWM信号经高压互锁环路返回信号回检输入端，并经滤波电容滤波后进入监控芯片。The high voltage interlock detection circuit provided by the embodiment of the present application includes a high voltage interlock loop and a high voltage interlock circuit. The high voltage interlock loop has a loop input end and a loop output end, and the high voltage interlock circuit has a PWM signal output end and a signal. The PWM signal output end is connected to the loop input end via a first current limiting resistor, and the loop output end is connected to the signal check input end via a second current limiting resistor, wherein the high voltage interlock circuit includes a monitoring chip and The filter capacitor, the monitor chip and the filter capacitor are connected with the signal check input terminal, and the PWM signal outputted from the PWM signal output terminal is returned to the signal detection input terminal through the high voltage interlock loop, and filtered by the filter capacitor to enter the monitor chip.
针对相关技术中的高压互锁检测电路的复杂度较高等问题，可在高压互锁电路的信号回检输入端增加监控芯片(看门狗芯片)。In view of the high complexity of the high voltage interlock detection circuit in the related art, the monitoring chip (watchdog chip) can be added to the signal return input end of the high voltage interlock circuit.
图1示出了根据本申请的一个实施例的高压互锁检测电路的电路图。FIG. 1 shows a circuit diagram of a high voltage interlock detection circuit in accordance with one embodiment of the present application.
如图1所示，高压回路连接良好即高压互锁环路为低阻抗时，MCU输出PWM信号经电阻R11至高压互锁环路，再回到本电路的R12，经C11滤 波后给到看门狗芯片。As shown in Figure 1, when the high voltage loop is well connected, that is, when the high voltage interlock loop is low impedance, the MCU outputs the PWM signal through the resistor R11 to the high voltage interlock loop, and then returns to the R12 of the circuit, and is filtered by the C11. The wave is given to the watchdog chip.
经C11滤波后的波形最大电压值高于看门狗芯片输入信号的高电平判定阀值VOH，波形最小电压值低于看门狗芯片输入信号的低电平判定阀值VOL。经滤波后的波形满足看门狗芯片U11的喂狗时序要求，其Reset输出为无效电平，MCU检测该Reset信号的状态即可得知高压回路连接良好，可以正常工作。The maximum voltage value of the waveform filtered by C11 is higher than the high-level determination threshold VOH of the input signal of the watchdog chip, and the minimum voltage value of the waveform is lower than the low-level determination threshold VOL of the input signal of the watchdog chip. The filtered waveform satisfies the dog timing requirement of the watchdog chip U11, and its Reset output is an inactive level. The MCU detects the state of the Reset signal to know that the high voltage loop is well connected and can work normally.
高压回路连接断路时，高压互锁环路也体现为高阻抗，MCU输出PWM信号经电阻R11至高压互锁环路，但因为该环路为高阻抗，信号无法回到本回路的R12，经C11滤波后的波形为某直流电压，无法满足看门狗芯片U11的喂狗时序要求，其Reset输出为有效电平，MCU检测该Reset信号的状态即可得知高压回路连接出现问题，进而采取报警、切断输出等措施。When the high voltage loop is disconnected, the high voltage interlock loop also exhibits high impedance. The MCU outputs a PWM signal through the resistor R11 to the high voltage interlock loop, but because the loop is high impedance, the signal cannot return to the R12 of the loop. The waveform after C11 filtering is a DC voltage, which cannot meet the dog timing requirement of the watchdog chip U11. The Reset output is an active level, and the MCU detects the state of the Reset signal to know that there is a problem in the connection of the high voltage loop, and then takes Measures such as alarming and cutting off the output.
通过以上技术方案，采用单路PWM输出和监控芯片，以简化高压互锁检测电路，MCU仅检测看门狗输出的电平信号，减少了MCU运算资源占用，并且，MCU检测输出仅使用通用数字输入口即可，降低了对MCU硬件端口资源的要求。Through the above technical solution, a single PWM output and monitoring chip is used to simplify the high voltage interlock detection circuit, the MCU only detects the level signal of the watchdog output, reduces the occupation of the MCU computing resources, and the MCU detection output uses only the general number. The input port can be used, which reduces the requirements for the MCU hardware port resources.
需要补充的是，电容C11的取值要结合RC时间常数进行选取，使其与MCU输出PWM的周期的一半接近，这样能最大程度滤波增强抗扰度，并有利于支持进行高压互锁接口的短路到地、短路到电源等诊断It should be added that the value of the capacitor C11 should be selected in combination with the RC time constant to be close to half of the period of the MCU output PWM, so as to maximize the filtering of the enhanced immunity and facilitate the support of the high voltage interlock interface. Short circuit to ground, short circuit to power supply, etc.
如图2所示，高压回路连接良好即高压互锁环路为低阻抗时，MCU输出PWM信号，经反相器U21放大驱动能力后，经电阻R22至高压互锁环路，再回到本电路的R23，经电容C21滤波后给到看门狗芯片U22。As shown in Figure 2, when the high-voltage loop is well connected, that is, when the high-voltage interlock loop is low impedance, the MCU outputs a PWM signal, which is amplified by the inverter U21, and then returns to the high-voltage interlock loop through the resistor R22. The R23 of the circuit is filtered by the capacitor C21 and supplied to the watchdog chip U22.
其中，反相器U21位于PWM信号输出端和R22之间，用于放大驱动能力，这样，使电路可以有更强的PWM输出能力，便于完成PWM的输出电路诊断。The inverter U21 is located between the PWM signal output terminal and R22 for amplifying the driving capability, so that the circuit can have a stronger PWM output capability, and is convenient for completing the PWM output circuit diagnosis.
经电容C21滤波后的波形最大电压值高于看门狗芯片输入信号的高电平判定阀值VOH，波形最小电压值低于看门狗芯片输入信号的低电平判定阀 值VOL。经滤波后的波形满足看门狗芯片U22的喂狗时序要求，其Reset输出为无效电平，MCU检测该Reset信号的状态即可得知高压回路连接良好，可以正常工作。The maximum voltage value of the waveform filtered by the capacitor C21 is higher than the high-level determination threshold VOH of the input signal of the watchdog chip, and the minimum voltage value of the waveform is lower than the low-level determination valve of the input signal of the watchdog chip. Value VOL. The filtered waveform satisfies the dog timing requirement of the watchdog chip U22, and its Reset output is an inactive level. The MCU detects the state of the Reset signal to know that the high voltage loop is well connected and can work normally.
高压回路连接断路时，高压互锁环路也体现为高阻抗，MCU输出PWM信号，经反相器U21放大驱动能力后，经电阻R22至高压互锁环路，但因为该环路为高阻抗，信号无法回到本回路的R23。经电容C21滤波后的波形为某直流电压，无法满足看门狗芯片U22的喂狗时序要求，其Reset输出为有效电平，MCU检测该Reset信号的状态即可得知高压回路连接出现问题，进而采取报警、切断输出等措施。When the high voltage loop is disconnected, the high voltage interlock loop also exhibits high impedance. The MCU outputs a PWM signal, which is amplified by the inverter U21 and then passed through the resistor R22 to the high voltage interlock loop, but because the loop is high impedance. The signal cannot return to R23 of this circuit. The waveform filtered by the capacitor C21 is a DC voltage, which cannot meet the dog timing requirement of the watchdog chip U22, and the Reset output is an active level, and the MCU detects the state of the Reset signal to know that there is a problem in the connection of the high voltage loop. In addition, measures such as alarming and cutting off the output are taken.
需要补充的是，电容C21的取值要结合RC时间常数进行选取，使其与MCU输出PWM的周期的一半接近，这样能最大程度滤波增强抗扰度，并有利于支持进行高压互锁接口的短路到地、短路到电源等诊断It should be added that the value of the capacitor C21 should be selected in combination with the RC time constant to be close to half of the period of the MCU output PWM, so as to maximize the filtering of the enhanced immunity and facilitate the support of the high voltage interlock interface. Short circuit to ground, short circuit to power supply, etc.
如图3所示，高压回路连接良好即高压互锁环路为低阻抗时，MCU输出PWM信号，经传输门U31放大驱动能力后，经电阻R32至高压互锁环路，再回到本电路的电阻R33，经电容C31滤波后给到看门狗芯片U32。As shown in Fig. 3, when the high-voltage circuit is well connected, that is, when the high-voltage interlocking loop is low impedance, the MCU outputs a PWM signal, and after amplifying the driving capability through the transmission gate U31, it returns to the circuit through the resistor R32 to the high-voltage interlocking loop. The resistor R33 is filtered by the capacitor C31 and supplied to the watchdog chip U32.
其中，传输门U31位于PWM信号输出端和R22之间，用于放大驱动能力，这样，使电路可以有更强的PWM输出能力，便于完成PWM的输出电路诊断。The transmission gate U31 is located between the PWM signal output end and R22 for amplifying the driving capability, so that the circuit can have a stronger PWM output capability, and is convenient for completing the PWM output circuit diagnosis.
经电容C31滤波后的波形最大电压值高于看门狗芯片输入信号的高电平判定阀值VOH，波形最小电压值低于看门狗芯片输入信号的低电平判定阀值VOL。经滤波后的波形满足看门狗芯片U32的喂狗时序要求，其Reset输出为无效电平，MCU检测该Reset信号的状态即可得知高压回路连接良好，可以正常工作。The maximum voltage value of the waveform filtered by the capacitor C31 is higher than the high-level determination threshold VOH of the input signal of the watchdog chip, and the minimum voltage value of the waveform is lower than the low-level determination threshold VOL of the input signal of the watchdog chip. The filtered waveform satisfies the dog feed timing requirement of the watchdog chip U32, and its Reset output is an inactive level. The MCU detects the state of the Reset signal to know that the high voltage loop is well connected and can work normally.
高压回路连接断路时，高压互锁环路也体现为高阻抗，MCU输出PWM信号，经传输门U31放大驱动能力后，经电阻R32至高压互锁环路，但因为该环路的高阻抗，信号无法回到本回路的R33。经电容C31滤波后的波形为 某直流电压，无法满足看门狗芯片U32的喂狗时序要求，其Reset输出为有效电平，MCU检测该Reset信号的状态即可得知高压回路连接出现问题，进而采取报警、切断输出等措施。When the high-voltage circuit is connected to open circuit, the high-voltage interlocking loop is also embodied as high impedance. The MCU outputs a PWM signal, which is amplified by the transmission gate U31 and then passed through the resistor R32 to the high-voltage interlocking loop, but because of the high impedance of the loop, The signal cannot return to R33 of this circuit. The waveform filtered by capacitor C31 is A DC voltage cannot meet the dog timing requirement of the watchdog chip U32, and its Reset output is an active level. The MCU detects the state of the Reset signal to know that there is a problem with the connection of the high voltage circuit, and then takes measures such as alarming and cutting off the output. .
需要补充的是，电容C31的取值要结合RC时间常数进行选取，使其与MCU输出PWM的周期的一半接近，这样能最大程度滤波增强抗扰度，并有利于支持进行高压互锁接口的短路到地、短路到电源等诊断It should be added that the value of the capacitor C31 should be selected in combination with the RC time constant to be close to half of the period of the MCU output PWM, so as to maximize the filtering of the enhanced immunity and facilitate the support of the high voltage interlock interface. Short circuit to ground, short circuit to power supply, etc.
在本申请的一个实施例中，在高压互锁检测电路中还可以包括第一回检模块，第一回检模块的一端连接在第一限流电阻与环路输入端之间，另一端连接至信号回检输入端。In an embodiment of the present application, the first checkback module may be further included in the high voltage interlock detection circuit, and one end of the first checkback module is connected between the first current limiting resistor and the loop input end, and the other end is connected. To the signal check input.
具体地，在图2中，当MCU输出的PWM信号经R22输出的同时，可以经由电阻R21被MCU回检，并与当前PWM输出状态对比即可得知输出电路是否出现了故障。Specifically, in FIG. 2, when the PWM signal output by the MCU is output through R22, it can be checked back by the MCU via the resistor R21, and compared with the current PWM output state, it can be known whether the output circuit has a fault.
其中，R21、R22和R23的阻值大于或等于100欧姆，这样可以将输出电流限制在较小的范围以防输出功率过大损坏电路，也可以在断开有短路到电源等异常时限制输入电流从而保护电路不致损坏。Among them, the resistance of R21, R22 and R23 is greater than or equal to 100 ohms, so that the output current can be limited to a small range to prevent the output power from being too large to damage the circuit, or to limit the input when there is an abnormality such as short circuit to power supply. The current thus protects the circuit from damage.
在图3中，当MCU输出的PWM信号经R32输出的同时，可以经由电阻R31被MCU回检，并与当前PWM输出状态对比即可得知输出电路是否出现了故障。In FIG. 3, when the PWM signal output by the MCU is output through R32, it can be checked back by the MCU via the resistor R31, and compared with the current PWM output state, it can be known whether the output circuit has a fault.
需要补充的是，R31、R32和R33的阻值大于或等于100欧姆，这样可以将输出电流限制在较小的范围以防输出功率过大损坏电路，也可以在断开有短路到电源等异常时限制输入电流从而保护电路不致损坏。It should be added that the resistance values of R31, R32 and R33 are greater than or equal to 100 ohms, so that the output current can be limited to a small range to prevent the output power from being too large to damage the circuit, or to disconnect the short circuit to the power supply. The input current is limited to protect the circuit from damage.
在本申请的一个实施例中，高压互锁检测电路中还可以包括第二回检模块，第二回检模块的一端连接至第二限流电阻的输出端，另一端连接至信号回检输入端，与监控芯片并联。这样，可以有更强的PWM输出能力，以及可以完成PWM的输出电路诊断、端口短路到电源诊断、端口短路到地诊断等。 In an embodiment of the present application, the high voltage interlock detection circuit may further include a second checkback module, one end of the second checkback module is connected to the output end of the second current limiting resistor, and the other end is connected to the signal check input. End, in parallel with the monitoring chip. In this way, it can have stronger PWM output capability, and can complete PWM output circuit diagnosis, port short circuit to power supply diagnosis, port short circuit to ground diagnosis and so on.
如图4所示，高压回路连接良好即高压互锁环路为低阻抗时，MCU输出PWM信号，经传输门U51放大驱动能力后，经电阻R52至高压互锁环路，再回到本电路的电阻R53，经电容C51滤波后给到看门狗芯片U52。As shown in Figure 4, when the high-voltage circuit is well connected, that is, when the high-voltage interlocking loop is low impedance, the MCU outputs a PWM signal, and after amplifying the driving capability through the transmission gate U51, it returns to the circuit through the resistor R52 to the high-voltage interlocking loop. The resistor R53 is filtered by the capacitor C51 and supplied to the watchdog chip U52.
经电容C51滤波后的波形最大电压值高于看门狗芯片输入信号的高电平判定阀值VOH，波形最小电压值低于看门狗芯片输入信号的低电平判定阀值VOL。经滤波后的波形满足看门狗芯片U52的喂狗时序要求，其Reset输出为无效电平，MCU检测该Reset信号的状态即可得知高压回路连接良好，可以正常工作。The maximum voltage value of the waveform filtered by the capacitor C51 is higher than the high-level determination threshold VOH of the input signal of the watchdog chip, and the minimum voltage value of the waveform is lower than the low-level determination threshold VOL of the input signal of the watchdog chip. The filtered waveform satisfies the dog timing requirement of the watchdog chip U52, and its Reset output is an inactive level. The MCU detects the state of the Reset signal to know that the high voltage loop is well connected and can work normally.
高压回路连接断路时，高压互锁环路也体现为高阻抗，MCU输出PWM信号，经传输门U51放大驱动能力后，经电阻R52至高压互锁环路，但因为该环路为高阻抗，信号无法回到本回路的R53，经电容C51滤波后的波形为某直流电压，无法满足看门狗芯片U52的喂狗时序要求，其Reset输出为有效电平，MCU检测该Reset信号的状态即可得知高压回路连接出现问题，进而采取报警、切断输出等措施。When the high-voltage loop is connected, the high-voltage interlocking loop is also reflected as high impedance. The MCU outputs a PWM signal, which is amplified by the transmission gate U51 and then passed through the resistor R52 to the high-voltage interlocking loop, but because the loop is high impedance, The signal cannot return to the R53 of the loop. The waveform filtered by the capacitor C51 is a DC voltage, which cannot meet the dog timing requirement of the watchdog chip U52. The Reset output is an active level, and the MCU detects the state of the Reset signal. It can be known that there is a problem with the connection of the high-voltage circuit, and then measures such as alarming and cutting off the output are taken.
当MCU输出的PWM信号经R52输出的同时，可以经由电阻R51被MCU回检，并与当前PWM输出状态对比即可得知输出电路是否出现了故障。When the PWM signal output by the MCU is output through R52, it can be checked back by the MCU via the resistor R51, and compared with the current PWM output state, it can be known whether the output circuit has a fault.
当R53外侧端口连接线短路到地时，看门狗U52的输入端电压接近0，该电压同时提供给MCU进行检测，MCU检测到该信号持续接近0则判定为R43外侧端口连接线短路到地。When the R53 outer port connection line is short-circuited to ground, the voltage of the input terminal of the watchdog U52 is close to 0. The voltage is simultaneously supplied to the MCU for detection. When the MCU detects that the signal continues to approach 0, it is determined that the R43 outer port connection line is short-circuited to ground. .
当R43外侧端口连接线短路到供电正极例如12V或24V时，看门狗U52的输入端电压接近VCC，该电压同时提供给MCU进行检测，MCU检测到该信号持续接近VCC则判定为R43外侧连接线短路到供电正极。When the R43 outer port connection line is short-circuited to the positive supply terminal, for example, 12V or 24V, the input voltage of the watchdog U52 is close to VCC, and the voltage is simultaneously supplied to the MCU for detection. When the MCU detects that the signal continues to approach VCC, it determines that the R43 is connected outside. The line is shorted to the positive supply.
在本申请的一个实施例中，第二回检模块包括第一比较器和第二比较器，第一比较器的同相输入端连接至第二限流电阻的输出端，第二比较器与第一比较器并联，第二比较器的反相输入端连接至第二限流电阻的输出端，第二限流电阻的外侧端口连接线短路到地或短路到供电正极。 In an embodiment of the present application, the second checkback module includes a first comparator and a second comparator, the non-inverting input of the first comparator is connected to the output of the second current limiting resistor, and the second comparator and the second comparator A comparator is connected in parallel, and an inverting input terminal of the second comparator is connected to an output terminal of the second current limiting resistor, and an outer port connection line of the second current limiting resistor is short-circuited to ground or short-circuited to the positive terminal of the power supply.
这样，可以有更强的PWM输出能力，以及可以完成PWM的输出电路诊断、端口短路到电源诊断、端口短路到地诊断等。具体地，如图5所示，高压回路连接良好即高压互锁环路为低阻抗时，MCU输出PWM信号，经传输门U41放大驱动能力后，经电阻R42至高压互锁环路，再回到本电路的电阻R43，经电容C41滤波后给到看门狗芯片U42。In this way, it can have stronger PWM output capability, and can complete PWM output circuit diagnosis, port short circuit to power supply diagnosis, port short circuit to ground diagnosis and so on. Specifically, as shown in FIG. 5, when the high-voltage circuit is well connected, that is, when the high-voltage interlocking loop is low impedance, the MCU outputs a PWM signal, and after amplifying the driving capability through the transmission gate U41, the resistor R42 is connected to the high-voltage interlocking loop, and then returned. The resistor R43 to the circuit is filtered by the capacitor C41 and supplied to the watchdog chip U42.
经电容C41滤波后的波形最大电压值高于看门狗芯片输入信号的高电平判定阀值VOH，波形最小电压值低于看门狗芯片输入信号的低电平判定阀值VOL。经滤波后的波形满足看门狗芯片U42的喂狗时序要求，其Reset输出为无效电平，MCU检测该Reset信号的状态即可得知高压回路连接良好，可以正常工作。The maximum voltage value of the waveform filtered by the capacitor C41 is higher than the high-level determination threshold VOH of the input signal of the watchdog chip, and the minimum voltage value of the waveform is lower than the low-level determination threshold VOL of the input signal of the watchdog chip. The filtered waveform satisfies the dog timing requirement of the watchdog chip U42, and its Reset output is an inactive level. The MCU detects the state of the Reset signal to know that the high voltage loop is well connected and can work normally.
高压回路连接断路时，高压互锁环路也体现为高阻抗，MCU输出PWM信号，经传输门U41放大驱动能力后，经电阻R42至高压互锁环路，但因为该环路为高阻抗，信号无法回到本回路的R43。经电容C41滤波后的波形为某直流电压，无法满足看门狗芯片U42的喂狗时序要求，其Reset输出为有效电平，MCU检测该Reset信号的状态即可得知高压回路连接出现问题，进而采取报警、切断输出等措施。When the high-voltage circuit is disconnected, the high-voltage interlocking loop also exhibits high impedance. The MCU outputs a PWM signal, which is amplified by the transmission gate U41, and then passes through the resistor R42 to the high-voltage interlocking loop, but because the loop is high impedance, The signal cannot be returned to R43 of this circuit. The waveform filtered by the capacitor C41 is a DC voltage, which cannot meet the dog timing requirement of the watchdog chip U42. The Reset output is an active level, and the MCU detects the state of the Reset signal to know that there is a problem with the high voltage loop connection. In addition, measures such as alarming and cutting off the output are taken.
当MCU输出的PWM信号经R42输出的同时，可以经由电阻R41被MCU回检，并与当前PWM输出状态对比即可得知输出电路是否出现了故障。When the PWM signal output by the MCU is output through R42, it can be checked back by the MCU via the resistor R41, and compared with the current PWM output state, it can be known whether the output circuit has a fault.
当R43外侧端口连接线短路到地时，比较器U43的同相输入端电压接近0，低于设定电压V1，比较器U43输出下拉报警信号给MCU，MCU检测到该报警信号则判定为R43外侧端口连接线短路到地。When the R43 outer port connection line is short-circuited to ground, the voltage of the non-inverting input terminal of the comparator U43 is close to 0, lower than the set voltage V1, the comparator U43 outputs a pull-down alarm signal to the MCU, and the MCU detects the alarm signal and determines that it is outside the R43. The port cable is shorted to ground.
当R43外侧端口连接线短路到供电正极例如12V或24V时，比较器U44的反相输入端电压接近VCC，高于设定电压V2，比较器U44输出下拉报警信号给MCU，MCU检测到该报警信号则判定为R43外侧连接线短路到供电正极。When the R43 outer port connection line is short-circuited to the power supply positive terminal, for example, 12V or 24V, the voltage of the inverting input terminal of the comparator U44 is close to VCC, which is higher than the set voltage V2, and the comparator U44 outputs a pull-down alarm signal to the MCU, and the MCU detects the alarm. The signal is determined to be shorted to the positive supply of R43.
需要补充的是，在本申请上述实施例中，第一回检模块和/或第二回检模 块还包括箝位二极管，箝位二极管优选为肖特基二极管，其较低的正向导通压降使其具有更强的箝位保护能力。It should be noted that, in the above embodiment of the present application, the first check module and/or the second check module The block also includes a clamping diode, which is preferably a Schottky diode with a lower forward voltage drop for greater clamping protection.
以上结合附图详细说明了本申请的技术方案，通过本申请的技术方案，采用单路PWM输出和监控芯片，以简化高压互锁检测电路，MCU仅检测看门狗输出的电平信号，减少了MCU运算资源占用，并且，MCU检测输出仅使用通用数字输入口即可，降低了对MCU硬件端口资源的要求。The technical solution of the present application is described in detail above with reference to the accompanying drawings. By adopting the technical solution of the present application, a single PWM output and monitoring chip is adopted to simplify the high voltage interlock detection circuit, and the MCU only detects the level signal of the watchdog output, and reduces The MCU computing resource is occupied, and the MCU detection output only uses the universal digital input port, which reduces the requirement for the MCU hardware port resource.
在本申请实施例中使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本申请。在本申请实施例和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。The terms used in the embodiments of the present application are for the purpose of describing particular embodiments only, and are not intended to limit the application. The singular forms "a", "the", and "the"
应当理解，本文中使用的术语“和/或”仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系。It should be understood that the term "and/or" as used herein is merely an association describing the associated object, indicating that there may be three relationships, for example, A and/or B, which may indicate that A exists separately, while A and B, there are three cases of B alone. In addition, the character "/" in this article generally indicates that the contextual object is an "or" relationship.
取决于语境，如在此所使用的词语“如果”可以被解释成为“在......时”或“当......时”或“响应于确定”或“响应于检测”。类似地，取决于语境，短语“如果确定”或“如果检测(陈述的条件或事件)”可以被解释成为“当确定时”或“响应于确定”或“当检测(陈述的条件或事件)时”或“响应于检测(陈述的条件或事件)”。Depending on the context, the word "if" as used herein may be interpreted as "when" or "when" or "in response to a determination" or "in response to Detection". Similarly, depending on the context, the phrase "if determined" or "if detected (conditions or events stated)" may be interpreted as "when determined" or "in response to determination" or "when detected (stated condition or event) "Time" or "in response to a test (condition or event stated)".
在本申请各个实施例中的各功能模块可以集成在一个处理模块中，也可以是各个模块单独物理存在，也可以两个或两个以上模块集成在一个模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用硬件加软件功能模块的形式实现。The functional modules in the various embodiments of the present application may be integrated into one processing module, or each module may exist physically separately, or two or more modules may be integrated into one module. The above integrated modules can be implemented in the form of hardware or in the form of hardware plus software function modules.
以上所述仅为本申请的较佳实施例而已，并不用以限制本申请，凡在本申请的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本申请保护的范围之内。 The above is only the preferred embodiment of the present application, and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc., which are made within the spirit and principles of the present application, should be included in the present application. Within the scope of protection.

Claims (10)

  1. 一种高压互锁检测电路，其特征在于，包括：A high voltage interlock detection circuit, comprising:
    高压互锁环路，所述高压互锁环路具有环路输入端和环路输出端；a high voltage interlocking loop having a loop input end and a loop output end;
    高压互锁电路，所述高压互锁电路具有PWM信号输出端和信号回检输入端，所述PWM信号输出端经第一限流电阻与所述环路输入端连通，所述环路输出端经第二限流电阻与所述信号回检输入端连通，其中，a high voltage interlock circuit having a PWM signal output end and a signal check input end, wherein the PWM signal output end is connected to the loop input end via a first current limiting resistor, the loop output end Connected to the signal return input through a second current limiting resistor, wherein
    所述高压互锁电路包括监控芯片和滤波电容，所述监控芯片和所述滤波电容与所述信号回检输入端连通，所述PWM信号输出端输出的PWM信号经所述高压互锁环路返回所述信号回检输入端，并经所述滤波电容滤波后进入所述监控芯片。The high voltage interlock circuit includes a monitoring chip and a filter capacitor, the monitor chip and the filter capacitor are connected to the signal check input end, and the PWM signal outputted by the PWM signal output end passes through the high voltage interlock loop Returning to the signal check input terminal, and filtering through the filter capacitor to enter the monitoring chip.
  2. 根据权利要求1所述的高压互锁检测电路，其特征在于，所述高压互锁电路还包括：The high voltage interlock detection circuit according to claim 1, wherein the high voltage interlock circuit further comprises:
    反相器，位于所述PWM信号输出端和所述第一限流电阻之间。An inverter is disposed between the PWM signal output terminal and the first current limiting resistor.
  3. 根据权利要求1所述的高压互锁检测电路，其特征在于，所述高压互锁电路还包括：The high voltage interlock detection circuit according to claim 1, wherein the high voltage interlock circuit further comprises:
    传输门，位于所述PWM信号输出端和所述第一限流电阻之间。a transmission gate is located between the PWM signal output terminal and the first current limiting resistor.
  4. 根据权利要求1至3中任一项所述的高压互锁检测电路，其特征在于，所述高压互锁电路还包括：The high voltage interlock detection circuit according to any one of claims 1 to 3, wherein the high voltage interlock circuit further comprises:
    第一回检模块，所述第一回检模块的一端连接在所述第一限流电阻与所述环路输入端之间，另一端连接至所述信号回检输入端。a first checkback module, one end of the first checkback module is connected between the first current limiting resistor and the loop input end, and the other end is connected to the signal checkback input end.
  5. 根据权利要求4所述的高压互锁检测电路，其特征在于，所述第一回检模块还包括第三限流电阻。The high voltage interlock detection circuit according to claim 4, wherein the first return detection module further comprises a third current limiting resistor.
  6. 根据权利要求5所述的高压互锁检测电路，其特征在于，所述第一限流电阻、所述第二限流电阻和所述第三限流电阻的阻值大于或等于100欧姆。The high voltage interlock detection circuit according to claim 5, wherein the resistances of the first current limiting resistor, the second current limiting resistor, and the third current limiting resistor are greater than or equal to 100 ohms.
  7. 根据权利要求4所述的高压互锁检测电路，其特征在于，所述高压 互锁电路还包括：The high voltage interlock detection circuit according to claim 4, wherein said high voltage The interlock circuit also includes:
    第二回检模块，所述第二回检模块的一端连接至所述第二限流电阻的输出端，另一端连接至所述信号回检输入端，与所述监控芯片并联。a second check module, one end of the second check module is connected to the output end of the second current limiting resistor, and the other end is connected to the signal check input end, and is connected in parallel with the monitoring chip.
  8. 根据权利要求7所述的高压互锁检测电路，其特征在于，所述第二回检模块包括：The high voltage interlock detection circuit according to claim 7, wherein the second checkback module comprises:
    第一比较器，所述第一比较器的同相输入端连接至所述第二限流电阻的输出端；a first comparator, a non-inverting input terminal of the first comparator is connected to an output end of the second current limiting resistor;
    第二比较器，与所述第一比较器并联，所述第二比较器的反相输入端连接至所述第二限流电阻的输出端；以及a second comparator, in parallel with the first comparator, an inverting input of the second comparator being coupled to an output of the second current limiting resistor;
    所述第二限流电阻的外侧端口连接线短路到地或短路到供电正极。The outer port connection line of the second current limiting resistor is shorted to ground or shorted to the positive supply.
  9. 根据权利要求7所述的高压互锁检测电路，其特征在于，所述第一回检模块和/或所述第二回检模块还包括箝位二极管。The high voltage interlock detection circuit according to claim 7, wherein the first checkback module and/or the second checkback module further comprises a clamp diode.
  10. 根据权利要求9所述的高压互锁检测电路，其特征在于，所述箝位二极管为肖特基二极管。 The high voltage interlock detection circuit according to claim 9, wherein said clamp diode is a Schottky diode.
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