WO2018059093A1 - 移位寄存器单元、栅极扫描电路、驱动方法、显示装置 - Google Patents

移位寄存器单元、栅极扫描电路、驱动方法、显示装置 Download PDF

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Publication number
WO2018059093A1
WO2018059093A1 PCT/CN2017/094064 CN2017094064W WO2018059093A1 WO 2018059093 A1 WO2018059093 A1 WO 2018059093A1 CN 2017094064 W CN2017094064 W CN 2017094064W WO 2018059093 A1 WO2018059093 A1 WO 2018059093A1
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Prior art keywords
node
shift register
register unit
signal
control
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PCT/CN2017/094064
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English (en)
French (fr)
Inventor
张小祥
陈曦
刘明悬
郭会斌
罗丽平
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京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/751,120 priority Critical patent/US10510279B2/en
Publication of WO2018059093A1 publication Critical patent/WO2018059093A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a shift register unit, a gate scan circuit, a driving method, and a display device.
  • the gate driving circuit integrated on the array substrate is composed of a multi-stage shift register (hereinafter sometimes referred to as SR) unit, and each shift register unit sequentially shifts and outputs one scan pulse to each row.
  • SR shift register
  • the corresponding thin film transistor is turned on, thereby implementing a driving process for each row of pixel units.
  • the present disclosure provides a shift register unit, a gate scan circuit and a method of driving the same, and a display device.
  • a shift register unit including an output module, an input module, a reset module, a first pull-down control module, a second pull-down control module, and a second node control module:
  • the output module is connected to the first node, the first clock signal input end and the shift register unit output end, and is configured to transmit the signal of the first clock signal input end to the output of the shift register unit under the control of the first node ;
  • the input module is connected to the first node, the shift register unit input end, and configured to transmit the signal of the input end of the shift register unit to the first node under the control of the input end of the shift register unit;
  • the reset module is connected to the reset control signal input end, the first node, and the shift register unit letter
  • the output end and the signal control end are configured to transmit the signal of the signal control end to the signal output end of the first node and the shift register unit under the control of the input of the reset control signal;
  • the first pull-down control module is connected to the second node, the first node, the shift register unit signal output end, and the signal control end, and is configured to transmit the signal of the signal control end to the first node under the control of the second node And a shift register unit signal output terminal;
  • the second pull-down control module is connected to the third node, the first node and the shift register unit signal output end, and the signal control end, and is configured to transmit the signal of the signal control end to the first node under the control of the third node and Shift register unit signal output terminal;
  • the second node control module is configured to connect the first node, the second node, the second clock signal input end, and the signal control end, and is configured to signal the signal control end under the control of the first node and the second clock signal input end a signal output to the second clock signal to the second node;
  • the third node control signal input terminal is connected to the third node.
  • the reset module includes a second transistor and a fifth transistor;
  • the gate of the second transistor is connected to the reset control signal input end, one of the source and the drain is connected to the first node, and the other electrode is connected to the signal control end, and is configured to be under the control of the reset control signal input end One node is turned on or off with the signal control terminal;
  • the gate of the fifth transistor is connected to the reset control signal input end, one of the source and the drain is connected to the output of the shift register unit, and the other electrode is connected to the signal control end, and is configured to be controlled at the input of the reset control signal
  • the output of the shift register unit is turned on or off with the signal control terminal.
  • the first pull-down control module includes a third transistor and a sixth transistor;
  • the gate of the third transistor is connected to the second node, one of the source and the drain is connected to the first node, and the other electrode is connected to the signal control end, and is configured to connect the first node with the control of the second node
  • the signal control terminal is turned on or off;
  • the gate of the sixth transistor is connected to the second node, one of the source and the drain is connected to the shift register unit signal output end, and the other electrode is connected to the signal control end, and is configured to be under the control of the second node
  • the shift register unit signal output terminal is turned on or off from the signal control terminal.
  • the second pull-down control module includes a first transistor and a fourth transistor;
  • the gate of the first transistor is connected to the third node, one of the source and the drain is connected to the first node, and the other electrode is connected to the signal control end, and is configured to be the first node under the control of the third node Conducted with the signal control terminal;
  • the gate of the fourth transistor is connected to the third node, one of the source and the drain is connected to the output of the shift register unit, and the other electrode is connected to the signal control terminal, and is configured to be under the control of the third node. Turn the output of the shift register unit to the signal control terminal.
  • the second node control module includes an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor;
  • the gate of the eighth transistor and one of the source and the drain are connected to the second clock signal input end, and the other electrode is connected to the fourth node, configured to be the second clock under the control of the second clock signal input end
  • the signal input terminal is turned on or off with the fourth node
  • the gate of the ninth transistor is connected to the fourth node, one of the source and the drain is connected to the second clock signal input terminal, and the other electrode is connected to the second node, and is configured to be the second clock under the control of the fourth node
  • the signal input end is turned on or off with the second node
  • the gate of the tenth transistor is connected to the first node, one of the source and the drain is connected to the fourth node, and the other electrode is connected to the signal control end, and is configured to control the fourth node and the signal under the control of the first node Turn on or off;
  • the gate of the eleventh transistor is connected to the first node, one of the source and the drain is connected to the second node, and the other electrode is connected to the signal control end, and is configured to connect the second node and the signal under the control of the first node
  • the control terminal is turned on or off.
  • a third pull-down control module is further included;
  • the third pull-down control module is connected to the second clock signal input end, the shift register unit signal output end, and the signal control end, and configured to transmit the signal of the signal control end to the shift register unit under the control of the second clock signal input end Signal output.
  • the third pull-down control module includes a seventh transistor
  • the gate of the seventh transistor is connected to the input end of the second clock signal, one of the source and the drain is connected to the signal output end of the shift register unit, and the other electrode is connected to the signal control end, and is configured to be at the input end of the second clock signal. Under the control, the signal output terminal of the shift register unit is turned on or off with the signal control terminal.
  • the input module comprises a twelfth transistor
  • the gate of the twelfth transistor is connected to the input end of the shift register unit, one of the source and the drain One electrode is connected to the input of the shift register unit, and the other electrode is connected to the first node, and is configured to turn the shift register unit input terminal on or off with the first node under the control of the input of the shift register unit.
  • the output module includes a thirteenth transistor and a first capacitor
  • the gate of the thirteenth transistor is connected to the first node, one of the source and the drain is connected to the first clock signal input end, and the other electrode is connected to the output of the shift register unit, and is configured to be at the first node Controlling the first clock signal input end and the shift register unit output end to be turned on or off; one end of the first capacitor is connected to the first node, and the other end is connected to the shift register unit signal output end.
  • a gate scan circuit comprising: a plurality of cascaded shift register units, the shift register unit being a shift register unit as described above, the gate scan circuit further comprising Multiple clock signal lines;
  • the first clock signal input end of each of the odd-numbered shift register units is connected to the first clock signal line, and the second clock signal input end is connected to the second clock signal line;
  • the first stage of each shift register unit of the even-numbered stages The clock signal input end is connected to the second clock signal line, and the second clock signal input end is connected to the first clock signal line;
  • the output of the shift register unit of the shift register unit of the previous stage is connected to the input of the shift register unit of the shift register unit of the next stage, and the reset of the shift register unit of the previous stage
  • the control signal input end is connected to the shift register unit output end of the next stage shift register unit
  • the third node control signal input end of the upper stage shift register unit is connected to the second node of the next stage shift register unit.
  • a driving method for driving the above-described gate scanning circuit includes:
  • the third node of the nth stage shift register unit resets the nth stage shift register unit under control of the second node of the n+1th stage shift register unit, where n is a positive integer.
  • a display device including the gate scan circuit described above.
  • 1 is a schematic structural diagram of a related shift register unit
  • FIG. 3 is a schematic structural diagram of a shift register unit module according to the present disclosure.
  • FIG. 4 is a schematic structural diagram of a gate scanning circuit provided by the present disclosure.
  • FIG. 5 is a schematic structural diagram of still another shift register unit module according to the present disclosure.
  • FIG. 6 is a schematic structural diagram of a shift register unit circuit provided by the present disclosure.
  • FIG. 7 is a timing diagram corresponding to a shift register unit provided by the present disclosure.
  • FIG. 8 is a timing diagram corresponding to a shift register unit provided by the present disclosure.
  • Each of the shift register units in the gate drive circuit which is common in the related art is mainly composed of a thin film transistor (hereinafter sometimes referred to as TFT) and a capacitor device as shown in FIG.
  • TFT thin film transistor
  • FIG. 1 the timing diagram is as shown in FIG. 2
  • the PU The node and OUT nodes are susceptible to CLK high-level signals, resulting in charge accumulation on the PU and OUT nodes.
  • the threshold voltage of the thin film transistor TFT may be temperature drifted, resulting in more serious charge accumulation on the PU node and the OUT node, which may cause the shift register unit to output incorrectly. How to improve the reset capability of these key nodes and avoid the charge accumulation on these critical nodes is an important issue of this kind of gate drive circuit.
  • An object of the present disclosure is to provide a novel shift register unit for improving the reset capability of a shift register unit therein, thereby preventing the shift register units therein from being erroneously outputted during a period in which the scan pulse is not to be output.
  • the level corresponding to the scan pulse is not limited to the scan pulse.
  • the present disclosure provides a shift register unit, see FIG. 3, including an output module 100, an input module 200, a reset module 300, a first pull-down control module 400, a second pull-down control module 500, and a second node.
  • Control module 600 :
  • the output module 100 is connected to the first node PU, the first clock signal input terminal CLK, and the shift register unit output terminal OUTPUT, and is configured to transmit the signal of the first clock signal input terminal CLK to the shift under the control of the first node PU.
  • the input module 200 is connected to the first node PU and the shift register unit input terminal INPUT, and is configured to transmit the signal of the shift register unit input terminal INPUT to the first node PU under the control of the signal of the shift register unit input terminal INPUT. ;
  • the reset module 300 is connected to the reset control signal input terminal RESET, the first node PU, the shift register unit signal output terminal OUTPUT, and the signal control terminal VSS, and configured to control the signal control terminal under the control of the signal of the reset control signal input terminal RESET
  • the VSS signal is transmitted to the first node PU and the shift register unit signal output terminal OUTPUT;
  • the first pull-down control module 400 is connected to the second node PD1, the first node PU, the shift register unit signal output terminal OUTPUT, and the signal control terminal VSS, and configured to control the signal control terminal VSS under the control of the second node PD1. Signal is transmitted to the first node PU and the shift register unit signal output terminal OUTPUT;
  • the second pull-down control module 500 is connected to the third node PD2, the first node PU, the shift register unit signal output terminal OUTPUT, and the signal control terminal VSS, and configured to signal the signal control terminal VSS under the control of the third node PD2. Transmitting to the first node PU and the shift register unit signal output terminal OUTPUT;
  • the second node control module 600 is connected to the first node PU, the second node PD1, the second clock signal input terminal CLKB, and the signal control terminal VSS, and is configured to be under the control of the first node PU and the second clock signal input terminal CLKB. Outputting a signal of the signal control terminal VSS or a signal of the second clock signal input terminal CLKB to the second node PD1;
  • the shift register unit further includes a third node control signal input terminal coupled to the third node PD2.
  • the second pull-down control module is connected to the third node, and is configured to cooperate with the reset module and the first pull-down control module under the control of the signal of the third node control signal input end,
  • the shift register unit should not output the phase of the scan pulse together for the shift
  • the register unit is reset, so that the shift register unit can be effectively prevented from outputting the scan pulse at a stage where the scan pulse is not to be output.
  • the present disclosure provides a gate scan circuit, as shown in FIG. 4, including a plurality of cascaded shift register units, the shift register unit being the shift register unit of the first aspect, and including Multiple clock signal lines.
  • the first clock signal input terminal CLK of each of the odd-numbered shift register units is connected to the first clock signal line CLK, and the second clock signal input terminal CLKB is connected to the second clock signal line CLKB;
  • the first clock signal input terminal CLK of the unit is connected to the second clock signal line CLKB, and the second clock signal input end is connected to the first clock signal line CLK;
  • the shift register unit output terminal OUTPUT of the shift register unit of the previous stage is connected to the shift register unit input terminal INPUT of the next shift register unit, and the shift register unit of the previous stage
  • the reset control signal input terminal RESET is connected to the shift register unit output terminal OUTPUT of the next stage shift register unit, and the third node control signal input end (ie, the third node PD2) of the upper shift register unit is connected to the next stage.
  • the second node PD1 of the shift register unit is connected to the shift register unit input terminal INPUT of the next shift register unit.
  • the third node control signal input terminal of the upper stage shift register unit is connected to the second node PD1 of the next stage shift register unit, thereby causing the shift register described in the first aspect.
  • the second pull-down control module in the unit can cooperate with the reset module and the first pull-down control module under the control of the second node PD1 of the next-stage shift register unit, and the stage in which the shift register unit should not output the scan pulse
  • the shift register unit is reset, so that the shift register unit can be effectively prevented from outputting a scan pulse at a stage where the scan pulse is not to be output.
  • the reset module 300 can include a second transistor M2 and a fifth transistor M5.
  • the gate of the second transistor M2 is connected to the reset control signal input terminal RESET, one of the source and the drain is connected to the first node PU, and the other electrode is connected to the signal control terminal VSS, and is configured to be at the reset control signal input end.
  • the first node PU and the signal control terminal VSS are turned on or off under the control of RESET.
  • the gate of the fifth transistor M5 is connected to the reset control signal input terminal RESET, one of the source and the drain is connected to the output terminal OUTPUT of the shift register unit, and the other electrode is connected to the signal control terminal VSS. It is configured to turn the shift register unit output terminal OUTPUT and the signal control terminal VSS on or off under the control of the reset control signal input terminal RESET.
  • the reset control signal input terminal RESET when the reset control signal input terminal RESET is low level, the second transistor M2 and the fifth transistor M5 is turned off. At this time, the signal of the first node PU and the output terminal OUTPUT of the shift register unit is not affected by the signal control terminal VSS.
  • the reset control signal input terminal RESET is at a high level, the second transistor M2 and the fifth transistor M5 are both turned on, so that the first node PU and the signal control terminal VSS are turned on, the shift register unit output terminal OUTPUT and the signal control terminal VSS Turn on.
  • the signal control terminal VSS may be a signal control terminal that applies a low-level DC signal, so that the voltage of the first node PU is set to a low level, and the voltage of the output terminal OUTPUT of the shift register unit is set to a low level.
  • the reset module 300 can also be implemented in other manners. Under the premise that the function of the reset module 300 can be implemented, the specific structure of the reset module 300 does not affect the protection scope of the present disclosure.
  • the first pull-down control module 400 may include a third transistor M3 and a sixth transistor M6.
  • the gate of the third transistor M3 is connected to the second node PD1, one of the source and the drain is connected to the first node PU, and the other electrode is connected to the signal control terminal VSS, and is configured to be under the control of the second node PD1.
  • the electrode connection signal control terminal VSS is configured to turn on or off the shift register unit signal output terminal OUTPUT and the signal control terminal VSS under the control of the second node PD1.
  • the operation principle of the first pull-down control module 400 is described in detail below by taking the third transistor M3 and the sixth transistor M6 as N-type TFTs as an example: when the second node PD1 is at a low level, the third transistor M3 and the The six transistors M6 are all turned off. At this time, the signals of the first node PU and the output terminal OUTPUT of the shift register unit are not affected by the signal control terminal VSS.
  • the second node PD1 is at a high level
  • the third transistor M3 and the sixth transistor M6 are both turned on, so that the first node PU is turned on with the signal control terminal VSS, and the shift register unit output terminal OUTPUT and the signal control terminal VSS are turned on. through.
  • the signal control terminal VSS may be a signal control terminal to which a low-level DC signal is applied, so that the voltage of the first node PU is turned to a low level after the third transistor M3 is turned on, and the sixth After the transistor M6 is turned on, the voltage of the shift register unit output terminal OUTPUT is set to a low level, thereby realizing the signal of the first node PU and the shift register unit output terminal OUTPUT at the stage where the second node PD1 is at the high level. Pull down function.
  • the first pull-down control module 400 can also be implemented in other manners. Under the premise that the function of the first pull-down control module 400 can be implemented, what is the first pull-down control module 400? The structure does not affect the scope of protection of the present disclosure.
  • the second node control module 600 may include an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, and an eleventh transistor M11.
  • the gate of the eighth transistor M8 is connected to the second clock signal input terminal CLKB, and one of the source and the drain is also connected to the second clock signal input terminal CLKB, and the other electrode is connected to the fourth node PDCN, and is configured to be configured as
  • the second clock signal input terminal CLKB is turned on or off under the control of the second clock signal input terminal CLKB
  • the gate of the ninth transistor M9 is connected to the fourth node PDCN, in the source and the drain
  • One electrode is connected to the second clock signal input terminal CLKB, and the other electrode is connected to the second node PD1, and is configured to turn on or off the second clock signal input terminal CLKB and the second node PD1 under the control of the fourth node PDCN
  • the gate of the tenth transistor M10 is connected to the first node PU, one of the source and the drain is connected to the fourth node PDCN, and the other electrode is connected to the signal control terminal VSS, and is configured to be under the control of the first node PU
  • the working principle of the second node control module 600 is described in detail below by taking the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, and the eleventh transistor M11 as N-type transistors as an example.
  • the tenth transistor M10, the eleventh transistor M11, and the eighth transistor M8 are turned on.
  • the fourth node PDCN is turned on with the signal control terminal VSS, and the fourth node PDCN is also turned on with the second clock signal input terminal CLKB.
  • the voltage of the signal control terminal VSS and the voltage value of the second clock signal input terminal CLKB may be set and/or the width and length of the tenth transistor M10 and the eighth transistor M8 may be set.
  • the tenth transistor M10 and the eleventh transistor M11 are turned on, the eighth transistor M8 is turned off, and the fourth node PDCN is at the signal control end.
  • the VSS is set to a low level, so the ninth transistor M9 is turned off, so that the second node is set to a low level by the signal control terminal VSS;
  • the tenth transistor M10 and the eleventh transistor M11 are turned off, and the eighth transistor M8 is turned on. Since the eighth transistor M8 is turned on, the fourth node is set to a high level by the second clock signal input terminal CLKB.
  • the ninth transistor M9 is turned on after the fourth node PDCN is set to a high level, so that the second node PD1 is set to a high level by the fourth node PDCN;
  • the eighth transistor M8 When the first node is at a low level, and the second clock signal input terminal CLKB is at a low level, the eighth transistor M8, the tenth transistor M10, and the eleventh transistor M11 are all turned off.
  • the voltage of the fourth node PDCN is lower than the turn-on voltage of the ninth transistor M9, so the ninth transistor M9 is also turned off.
  • the second node PD1 is in a low state.
  • the working principle of the second node control module 600 can be simply summarized as: when the first node PU is at a high level, the second node PD1 is kept in a low state. When the first node PU is at a low level, the signal of the second node PD1 and the signal of the second clock signal input terminal CLKB are always consistent.
  • the second node control module 600 can also be implemented in other manners. Under the premise that the function of the second node control module 600 can be implemented, the second node control module 600 does not affect the specific structure. The scope of protection of the present disclosure.
  • the second pull-down control module 500 can include a first transistor M1 and a fourth transistor M4.
  • the gate of the first transistor M1 is connected to the third node PD2, one of the source and the drain is connected to the first node PU, and the other electrode is connected to the signal control terminal VSS, and is configured to be under the control of the third node PD2.
  • the first node PU is turned on or off with the signal control terminal VSS.
  • the gate of the fourth transistor M4 is connected to the third node PD2, one of the source and the drain is connected to the output terminal OUTPUT of the shift register unit, and the other electrode is connected to the signal control terminal VSS, and is configured to be at the third node PD2. Under the control The shift register unit output terminal OUTPUT and the signal control terminal VSS are turned on or off.
  • the working principle of the second pull-down control module 500 is as follows: when the third node PD2 is low level under the action of PD1(n+1) of the shift register of the next stage, the first transistor M1 and the fourth transistor M4 are all turned off. The signals of the first node PU and the shift register unit output terminal OUTPUT are not affected by the signal control terminal VSS. When the third node PD2 is at a high level under the action of PD1(n+1) of the next stage shift register, the first transistor M1 and the fourth transistor M4 are both turned on, thereby causing the first node PU and the signal control terminal VSS Turning on, the shift register unit output terminal OUTPUT is turned on with the signal control terminal VSS.
  • the second pull-down control module 500 can also be implemented in other manners. Under the premise that the function of the second pull-down control module 500 can be implemented, the second pull-down control module 500 does not specifically structure. Affects the scope of protection of the present disclosure.
  • the shift register provided by the present disclosure may further include a third pull-down control. Module 700.
  • the third pull-down control module 700 is connected to the second clock signal input terminal CLKB, the shift register unit signal output terminal OUTPUT, and the signal control terminal VSS, and configured to control the signal control terminal VSS under the control of the second clock signal input terminal CLKB.
  • the signal is transmitted to the shift register unit signal output terminal OUTPUT.
  • the third pull-down control module 700 can include a seventh transistor M7.
  • the gate of the seventh transistor M7 is connected to the second clock signal input terminal CLKB, one of the source and the drain is connected to the shift register unit signal output terminal OUTPUT, and the other electrode is connected to the signal control terminal VSS, and is configured to be in the second When the clock signal input terminal CLKB is at a high level, the shift register unit signal output terminal OUTPUT and the signal control terminal VSS are turned on or off, thereby further lowering the shift register unit signal output terminal OUTPUT.
  • the input module 200 may specifically include a twelfth transistor M12, the gate of the twelfth transistor M12 is connected to the input terminal INPUT of the shift register unit, and one of the source and the drain is also connected to the shift register unit.
  • Input INPUT another electrode in the source and drain Connected to the first node PU; configured to turn the shift register unit input terminal INPUT and the first node PU on or off under the control of the shift register unit input terminal INPUT.
  • the output module 100 may specifically include a thirteenth transistor M13 and a first capacitor C1; a gate of the thirteenth transistor M13 is connected to the first node PU, and one of the source and the drain is connected to the first clock signal input terminal CLK.
  • the other electrode is connected to the shift register unit output terminal OUTPUT, and is adapted to conduct the first clock signal input terminal CLK and the shift register unit output terminal OUTPUT under the control of the first node PU; one end of the first capacitor C1 is connected to the first The node PU is connected to the shift register unit signal output terminal OUTPUT.
  • a driving method for driving a gate scanning circuit composed of a plurality of n-th stage shift register units as shown in FIG. 5 and a function thereof to realize the functions thereof will be described below with reference to the timing charts shown in FIGS. 7 and 8.
  • the principle is elaborated.
  • the working principle of each stage will be described in detail below by taking each transistor as an N-type transistor as an example.
  • the driving method may specifically include:
  • the third node PD2 of the nth stage shift register unit resets the nth stage shift register unit under the control of the second node PD1 of the n+1th stage shift register unit, where n is positive Integer. This ensures that the nth stage shift register unit is not affected by the input of the first clock signal, and can continuously output a stable non-scan signal during the non-scanning phase.
  • the voltage is the same as the input terminal INPUT of the shift register unit, and is set to a high level; the first node PU is pulled high, causing the transistor M13 to be turned on, and the conduction of the transistor M13 causes the shift register unit output terminal OUTPUT to be connected to the first On the clock signal input terminal CLK, since the first clock signal input terminal CLK is at a low level, the output terminal OUTPUT of the shift register unit is at a low level; since the first node PU is pulled high, the transistor M10 is turned on, The second node PD1 is connected to the signal control terminal VSS.
  • the second node PD Since the signal control terminal VSS generally inputs a low level, the second node PD is set to a low level; the second node PD is at a low level, which causes the transistor M3 and the transistor M6. Be turned off; And at this stage, the reset control signal input terminal RESET is at a low level, so that the transistors M2 and M5 are all turned off. Furthermore, since the first node PU is pulled high, the transistor M11 is turned on, and the fourth node PDCN is also connected to the signal control terminal VSS. However, the fourth node PDCN is also controlled by the second clock signal input terminal CLKB.
  • the second clock signal input terminal CLKB is at a high level, so that the transistor M8 is turned on, and the fourth node PDCN is connected to the second clock signal input terminal CLKB.
  • the voltage of the fourth node PDCN at this time is low.
  • the voltage of the voltage is turned on by the transistor M9, so the transistor M9 is turned off at this time, so that the second node PD1 is not pulled high by CLKB at this stage.
  • transistor M7 is turned on, so that the shift register unit output terminal OUTPUT keeps a low signal at this stage.
  • the third node PD2 is connected to the second node PD1 of the n+1th stage shift register SR(n+1), since the n+1th stage shift register SR(n+1) has not yet received the nth The input of the stage shift register SR(n), so the first node PU point is low, and the second node PD1 of the n+1th stage shift register SR(n+1) is only subjected to the n+1th stage.
  • the CLKB of the n+1th stage shift register SR(n+1) is low, so the second node PD1 of the n+1th stage shift register SR(n+1) is low.
  • the third node PD2 of the nth stage shift register SR(n) is at a low level at this stage, and the transistors M1 and M4 are both turned off, thereby avoiding pulling the first node PU low.
  • This phase completes the process of pulling the voltage on the first node PU.
  • the transistors M10 and M11 are both turned off. Since CLKB is low at this time, transistors M8 and M9 are both turned off, and the second node PD1 and the fourth node PDCN are both low, so the n+1th shift register SR(n) in this stage.
  • the second node PD1 of +1) does not affect the third node PD2 of the nth stage shift register SR(n), and the third node PD2 of the nth stage shift register SR(n) is kept low. To avoid pulling the first node PU of the nth stage shift register SR(n) low at this stage.
  • the shift register unit input terminal INPUT is low level, the transistor M12 is turned off, and the second clock signal input terminal CLKB Low level, transistor M7, transistor M8, and transistor M9 are turned off, making The four-node PDCN is not affected by CLKB, and the first clock signal input terminal CLK is at a high level.
  • the first node PU is maintained at a high level by the first capacitor C1, so the transistor M13 is turned on, so that the shift register unit outputs
  • the terminal OUTPUT is set to the level of the first clock signal input terminal CLK1, that is, the high level.
  • the first node PU Under the coupling of the first capacitor C1, the first node PU is further pulled high, and the shift register unit output terminal OUTPUT starts to output high power.
  • Flat voltage at this stage, the first node PU is at a high level, and the transistors M10 and M11 are turned on, so that the fourth node PDCN and the second node PD1 are set to a low level, so that the transistors M3 and M6 remain off. , to avoid pulling the first node PU low;
  • the shift register unit input terminal INPUT is at a high level
  • the first clock signal input terminal CLK is at a low level at this time.
  • the second clock signal input terminal CLKB is at a high level at this time; the condition of the accessed signal is exactly the same as that of the nth-stage shift register SR(n) in the first phase, and the n+1th shift is performed at this time.
  • the first node PU in the register SR(n+1) is also set to a high level; the corresponding fourth node PDCN and the second node PD1 are set to a low level;
  • the reset control signal input terminal RESET in the nth stage shift register SR(n) is at a low level, since the shift of the n+1th stage shift register SR(n+1) at this time
  • the reset control signal input terminal RESET of the n+1th stage shift register SR(n+1) is also at a low level, so that the transistors M2 and M5 are turned off, and the other nth
  • the second node PD1 of the +1 stage shift register SR(n+1) is also at a low level, so that the third node PD2 of the nth stage shift register SR(n) is not set to a high level, so the transistor M1 and M4 are turned off, thereby avoiding setting the first node PU to a low level, and ensuring that the nth stage shift register SR(n) can output a high level well;
  • the condition of the signal accessed by the n+1th stage shift register SR(n+1) and the level state of the key node of the nth stage shift register SR(n) in the second stage t2 are completely Similarly, correspondingly, the state of the key node in the n+1th stage shift register SR(n+1) and the level state of the key node of the nth stage shift register SR(n) in the second stage t2 are completely The same; at this time, the shift register unit output terminal OUTPUT of the n+1th stage shift register SR(n+1) starts to output a high level scan pulse, thereby making the nth stage shift register SR(n)
  • the reset control signal input terminal RESET is set to a high level, and the transistors M2 and M5 are turned on; at this time, CLKB is at a high level, and the transistor M7, M8 is turned on, the fourth node PDCN is set to a high level, and the transistor M9 is turned on,
  • the first pull-down control module 400 (including the transistors M3 and M6) Both reset the first node PU and the shift register unit output terminal OUTPUT;
  • the signal state of the n+1th shift register SR(n+1) is the same as that of the nth stage shift register SR(n) at the second stage t2. Therefore, the n+1th stage shift register SR(n+1) is at a low level in the second node PD1 at this stage, so the third node PD2 of the nth stage shift register SR(n) is also low. Leveling, so that the transistors M1 and M4 are turned off, and the first node is not pulled down in this stage;
  • the fourth phase t4 (ie, the auxiliary reset phase), the case of the signal accessed by the n+1th stage shift register SR(n+1) and the nth stage shift register SR(n) are critical in the third stage t3.
  • the level state of the node is exactly the same.
  • the state of the key node in the n+1th stage shift register SR(n+1) and the nth stage shift register SR(n) are the key in the third stage t3.
  • the level state of the node is exactly the same; that is, in the n+1th stage shift register SR(n+1), the second node PD1 is set to a high level, therefore, the nth stage shift register in this stage
  • the third node PD2 of SR(n) is at a high level, so that the transistors M1 and M4 are turned on, and the first node PU and the shift register unit output terminal OUTPUT are pulled down and reset;
  • the present disclosure also provides a display device comprising the gate scan circuit of the second aspect.
  • N-type transistor is specifically described as an example in the above embodiment, the present disclosure is not limited thereto. In fact some embodiments of the present disclosure are equally applicable to P-type transistors.
  • the display device here can be: electronic paper, mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator and the like with any display product or component.
  • the second pull-down control module is connected to the third node, and is configured to cooperate with the reset module and the first pull-down control module under the control of the third node control signal input end.
  • the stage in which the shift register unit should not output the scan pulse collectively resets the shift register unit, thereby effectively preventing the shift register unit from outputting the scan pulse at a stage where the scan pulse is not to be output.

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Abstract

一种移位寄存器单元、栅极扫描电路、驱动方法以及显示装置，该移位寄存器单元，包括：复位模块(300)，被配置为在复位控制信号输入端的控制下将信号控制端的信号传输给第一节点和移位寄存器单元信号输出端；第一下拉控制模块(400)，被配置为在第二节点的控制下将信号控制端的信号传输给第一节点和移位寄存器单元信号输出端；第二下拉控制模块(500)，被配置为在与第三节点连接的第三节点控制信号输入端的控制下将信号控制端的信号传输给第一节点和移位寄存器单元信号输出端，从而与复位模块(300)以及第一下拉控制模块（400）相配合，在该移位寄存器单元不应输出的阶段共同对该移位寄存器单元进行复位，有效避免该移位寄存器单元在不该输出的阶段输出。

Description

移位寄存器单元、栅极扫描电路、驱动方法、显示装置
相关申请的交叉引用
本申请要求于2016年9月30日递交的题为“移位寄存器单元、栅极扫描电路、驱动方法、显示装置”的中国专利申请(申请号201610875041.4)的优先权，在此以全文引用的方式将该中国专利申请并入本文中。
技术领域
本公开涉及显示技术领域，尤其是涉及一种移位寄存器单元、栅极扫描电路、驱动方法、显示装置。
背景技术
GOA(Gate Driver On Array，栅极驱动电路集成到阵列基板上)是实现显示装置窄边化的一种重要手段。一般的，集成到阵列基板上的栅极驱动电路由多级的移位寄存器(Shift Register，下文中有时简称为SR)单元组成，每一级移位寄存器单元依次移位输出一个扫描脉冲到各行像素单元中的薄膜晶体管的栅极上，使得对应的薄膜晶体管导通，从而实现对各行像素单元的驱动过程。
发明内容
本公开提供了一种移位寄存器单元、栅极扫描电路及其驱动方法、以及显示装置。
一方面，提供了一种移位寄存器单元，包括输出模块、输入模块、复位模块、第一下拉控制模块、第二下拉控制模块以及第二节点控制模块：
所述输出模块，连接第一节点、第一时钟信号输入端以及移位寄存器单元输出端，被配置为在第一节点的控制下将第一时钟信号输入端的信号传输给移位寄存器单元输出端；
所述输入模块，连接第一节点、移位寄存器单元输入端，被配置为在移位寄存器单元输入端的控制下将移位寄存器单元输入端的信号传输给第一节点；
所述复位模块，连接复位控制信号输入端、第一节点、移位寄存器单元信 号输出端以及信号控制端，被配置为在复位控制信号输入端的控制下将信号控制端的信号传输给第一节点和移位寄存器单元信号输出端；
所述第一下拉控制模块，连接第二节点、第一节点、移位寄存器单元信号输出端以及信号控制端，被配置为在第二节点的控制下将信号控制端的信号传输给第一节点和移位寄存器单元信号输出端；
所述第二下拉控制模块，连接第三节点、第一节点和移位寄存器单元信号输出端以及信号控制端，被配置为在第三节点的控制下将信号控制端的信号传输给第一节点和移位寄存器单元信号输出端；
所述第二节点控制模块，连接第一节点、第二节点、第二时钟信号输入端以及信号控制端，被配置为在第一节点以及第二时钟信号输入端的控制下将信号控制端的信号或第二时钟信号输入端的信号输出给第二节点；以及
第三节点控制信号输入端，与所述第三节点连接。
优选地，所述复位模块包括第二晶体管以及第五晶体管；
所述第二晶体管的栅极连接复位控制信号输入端，源极和漏极中的一个电极连接第一节点，另一个电极连接信号控制端，被配置为在复位控制信号输入端的控制下将第一节点与信号控制端导通或关断；
所述第五晶体管的栅极连接复位控制信号输入端，源极和漏极中的一个电极连接移位寄存器单元输出端，另一个电极连接信号控制端，被配置为在复位控制信号输入端的控制下将移位寄存器单元输出端与信号控制端导通或关断。
优选地，所述第一下拉控制模块包括第三晶体管以及第六晶体管；
所述第三晶体管的栅极连接第二节点，源极和漏极中的一个电极连接第一节点，另一个电极连接信号控制端，被配置为在第二节点的控制下将第一节点与信号控制端导通或关断；
所述第六晶体管的栅极连接第二节点、源极和漏极中的一个电极连接移位寄存器单元信号输出端，另一个电极连接信号控制端，被配置为在第二节点的控制下将移位寄存器单元信号输出端与信号控制端导通或关断。
优选地，所述第二下拉控制模块包括第一晶体管和第四晶体管；
所述第一晶体管的栅极连接第三节点，源极和漏极中的一个电极连接第一节点，另一个电极连接信号控制端，被配置为在第三节点的控制下将第一节点 与信号控制端导通；
所述第四晶体管的栅极连接第三节点，源极和漏极中的一个电极连接移位寄存器单元输出端，另一个电极连接信号控制端导通，被配置为在第三节点的控制下将移位寄存器单元输出端与信号控制端导通或关断。
优选地，所述第二节点控制模块包括第八晶体管、第九晶体管、第十晶体管以及第十一晶体管；
其中，第八晶体管的栅极以及源极和漏极中的一个电极连接第二时钟信号输入端，另一个电极连接第四节点，被配置为在第二时钟信号输入端的控制下将第二时钟信号输入端与第四节点导通或关断；
第九晶体管的栅极连接第四节点，源极和漏极中的一个电极连接第二时钟信号输入端，另一个电极连接第二节点，被配置为在第四节点的控制下将第二时钟信号输入端与第二节点导通或关断；
第十晶体管的栅极连接第一节点，源极和漏极中的一个电极连接第四节点，另一个电极连接信号控制端，被配置为在第一节点的控制下将第四节点与信号控制端导通或关断；
第十一晶体管的栅极连接第一节点，源极和漏极中的一个电极连接第二节点，另一个电极连接信号控制端，被配置为在第一节点的控制下将第二节点与信号控制端导通或关断。
优选地，还包括第三下拉控制模块；
所述第三下拉控制模块连接第二时钟信号输入端、移位寄存器单元信号输出端以及信号控制端，被配置为在第二时钟信号输入端的控制下将信号控制端的信号传输给移位寄存器单元信号输出端。
优选地，所述第三下拉控制模块包括第七晶体管；
第七晶体管的栅极连接第二时钟信号输入端，源极和漏极中的一个电极连接移位寄存器单元信号输出端，另一个电极连接信号控制端，被配置为在第二时钟信号输入端的控制下将移位寄存器单元信号输出端与信号控制端导通或关断。
优选地，所述输入模块包括第十二晶体管；
所述第十二晶体管的栅极连接移位寄存器单元输入端，源极和漏极中的一 个电极连接移位寄存器单元输入端，另一个电极连接第一节点，被配置为在移位寄存器单元输入端的控制下将移位寄存器单元输入端与第一节点导通或关断。
优选地，所述输出模块包括第十三晶体管和第一电容；
所述第十三晶体管的栅极连接第一节点，源极和漏极中的一个电极连接第一时钟信号输入端，另一个电极连接移位寄存器单元输出端，被配置为在第一节点的控制下将第一时钟信号输入端与移位寄存器单元输出端导通或关断；第一电容的一端连接第一节点，另一端连接移位寄存器单元信号输出端。
另一方面，提供了一种栅极扫描电路，包括：多个级联的移位寄存器单元，所述移位寄存器单元为如上述所述的移位寄存器单元，所述栅极扫描电路还包括多条时钟信号线；
其中，奇数级的各个移位寄存器单元的第一时钟信号输入端均连接第一时钟信号线，第二时钟信号输入端均连接第二时钟信号线；偶数级的各个移位寄存器单元的第一时钟信号输入端均连接第二时钟信号线，第二时钟信号输入端均连接第一时钟信号线；
相邻两级的移位寄存器单元中：上一级移位寄存器单元的移位寄存器单元输出端连接下一级移位寄存器单元的移位寄存器单元输入端，上一级移位寄存器单元的复位控制信号输入端连接下一级移位寄存器单元的移位寄存器单元输出端，上一级移位寄存器单元的第三节点控制信号输入端连接下一级移位寄存器单元的第二节点。
另一方面，还提供了一种驱动方法，用于驱动上述所述的栅极扫描电路，所述驱动方法包括：
在辅助复位阶段，第n级移位寄存器单元的第三节点在第n+1级移位寄存器单元的第二节点的控制下对第n级移位寄存器单元进行复位，其中n为正整数。
另一方面，提供了一种显示装置，包括上述所述的栅极扫描电路。
附图说明
通过参考附图会更加清楚的理解本公开的特征信息和优点，附图是示意性 的而不应理解为对本公开进行任何限制，在附图中：
图1为相关的移位寄存器单元结构示意图；
图2为相关的移位寄存器单元对应的时序示意图；
图3为本公开提供的一种移位寄存器单元模块结构示意图；
图4为本公开提供的栅极扫描电路结构示意图；
图5为本公开提供的又一种移位寄存器单元模块结构示意图；
图6为本公开提供的移位寄存器单元电路结构示意图；
图7为本公开提供的移位寄存器单元对应的时序图；以及
图8为本公开提供的移位寄存器单元对应的时序图。
具体实施方式
为了能够更清楚地理解本公开的上述目的、特征和优点，下面结合附图和具体实施方式对本公开进行进一步的详细描述。需要说明的是，在不冲突的情况下，本申请的实施例及实施例中的特征可以相互组合。
在下面的描述中阐述了很多具体细节以便于充分理解本公开，但是，本公开还可以采用其他不同于在此描述的其他方式来实施，因此，本公开的保护范围并不受下面公开的具体实施例的限制。
相关技术中常见的栅极驱动电路中的每一级移位寄存器单元如图1所示主要由薄膜晶体管(Thin Film Transistor，下文中有时简称为TFT)和电容器件构成。对于图1所示的移位寄存器单元来说(其时序图如图2所示)，在其本次输出扫描脉冲之后下一次输出扫描脉冲之间的过程中，由于耦合电容CP的存在，PU节点和OUT节点容易受到CLK高电平信号的影响，导致PU节点和OUT节点上容易产生电荷累积。尤其是在高温工作的情况下，薄膜晶体管TFT的阈值电压会发生温漂，导致PU节点和OUT节点上的电荷累积更为严重，可能导致该移位寄存器单元错误输出。如何提高对这些关键节点的复位能力，避免这些关键节点上电荷累积是这类栅极驱动电路的一个重要课题。
本公开的一个目的在于提供一种新型的移位寄存器单元，用以提高对其中的移位寄存器单元的复位能力，从而避免其中的各级移位寄存器单元在不该输出扫描脉冲的阶段错误输出扫描脉冲对应的电平。
第一方面，本公开提供了一种移位寄存器单元，参见图3，包括输出模块100、输入模块200、复位模块300、第一下拉控制模块400、第二下拉控制模块500以及第二节点控制模块600：
输出模块100，连接第一节点PU、第一时钟信号输入端CLK以及移位寄存器单元输出端OUTPUT，被配置为在第一节点PU的控制下将第一时钟信号输入端CLK的信号传输给移位寄存器单元输出端OUTPUT；
输入模块200，连接第一节点PU、移位寄存器单元输入端INPUT，被配置为在移位寄存器单元输入端INPUT的信号的控制下将移位寄存器单元输入端INPUT的信号传输给第一节点PU；
复位模块300，连接复位控制信号输入端RESET、第一节点PU、移位寄存器单元信号输出端OUTPUT以及信号控制端VSS，被配置为在复位控制信号输入端RESET的信号的控制下将信号控制端VSS的信号传输给第一节点PU和移位寄存器单元信号输出端OUTPUT；
第一下拉控制模块400，连接第二节点PD1、第一节点PU、移位寄存器单元信号输出端OUTPUT以及信号控制端VSS，被配置为在第二节点PD1的控制下将信号控制端VSS的信号传输给第一节点PU和移位寄存器单元信号输出端OUTPUT；
第二下拉控制模块500，连接第三节点PD2、第一节点PU和移位寄存器单元信号输出端OUTPUT以及信号控制端VSS，被配置为在第三节点PD2的控制下将信号控制端VSS的信号传输给第一节点PU和移位寄存器单元信号输出端OUTPUT；
第二节点控制模块600，连接第一节点PU、第二节点PD1、第二时钟信号输入端CLKB以及信号控制端VSS，被配置为在第一节点PU以及第二时钟信号输入端CLKB的控制下将信号控制端VSS的信号或第二时钟信号输入端CLKB的信号输出给第二节点PD1；
移位寄存器单元还包括第三节点控制信号输入端，与第三节点PD2连接。
本公开提供的移位寄存器单元中，第二下拉控制模块与第三节点相连，被配置为在第三节点控制信号输入端的信号的控制下与复位模块以及第一下拉控制模块相配合，在该移位寄存器单元不应输出扫描脉冲的阶段共同对该移位 寄存器单元进行复位，从而能够有效避免该移位寄存器单元在不该输出扫描脉冲的阶段输出扫描脉冲。
第二方面，本公开提供了一种栅极扫描电路，如图4所示，包括多个级联的移位寄存器单元，移位寄存器单元为第一方面所述的移位寄存器单元，还包括多条时钟信号线。
其中，奇数级的各个移位寄存器单元的第一时钟信号输入端CLK均连接第一时钟信号线CLK，第二时钟信号输入端CLKB均连接第二时钟信号线CLKB；偶数级的各个移位寄存器单元的第一时钟信号输入端CLK均连接第二时钟信号线CLKB，第二时钟信号输入端均连接第一时钟信号线CLK；
相邻两级的移位寄存器单元中：上一级移位寄存器单元的移位寄存器单元输出端OUTPUT连接下一级移位寄存器单元的移位寄存器单元输入端INPUT，上一级移位寄存器单元的复位控制信号输入端RESET连接下一级移位寄存器单元的移位寄存器单元输出端OUTPUT，上一级移位寄存器单元的第三节点控制信号输入端(即第三节点PD2)连接下一级移位寄存器单元的第二节点PD1。
本公开提供的栅极扫描电路中，上一级移位寄存器单元的第三节点控制信号输入端连接下一级移位寄存器单元的第二节点PD1，从而使得第一方面所述的移位寄存器单元中第二下拉控制模块能够在下一级移位寄存器单元的第二节点PD1控制下，与复位模块以及第一下拉控制模块相配合，在该移位寄存器单元不应输出扫描脉冲的阶段共同对该移位寄存器单元进行复位，从而能够有效避免该移位寄存器单元在不该输出扫描脉冲的阶段输出扫描脉冲。
下面结合图6所示电路图对本公开提供的移位寄存器单元进行具体说明：
复位模块300可以包括第二晶体管M2以及第五晶体管M5。其中，第二晶体管M2的栅极连接复位控制信号输入端RESET，源极和漏极中的一个电极连接第一节点PU，另一个电极连接信号控制端VSS，被配置为在复位控制信号输入端RESET的控制下将第一节点PU与信号控制端VSS导通或关断。第五晶体管M5的栅极连接复位控制信号输入端RESET，源极和漏极中的一个电极连接移位寄存器单元输出端OUTPUT，另一个电极连接信号控制端VSS， 被配置为在复位控制信号输入端RESET的控制下将移位寄存器单元输出端OUTPUT与信号控制端VSS导通或关断。
下面以第二晶体管M2以及第五晶体管M5均为N型TFT为例，对复位模块300的工作原理进行详细说明：当复位控制信号输入端RESET为低电平时，第二晶体管M2以及第五晶体管M5均关断，此时，第一节点PU以及移位寄存器单元输出端OUTPUT的信号不受信号控制端VSS的影响。当复位控制信号输入端RESET为高电平时，第二晶体管M2以及第五晶体管M5均导通，使得第一节点PU与信号控制端VSS导通，移位寄存器单元输出端OUTPUT与信号控制端VSS导通。这里的信号控制端VSS可以为施加低电平直流信号的信号控制端，因此使得第一节点PU的电压被置为低电平，移位寄存器单元输出端OUTPUT的电压被置为低电平，从而实现将第一节点PU以及移位寄存器单元输出端OUTPUT复位的功能。当然在具体实施时，这里的复位模块300也可以通过其他方式实施，在能够实现上述的复位模块300的功能的前提下，复位模块300具体为何种结构不会影响本公开的保护范围。
第一下拉控制模块400可以包括第三晶体管M3以及第六晶体管M6。其中，第三晶体管M3的栅极连接第二节点PD1，源极和漏极中的一个电极连接第一节点PU，另一个电极连接信号控制端VSS，被配置为在第二节点PD1的控制下将第一节点PU与信号控制端VSS导通或关断；第六晶体管M6的栅极连接第二节点PD1、源极和漏极中的一个电极连接移位寄存器单元信号输出端OUTPUT，另一个电极连接信号控制端VSS，被配置为在第二节点PD1的控制下将移位寄存器单元信号输出端OUTPUT与信号控制端VSS导通或关断。
下面以第三晶体管M3以及第六晶体管M6均为N型TFT为例，对第一下拉控制模块400的工作原理进行详细说明：当第二节点PD1为低电平时，第三晶体管M3以及第六晶体管M6均关断。此时，第一节点PU以及移位寄存器单元输出端OUTPUT的信号不受信号控制端VSS的影响。当第二节点PD1为高电平时，第三晶体管M3以及第六晶体管M6均导通，从而使得第一节点PU与信号控制端VSS导通，移位寄存器单元输出端OUTPUT与信号控制端VSS导通。这里的信号控制端VSS可以为施加低电平直流信号的信号控制端，因此第三晶体管M3导通之后第一节点PU的电压被置为低电平，第六 晶体管M6导通之后移位寄存器单元输出端OUTPUT的电压被置为低电平，从而实现在第二节点PD1为高电平的阶段将第一节点PU以及移位寄存器单元输出端OUTPUT的信号进行下拉的功能。当然在具体实施时，这里的第一下拉控制模块400也可以通过其他方式实施，在能够实现上述的第一下拉控制模块400的功能的前提下，第一下拉控制模块400具体为何种结构不会影响本公开的保护范围。
第二节点控制模块600可以包括第八晶体管M8、第九晶体管M9、第十晶体管M10以及第十一晶体管M11。
其中，第八晶体管M8的栅极连接第二时钟信号输入端CLKB，且源极和漏极中的一个电极也连接第二时钟信号输入端CLKB，另一个电极连接第四节点PDCN，被配置为在第二时钟信号输入端CLKB的控制下将第二时钟信号输入端CLKB与第四节点PDCN导通或关断；第九晶体管M9的栅极连接第四节点PDCN，源极和漏极中的一个电极连接第二时钟信号输入端CLKB，另一个电极连接第二节点PD1，被配置为在第四节点PDCN的控制下将第二时钟信号输入端CLKB与第二节点PD1导通或关断；第十晶体管M10的栅极连接第一节点PU，源极和漏极中的一个电极连接第四节点PDCN，另一个电极连接信号控制端VSS，被配置为在第一节点PU的控制下将第四节点PDCN与信号控制端VSS导通或关断；第十一晶体管M11的栅极连接第一节点PU，源极和漏极中的一个电极连接第二节点PD1，另一个电极连接信号控制端VSS，被配置为在第一节点PU的控制下将第二节点PD1与信号控制端VSS导通或关断。
下面以第八晶体管M8、第九晶体管M9、第十晶体管M10以及第十一晶体管M11均为N型晶体管为例，对第二节点控制模块600的工作原理进行详细说明：
当第一节点为高电平时，且第二时钟信号输入端CLKB为高电平时，第十晶体管M10、第十一晶体管M11以及第八晶体管M8导通。此时，第四节点PDCN与信号控制端VSS导通，同时第四节点PDCN还与第二时钟信号输入端CLKB导通。这时，可以通过设置信号控制端VSS的电压与第二时钟信号输入端CLKB的电压值和/或设置第十晶体管M10和第八晶体管M8的宽长 比，使得第四节点PDCN当前的电压值低于第九晶体管M9的开启电压，从而使得第九晶体管M9关断，第二节点PD1在信号控制端VSS的作用下被置为低电平；
当第一节点为高电平时，且第二时钟信号输入端CLKB为低电平时，第十晶体管M10和第十一晶体管M11导通，第八晶体管M8关断，第四节点PDCN在信号控制端VSS的作用下被置为低电平，因此第九晶体管M9关断，从而使得第二节点在信号控制端VSS的作用下被置为低电平；
当第一节点为低电平时，且第二时钟信号输入端CLKB为高电平时，第十晶体管M10与第十一晶体管M11关断，第八晶体管M8导通。由于第八晶体管M8导通使得第四节点在第二时钟信号输入端CLKB的作用下被置为高电平。在第四节点PDCN置为高电平之后第九晶体管M9导通，从而使得第二节点PD1在第四节点PDCN的作用下被置为高电平；
当第一节点为低电平时，且第二时钟信号输入端CLKB为低电平时，第八晶体管M8、第十晶体管M10以及第十一晶体管M11均关断。第四节点PDCN的电压低于第九晶体管M9导通的开启电压，因此第九晶体管M9也关断。此时，第二节点PD1为低电平状态。
简单来说，上述第二节点控制模块600的工作原理可以简单概括为：在第一节点PU为高电平时，使第二节点PD1保持低电平状态。在第一节点PU为低电平时，使第二节点PD1的信号与第二时钟信号输入端CLKB的信号始终保持一致。
可以理解的是，这里的第二节点控制模块600也可以通过其他方式实施，在能够实现上述的第二节点控制模块600的功能的前提下，第二节点控制模块600具体为何种结构不会影响本公开的保护范围。
第二下拉控制模块500可以包括第一晶体管M1和第四晶体管M4。其中，第一晶体管M1的栅极连接第三节点PD2，源极和漏极中的一个电极连接第一节点PU，另一个电极连接信号控制端VSS，被配置为在第三节点PD2的控制下将第一节点PU与信号控制端VSS导通或关断。第四晶体管M4的栅极连接第三节点PD2，源极和漏极中的一个电极连接移位寄存器单元输出端OUTPUT，另一个电极连接信号控制端VSS导通，被配置为在第三节点PD2的控制下将 移位寄存器单元输出端OUTPUT与信号控制端VSS导通或关断。
第二下拉控制模块500的工作原理如下：当第三节点PD2在下一级移位寄存器的PD1(n+1)的作用下为低电平时，第一晶体管M1以及第四晶体管M4均关断，第一节点PU以及移位寄存器单元输出端OUTPUT的信号不受信号控制端VSS的影响。当第三节点PD2在下一级移位寄存器的PD1(n+1)的作用下为高电平时，第一晶体管M1以及第四晶体管M4均导通，从而使得第一节点PU与信号控制端VSS导通，移位寄存器单元输出端OUTPUT与信号控制端VSS导通。因此在第一晶体管M1导通之后第一节点PU的电压被置为低电平，在第四晶体管M4导通之后移位寄存器单元输出端OUTPUT的电压被置为低电平，从而将第一节点PU以及移位寄存器单元输出端OUTPUT的信号进行进一步下拉。当然在具体实施时，这里的第二下拉控制模块500也可以通过其他方式实施，在能够实现上述的第二下拉控制模块500的功能的前提下，第二下拉控制模块500具体为何种结构不会影响本公开的保护范围。
在具体实施时，为了对移位寄存器单元输出端OUTPUT在非输出阶段的电平进行进一步下拉，在具体实施时，如图5所示，本公开提供的移位寄存器还可包括第三下拉控制模块700。
其中，第三下拉控制模块700连接第二时钟信号输入端CLKB、移位寄存器单元信号输出端OUTPUT以及信号控制端VSS，被配置为在第二时钟信号输入端CLKB的控制下将信号控制端VSS的信号传输给移位寄存器单元信号输出端OUTPUT。
如图6所示，第三下拉控制模块700可以包括第七晶体管M7。第七晶体管M7的栅极连接第二时钟信号输入端CLKB，源极和漏极中的一个电极连接移位寄存器单元信号输出端OUTPUT，另一个电极连接信号控制端VSS，被配置为在第二时钟信号输入端CLKB的为高电平时将移位寄存器单元信号输出端OUTPUT与信号控制端VSS导通或关断，从而将移位寄存器单元信号输出端OUTPUT进一步拉低。
此外，输入模块200可以具体包含一个第十二晶体管M12，该第十二晶体管M12的栅极连接移位寄存器单元的输入端INPUT，且源极和漏极中的一个电极也连接移位寄存器单元输入端INPUT，源极和漏极中的另一个电极连 接第一节点PU；被配置为在移位寄存器单元输入端INPUT的控制下将移位寄存器单元输入端INPUT与第一节点PU导通或关断。
而输出模块100可以具体包括第十三晶体管M13和第一电容C1；第十三晶体管M13的栅极连接第一节点PU，源极和漏极中的一个电极连接第一时钟信号输入端CLK，另一个电极连接移位寄存器单元输出端OUTPUT，适于在第一节点PU的控制下将第一时钟信号输入端CLK与移位寄存器单元输出端OUTPUT导通；第一电容C1的一端连接第一节点PU，另一端连接移位寄存器单元信号输出端OUTPUT。
在能够达到本公开的基本目的的前提下，输入模块200、输出模块100具体采用何种结构也不会影响本公开的保护范围。
下面结合图7以及图8所示的时序图，对由多个如图5所示的第n级移位寄存器单元组成的栅极扫描电路进行驱动的其中一种驱动方法以及其实现其功能的原理进行详细阐述。为方便说明，下面以各个晶体管为N型晶体管为例对各个阶段的工作原理进行详细说明。
该驱动方法可以具体包括：
在辅助复位阶段，第n级移位寄存器单元的第三节点PD2在第n+1级移位寄存器单元的第二节点PD1的控制下对第n级移位寄存器单元进行复位，其中n为正整数。这样保证第n级移位寄存器单元不受第一时钟信号输入端的影响，能够在非扫描阶段持续输出稳定的非扫描信号。
在第一阶段t1，对于第n级移位寄存器SR(n)来说，移位寄存器单元输入端INPUT上输入高电平，会将晶体管M12导通；晶体管M12的导通导致第一节点PU的电压与移位寄存器单元输入端INPUT相同，被置为高电平；第一节点PU被拉高，导致晶体管M13导通，晶体管M13的导通使得移位寄存器单元输出端OUTPUT连接到第一时钟信号输入端CLK上，由于此时第一时钟信号输入端CLK为低电平，则移位寄存器单元输出端OUTPUT为低电平；由于第一节点PU被拉高，晶体管M10导通，则使得第二节点PD1与信号控制端VSS相连，由于信号控制端VSS一般输入低电平，因此第二节点PD被置为低电平；第二节点PD为低电平会导致晶体管M3以及晶体管M6被关断； 并且该阶段，复位控制信号输入端RESET为低电平，使得晶体管M2、M5均关断。此外，由于第一节点PU被拉高，晶体管M11导通，还使得第四节点PDCN与信号控制端VSS相连。但第四节点PDCN还受到第二时钟信号输入端CLKB的控制，此时第二时钟信号输入端CLKB为高电平，使得晶体管M8导通，第四节点PDCN与第二时钟信号输入端CLKB相连。然而由于对信号控制端VSS的电压以及第二时钟信号输入端CLKB的电压进行了设置，和/或对晶体管M8以及晶体管M10的宽长比的设置，此时的第四节点PDCN的电压为低于晶体管M9开启电压的电压，因此晶体管M9此时关断，使得第二节点PD1不会在这一阶段被CLKB拉高。在CLKB的作用下，晶体管M7导通，使移位寄存器单元输出端OUTPUT在这一阶段保持低信号。
此外，第三节点PD2连接第n+1级移位寄存器SR(n+1)的第二节点PD1，由于第n+1级移位寄存器SR(n+1)的此时尚未接收到第n级移位寄存器SR(n)的输入，因此第一节点PU点为低电平，此时第n+1级移位寄存器SR(n+1)的第二节点PD1只受到第n+1级移位寄存器SR(n+1)的CLKB的影响。而在这一阶段第n+1级移位寄存器SR(n+1)的CLKB为低电平，因此第n+1级移位寄存器SR(n+1)的第二节点PD1为低电平，因此，第n级移位寄存器SR(n)的第三节点PD2在这一阶段为低电平，晶体管M1与M4均关断，从而避免将第一节点PU拉低。该阶段完成了对第一节点PU的电压拉高的过程。
另一方面，对于第n+1级移位寄存器SR(n+1)来说，由于第一节点PU尚未被置为高电平，此时晶体管M10以及M11均关断。由于CLKB此时为低电平，因此晶体管M8以及M9均关断，第二节点PD1以及第四节点PDCN均为低电平，所以在这一阶段内第n+1级移位寄存器SR(n+1)的第二节点PD1不会对第n级移位寄存器SR(n)的第三节点PD2造成影响，使第n级移位寄存器SR(n)的第三节点PD2保持低电平状态，避免在此阶段将第n级移位寄存器SR(n)的第一节点PU拉低。
在第一阶段t1之后的第二阶段t2，对于第n级移位寄存器SR(n)来说，移位寄存器单元输入端INPUT为低电平，晶体管M12关断，第二时钟信号输入端CLKB为低电平，晶体管M7、晶体管M8以及晶体管M9关断，使得第 四节点PDCN不受到CLKB的影响，第一时钟信号输入端CLK为高电平，此时第一节点PU被第一电容C1维持为高电平，因此晶体管M13导通，使得移位寄存器单元输出端OUTPUT置为第一时钟信号输入端CLK1的电平，即高电平，在第一电容C1的耦合作用下，第一节点PU进一步被拉高，移位寄存器单元输出端OUTPUT开始输出高电平的电压；该阶段，第一节点PU为高电平，晶体管M10以及M11导通，使得第四节点PDCN以及第二节点PD1被置为低电平，从而使得晶体管M3以及M6保持关断状态，避免将第一节点PU拉低；
对于第n+1级移位寄存器SR(n+1)来说，在第二阶段t2，其移位寄存器单元输入端INPUT为高电平，第一时钟信号输入端CLK此时为低电平，第二时钟信号输入端CLKB此时为高电平；接入的信号的情况与第n级移位寄存器SR(n)在第一阶段的情况完全相同，此时第n+1级移位寄存器SR(n+1)中的第一节点PU也被置为高电平；相应的第四节点PDCN以及第二节点PD1被置为低电平；
这样在第二阶段t2，在第n级移位寄存器SR(n)中的复位控制信号输入端RESET为低电平，由于此时第n+1级移位寄存器SR(n+1)的移位寄存器单元输出端OUTPUT为低电平，则第n+1级移位寄存器SR(n+1)的复位控制信号输入端RESET也为低电平，使得晶体管M2以及M5关断，另外第n+1级移位寄存器SR(n+1)的第二节点PD1也为低电平，使得第n级移位寄存器SR(n)的第三节点PD2不会被置为高电平，因此晶体管M1以及M4关断，从而避免将第一节点PU置为低电平，保证第n级移位寄存器SR(n)能够很好的输出高电平；
在第三阶段t3，第n+1级移位寄存器SR(n+1)接入的信号的情况与第n级移位寄存器SR(n)在第二阶段t2中关键节点的电平状态完全相同，相应的，此时第n+1级移位寄存器SR(n+1)中关键节点的状态与第n级移位寄存器SR(n)在第二阶段t2中关键节点的电平状态完全相同；此时，第n+1级移位寄存器SR(n+1)的移位寄存器单元输出端OUTPUT开始输出高电平的扫描脉冲，从而使得第n级移位寄存器SR(n)中的复位控制信号输入端RESET被置为高电平，晶体管M2以及M5导通；此时CLKB为高电平，晶体管M7、 M8导通，第四节点PDCN被置为高电平，晶体管M9导通，进而使得第n级移位寄存器SR(n)的第二节点PD1与CLKB导通被置为高电平；第二节点PD1为高电平，使得晶体管M3以及M6导通；在晶体管M2以及M5，晶体管M3以及M6以及晶体管M7的作用下，第n级移位寄存器SR(n)的第一节点PU和移位寄存器单元输出端OUTPUT均被置为低电平；使得第n级移位寄存器SR(n)的移位寄存器单元输出端OUTPUT不再输出高电平的电压，从而实现在该阶段利用复位模块300(包括晶体管M2以及M5)以及第一下拉控制模块400(包括晶体管M3以及M6)对第n级移位寄存器SR(n)的第一节点PU以及移位寄存器单元输出端OUTPUT的复位；
可以理解的是，由于在该阶段之后至下一帧的第一阶段之前，第n级移位寄存器SR(n)中的第一节点PU均不会被置为高电平，使得在该阶段之后，第二节点PD1的电平状态与第二时钟信号输入端CLKB的电平状态一致，每一次第二时钟信号CLKB为高电平时，第一下拉控制模块400(包括晶体管M3以及M6)均会对第一节点PU以及移位寄存器单元输出端OUTPUT进行一次复位；
另外，在该阶段时对第n+1级移位寄存器SR(n+1)来说，其接入的信号状态与第n级移位寄存器SR(n)在第二阶段t2时的状态相同，因此第n+1级移位寄存器SR(n+1)在该阶段第二节点PD1为低电平，所以此时第n级移位寄存器SR(n)的第三节点PD2也为低电平，使得晶体管M1以及M4关断，在本阶段中对第一节点不起到下拉的作用；
在第四阶段t4(即辅助复位阶段)，第n+1级移位寄存器SR(n+1)接入的信号的情况与第n级移位寄存器SR(n)在第三阶段t3中关键节点的电平状态完全相同，相应的，此时第n+1级移位寄存器SR(n+1)中关键节点的状态与第n级移位寄存器SR(n)在第三阶段t3中关键节点的电平状态完全相同；即在第n+1级移位寄存器SR(n+1)中，第二节点PD1会被置为高电平，因此，在该阶段内第n级移位寄存器SR(n)的第三节点PD2为高电平，使得晶体管M1和M4导通，将第一节点PU以及移位寄存器单元输出端OUTPUT进行下拉复位；
可以理解的是，在该阶段之后至这一帧结束的期间内，由于第n级移位寄 存器SR(n)接入的CLKB信号与第三节点控制输入端接入的第n+1级移位寄存器SR(n+1)的第二节点PD1信号互为相反的信号，因此，在CLKB以及第n+1级移位寄存器SR(n+1)的第二节点PD1的控制下，第二节点PD1与第三节点PD2交替被置为高电平，使得第一下拉控制模块300(包括晶体管M3、M6)以及第二下拉控制模块400(包括晶体管M1和M4)交替对第一节点PU以及移位寄存器单元输出端OUTPUT进行下拉复位，避免该移位寄存器单元在不该输出扫描脉冲的阶段输出扫描脉冲。
综合上述的分析可以得知，对于本公开提供的移位寄存器单元以及栅极驱动电路来说，在每一级移位寄存器单元中的各个模块能够实现相应的功能的前提下，各个模块如何实现并不会影响本公开的实施，相应的技术方案也均应该落入本公开的保护范围。
第三方面，本公开还提供了一种显示装置，包括第二方面所述的栅极扫描电路。
此外，尽管以上实施例中以N型晶体管为例加以具体说明，但本公开不限于此。事实上本公开一些实施例同样也适用于P型晶体管。
这里的显示装置可以为：电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开提供的移位寄存器单元中，第二下拉控制模块与第三节点相连，被配置为在第三节点控制信号输入端的控制下，与复位模块以及第一下拉控制模块相配合，在该移位寄存器单元不应输出扫描脉冲的阶段共同对该移位寄存器单元进行复位，从而能够有效避免该移位寄存器单元在不该输出扫描脉冲的阶段输出扫描脉冲。
最后应说明的是：以上实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述实施例对本公开进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的精神和范围。

Claims (16)

  1. 一种移位寄存器单元，包括：
    输出模块，连接第一节点、第一时钟信号输入端以及移位寄存器单元输出端，被配置为在第一节点的控制下将第一时钟信号输入端的信号传输给移位寄存器单元输出端；
    输入模块，连接第一节点、移位寄存器单元输入端，被配置为在移位寄存器单元输入端的控制下将移位寄存器单元输入端的信号传输给第一节点；
    复位模块，连接复位控制信号输入端、第一节点、移位寄存器单元信号输出端以及信号控制端，被配置为在复位控制信号输入端的控制下将信号控制端的信号传输给第一节点和移位寄存器单元信号输出端；
    第一下拉控制模块，连接第二节点、第一节点、移位寄存器单元信号输出端以及信号控制端，被配置为在第二节点的控制下将信号控制端的信号传输给第一节点和移位寄存器单元信号输出端；
    第二下拉控制模块，连接第三节点、第一节点和移位寄存器单元信号输出端以及信号控制端，被配置为在第三节点的控制下将信号控制端的信号传输给第一节点和移位寄存器单元信号输出端；
    第二节点控制模块，连接第一节点、第二节点、第二时钟信号输入端以及信号控制端，被配置为在第一节点以及第二时钟信号输入端的控制下将信号控制端的信号或第二时钟信号输入端的信号输出给第二节点；以及
    第三节点控制信号输入端，与所述第三节点连接。
  2. 如权利要求1所述的移位寄存器单元，其中，所述复位模块包括第二晶体管以及第五晶体管；
    所述第二晶体管的栅极连接复位控制信号输入端，源极和漏极中的一个电极连接第一节点，另一个电极连接所述信号控制端，被配置为在复位控制信号输入端的控制下将第一节点与所述信号控制端导通或关断；
    所述第五晶体管的栅极连接复位控制信号输入端，源极和漏极中的一个电极连接移位寄存器单元输出端，另一个电极连接所述信号控制端，被配置为在复位控制信号输入端的控制下将移位寄存器单元输出端与所述信号控制端导 通或关断。
  3. 如权利要求1-2任一项所述的移位寄存器单元，其中，所述第一下拉控制模块包括第三晶体管以及第六晶体管；
    所述第三晶体管的栅极连接第二节点，源极和漏极中的一个电极连接第一节点，另一个电极连接所述信号控制端，被配置为在第二节点的控制下将第一节点与所述信号控制端导通或关断；
    所述第六晶体管的栅极连接第二节点、源极和漏极中的一个电极连接移位寄存器单元信号输出端，另一个电极连接所述信号控制端，被配置为在第二节点的控制下将移位寄存器单元信号输出端与所述信号控制端导通或关断。
  4. 如权利要求1-3任一项所述的移位寄存器单元，其中，所述第二下拉控制模块包括第一晶体管和第四晶体管；
    所述第一晶体管的栅极连接第三节点，源极和漏极中的一个电极连接第一节点，另一个电极连接信号控制端，被配置为在第三节点的控制下将第一节点与信号控制端导通或关断；
    所述第四晶体管的栅极连接第三节点，源极和漏极中的一个电极连接移位寄存器单元输出端，另一个电极连接信号控制端导通，被配置为在第三节点的控制下将移位寄存器单元输出端与信号控制端导通或关断。
  5. 如权利要求1-4任一项所述的移位寄存器单元，其中，所述第二节点控制模块包括第八晶体管、第九晶体管、第十晶体管以及第十一晶体管；
    其中，第八晶体管的栅极连接第二时钟信号输入端，源极和漏极中的一个电极连接第二时钟信号输入端，另一个电极连接第四节点，被配置为在第二时钟信号输入端的控制下将第二时钟信号输入端与所述第四节点导通或关断；
    第九晶体管的栅极连接所述第四节点，源极和漏极中的一个电极连接第二时钟信号输入端，另一个电极连接所述第二节点，被配置为在所述第四节点的控制下将第二时钟信号输入端与第二节点导通或关断；
    第十晶体管的栅极连接第一节点，源极和漏极中的一个电极连接第四节点，另一个电极连接所述信号控制端，被配置为在第一节点的控制下将第四节点与所述信号控制端导通或关断；
    第十一晶体管的栅极连接第一节点，源极和漏极中的一个电极连接第二节 点，另一个电极连接所述信号控制端，被配置为在第一节点的控制下将第二节点与所述信号控制端导通或关断。
  6. 如权利要求1-5任一项所述的移位寄存器单元，还包括：
    第三下拉控制模块，其连接第二时钟信号输入端、移位寄存器单元信号输出端以及信号控制端，被配置为在第二时钟信号输入端的控制下将信号控制端的信号传输给移位寄存器单元信号输出端。
  7. 如权利要求6所述的移位寄存器单元，其中，所述第三下拉控制模块包括第七晶体管；
    第七晶体管的栅极连接第二时钟信号输入端，源极和漏极中的一个电极连接移位寄存器单元信号输出端，另一个电极连接所述信号控制端，被配置为在第二时钟信号输入端的控制下将移位寄存器单元信号输出端与所述信号控制端导通或关断。
  8. 如权利要求1-7任一项所述的移位寄存器单元，其中，所述输入模块包括第十二晶体管；
    所述第十二晶体管的栅极连接移位寄存器单元输入端，源极和漏极中的一个电极连接移位寄存器单元输入端，另一个电极连接第一节点，被配置为在移位寄存器单元输入端的控制下将移位寄存器单元输入端与第一节点导通或关断。
  9. 如权利要求1-8任一项所述的移位寄存器单元，其中，所述输出模块包括第十三晶体管和第一电容；
    所述第十三晶体管的栅极连接第一节点，源极和漏极中的一个电极连接第一时钟信号输入端，另一个电极连接移位寄存器单元输出端，被配置为在第一节点的控制下将第一时钟信号输入端与移位寄存器单元输出端导通或关断；第一电容的一端连接第一节点，另一端连接移位寄存器单元信号输出端。
  10. 一种栅极扫描电路，包括多个级联的移位寄存器单元，所述移位寄存器单元为如权利要求1-9中任一项所述的移位寄存器单元，所述栅极扫描电路还包括多条时钟信号线；
    其中，奇数级的各个移位寄存器单元的第一时钟信号输入端均连接第一时钟信号线，第二时钟信号输入端均连接第二时钟信号线；偶数级的各个移位寄 存器单元的第一时钟信号输入端均连接第二时钟信号线，第二时钟信号输入端均连接第一时钟信号线；
    相邻两级的移位寄存器单元中：上一级移位寄存器单元的移位寄存器单元输出端连接下一级移位寄存器单元的移位寄存器单元输入端，上一级移位寄存器单元的复位控制信号输入端连接下一级移位寄存器单元的移位寄存器单元输出端，上一级移位寄存器单元的第三节点控制信号输入端连接下一级移位寄存器单元的第二节点。
  11. 一种驱动方法，用于驱动如权利要求10所述的栅极扫描电路，所述驱动方法包括：
    在辅助复位阶段，第n级移位寄存器单元的第三节点在第n+1级移位寄存器单元的第二节点的控制下对第n级移位寄存器单元进行复位，其中n为正整数。
  12. 如权利要求11所述的驱动方法，还包括：
    在第一阶段，针对第n级移位寄存器单元，向移位寄存器单元输入端输入高电平，向第一时钟信号输入端输入低电平，向第二时钟信号输入端输入高电平，向信号控制端输入低电平，向复位控制信号输入端输入低电平，向第三节点输入低电平，使得第n级移位寄存器单元输出端输出低电平。
  13. 如权利要求11-12任一项所述的驱动方法，还包括：
    在第二阶段，针对第n级移位寄存器单元，向移位寄存器单元输入端输入低电平，向第一时钟信号输入端输入高电平，向第二时钟信号输入端输入低电平，向信号控制端输入低电平，向复位控制信号输入端输入低电平，向第三节点输入低电平，使得第n级移位寄存器单元输出端输出高电平。
  14. 如权利要求11-13任一项所述的驱动方法，还包括：
    在第三阶段，针对第n级移位寄存器单元，向移位寄存器单元输入端输入低电平，向第一时钟信号输入端输入低电平，向第二时钟信号输入端输入高电平，向信号控制端输入低电平，向复位控制信号输入端输入高电平，向第三节点输入低电平，使得第n级移位寄存器单元输出端输出低电平。
  15. 如权利要求11-14任一项所述的驱动方法，所述在辅助复位阶段，第n级移位寄存器单元的第三节点在第n+1级移位寄存器单元的第二节点的控制 下对第n级移位寄存器单元进行复位的步骤包括：
    针对第n级移位寄存器单元，向移位寄存器单元输入端输入低电平，向第一时钟信号输入端输入高电平，向第二时钟信号输入端输入低电平，向信号控制端输入低电平，向复位控制信号输入端输入低电平，向第三节点输入高电平，使得第n级移位寄存器单元输出端输出低电平。
  16. 一种显示装置，包括如权利要求10所述的栅极扫描电路。
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