WO2018042587A1 - インテリジェント電子デバイス - Google Patents
インテリジェント電子デバイス Download PDFInfo
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- WO2018042587A1 WO2018042587A1 PCT/JP2016/075621 JP2016075621W WO2018042587A1 WO 2018042587 A1 WO2018042587 A1 WO 2018042587A1 JP 2016075621 W JP2016075621 W JP 2016075621W WO 2018042587 A1 WO2018042587 A1 WO 2018042587A1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H1/00—Details of emergency protective circuit arrangements
- H02H1/0007—Details of emergency protective circuit arrangements concerning the detecting means
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
- H02H3/02—Details
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H1/00—Details of emergency protective circuit arrangements
- H02H1/0092—Details of emergency protective circuit arrangements concerning the data processing means, e.g. expert systems, neural networks
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B15/00—Systems controlled by a computer
- G05B15/02—Systems controlled by a computer electric
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
- H02H3/08—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current
- H02H3/093—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current with timing means
- H02H3/0935—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current with timing means the timing being determined by numerical means
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B17/00—Monitoring; Testing
- H04B17/20—Monitoring; Testing of receivers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B3/00—Line transmission systems
- H04B3/02—Details
- H04B3/46—Monitoring; Testing
Definitions
- the present disclosure relates to an intelligent electronic device that receives a signal from a merging unit that collects current and voltage information of a power system and performs a protection relay calculation based on the received signal.
- a process bus application protection system in which a conventional protection relay is divided into a merging unit (MU) and an intelligent electronic device (IED) and connected by a process bus is becoming common (for example, JP, 2015-089182, A (patent documents 1)).
- an MU is installed in the vicinity of a power device provided in a substation or the like, and an electric quantity (current and voltage) signal (current signal and voltage signal) of the power system is captured by the MU.
- the MU performs A / D (Analog to Digital) conversion on the captured electric quantity signal, and transmits the A / D converted digital signal to the IED as serial data via the process bus.
- sample rate when the MU takes in the amount of electricity in the power system for protection control, it is an international standard for instrument transformer digital interface (IEC61869-9, Edition 1.0, 2016-04 (non-patent literature) In 1)
- 4800 Hz is specified as a recommended value. This sample rate is the same whether the system frequency is 50 Hz or 60 Hz, and does not depend on the fluctuation of the system frequency.
- the IED receives the electric quantity data sampled at 4800 Hz from the MU via the process bus, and performs a protection relay calculation based on the received data.
- a protection relay calculation period As the sampling period of data used for protection relay calculation (referred to as “relay calculation period” or “calculation period” in this specification, and its reciprocal number is referred to as a relay calculation frequency), normally, the amount of electricity in the power system (system frequency is defined as Having an electrical angle of 15 °, 22.5 °, 30 °, or the like.
- the sample rate at the time of signal acquisition at the MU is fixed at, for example, 4800 Hz.
- the system frequency f is assumed to be equal to the rated frequency Fn.
- the sample rate of 4800 Hz corresponds to 96f.
- delay calculation frequency 12f
- the system frequency f is 60 Hz
- the relay calculation cycle is changed according to the rated frequency, the electric angle of the data used for the calculation is different, so that the calculation algorithm must be changed as a matter of course. If the calculation algorithm is changed according to the rated frequency of the power system in this way, the development cost of the protection relay will be increased.
- a / D conversion is executed by the MU, not the IED that performs the protection operation, and the sampling frequency is specified, so that the sampling is controlled at a timing suitable for the protection operation. It is difficult to do.
- a possible first countermeasure is to convert the digital data received from the MU back to an analog signal by D / A (Digital to Analog) conversion again in the IED. Then, A / D conversion can be performed at a necessary timing in the IED.
- this method is disadvantageous in cost because it requires the addition of a D / A conversion circuit, an analog circuit, and an A / D conversion circuit in the IED.
- the present invention has been made in consideration of the above-mentioned problems, and its main object is to perform a relay operation cycle even if the sampling timing of current data and / or voltage data received from the merging unit is determined by the merging unit.
- the intelligent electronic device is configured so that the sample timing can be arbitrarily controlled.
- This invention is an intelligent electronic device comprising a communication circuit, an up-conversion unit, a down-conversion unit, and a relay operation unit.
- the communication circuit receives from the merging unit first time-series data having a first sample rate representing the amount of electricity in the power system.
- the up-conversion unit converts the first time-series data into second time-series data having a second sample rate higher than the first sample rate by interpolating the first time-series data. .
- the down-conversion unit periodically takes out a data point at an arbitrary sample time that can be changed from the second time-series data, and thereby extracts the second time-series data from the second time-series data at a lower rate than the first sample rate. It converts into the 3rd time series data which has a sample rate.
- the relay calculation unit performs a protection relay calculation using the third time series data.
- the intelligent electronic device does not convert the digital data received from the merging unit into analog data, but converts it into high sample rate digital data.
- the relay operation cycle The sample timing can be arbitrarily controlled.
- FIG. 1 It is a figure which shows arrangement
- FIG. It is a flowchart which shows operation
- FIG. 10 is a diagram for explaining a down conversion process in a modified example of the first embodiment.
- 6 is a functional block diagram of an IED according to Embodiment 2.
- FIG. 12 is a flowchart showing the operation of the IED of FIG. It is a figure for demonstrating the time series data accumulate
- FIG. 10 is a diagram for explaining a down conversion process in a modified example of the first embodiment.
- 6 is a functional block diagram of an IED according to Embodiment 2.
- FIG. 12 is a flowchart showing the operation of the IED of FIG. It is a figure for demonstrating the time series data accumulate
- FIG. 16 is a timing diagram for explaining a sampling synchronization method in the power line protection current differential relay of FIG. 15.
- FIG. 16 is a functional block diagram of an IED on the Q end side in FIG. 15. It is a flowchart which shows operation
- the current frequency of the power system is called the system frequency.
- the system frequency may be different from the rated frequency (50 Hz or 60 Hz) of the power system.
- the system frequency is described as f
- the rated frequency is described as Fn.
- Amount of electricity At least one of the current or voltage of the power system is called the amount of electricity.
- sampling frequency sample rate
- sampling period A time interval between temporally adjacent data points of time series data is called a sampling period [unit: second].
- sampling frequency or sample rate [unit: Hz].
- the relay calculation cycle (also simply referred to as a calculation cycle) refers to a sampling cycle of time-series data of electric quantities used in a protection relay calculation (also referred to as a protection calculation). Usually, the relay calculation cycle is 15 °, 22.5 °, or 30 ° with the electrical angle of the amount of electricity in the power system as a unit.
- the reciprocal of the relay calculation cycle [unit: second] is referred to as a relay calculation frequency (also simply referred to as a calculation frequency). For protection relay calculation without error, it is desirable that the relay calculation cycle corresponds to the current frequency of the power system (system frequency f).
- Embodiment 1 FIG. [Problem of the first embodiment]
- the main problem of the first embodiment is that the current data and voltage data received from the merging unit are the same regardless of the system frequency even if the sample rate of the current data and voltage data is not an integer multiple of the relay operation frequency. It is to provide an intelligent electronic device capable of using a protection arithmetic algorithm.
- Embodiment 1 in addition to the above-described problem, a method for suppressing a protection relay calculation error that may occur when the system frequency fluctuates from the rated frequency will be described.
- the relay calculation cycle is determined based on the sampling cycle at the MU, the fact that the system frequency is equal to the rated frequency (50 Hz or 60 Hz) is a premise for performing the protection relay calculation. For this reason, if the system frequency f deviates from the rated frequency Fn, an error occurs in the calculation result.
- Patent Document 2 discloses a method of correcting an error due to frequency fluctuation by calculation without detecting the current frequency.
- the IED of this document performs a correction calculation using data that is previous by a sampling period corresponding to 180 ° at the rated frequency.
- This method can also be applied to a system in which the protection relay is separated into MU and IED.
- the required calculation processing increases, so that the processing time of the CPU increases, resulting in an increase in the cost of the protection relay. Therefore, there is a need for a method for correcting a protection calculation error caused by fluctuations in system frequency by a simpler method.
- FIG. 1 is a diagram showing the arrangement of the MU and IED in the power system.
- a current transformer 2 (CT: Current Transformer), a voltage transformer 3 (VT: Voltage Transformer), and a circuit breaker 4 are provided on a three-phase line 1 representing a power transmission line or bus. Is provided.
- the current transformer 2 converts the current flowing through the three-phase line 1 into a current having a magnitude suitable for input to the MU 10.
- the current converted by the current transformer 2 is input to the MU 10.
- the voltage transformer 3 converts the voltage of the three-phase line 1 into a voltage having a magnitude suitable for input to the MU 10.
- the voltage after conversion by the voltage transformer 3 is input to the MU 10.
- MU (Merging Unit) 10 collects information necessary for protection and control of the power system, such as current signals and voltage signals output from the current transformer 2 and the voltage transformer 3, respectively.
- the MU 10 converts the acquired current signal and voltage signal from analog to digital (A / D: Analog to Digital) at a constant sampling period (for example, 4800 Hz) defined by the process bus standard.
- the MU 10 outputs digital data obtained by A / D conversion to the IED 40 via a communication line 6 called a process bus according to a predetermined protocol.
- the IED 40 performs a protection operation (also referred to as a relay operation) based on data received from the MU 10 via the communication line 6.
- the sampling period of data used for the protection calculation (referred to as “relay calculation period” or “calculation period” in order to distinguish from the data acquisition sampling period in the MU as described above) is, for example, 30 ° of the system frequency. It is. If the IED 40 determines that an accident has occurred in the power system as a result of the protection calculation, the IED 40 outputs a trip signal TS to the circuit breaker 4.
- the output circuit of the trip signal TS may be provided in the MU 10.
- the IED 40 transmits a command signal for operating the trip signal output circuit to the MU 10, and the MU 10 outputs a trip signal from the output circuit according to the command signal.
- FIG. 2 is a block diagram illustrating an example of a hardware configuration of the MU and the IED.
- MU 10 includes an input conversion unit 11, an A / D conversion unit 15, an arithmetic processing unit 20, and an interface unit 30.
- the input conversion unit 11 is an input unit to which the current signal of each phase output from the current transformer 2 in FIG. 1 and the voltage signal of each phase output from the voltage transformer 3 in FIG. 1 are input.
- the input converter 11 is provided with a transformer as an input converter 12 (12_1, 12_2,...) (INCONV) for each channel. Each channel is supplied with a current signal for each phase and a current signal for each phase (in FIG. 2, only two channels are representatively shown).
- Each input converter 12 converts the current signal and the voltage signal from the current transformer 2 and the voltage transformer 3 into a signal having a voltage level suitable for signal processing in the A / D converter 15 and the arithmetic processing unit 20.
- the A / D converter 15 includes an analog filter 16 (AF: Analog Filter), a sample hold circuit 17 (S / H: Sample and Hold Circuit), a multiplexer 18 (MPX: Multiplexer), and analog digital (A / D). ) Converter 19.
- analog filters 16 (16_1, 16_2, etc.
- sample hold circuits 17 (17_1, 17_2, etc. Is provided for each channel corresponding to the plurality of input converters 12 (12_1, 12_2,).
- Each analog filter 16 is a filter provided to remove aliasing errors during A / D conversion.
- Each sample and hold circuit 17 samples and holds the signal that has passed through the corresponding analog filter 16 at a predetermined sample rate (also referred to as sampling frequency) (for example, 4800 Hz).
- the multiplexer 18 sequentially selects the voltage signal held in each sample and hold circuit 17.
- the A / D converter 19 converts the signal selected by the multiplexer into a digital value.
- the arithmetic processing unit 20 includes a CPU 21 (Central Processing Unit), a RAM 22 (Random Access Memory), and a ROM 23 (Read Only Memory). Each of these elements is connected to each other via a bus 24.
- the arithmetic processing unit 20 may include an electrically rewritable nonvolatile memory (not shown) such as a flash memory.
- the RAM 22 and ROM 23 are used as the main memory of the CPU 21.
- the CPU 21 controls the overall operation of the MU 10 in accordance with a program stored in the ROM 23 and the nonvolatile memory.
- the interface unit 30 includes a communication circuit 31 (TX / RX) that transmits data to the IED 40 via the communication line 6 (process bus).
- TX / RX communication circuit 31
- the IED 40 includes an interface unit 41 and an arithmetic processing unit 50.
- the interface unit 41 includes a communication circuit 42 (TX / RX1), a transmission / reception circuit 43 (TX / RX2), and a digital output circuit 44 (D / O: Digital Output).
- the communication circuit 42 receives data output from the communication circuit 31 (TX / RX) of the MU 10 and transmitted via the communication line 6 (process bus).
- the transmission / reception circuit 43 (TX / RX2) performs communication according to a predetermined protocol with a higher-level computer (not shown) via a communication line (not shown) called a station bus.
- the digital output circuit 44 (D / O) is an interface circuit for outputting a signal to an external device. For example, the digital output circuit 44 outputs a trip signal TS to the circuit breaker 4 of FIG.
- the trip signal TS may be output from the communication circuit 42 to the communication line 6, received by the communication circuit 31, and output to the circuit breaker 4 via the MU 10.
- the arithmetic processing unit 50 includes a CPU 51, a RAM 52, and a ROM 53. Each of these elements is connected to each other via a bus 54.
- the arithmetic processing unit 50 may include an electrically rewritable nonvolatile memory (not shown) such as a flash memory.
- the RAM 52 and ROM 53 are used as the main memory of the CPU 51.
- the CPU 51 operates according to a program stored in the ROM 53 and the nonvolatile memory. Next, the operation of the arithmetic processing unit 50 in the IED 40 will be described in detail.
- FIG. 3 is a functional block diagram of the IED according to the first embodiment.
- the arithmetic processing unit 50 of the IED 40 includes a digital filter processing unit 60 (DF1), a frequency calculation unit 61 (FCALC), a sample timing control unit 62 (ST), an up-conversion unit 64 (UPCONV), a digital It functions as a filter processing unit 65 (DF2), a data storage unit 66 (DT1), a down conversion unit 67 (DOWNCONV), a data storage unit 68 (DT2), and a relay calculation unit 69 (RY).
- DF1 digital filter processing unit 60
- FCALC frequency calculation unit 61
- ST sample timing control unit 62
- UPCONV up-conversion unit 64
- a digital It functions as a filter processing unit 65 (DF2), a data storage unit 66 (DT1), a down conversion unit 67 (DOWNCONV), a data storage unit 68 (DT2), and a relay calculation unit 69 (RY).
- DF1 digital filter
- the sampling data of the current signal Id and the voltage signal Vd transmitted from the MU 10 in FIG. 1 via the process bus 6 is received by the communication circuit 42 (TX / RX1) of the IED 40.
- the sample rate of this received data is 4800 Hz, for example.
- the digital filter processing unit 60 removes harmonic distortion included in the time-series data (current signal Id and voltage signal Vd) received by the communication circuit 42 (TX / RX1).
- the frequency calculation unit 61 (FCALC) calculates the frequency of the time series data from which harmonic distortion has been removed. Based on the frequency calculation result of the frequency calculation unit 61 (FCALC), the sample timing control unit 62 (ST) determines the number of sampling data points corresponding to an integer multiple of a relay calculation cycle (for example, 30 ° in electrical angle) Data points after conversion).
- the sample timing control unit 62 (ST) outputs a control signal 75 indicating the determined number of sampling data points to the down conversion unit 67 (DOWNCONV).
- the up-conversion unit 64 converts (up-converts) the sample rate of the received data of the communication circuit 42 (TX / RX1) to a higher sample rate.
- the digital filter processing unit 65 removes high frequency components included in the time series data after conversion to a high sample rate. This high-frequency rejection filter provides the necessary attenuation for the harmonic region exceeding 1/2 of the relay calculation frequency.
- the data accumulation unit 66 accumulates the time series data after the filter processing by the digital filter processing unit 65 (DF2) for the time necessary for the relay calculation from the present time.
- the down-conversion unit 67 extracts data from the data storage unit 66 (DT1) for each data point corresponding to the relay calculation cycle determined by the sample timing control unit 62 (ST). That is, the received data sample rate is frequency-converted (down-converted) to a lower sample rate (relay operation frequency).
- the data accumulating unit 68 (DT2) accumulates sampling data for each relay operation cycle extracted by the down conversion unit 67 (DOWNCONV).
- the relay calculation unit 69 (RY) performs relay calculation using the data stored in the data storage unit 68 (DT2).
- the relay calculation unit 69 (RY) determines that an accident has occurred in the power system as a result of the relay calculation, the relay calculation unit 69 (RY) outputs a trip signal via the digital output circuit 44 (D / O).
- FIG. 4 is a flowchart showing the operation of the IED of FIG.
- the operation of the IED 40 will be described in more detail with reference mainly to FIGS. 3 and 4.
- the communication circuit 42 receives current data and voltage data sampled by the MU.
- the received sampling data is taken into the arithmetic processing unit 50.
- the sampling frequency of current data and voltage data is 4800 Hz, for example.
- 4800 Hz corresponds to 96 Fn
- 4800 Hz corresponds to 80 Fn.
- the digital filter processing unit 60 performs digital filter processing in order to remove waveform distortion caused by harmonics.
- the digital filter processing for example, moving average processing (averaging several sample values) is performed.
- the frequency calculation performed in the next step S130 is generally based on the premise that the input signal is an AC waveform, and therefore the frequency cannot be calculated correctly if the input signal contains a harmonic component. For this reason, unnecessary harmonic components are removed by digital filter processing. In the case of a frequency calculation algorithm that can calculate the frequency without any problem even if there is waveform distortion, the processing in step S120 is not necessary.
- the frequency calculation unit 61 calculates the frequency of the input current signal or the input voltage signal after the digital filter processing. This frequency calculation can be performed using any known method.
- the system frequency can be calculated from the interval between adjacent zero cross points.
- the zero cross point can be obtained by interpolating between sample points before and after the zero cross point by linear approximation.
- the system frequency can be calculated based on the ratio between the amplitude value of the AC electric quantity and the amplitude value of the difference between the electric quantities.
- the electrical angle corresponding to the predetermined period T at the rated frequency Fn is ⁇ n (for example, electrical angle 30 °), and the electrical angle corresponding to the predetermined period T when the system frequency is f is ⁇ .
- the electric quantity at the current time t is V (t)
- the sample timing control unit 62 (ST) determines the number of sampling data points corresponding to an integer multiple of the relay operation period based on the current system frequency (however, This data point is for the data point sequence after up-conversion). Specifically, as shown in FIG. 6, for each system frequency, a table indicating the correspondence between the electrical angle (corresponding to an integral multiple of the relay operation cycle) and the number of data points is stored in advance in the ROM 53 or nonvolatile memory (not shown). ) And so on. Based on this table, the sample timing control unit 62 (ST) determines the number of data points corresponding to an integral multiple of the relay calculation cycle. Details of the table in FIG. 6 will be described later.
- step S150 of FIG. 4 the up-conversion unit 64 (UPCONV) performs an up-conversion process for changing to a higher sample rate using the data received in step S110.
- the sample rate of data after up-conversion is determined as follows.
- the sample rate of the input signal 4800 Hz
- the sample rate of the input signal is 96 Fn when the rated frequency Fn is 50 Hz, and 80 Fn when the rated frequency Fn is 60 Hz.
- the relay calculation frequency is 12f.
- the least common multiple of 96Fn, 80Fn, 12f is calculated to be 480Fn.
- the sample rate of the data after up-conversion is set to an integer multiple of the least common multiple 480Fn. By setting the sample rate in this way, the relay calculation cycle data can be easily extracted by performing the down-conversion process in step S180 later.
- the sample rate of the data after up-conversion is 480 Fn (1 times the least common multiple of 480 Fn)
- the data is taken out every 40 samples (that is, the thinning process of 39 samples in between is performed)
- Sampling data of the relay calculation frequency 12f can be obtained.
- the first rated frequency is Fn1 [Hz] and the second rated frequency is Fn2 [Hz] (Fn1 and Fn2 are integers).
- the sample rate of the data after up-conversion is equal to an integral multiple of the least common multiple of P, Q, and the relay operation frequency.
- the sample rate of the data after up-conversion is set to a multiple of 240f which is the least common multiple of 80f and 12f. Good.
- the sample rate of data after up-conversion is 240f (1 times the least common multiple of 240f)
- data points are extracted every 20 samples (that is, thinning processing is performed to thin out 19 samples in between).
- sampling data of the relay calculation frequency 12f can be easily obtained.
- the up-conversion process can be performed by interpolating (interpolating) between adjacent data points.
- interpolating interpolating
- various known methods such as linear interpolation, polynomial interpolation, and trigonometric function interpolation can be used.
- a method of performing linear interpolation using moving average processing will be exemplified as a method with a small amount of calculation and a relatively low load on the CPU.
- FIG. 5 is a timing diagram for explaining the up-conversion process using the moving average.
- FIG. 5 illustrates a case where the power system frequency f is 50 Hz and the sample rate of data received from the MU is 96 f (4800 Hz). Further, a case is shown in which the received data is up-converted to 480f which is one times the least common multiple 480f of 96f, 80f and 12f.
- the horizontal axis represents time t.
- the short arrow in FIG. 5A indicates the sampling timing of the received data
- the short arrow in FIG. 5B indicates the sampling timing of the data after up-conversion
- the thick solid line arrow in FIG. The timing of sampling data after down conversion is shown.
- White circles in FIG. 5B indicate sample points of actual received data.
- an averaging process (that is, a moving average process) for sequentially averaging five consecutive data is performed.
- the sample value at the current time t is I (t)
- the sampling data of 96f is I (t), I (t ⁇ T), I (t ⁇ 2T),.
- the sampling data of 480f before the averaging process is I (t), I (t-1), I (t-2),...
- the sampling data of 480f after the averaging process is Ir (t), Ir (t -1), Ir (t-2),.
- Ir (t) (1/5) ⁇ I (t) + (4/5) ⁇ I (tT)... (7)
- Ir (t-1) (5/5) ⁇ I (tT)
- Ir (t-2) (4/5) ⁇ I (tT) + (1/5) ⁇ I (t-2T)... (9)
- Ir (t-3) (3/5) ⁇ I (tT) + (2/5) ⁇ I (t-2T)... (10)
- Ir (t-4) (2/5) ⁇ I (tT) + (3/5) ⁇ I (t-2T)... (11)
- Ir (t-4) (1/5) ⁇ I (tT) + (4/5) ⁇ I (t-2T)... (12) Is established.
- the interpolation data points after the moving average processing are the same as those obtained by linear interpolation using the reception data points on both sides thereof.
- the actual waveform and the waveform after the averaging process are indicated by solid lines.
- m-1 new data points are arranged at equal intervals between adjacent data points.
- m ⁇ 1 data points are equally spaced in time so as to have the same value as the latest sample value. Be placed.
- a moving average process that sequentially averages every m consecutive data points is performed.
- data after up-conversion is obtained.
- each data point may be shifted by a time corresponding to m-1 times the sampling period of the data after up-conversion. If not necessary, this processing need not be performed.
- the digital filter processing unit 65 performs digital filter processing on the data after up-converting to a sample rate of 480 Fn.
- the waveform distortion caused by the up-conversion process performed in step S150 can be removed, and an anti-aliasing filter for the down-conversion process (sampling at the relay calculation frequency) executed in later step S180 can be configured.
- the relay calculation cycle is 12f
- a frequency component higher than 6f becomes an error. Therefore, in order to remove the error component, a higher-order frequency component than 6f is attenuated.
- the digital filter processing unit 65 having the above characteristics can be configured by any known digital filter.
- a desired cutoff is achieved by appropriately setting the weight (also referred to as a tap coefficient).
- a low-pass filter having a frequency (high-frequency removal filter) can be realized.
- the data storage unit 66 stores the latest data of the sample rate of 480 Fn after the above digital filter processing for the time necessary for the relay calculation.
- a storage area for storing data corresponding to, for example, about three cycles at the system frequency.
- a storage area for example, about 500 milliseconds for a time longer than the time when the system accident has occurred is used. It is necessary to secure.
- the down-conversion unit 67 extracts data from the data storage unit 66 (DT1) for each data point corresponding to the relay operation cycle determined in step S140.
- the system frequency calculated by the frequency calculation unit 61 FCALC
- FCALC frequency calculation unit 61
- the sample timing control unit 62 determines the relay calculation cycle based on a table (described later in FIG. 6) that defines the relationship between the relay calculation cycle and the number of data points for each system frequency. The number of data points corresponding to is determined.
- the relay calculation unit 69 (RY) performs relay calculation using the data stored in the data storage unit 68 (DT2).
- the relay calculation unit 69 (RY) determines that an accident has occurred in the power system as a result of the relay calculation (YES in step S200)
- the relay calculation unit 69 (RY) outputs a trip signal via the digital output circuit 44. If a power system failure has not occurred (NO in step S200), the process from step S110 to step S190 is repeated.
- FIG. 6 is a diagram showing an example of a table for determining the number of data points corresponding to the relay calculation cycle in step S140 of FIG.
- the table in FIG. 6 shows the case where the rated frequency Fn is 50 Hz and the maximum fluctuation range is ⁇ 1 Hz (ie, ⁇ 49 Hz to +51 Hz). Typically, cases of 49.0, 49.5, 49.9, 50.0, 50.1, 50.5, 51.0 Hz are shown, but in an actual table, an arbitrary data delimiter width is shown. Is possible. For example, assuming that the frequency is divided every 0.1 Hz, it is assumed that the frequency within ⁇ 0.05 Hz corresponds to the displayed frequency. For example, in the case of 50.0 Hz, a frequency greater than ⁇ 49.95 Hz and less than or equal to 50.05 Hz is applicable. The frequency increment may be made finer, for example, every 0.01 Hz. In FIG. 6, the case where the rated frequency is 60 Hz and the same frequency fluctuation rate is shown.
- the relay calculation cycle is 12 f (relay calculation is performed at an electrical angle of 30 ° at the rated frequency), and the sample rate of data after up-conversion is 480 Fn. That is, the table in FIG. 6 shows how many data points before the current time are the data points after the up-conversion for each 30 ° electrical angle.
- FIG. 7 is a diagram for explaining an example in which the down conversion process is performed using the table shown in FIG.
- FIG. 7A shows a case where the system frequency is equal to the rated frequency 50 Hz
- FIG. 7B shows a case where the system frequency is changed to 49 Hz.
- the current data point I (t) is selected according to the system frequency f, and the data point sequence I (t), I (t-40), I (t-80) is selected according to the system frequency f. ), ... need not be re-selected every time.
- the data point I (t) selected at a certain point in time is selected from the present time when the next data point after a time corresponding to an electrical angle of 30 ° (corresponding to 40 samples in the data after up-conversion) has elapsed. Is also used as it is as a data point 30 ° before.
- the data of 480 Fn stored in the data storage unit 66 (DT1) in FIG. 3 is the same as when the system frequency is the rated frequency.
- the data point 30 degrees before the current electrical angle from the present time is 41 points before the data point.
- the data point 60 degrees before the current angle in terms of electrical angle corresponds to the data point 82 times before (+2 with respect to 50 Hz).
- the data point m ⁇ 30 ° before the current angle (m is an integer equal to or greater than 1) (m is an integer equal to or greater than 1) is converted into data at a sample rate of 480 Fn.
- the data after the decimal point is rounded off. Therefore, the data after down-conversion stored in the data storage unit 68 (DT2) in FIG. 3 is I (t), I (t-41), I (t-82), I (t-122),. It becomes.
- the current data point I (t) is selected according to the system frequency f, and I (t), I (t ⁇ 41), I (t-82),... Are not reselected every time.
- the data point I (t) selected at a certain point in time is data that is 30 ° before the current point after a lapse of time corresponding to an electrical angle of 30 ° (corresponding to 41 samples in the data after up-conversion). It is used as a point as it is.
- the number of data points corresponding to data 390 degrees before the current electrical angle from the current time corresponds to 490 data points corresponding to one cycle before and the current 30 degrees before the current electrical angle.
- 531 is obtained.
- the number of samples corresponding to the relay calculation cycle can also be obtained directly by calculation.
- the rated frequency is Fn
- the current system frequency is f
- the relay operation frequency is Q ⁇ f (Q is an integer)
- the sample rate of the data after up-conversion is P ⁇ Q ⁇ Fn (P Is an integer).
- the system frequency f is equal to the rated frequency Fn
- the number of data points after up-conversion corresponding to m times the relay operation cycle (m is an integer of 1 or more) is given by m ⁇ P.
- the number of data points after up-conversion corresponding to m times the relay operation cycle (m is an integer of 1 or more) is m ⁇ P ⁇ Fn / f.
- the values in the table of FIG. 6 are obtained by rounding off the decimals of the calculation results.
- the CPU has sufficient processing capacity, it is desirable to obtain the number of data points corresponding to an integral multiple of the relay calculation cycle by the above calculation.
- the sample rate of the data after up-conversion is the sample rate 96Fn before up-conversion (when the rated frequency is 50 Hz) and 80 Fn (when the rated frequency is 60 Hz) and the relay operation frequency 12f (assuming to be equal to 12Fn). 1 times the 480 Fn, which is the least common multiple of.
- the sample rate of the data after up-conversion may be set to twice or more of the least common multiple 480Fn. In this way, by increasing the sample rate of data after up-conversion, the number of data points corresponding to the relay calculation cycle can be adjusted more finely according to fluctuations in the system frequency, thus reducing the error in protection relay calculations. Can be made.
- FIG. 8 is a diagram showing another example of a table for determining the number of data points in step S140 of FIG.
- the range of the system frequency is divided in increments of 0.1 Hz
- the range of the system frequency is divided in increments of 0.3125%.
- the sample rate of the data after the up-conversion is set to 8 times 480 Fn.
- the number of data points P in the case of the rated frequency
- the frequency increment ⁇ [%] is defined as the reciprocal of P (1 / P).
- f is a frequency measurement value
- Fn is a rated frequency
- g represents a positive integer including zero that determines the range of the measured frequency.
- the sample rate of the data after up-conversion is set to the sample rate 96 Fn (when the rated frequency is 50 Hz) and 80 Fn (when the rated frequency is 60 Hz) before the up-conversion and the relay calculation frequency 12f (equal to 12 Fn).
- 480Fn which is the least common multiple of 480Fn
- the sample timing control unit 62 uses the frequency calculation result of the frequency calculation unit 61 (FCALC), the down conversion unit 67 (DOWNCONV) receives data from the data storage unit 66 (DT1). At the time of extraction, the number of data points to be extracted is determined.
- the sample timing control unit 62 (ST) may function as a timing signal generation unit that generates a timing signal having a period corresponding to the frequency calculation result of the frequency calculation unit 61 (FCALC).
- the sample timing control unit 62 (ST) outputs the generated timing signal to the down conversion unit 67 (DOWNCONV).
- the down conversion unit 67 (DOWNCONV) takes out the data point immediately after the timing specified by the timing signal or the data point closest to the timing from the data storage unit 66 (DT1).
- FIG. 9 is a flowchart showing the operation of the IED according to the modification of the first embodiment.
- steps S140 and S180 in the flowchart of FIG. 4 are changed to steps S140A and S180A, respectively. Since the other points of FIG. 9 are the same as those of FIG. 4, the same reference numerals are assigned to the same processes, and the description will not be repeated.
- step S140A sample timing control unit 62 (ST) performs a timing signal (corresponding to reference numeral 75 in FIG. 3) having a calculation frequency (for example, 12f) corresponding to calculated system frequency f. And the generated timing signal 75 is output to the down conversion unit 67 (DOWNCONV). Specifically, the period of the timing signal 75 decreases as the calculated system frequency value becomes higher than the rated frequency, and increases as the calculated system frequency value becomes lower than the rated frequency.
- step S180A the down-conversion unit 67 (DOWNCONV) performs the data point immediately after the timing specified by the timing signal generated in step S140A, the data point immediately before, or the data point immediately before the specified timing.
- the data point immediately before or immediately after the designated timing is taken out from the data storage unit 66 (DT1).
- data points are extracted from the data storage unit 66 (DT1) for each number of data points according to the system frequency.
- FIG. 10 is a diagram for explaining the down-conversion process in the modification of the first embodiment.
- the down-conversion unit 67 (DOWNCONV) extracts the data point immediately after the timing specified by the timing signal from the data storage unit 66 (DT1) and stores it in the data storage unit 68 (DT2).
- the data after down-conversion stored in the data storage unit 68 (DT2) in FIG. 3 is I (t), I (t-40), I (t-80), I (t-120), ..., which is the same as the case of FIG.
- the current system frequency is measured, and the period of data taken out when performing the down-conversion process (that is, the number of data points corresponding to the relay operation frequency) is adjusted according to the measured system frequency.
- the relay calculation cycle can be kept constant regardless of fluctuations in the system frequency.
- the same relay calculation algorithm as that at the rated frequency can be used.
- FIG. [Task] As described with reference to FIG. 3, the latest current data and voltage data having the sample rate after up-conversion are accumulated in the data accumulation unit 66 (DT1) of the IED 40 for the time necessary for the relay calculation.
- DT1 data accumulation unit 66
- a storage area for accumulating data for about three cycles at the system frequency may be secured.
- a storage area for example, about 500 milliseconds
- the data area becomes larger than usual.
- Embodiment 2 provides means for reducing the data storage area in the latter case. Specifically, the amount of data to be stored is reduced by storing only the data up to several cycles before the current time and the data of several cycles up to the occurrence of the accident, and not storing the data in the middle. .
- the amount of data to be stored is reduced by storing only the data up to several cycles before the current time and the data of several cycles up to the occurrence of the accident, and not storing the data in the middle.
- FIG. 11 is a functional block diagram of the IED according to the second embodiment.
- the functional block diagram of FIG. 11 corresponds to FIG. 3 of the first embodiment.
- the arithmetic processing unit 50 of the IED 40 of FIG. 11 is different from the arithmetic processing unit 50 of FIG. 3 in that it further includes a data storage unit 70 (DT3) and a counter 71.
- DT3 data storage unit 70
- the filtered current data and voltage data output from the digital filter processing unit 65 are input to the data storage unit 66 (DT1) and also stored in the data storage unit 70 (DT3). Is done. Further, a control signal is input to the data storage unit 70 (DT3) and the counter 71 from the relay calculation unit 69 (RY). This control signal represents, for example, an accident detection or return to a normal state.
- the data storage unit 70 (DT3) has a latch function (data update stop) and a latch release function (data update restart). Specifically, when the data storage unit 70 (DT3) receives a control signal (referred to as an accident detection signal) indicating an accident detection from the relay calculation unit 69 (RY), the data storage unit 70 (DT3) latches the data stored at the present time ( That is, the update of the accumulated data is stopped). The data storage unit 70 (DT3) latches the stored data when a predetermined time has elapsed from the start of the latch function or when a control signal indicating the return to the normal state is received from the relay calculation unit 69 (RY). Release (that is, resume data update).
- a function of the data storage unit 70 can be realized by controlling data writing to an area corresponding to the data storage unit 70 (DT3) of the RAM 52 by the CPU 51 of FIG.
- the counter 71 starts counting when an accident detection signal is received from the relay calculation unit 69 (RY).
- the counter 71 is for detecting how many cycles have elapsed with reference to the sampling cycle of the time-series data after up-conversion.
- the current counter value (corresponding to the number of cycles) by the counter 71 is stored in the data storage unit 70 (DT3).
- the counter 71 receives a control signal indicating the return to the normal state from the relay operation unit 69 (RY)
- the counter 71 ends the count (the counter value is reset to 0).
- FIG. 12 is a flowchart showing the operation of the IED of FIG.
- the difference from the operation of the IED of the first embodiment (the flowchart of FIG. 4) will be mainly described.
- step S160 the digital filter processing unit 65 (DF2) performs digital filter processing on the data after up-conversion to the sample rate 480Fn.
- step S170 the data accumulating unit 66 (DT1) accumulates the latest electric quantity data (after the up-conversion to 480Fn) after the above digital filter processing for a necessary period.
- step S171 the data accumulation unit 70 (DT3) accumulates the latest electric quantity data after the above digital filter processing only for a necessary period.
- the above data storage time is the period used by the protection elements that require the most past data among the protection elements that do not particularly require the data before the accident.
- Normal data storage time is about 3 cycles before the current time.
- a margin for one cycle at the rated frequency is added to the data accumulation time by taking into account the increase in the number of data points due to frequency fluctuations. That is, each of the data storage unit 66 (DT1) and the data storage unit 70 (DT3) stores data from the current time to four cycles before the rated frequency.
- Step S172 is executed when a system fault is detected by the relay calculation unit 69 (RY) (YES in step S200).
- the data storage unit 70 DT3 stops updating data storage (that is, starts latching data).
- the data before the accident is stored in the data storage unit 70 (DT3).
- the counter 71 starts counting from zero.
- the current counter value is stored in the data storage unit 70 (DT3).
- the relay calculation unit 69 (RY) can detect a system fault at high speed (within one cycle from the occurrence of the accident)
- the data storage unit 70 (DT3) has stored data from the present time to four cycles before.
- three cycles excluding one cycle before and after the occurrence of the accident can be used as data before the occurrence of the system accident.
- Step S174 is performed when a predetermined time (for example, 500 milliseconds) elapses after a system fault is detected by the relay operation unit 69 (RY) (or after latching is started by the data storage unit 70 (DT3)) (step S174). This is executed when a release signal is output from the relay operation unit 69 (RY) in step S173, or in step S174, the data storage unit 70 (DT3) resumes data storage (that is, data latch). Further, the counter 71 finishes counting, and the counter value is reset to zero.
- a predetermined time for example, 500 milliseconds
- FIG. 13 is a diagram for explaining time-series data accumulated after the down-conversion process in step S180 of FIG.
- step S180 of FIG. 12 the down-conversion unit 67 (DOWNCONV) receives data from the data storage unit 66 (DT1) and the data storage unit 70 (DT3) for each data point corresponding to the relay calculation cycle determined in step S140. Take out. As shown in FIG. 13A, the data extracted from the data storage unit 66 (DT1) is stored in the area 671 of the data storage unit DT2 (68), and the data extracted from the data storage unit 70 (DT3) is Data is stored in area 672 of data storage unit DT2 (68).
- the area 671 of the data storage unit DT2 (68) , 672 is data from the present time to approximately four cycles before.
- the data stored in the areas 671 and 672 is not exactly four cycles.
- the data retrieved from the data storage unit 70 (DT3) stored in the area 672 is in a state where updating is stopped when a latch (accident detection) signal is output from the relay calculation unit 69 (RY). Yes, updating is started when a reset (updating start) signal is output from the relay computing unit 69 (RY). Therefore, as shown in FIG. 13B, when no system fault is detected by the relay operation unit 69 (RY), four cycles before the current time stored in the area 671 of the data storage unit DT2 (68). The data up to is used for the relay calculation.
- the data stored in the area 671 of the data storage unit DT2 (68) up to the previous four cycles and the data storage unit DT2 (68) is from the detection of the accident to 4 cycles before.
- FIG. 14 is an explanatory diagram of data stored in a plurality of data storage units in FIG.
- FIG. 14A shows a case where the system frequency is equal to the rated frequency 50 Hz
- FIG. 14B shows a case where the system frequency is changed to 49 Hz.
- the time-series data stored in the data storage unit 70 (DT3) in FIG. 11 is I (t ⁇ m), I (t ⁇ (m + 1)), I (t ⁇ (m + 2)). ,..., I (t ⁇ (m + 1920)).
- the counter value m is 0. Therefore, the time series data stored in the data storage unit 70 (DT3) is the data storage unit 66 (DT1). It becomes the same as the time series data stored in.
- the counter value m is counted up by one every time the sampling period of time series data after up-conversion elapses.
- the time-series data after downconversion stored in the area 671 of the data storage unit 68 (DT2) in FIG. 13A is I (t), I (t-40), I (t-80), I (t-120),..., I (t-1920). If the counter value is m, the time-series data after downconversion stored in the area 672 of the data storage unit 68 (DT2) is I (t ⁇ m), I (t ⁇ (m + 40)), I (t ⁇ (M + 80)), I (t ⁇ (m + 120)),..., I (t ⁇ (m + 1920)).
- the data 30 degrees before the current electrical angle from the current time is converted into data points by 41 ( Corresponding to data of +1) with respect to the time of 50 Hz, the data 60 ° before the electrical angle from the current time corresponds to data of 82 before (+2 with respect to the time of 50 Hz) when converted into data points.
- the data one cycle before the current time corresponds to the data before 490 when converted to the number of data points, and the data three cycles and 330 degrees before the current time corresponds to the data points before 1918 when converted to the data points. Corresponds to data.
- the time-series data after down-conversion stored in the area 671 of the data storage unit 68 (DT2) in FIG. 13A is I (t), I (t-41), I (t-82), I (t-122), ..., I (t-1918).
- the time-series data after down-conversion stored in the area 672 of the data storage unit 68 (DT2) is I (t ⁇ m), I (t ⁇ (m + 41)), I (t ⁇ (M + 82)), I (t ⁇ (m + 122)),..., I (t ⁇ (m + 1918)).
- the relay calculation unit 69 (RY) When the relay calculation unit 69 (RY) performs relay calculation using the data 3 to 4 cycles before the current time and the data before the accident, the relay calculation unit 69 (RY) is an area of the data storage unit 68 (DT2). From 672, data corresponding to the necessary number of cycles is extracted. By using the counter value m, pre-accident data before an integer cycle from the present time can be obtained as follows.
- the timing of accident detection by the relay calculation unit 69 (RY) is less than one cycle from the occurrence of the accident.
- the current counter value is X
- the number of data points corresponding to one cycle corresponding to the system frequency is S (S varies depending on the difference between the system frequency and the rated frequency)
- the current electric quantity data is I (t).
- the data at the time of detecting an accident at the start of latching of the data storage unit 70 (DT3)
- I (t ⁇ X) means that the data is X cycles before the present time with reference to the sampling cycle after up-conversion.
- the intelligent electronic device is provided with the data storage unit 70 (DT3) for separately storing data for several cycles before the accident detection as compared with the case of the first embodiment. ing. Therefore, there is an effect that the amount of accumulated time series data of the amount of electricity necessary for the relay calculation can be reduced.
- Embodiment 3 FIG. [Task]
- a current differential relay for power transmission line protection using a protection system having an MU and an IED
- it is necessary to perform a current differential relay operation using data detected at the same time in MUs at both ends of the power transmission line. is there.
- synchronization between the IEDs at both ends of the transmission line is first established, and then a synchronization signal is supplied from each IED to the corresponding MU (see, for example, JP-A-2015-089182 (see Patent Document 1). )).
- FIG. 15 is a block diagram showing a configuration of a current differential relay for power transmission line protection.
- the current transformer 2P converts the current flowing through the P end of the transmission line 1 into a magnitude suitable for input to the MU.
- the analog current signal IPa from the current transformer 2P is input to the MU 10P.
- the MU 10P samples the input current signal IPa at a predetermined sample rate (for example, 4800 Hz), and further performs A / D conversion.
- the digital current signal IPd after A / D conversion is input to the IED 40P via the process bus 6P.
- the current transformer 2Q converts the current flowing through the Q end of the transmission line 1 into a magnitude suitable for input to the MU.
- the analog current signal IQa from the current transformer 2Q is input to the MU 10Q.
- the MU 10Q samples the input current signal IQa at a predetermined sample rate (for example, 4800 Hz) and further performs A / D conversion.
- the digital current signal IQd after A / D conversion is input to the IED 40Q via the process bus 6Q.
- the IED 40P and the IED 40Q transmit the digital current signals IPd and IQd at both ends of the transmission line 1 to each other via the digital transmission path 90.
- each of IED40P and IED40Q compares the electric current signal which self detected with the electric current signal which the other party detected, and determines the presence or absence of the accident of the transmission line 1 based on a comparison result. For example, when the output of the current transformer 2P and the output of the current transformer 2Q are the same in magnitude and opposite in polarity, that is, the addition result of the current signal IPd and the current signal IQd is 0. In this case, there is no accident inside the transmission line 1.
- the sampling timing of the P-terminal current signal IPd and the sampling timing of the Q-terminal current signal IQd must be the same.
- This sample timing synchronization is based on the premise that the transmission delay time from the P-end side IED 40P to the Q-end side IED 40Q via the digital transmission path 90 is equal to the transmission delay time from the Q-end side IED 40Q to the P-end side IED 40P. It is established while transmitting current signals to each other.
- the IEDs 40P and 40Q of the present embodiment for example, 480Fn (Fn is the time series data of the current signals IPd and IQd received from the corresponding MUs 10P and 10Q, as in the case of the first and second embodiments. Up-convert to time series data that is an integral multiple of the rated frequency.
- the IEDs 40P and 40Q down-convert the time series data after the up-conversion to a relay calculation frequency (for example, 12f).
- the IED 40Q on the Q-end side ordinary side adjusts the sample timing of the data data IQd after down-conversion by adjusting which sample time data is selected from the time-series data after up-conversion.
- FIG. 16 is a timing chart for explaining a sampling synchronization method in the power line protection current differential relay of FIG.
- the IED 40P on the P end side is referred to as a master ('Master' or 'parent'), and the IED 40Q on the Q end side is referred to as an ordinary ('Ordinary' or 'child').
- master (P-end side) IED 40P digitally transmits P-end side current data IPd for each relay calculation cycle (for example, calculation frequency 12f, f is a system frequency).
- the data is transmitted to the IED 40Q on the ordinary (Q end side) via the path 90.
- the master (P-end side) IED 40P further sends a synchronization signal (hereinafter referred to as a synchronization signal SYp) together with the current data IPd at a cycle of about once per cycle via the digital transmission line 90 (ordinary Q-end).
- a synchronization signal SYp a synchronization signal
- the synchronization signal SYp is transmitted from the master (P-end side) IED 40P to the ordinary (Q-end side) IED 40Q at the times t1, t4, t7, and t9.
- the IED 40Q on the ordinary (Q end side) is supplied with the current data IQd on the Q end side via the digital transmission line 90 for each relay calculation cycle (for example, the calculation frequency is 12f, f is the system frequency). Transmit to IED 40P on the P end side.
- the ordinary (Q-end side) IED 40Q further sends a synchronization signal (hereinafter referred to as a synchronization signal SYq) together with the current data IQd at a cycle of about once per cycle via the digital transmission line 90 to the master (P-end).
- Side IED40P.
- the synchronization signal SYq is transmitted from the IED 40Q at the ordinary (Q end side) to the IED 40P at the master (P end side) at the times t2, t5, t8, and t10.
- the reason why the synchronization signals SYp and SYq are transmitted at a rate of about once per cycle is that the transmission / reception time difference Ts or Tr calculated as described later needs to be transmitted to the other end, so that the time required for the transmission is as follows. This is because a time of about one cycle is required. Depending on the design, the transmission period of the synchronization signals SYp and SYq may be different from one cycle.
- the times t1, t4, t7, and t9 coincide with the times t2, t5, t8, and t10, respectively.
- there is a deviation ⁇ t in the sample timing and the sample timing on the Q end side is delayed by ⁇ t from the sample timing on the P end side.
- the master (P-end side) IED 40P measures a transmission / reception time difference Ts from when the synchronization signal SYp is transmitted to when the synchronization signal SYq is received from the Q-end side.
- the measurement result of the transmission / reception time difference Ts is transmitted to the IED 40Q at the ordinary (Q end side).
- the ordinary (Q-end side) IED 40Q also measures the transmission / reception time difference Tr from when the synchronization signal SYq is transmitted until the synchronization signal SYp is received from the P-end side.
- the transmission delay time Td of the digital transmission path 90 from the P end IED 40P to the Q end IED 40Q is equal to the transmission delay time Td of the digital transmission path 90 from the Q end IED 40Q to the P end IED 40P, transmission is performed.
- Ordinary (Q end side) IED 40Q adjusts the data point to be selected so that ⁇ t becomes 0 when selecting 12f time-series data from the time-series data of sample rate 480Fn in the down-conversion unit.
- Ts> Tr as shown in FIG. 16 the IED 40Q selects a data point with an earlier sample time at the time of down conversion. If Ts ⁇ Tr, the IED 40Q selects a data point with a later sample time during downconversion.
- the calculation of the sample timing difference ⁇ t is performed, for example, every cycle according to the transmission period of the synchronization signals SYp and SYq.
- the ordinary (Q-end side) IED 40Q shifts data points to be selected one by one so that ⁇ t becomes 0 each time ⁇ t is calculated.
- the reason for shifting one by one is to prevent the protection relay calculation from being affected because the calculation period before and after the shift becomes too short if the shift is made one at a time. If there is no problem in calculation, it is possible to increase the synchronization speed by increasing the number of data points to be shifted. Such consideration is not necessary.
- the sample timing shift ⁇ t is calculated every cycle, the sample timing synchronization control is performed every cycle.
- FIG. 17 is a functional block diagram of the IED on the Q end side of FIG.
- the interface unit 41 (see FIG. 2) of the IED 40Q further includes a reception circuit 45 (RX) and a transmission circuit 46 (TX).
- the information of the transmission / reception time difference Ts (see FIG. 16) in the IED 40P is received.
- the transmission circuit 46 (TX) transmits the Q-side current signal IQd (sample rate 12f) and the synchronization signal SYq to the P-side IED 40P via the digital transmission line 90.
- the arithmetic processing unit 50 (see FIG. 2) of the IED 40Q includes an up-conversion unit 64 (UPCONV), a digital filter processing unit 65 (DF), a data storage unit 66 (DT1), a down-conversion unit 67 (DOWNCONV), and a data storage unit 68. (DT2), the synchronization processing unit 72, and the differential relay operation unit 69A.
- UPCONV up-conversion unit 64
- DF digital filter processing unit 65
- DT1 data storage unit
- DT1 down-conversion unit 67
- DT2 data storage unit 68.
- the sampling data of the current signal IQd transmitted from the MU 10Q of FIG. 15 via the process bus 6Q is received by the communication circuit 42 (TX / RX1) of the IED 40Q.
- the sample rate of this received data is 4800 Hz, for example.
- the up-conversion unit 64 converts the sample rate of the received data of the communication circuit 42 (TX / RX1) into time-series data with a higher sample rate. Specifically, when the sample rate of the received data is 4800 Hz and the rated frequency Fn is 50 Hz, the received data at the sample rate 96Fn is up-converted to time-series data at the sample rate 480Fn or an integer multiple thereof. Here, assuming that the integer multiple is 1, when the rated frequency Fn is 60 Hz, the reception data at the sample rate 80Fn is up-converted to time-series data at the sample rate 480Fn.
- the digital filter processing unit 65 removes high frequency components included in the time series data after conversion to a high sample rate.
- the attenuation is given.
- the relay calculation frequency is assumed to be 12f, but the relay calculation frequency is not limited to this, and may be 16f (electric angle 22.5 °) or 24f (electric angle 15 °). There may be.
- the data accumulation unit 66 (DT1) accumulates the time series data after the filter processing by the digital filter processing unit 65 (DF2) for the time necessary for the relay calculation from the present time.
- the down-conversion unit 67 takes out data from the data storage unit 66 (DT1) for each data point corresponding to the relay calculation cycle, so that the sample rate stored in the data storage unit 66 (DT1) is 480 Fn. Data is down-converted to time-series data having a relay calculation frequency (for example, 12f). At this time, it is adjusted according to the control signal 76 from the synchronization processing unit 72 which sample time data point is extracted from the data storage unit 66 (DT1).
- the synchronization processing unit 72 calculates a time difference Tr (see FIG. 16) between the transmission time of the current signal IQd in the transmission circuit 46 (TX) and the reception time of the current signal IPd in the reception circuit 45 (RX). Then, the synchronization processing unit 72 performs transmission / reception based on the comparison result between the transmission / reception time difference Ts (see FIG. 16) at the P-end IED 40P received via the reception circuit 45 (RX) and the calculated transmission / reception time difference Tr.
- a control signal 76 is output to the down conversion unit 67 (DOWNCONV) so that the time differences Ts and Tr are equal.
- the synchronization processing unit 72 outputs the P-terminal current signal IPd (sample rate 12f) received via the receiving circuit 45 (RX) as it is to the differential relay calculation unit 69A.
- the P-terminal current signal IPd is delayed by the transmission time of the digital transmission path 90. Therefore, the synchronization processing unit 72 generates the current signal IQd_c obtained by delaying the Q-terminal current signal IQd (sample plate 12f) stored in the data storage unit 68 (DT2) by the transmission delay time (Td in FIG. 16). Then, the generated current signal IQd_c is output to the differential relay operation unit 69A.
- the transmission delay time Td is the transmission / reception time difference in the IED 40P on the P end side. It becomes equal to Ts and the transmission / reception time difference Tr in the IED 40Q on the Q end side.
- the differential relay calculation unit 69A performs a relay calculation based on the P-terminal current signal IPd and the Q-terminal current signal IQd_c received from the synchronization processing unit 72.
- the relay calculation unit 69 (RY) determines that an accident has occurred in the transmission line 1 as a result of the relay calculation, the relay calculation unit 69 (RY) outputs a trip signal via the digital output circuit 44 (D / O).
- the arithmetic processing unit 50 of the master IED 40P on the P-end side has the same configuration as that of the ordinary IED 40Q on the Q-end side in FIG. However, the operations of the down-conversion unit 67 (DOWNCONV) and the synchronization processing unit 72 are different between the P-side IED 40P and the Q-side IED 40Q.
- the P-side IED 40P transmits the P-terminal current signal IPd to the Q-terminal at its own timing, so that the down-conversion unit 67 (DOWNCONV) takes out data from the data storage unit 66 (DT1). Do not adjust the data point sample time so that it matches the other end.
- the down-conversion unit 67 (DOWNCONV) takes out data from the data storage unit 66 (DT1). Do not adjust the data point sample time so that it matches the other end.
- FIG. 18 is a flowchart showing the operation of the IED on the Q end side in FIG.
- the operation of the IED 40Q at the Q end on the ordinary side will be described in more detail with reference mainly to FIG. 17 and FIG.
- the communication circuit 42 receives the current data and voltage data sampled by the MU 10Q in FIG.
- the received sampling data is taken into the arithmetic processing unit 50.
- the sampling frequency of current data and voltage data is 4800 Hz, for example.
- the rated frequency Fn is 50 Hz
- 4800 Hz corresponds to 96 Fn
- the rated frequency Fn is 60 Hz
- 4800 Hz corresponds to 80 Fn.
- step S320 the up-conversion unit 64 (UPCONV) performs an up-conversion process for changing to a higher sample rate using the data received in step S310.
- the sample rate of the data after up-conversion is the least common multiple of 96f, 80f, and 12f, assuming that the system frequency f is equal to the rated frequency Fn and the relay operation frequency is 12f, as in the first and second embodiments. It is set to an integer multiple of (480f).
- the digital filter processing unit 65 performs digital filter processing on the data after up-conversion to a sample rate that is an integral multiple of 480Fn.
- a low-pass that provides the necessary attenuation for frequencies exceeding 1/2 of the relay operation frequency.
- a filter is configured.
- the data accumulating unit 66 (DT1) accumulates the latest data having a sample rate that is an integer multiple of 480Fn after the digital filter processing for a time (about 3 cycles) necessary for the relay operation.
- the down-conversion unit 67 (DOWNCONV) is stored in the data storage unit 66 (DT1) by taking out data from the data storage unit 66 (DT1) for each data point corresponding to the relay calculation cycle.
- the data with the sample rate of 480 Fn is down-converted to time-series data having a relay calculation frequency (for example, 12f).
- a relay calculation frequency for example, 12f.
- one piece of data is taken out every 40 data points (ie, 39 data points will be thinned out).
- the Q-terminal current signal IQd at the sample rate 12f is obtained.
- the synchronization processing unit 72 includes a transmission / reception time difference Ts (see FIG. 16) in the PED IED 40P received via the reception circuit 45 (RX), and the calculated transmission / reception time difference Tr. Based on the comparison result, a control signal 76 is output to the down-conversion unit 67 (DOWNCONV) so that the transmission / reception time differences Ts and Tr are equal to each other. More specifically, when Ts> Tr, the synchronization processing unit 72 extracts a data point at a time earlier by one sampling period when extracting data from the data storage unit 66 (DT1).
- the differential relay calculation unit 69A performs the relay calculation based on the P terminal current signal IPd and the Q terminal current signal IQd_c (delayed by the transmission delay time Td) received from the synchronization processing unit 72. Do.
- the relay calculation unit 69 (RY) determines that an accident has occurred in the transmission line 1 as a result of the relay calculation (YES in step S390)
- the relay calculation unit 69 (RY) passes through the digital output circuit 44 (D / O).
- a trip signal is output (step S400). If no accident is detected by the differential relay calculation unit 69A, the above steps S310 to S380 are repeated.
- FIG. 19 is an explanatory diagram of the down-conversion process in step S350 of FIG.
- FIG. 19A shows a case where the transmission / reception time difference Ts at the P-end IED 40P is larger than the transmission / reception time difference Tr at the Q-end IED 40Q (Ts> Tr), and
- FIG. 19B shows a case where Ts ⁇ Tr. Indicates.
- time-series data stored in data storage unit 66 (DT1) in FIG. 17 is represented by I (t), I (t ⁇ 1), I ( t-2), and so on.
- the hatched data I (t), I (t-40), I (t-40 ⁇ 2),... are data extracted by the down conversion unit 67 (DOWNCONV).
- the received sample value I (t) at time t0 corresponds to I (t ⁇ 40).
- ⁇ 1 is output as the control signal 76 from the synchronization processing unit 72, so the down-conversion unit 67 (DOWNCONV) is I (t ⁇ 1) that is ⁇ t before I (t). Take the sample value of.
- the sample value I (t ⁇ 1) taken out is transmitted to the P-terminal IED 40P.
- ⁇ 1 is output as the control signal 76 from the synchronization processing unit 72, so that the down-conversion unit 67 (DOWNCONV) has I (t ⁇ 1) further before ⁇ (t ⁇ 1) by ⁇ t. -2) take out the sample value.
- the sample value I (t ⁇ 2) taken out is transmitted to the P-terminal IED 40P.
- time-series data stored in data storage unit 66 (DT1) in FIG. 17 are represented by I (t), I (t ⁇ 1), I ( t-2), and so on.
- the hatched data I (t), I (t-40), I (t-40 ⁇ 2),... are data extracted by the down conversion unit 67 (DOWNCONV).
- the down-conversion unit 67 (DOWNCONV) has a sample value of I (t + 1) that is ⁇ t later than I (t). Take out.
- the sample value I (t + 1) taken out is transmitted to the P-terminal IED 40P.
- the down-conversion unit 67 (DOWNCONV) is a sample of I (t + 2) further ⁇ t after I (t + 1). retrieve the value.
- the sample value I (t ⁇ 2) taken out is transmitted to the P-terminal IED 40P.
- sampling synchronization at both ends of the transmission line can be realized without requiring a synchronization signal from the IED to the MU.
- the up-conversion is set to 480 Fn, but higher sampling synchronization accuracy can be obtained by setting the integer multiple to a higher sample rate.
- the system frequency f is assumed to be equal to the rated frequency Fn. However, even if the system frequency f is different from the rated frequency Fn, sampling synchronization at both ends of the transmission line can be realized by the above method.
- the PED side and Q end side IED calculation processing units 50 include the digital filter processing unit 60 (DF1) and the frequency calculation unit 61 (FCALC). And a sample timing control unit 62 (ST) are further provided.
- the number of data points corresponding to the relay calculation cycle is adjusted based on the current system frequency f. Is done.
- the synchronization processing unit 72 may also function as the sample timing control unit 62 (ST).
- the calculation result of the system frequency by the frequency calculation unit 61 (FCALC) is input to the synchronization processing unit 72.
- the synchronization processing unit 72 outputs a control signal 76 (a timing signal in the case of the modification of the first embodiment) to the down conversion unit 67 (DOWNCONV) based on the transmission / reception time differences Ts and Tr and the system frequency value. .
- the arithmetic processing unit 50 may be configured by a circuit such as an application specific integrated circuit (ASIC) or a field-programmable gate array (FPGA).
- ASIC application specific integrated circuit
- FPGA field-programmable gate array
- the conventional protection relay has been described as being functionally divided into an MU and an IED, but the function of the IED is not limited to this.
- the IED may be configured to include a power system control function in addition to the protection relay calculation.
- 76 control signal (FIG. 17), 90 digital transmission path, Fn rated frequency, Id digital current signal, IPd P End side digital current signal, IQd Q end side digital current signal, TS trip signal, Td transmission delay time, Tr transmission / reception time difference (Q end side IED), Ts transmission / reception time difference (P end side IED).
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Abstract
Description
以下、本明細書中で使用する注意すべき用語の意味について説明する。
電力系統の現在の周波数を系統周波数という。系統周波数は電力系統の定格周波数(50Hzまたは60Hz)と異なる場合がある。この明細書では系統周波数をfと記載し、定格周波数をFnと記載する。
電力系統の電流または電圧の少なくとも一方を電気量という。
時系列データの時間的に隣接するデータ点の時間間隔をサンプリング周期[単位:秒]という。サンプリング周期の逆数をサンプリング周波数(またはサンプルレート)[単位:Hz]という。
リレー演算周期(単に演算周期とも称する)とは、保護リレー演算(保護演算とも称する)に用いられる電気量の時系列データのサンプリング周期をいう。通常、リレー演算周期は、電力系統の電気量の電気角を単位として15°、22.5°、30°が用いられる。リレー演算周期[単位:秒]の逆数をリレー演算周波数という(単に演算周波数とも称する)。誤差のない保護リレー演算のためには、リレー演算周期は、電力系統の現在の周波数(系統周波数f)に対応したものが望ましい。
[実施の形態1の課題]
実施の形態1の主な課題は、前述のように、マージングユニットから受信する電流データおよび電圧データのサンプルレートがリレー演算周波数の整数倍でなかったとしても、系統周波数の違いによらない同一の保護演算アルゴリズムを用いることが可能なインテリジェント電子デバイスを提供することである。
図1は、MUとIEDの電力系統における配置を示す図である。図1を参照して、電力用送電線または母線を表す三相線路1上には、電流変成器2(CT:Current Transformer)、電圧変成器3(VT:Voltage Transformer)、および遮断器4が設けられている。電流変成器2は、三相線路1を流れる電流をMU10への入力に適した大きさの電流に変換する。電流変成器2による変換後の電流はMU10に入力される。同様に、電圧変成器3は、三相線路1の電圧をMU10への入力に適した大きさの電圧に変換する。電圧変成器3による変換後の電圧はMU10に入力される。
図2は、MUおよびIEDのハードウェア構成の一例を示すブロック図である。図2を参照して、MU10は、入力変換部11と、A/D変換部15と、演算処理部20と、インターフェイス部30とを備える。
図3は、実施の形態1のIEDの機能ブロック図である。図3を参照して、IED40の演算処理部50は、デジタルフィルタ処理部60(DF1)、周波数演算部61(FCALC)、サンプルタイミング制御部62(ST)、アップコンバージョン部64(UPCONV)、デジタルフィルタ処理部65(DF2)、データ蓄積部66(DT1)、ダウンコンバージョン部67(DOWNCONV)、データ蓄積部68(DT2)、およびリレー演算部69(RY)として機能する。上記の各機能は、CPU51がプログラムに従って動作することによって実現される。以下、各機能部の動作の概要を説明する。
図4は、図3のIEDの動作を示すフローチャートである。以下、図3および図4を主として参照して、IED40の動作についてさらに詳しく説明する。
|V(t)|2=[V(t-3T)・V(t-3T)-V(t)・V(t-6T)]/(sin3T)2 …(1)
|dV(t)|2=[dV(t-3T)・dV(t-3T)-dV(t)・dV(t-6T)]/(sin3T)2 …(2)
によって表される。A=|dV(t)|/|V(t)|とすると(sin(3T)は打ち消されるので計算の必要はない)、電気角θは、
θ=sin-1(A/2) …(3)
によって表される。したがって、系統周波数fは、
f=fn・θ/θn …(4)
に従って計算することができる。
I(t-T)=I(t-1)=I(t-2)=I(t-3)=I(t-4)=I(t-5) …(5)
I(t-2T)=I(t-6)=I(t-7)=I(t-8)=I(t-9)=I(t-10) …(6)
が成立する。時刻t-3T以前のデータについても同様である。
Ir(t)=(1/5)・I(t)+(4/5)・I(t-T) …(7)
Ir(t-1)=(5/5)・I(t-T) …(8)
Ir(t-2)=(4/5)・I(t-T)+(1/5)・I(t-2T) …(9)
Ir(t-3)=(3/5)・I(t-T)+(2/5)・I(t-2T) …(10)
Ir(t-4)=(2/5)・I(t-T)+(3/5)・I(t-2T) …(11)
Ir(t-4)=(1/5)・I(t-T)+(4/5)・I(t-2T) …(12)
が成立する。上式によれば、移動平均処理後の補間データ点は、その両側の受信データ点を用いて直線補間することによって得られたものと同じであることがわかる。図5(C)では、実際の波形と、平均化処理後の波形とが実線で示されている。平均化処理後の波形を、4個のサンプル点に相当する時間分だけ各データ点をシフトすることによって、実際の波形にほぼ重ねることができる。
図6は、図4のステップS140においてリレー演算周期に対応するデータ点数を決定するためのテーブルの一例を示す図である。
図8は、図4のステップS140においてデータ点数を決定するためのテーブルの他の例を示す図である。図6のテーブルでは、0.1Hz刻みで系統周波数の範囲を分割していたのに対し、図8のテーブルでは、0.3125%の刻み幅で系統周波数の範囲を分割している。
Fn・(1-α/2)<f≦Fn・(1+α/2)のとき、対応するデータ点数はP
Fn・((1-(α/2))<f≦Fn・((1-3(α/2))のとき、対応するデータ点数はP+1
Fn・((1-3(α/2))<f≦Fn・((1-5(α/2))のとき、対応するデータ点数はP+2
一般に、Fn・((1-(2g+1)(α/2))<f≦Fn・((1-(2g+3)(α/2))のとき、対応するデータ点数はP+(g+1)となる。
Fn・((1+(α/2))<f≦Fn・((1+3(α/2))のとき、対応するデータ点数はP-1
Fn・((1+3(α/2))<f≦Fn・((1+5(α/2))のとき、対応するデータ点数はP-2
一般に、Fn・((1+(2g+1)(α/2))<f≦Fn・((1+(2g+3)(α/2))のとき、対応するデータ点数はP-(g+1)となる。
上記の実施の形態では、サンプルタイミング制御部62(ST)は、周波数演算部61(FCALC)の周波数演算結果に基づいて、ダウンコンバージョン部67(DOWNCONV)がデータ蓄積部66(DT1)からデータを取り出す際に何データ点数ごとにデータ点を取り出すかを決定していた。
上記のとおり実施の形態1のIEDによれば、電流データおよび電圧データは、補間処理によってMUでのA/D変換時のサンプルレートよりも高い周波数にアップコンバージョンされる。その後、ダウンコンバージョン処理(間引き処理)によってリレー演算用の電流データおよび電圧データが生成される。アップコンバージョン後のデータのサンプルレートが、A/D変換時のサンプルレートとリレー演算周波数との最小公倍数の倍数に設定されることによって、定格周波数に依存せずに同一のリレー演算アルゴリズムを使用することができる。
[課題]
図3で説明したように、IED40のデータ蓄積部66(DT1)には、アップコンバージョン後のサンプルレートを有する最新の電流データおよび電圧データがリレー演算に必要な時間分だけ蓄積される。通常のリレー演算の場合には系統周波数で3サイクル程度の時間分だけのデータを蓄積するための保存エリアを確保すればよい。リレー演算のために事故後の波形と事故前の波形との差分処理を行う場合には、系統事故の発生している時間よりも長い時間分の保存エリア(例えば、500ミリ秒程度)を確保する必要がある。この場合、サンプルレートのアップコンバージョンを行っているために通常よりもさらにデータ領域が大きくなる。
図11は、実施の形態2のIEDの機能ブロック図である。図11の機能ブロック図は、実施の形態1の図3に対応するものである。具体的に、図11のIED40の演算処理部50は、データ蓄積部70(DT3)およびカウンタ71をさらに備える点で、図3の演算処理部50と異なる。
図12は、図11のIEDの動作を示すフローチャートである。以下、図11および図12を参照して、実施の形態1のIEDの動作(図4のフローチャート)と異なる点を主に説明する。
X+Y=N・S …(13)
の関係が成立する。上式においてNは1以上の整数であり、Yは0≦Y<Sを満たす整数である。よって、Yは、
Y=S・N-X …(14)
によって計算することができる。上記(14)式において、SおよびXは既知であるので(Sは系統周波数に応じて変化する)、0≦Y<SとなるようにNを選択することよってYを決定することができる。
このように、実施の形態2のインテリジェント電子デバイスでは、実施の形態1の場合に比較して、事故検出前の数サイクル分のデータを別途保存するためのデータ蓄積部70(DT3)が設けられている。したがって、リレー演算に必要な電気量の時系列データの蓄積量を削減できる効果がある。
[課題]
MUとIEDとを有する保護システムを用いて送電線保護用電流差動リレーを構成する場合、送電線の両端のMUにおいて同時刻において検出されたデータを用いて電流差動リレー演算を行う必要がある。従来の方法では、送電線の両端のIED同士の同期がまず確立され、次に、各IEDから対応するMUに同期信号が供給される(たとえば、特開2015-089182号公報(特許文献1参照))。
図15は、送電線保護用電流差動リレーの構成を示すブロック図である。
図16は、図15の送電線保護用電流差動リレーにおいてサンプリング同期の方法について説明するためのタイミング図である。P端側のIED40Pをマスタ(‘Master’或いは‘親’)と称し、Q端側のIED40Qをオーディナリ(‘Ordinary’或いは‘子’)と称する。
Td=Ts-Δt=Tr+Δt …(15)
と表される。したがって、サンプルタイミングのずれΔtは、
Δt=(Ts-Tr)/2 …(16)
で与えられる。
図17は、図15のQ端側のIEDの機能ブロック図である。
図18は、図17のQ端側のIEDの動作を示すフローチャートである。以下、図17および図18を主として参照して、オーディナリ側であるQ端のIED40Qの動作についてさらに詳しく説明する。
上記のとおり、実施の形態3のIEDによれば、IEDからMUへの同期信号を必要としないで送電線両端でのサンプリング同期を実現することができる。なお、上記例ではアップコンバージョンとして480Fnとしたが、この整数倍としてさらに高サンプルレートにすることでより高いサンプリング同期精度が得られる。
上記の実施の形態1~3では、演算処理部50は、CPU、RAM、およびROMを含むマイクロコンピュータをベースに構成される例について説明した。これに代えて、演算処理部50をASIC(Application Specific Integrated Circuit)またはFPGA(Field-Programmable Gate Array)などの回路によって構成することもできる。
Claims (14)
- 電力系統の電気量を表す第1のサンプルレートの第1の時系列データをマージングユニットから受信する通信回路と、
前記第1の時系列データを補間することによって、前記第1の時系列データを前記第1のサンプルレートよりも高レートの第2のサンプルレートを有する第2の時系列データに変換するアップコンバージョン部と、
前記第2の時系列データから変更可能な任意のサンプル時刻のデータ点を周期的に取り出すことによって、前記第2の時系列データを前記第1のサンプルレートよりも低レートの第3のサンプルレートを有する第3の時系列データに変換するダウンコンバージョン部と、
前記第3の時系列データを用いて保護リレー演算を行うリレー演算部とを備える、インテリジェント電子デバイス。 - 前記ダウンコンバージョン部は、前記第1の時系列データに基づいて定められたデータ点数ごとに前記第2の時系列データから一部のデータを取り出す、請求項1に記載のインテリジェント電子デバイス。
- 前記第1の時系列データに基づいて、前記電力系統の現時点の系統周波数を算出する周波数演算部をさらに備え、
前記定められたデータ点数は、前記系統周波数に応じて調節される、請求項2に記載のインテリジェント電子デバイス。 - 前記定められたデータ点数は、前記系統周波数が定格周波数よりも大きくなるにつれて小さくなり、前記系統周波数が前記定格周波数よりも小さくなるにつれて大きくなる、請求項3に記載のインテリジェント電子デバイス。
- 前記第1の時系列データに基づいてタイミング信号を生成する、タイミング信号生成部をさらに備え、
前記ダウンコンバージョン部は、前記タイミング信号に従ったタイミングで前記第2の時系列データから一部のデータを取り出す、請求項1に記載のインテリジェント電子デバイス。 - 前記第1の時系列データに基づいて、前記電力系統の現時点の系統周波数を算出する周波数演算部をさらに備え、
前記タイミング信号生成部は、前記系統周波数に応じて前記タイミング信号の周期を調整する、請求項5に記載のインテリジェント電子デバイス。 - 前記タイミング信号の周期は、前記系統周波数が定格周波数よりも大きくなるにつれて小さくなり、前記系統周波数が前記定格周波数よりも小さくなるにつれて大きくなる、請求項6に記載のインテリジェント電子デバイス。
- 前記インテリジェント電子デバイスは、
現時刻から予め定められた時間だけ前までの前記第2の時系列データを順次更新しながら蓄積する、第1のデータ蓄積部および第2のデータ蓄積部と、
カウンタとをさらに備え、
前記リレー演算部によって前記電力系統に事故が検出されたとき、前記第1のデータ蓄積部は更新を継続し、前記第2のデータ蓄積部は更新を停止し、前記カウンタはカウントを開始し、
前記ダウンコンバージョン部は、前記第1および第2のデータ蓄積部の各々に蓄積されたデータを前記第3のサンプルレートを有する前記第3の時系列データに変換し、
前記インテリジェント電子デバイスは、第3のデータ蓄積部をさらに備え、
前記第3のデータ蓄積部は、前記第3の時系列データを蓄積するとともに、前記カウンタの値を格納する、請求項1~7のいずれか1項に記載のインテリジェント電子デバイス。 - 前記インテリジェント電子デバイスは、送電線の第1端に設けられ、
前記インテリジェント電子デバイスは、
デジタル伝送路を介して前記送電線の第2端に設けられた他のインテリジェント電子デバイスに、第1の同期信号ならびに前記第3の時系列データを前記第1端の電流信号として送信するための送信回路と、
前記他のインテリジェント電子デバイスから前記デジタル伝送路を介して送信された前記第2端の電流信号および第2の同期信号を受信するための受信回路とをさらに備え、
前記受信回路は、さらに、前記他のインテリジェント電子デバイスが前記第2の同期信号を送信してから前記第1の同期信号を受信するまでの時間差である、第1の送受信時間差の情報を前記他のインテリジェント電子デバイスから受信し、
前記インテリジェント電子デバイスは、同期処理部をさらに備え、
前記同期処理部は、前記第1の同期信号を送信してから前記第2の同期信号を受信するまでの時間差である、第2の送受信時間差を算出し、
前記ダウンコンバージョン部は、前記第3の時系列データを生成する際に、前記第1および第2の送受信時間差の比較結果に応じて異なるサンプル時刻のデータ点を前記第2の時系列データから取り出す、請求項1~8のいずれか1項に記載のインテリジェント電子デバイス。 - 前記第1の送受信時間差が前記第2の送受信時間差よりも大きいとき、前記ダウンコンバージョン部は、前記第3の時系列データを生成する際に、より早いサンプル時刻のデータ点を前記第2の時系列データから取り出し、
前記第1の送受信時間差が前記第2の送受信時間差よりも小さいとき、前記ダウンコンバージョン部は、前記第3の時系列データを生成する際に、より遅いサンプル時刻のデータ点を前記第2の時系列データから取り出す、請求項9に記載のインテリジェント電子デバイス。 - 前記インテリジェント電子デバイスは、送電線の第1端に設けられ、
前記インテリジェント電子デバイスは、前記送電線の第2端に設けられた他のインテリジェント電子デバイスと通信するための送信回路および受信回路をさらに備え、
前記ダウンコンバージョン部は、前記第1の時系列データの情報ととともに、前記受信回路を介して前記他のインテリジェント電子デバイスから受信した情報に基づいて、前記第2の時系列データから取り出すデータ点を変更する、請求項2~4のいずれか1項に記載のインテリジェント電子デバイス。 - 前記インテリジェント電子デバイスは、送電線の第1端に設けられ、
前記インテリジェント電子デバイスは、前記送電線の第2端に設けられた他のインテリジェント電子デバイスと通信するための送信回路および受信回路をさらに備え、
前記タイミング信号生成部は、前記第1の時系列データの情報ととともに、前記受信回路を介して前記他のインテリジェント電子デバイスから受信した情報に基づいて、前記タイミング信号を生成する、請求項5~7のいずれか1項に記載のインテリジェント電子デバイス。 - 前記第2のサンプルレートは、前記第1のサンプルレートと前記第3のサンプルレートの最小公倍数の整数倍に等しい、請求項1~12のいずれか1項に記載のインテリジェント電子デバイス。
- 前記インテリジェント電子デバイスは、前記電力系統の定格周波数として互いに異なる第1の定格周波数および第2の定格周波数の両方に適用可能であり、
前記第1のサンプルレートは、前記第1の定格周波数の第1の整数倍に等しく、前記第2の定格周波数の第2の整数倍に等しく、
前記第2のサンプルレートは、前記第1の整数と前記第2の整数と前記第3のサンプルレートとの最小公倍数の整数倍に等しい、請求項1~12のいずれか1項に記載のインテリジェント電子デバイス。
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007306638A (ja) * | 2006-05-08 | 2007-11-22 | Mitsubishi Electric Corp | サンプリング周波数変換装置 |
WO2014002191A1 (ja) * | 2012-06-26 | 2014-01-03 | 三菱電機株式会社 | 電流差動リレー |
JP5399592B1 (ja) * | 2013-03-15 | 2014-01-29 | 三菱電機株式会社 | 電力系統の情報を収集するマージングユニット |
JP2016034174A (ja) * | 2014-07-31 | 2016-03-10 | 株式会社東芝 | ディジタル形保護制御装置 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6396421B1 (en) * | 2001-07-31 | 2002-05-28 | Wind River Systems, Inc. | Method and system for sampling rate conversion in digital audio applications |
US6646500B2 (en) * | 2002-04-02 | 2003-11-11 | Motorola, Inc. | Integrated circuit having an FM demodulator and method therefor |
US6747858B1 (en) * | 2002-12-31 | 2004-06-08 | Texas Instruments Incorporated | Digital sample rate converter architecture |
JP4275696B2 (ja) | 2006-11-09 | 2009-06-10 | 三菱電機株式会社 | サンプリング周波数制御方式および保護継電器 |
US8619840B2 (en) * | 2010-02-26 | 2013-12-31 | Qualcomm Incorporated | Apparatus and methods for sampling rate conversion for wireless transceivers |
EP2410438A1 (en) * | 2010-07-20 | 2012-01-25 | European Space Agency | Method and telemetric device for resampling time series data |
JP5906961B2 (ja) * | 2012-06-27 | 2016-04-20 | ソニー株式会社 | 受信装置および方法、並びにプログラム |
JP6161514B2 (ja) | 2013-10-29 | 2017-07-12 | 三菱電機株式会社 | プロセスバス適用保護システム |
JP6230489B2 (ja) | 2014-06-04 | 2017-11-15 | 三菱電機株式会社 | デジタル保護リレー装置 |
-
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007306638A (ja) * | 2006-05-08 | 2007-11-22 | Mitsubishi Electric Corp | サンプリング周波数変換装置 |
WO2014002191A1 (ja) * | 2012-06-26 | 2014-01-03 | 三菱電機株式会社 | 電流差動リレー |
JP5399592B1 (ja) * | 2013-03-15 | 2014-01-29 | 三菱電機株式会社 | 電力系統の情報を収集するマージングユニット |
JP2016034174A (ja) * | 2014-07-31 | 2016-03-10 | 株式会社東芝 | ディジタル形保護制御装置 |
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