WO2018040245A1 - Hbt manufacturing method - Google Patents
Hbt manufacturing method Download PDFInfo
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- WO2018040245A1 WO2018040245A1 PCT/CN2016/102295 CN2016102295W WO2018040245A1 WO 2018040245 A1 WO2018040245 A1 WO 2018040245A1 CN 2016102295 W CN2016102295 W CN 2016102295W WO 2018040245 A1 WO2018040245 A1 WO 2018040245A1
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- Prior art keywords
- layer
- electrode
- emitter
- collector
- base
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims abstract description 11
- 238000000151 deposition Methods 0.000 claims abstract description 3
- 239000002184 metal Substances 0.000 claims description 30
- 230000015572 biosynthetic process Effects 0.000 claims description 29
- 229920002120 photoresistant polymer Polymers 0.000 claims description 20
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 11
- 239000012535 impurity Substances 0.000 claims description 8
- 210000001747 pupil Anatomy 0.000 claims description 8
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims description 5
- 238000001883 metal evaporation Methods 0.000 claims description 4
- 238000005566 electron beam evaporation Methods 0.000 claims description 3
- 238000001017 electron-beam sputter deposition Methods 0.000 claims description 3
- 238000009713 electroplating Methods 0.000 claims description 3
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 2
- 238000000137 annealing Methods 0.000 claims description 2
- 238000002360 preparation method Methods 0.000 claims 11
- 238000000034 method Methods 0.000 abstract description 19
- KRKNYBCHXYNGOX-UHFFFAOYSA-N citric acid Chemical compound OC(=O)CC(O)(C(O)=O)CC(O)=O KRKNYBCHXYNGOX-UHFFFAOYSA-N 0.000 description 6
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/6631—Bipolar junction transistors [BJT] with an active layer made of a group 13/15 material
- H01L29/66318—Heterojunction transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
Definitions
- An HBT manufacturing method including providing or forming a semiconductor substrate including a substrate stacked in order from bottom to top, and an n-type collector layer
- the present invention produces the emitter electrode, the base electrode lead-out line and the collector electrode lead-out line in the same process, eliminating the need for a separate emitter electrode fabrication process, thereby reducing Manufacturing costs and increased production efficiency.
- the emitter contact layer 7 is a highly cumbersome n-type InGaAs, and the contact barrier with the metal is low, and an ohmic contact can be directly formed between the emitter electrode 11 and the emitter contact layer 7 .
- the emitter electrode 11, the collector electrode lead-out line 12, and the base electrode lead-out line 13 are similarly defined and fabricated in the same process, which eliminates the prior art process of fabricating the emitter electrode, thereby saving The purpose of production costs.
Abstract
An HBT manufacturing method. The method comprises successively performing on a semiconductor substrate: emitter mesa etching, so as to leave an electrode forming region of an emitter electrode, to expose an electrode forming region of a base electrode layer (4) and to manufacture a base electrode (8), performing base electrode mesa etching so as to expose an electrode forming region of a collector electrode layer and to manufacture a collector electrode (9), depositing a dielectric layer (10) outside the electrode forming region of the emitter electrode, and etching the dielectric layer so as to open holes in regions corresponding to the base electrode and the collector electrode, and at the same time manufacturing a collector electrode lead-out wire (12), a base electrode lead-out wire (13) and an emitter electrode (11), and carrying out electrode interconnection wiring. An emitter electrode, a base electrode lead-out wire and a collector electrode lead-out wire are manufactured in the same process, thereby saving on the process of independently manufacturing the emitter electrode, and reducing the manufacturing costs.
Description
一种 HBT制造方法 HBT manufacturing method
技术领域 Technical field
[0001] 本发明涉及半导体技术， 特别是涉及一种 HBT制造方法。 [0001] The present invention relates to semiconductor technology, and more particularly to an HBT manufacturing method.
背景技术 Background technique
[0002] 异质结双极晶体管 (HBT)是发射极区、 基极区和集电极区由禁带宽度不同的材 料制成的晶体管， 是能够工作在超高频和超高速的一种重要的有源器件。 传统 H BT的制程， 在外延形成具有发射极区、 基极区和集电极区的半导体结构后， 依 次分别进行在发射极区形成发射极电极、 基极区形成基极电极、 集电极区形成 集电极电极、 通过金属布线实现电极互联等工艺过程。 上述各工艺过程都至少 需要进行以下步骤： 制作相应图形的光罩； 涂布光刻胶， 通过曝光、 显影将光 罩的图形转移至光刻胶上； 蒸发金属； 通过去除光刻胶而仅在图形相应的部分 残留金属的剥离过程以及多次清洗过程。 在实际生产制程中， 上述工艺过程的 具体制作工序都多达十几二十道。 [0002] Heterojunction Bipolar Transistor (HBT) is a transistor made up of a material with different band gaps in the emitter region, the base region and the collector region, and is an important function for operating at ultra high frequency and ultra high speed. Active device. The conventional H BT process, after epitaxially forming a semiconductor structure having an emitter region, a base region, and a collector region, sequentially forming an emitter electrode in the emitter region, forming a base electrode in the base region, and forming a collector region. Collector electrodes, electrode interconnection through metal wiring, and other processes. Each of the above processes requires at least the following steps: forming a mask of the corresponding pattern; coating the photoresist, transferring the pattern of the mask onto the photoresist by exposure and development; evaporating the metal; removing only the photoresist The stripping process of the residual metal in the corresponding part of the pattern and the multiple cleaning process. In the actual production process, the specific production process of the above process is as many as ten or twenty.
技术问题 technical problem
[0003] 因此， HBT的制程中， 往往存在伴随着制造工序数增加而使得制造成本增大的 问题， 同吋限制了生产效率以及产品的良率。 [0003] Therefore, in the process of HBT, there is often a problem that the manufacturing cost increases as the number of manufacturing processes increases, and the production efficiency and the yield of the product are limited.
问题的解决方案 Problem solution
技术解决方案 Technical solution
[0004] 本发明提供了一种 HBT制造方法， 其克服了现有技术所存在的不足之处。 The present invention provides an HBT manufacturing method that overcomes the deficiencies of the prior art.
[0005] 本发明解决其技术问题所采用的技术方案是： 一种 HBT制造方法， 包括提供或 形成半导体基片， 所述半导体基片包括由下至上依次层叠的衬底、 n型集电极层The technical solution adopted by the present invention to solve the technical problem thereof is: An HBT manufacturing method including providing or forming a semiconductor substrate including a substrate stacked in order from bottom to top, and an n-type collector layer
、 p型基极层、 n型发射极层以及发射极接触层， 还包括以下步骤： The p-type base layer, the n-type emitter layer, and the emitter contact layer further include the following steps:
[0006] 1) 对所述半导体基片进行发射极台面腐蚀以留出发射极的电极形成区域并露 出基极层的电极形成区域， 于基极层的电极形成区域上制作基极电极； [0006] 1) performing epitaxial etching on the semiconductor substrate to leave an electrode formation region of the emitter and exposing an electrode formation region of the base layer, and forming a base electrode on the electrode formation region of the base layer;
[0007] 2) 进行基极台面腐蚀以露出集电极层的电极形成区域， 于集电极层的电极形 成区域上制作集电极电极；
[0008] 3) 于发射极的电极形成区域之外沉积介质层， 腐蚀介质层以对基极电极、 集 电极电极相应的区域幵孔； [0007] 2) performing base mesa etching to expose an electrode formation region of the collector layer, and forming a collector electrode on the electrode formation region of the collector layer; [0008] 3) depositing a dielectric layer outside the electrode formation region of the emitter, etching the dielectric layer to pupil the corresponding region of the base electrode and the collector electrode;
[0009] 4) 同吋制作集电极电极引出线、 基极电极引出线以及发射极电极， 其中发射 极电极与发射极接触层形成欧姆接触； [0009] 4) simultaneously forming a collector electrode lead line, a base electrode lead line, and an emitter electrode, wherein the emitter electrode forms an ohmic contact with the emitter contact layer;
[0010] 5) 进行电极互联布线。 [0010] 5) Perform electrode interconnection wiring.
[0011] 优选的， 所述集电极层是 n型 GaAs， 所述基极层是 p型 GaAs， 所述发射极层是 n 型 InGaP。 [0011] Preferably, the collector layer is n-type GaAs, the base layer is p-type GaAs, and the emitter layer is n-type InGaP.
[0012] 优选的， 步骤 4) 是于介质层幵孔区域以及发射极的电极形成区域之外覆盖光 阻层， 进行金属蒸发形成金属层， 并通过金属剥离去除光阻层及其之上的金属 层， 从而形成位于介质层幵孔之中并与集电极电极相接的集电极电极引出线、 位于介质层幵孔之中并与基极电极相接的基极电极引出线以及位于发射极接触 层之上的发射极电极。 [0012] Preferably, in step 4), the photoresist layer is covered outside the electrode formation region of the dielectric layer and the electrode formation region of the emitter, metal evaporation is performed to form a metal layer, and the photoresist layer and the photoresist layer are removed by metal stripping. a metal layer, thereby forming a collector electrode lead line located in the pupil of the dielectric layer and contacting the collector electrode, a base electrode lead line located in the pupil of the dielectric layer and contacting the base electrode, and being located at the emitter An emitter electrode above the contact layer.
[0013] 优选的， 所述金属蒸发包括电子束蒸发、 溅射或电镀。 [0013] Preferably, the metal evaporation comprises electron beam evaporation, sputtering or electroplating.
[0014] 优选的， 所述金属层是由下至上为 Ti/Pt/Au且 Ti厚度为 40nm~60nm、 或 Pt/Ti/Pt/ Au且底层 Pt厚度为 5nm~60nm、 或 AuGe/Ti/Pt/Au且 AuGe厚度为 30nm~100nm的叠 层结构。 [0014] Preferably, the metal layer is Ti/Pt/Au from bottom to top and has a thickness of 40 nm to 60 nm, or Pt/Ti/Pt/ Au, and the thickness of the underlayer Pt is 5 nm to 60 nm, or AuGe/Ti/ A laminated structure of Pt/Au and AuGe having a thickness of 30 nm to 100 nm.
[0015] 优选的， 所述发射极接触层是 n型 InGaAs , 厚度为 70nm~100nm， 惨杂浓度大于 1x10 18 cm 3。 [0015] Preferably, the emitter contact layer is n-type InGaAs, the thickness is 70 nm to 100 nm, and the impurity concentration is greater than 1×10 18 cm 3 .
[0016] 优选的， 还包括一发射极盖层， 所述发射极盖层是 n型 GaAs， 形成于发射极接 触层以及发射极层之间。 [0016] Preferably, an emitter cap layer is further included, and the emitter cap layer is n-type GaAs formed between the emitter contact layer and the emitter layer.
[0017] 优选的， 所述集电极层包括一高惨杂浓度的 n型下集电极层以及一低惨杂浓度 的 n型上集电极层， 所述集电极电极形成于下集电极层之上； 步骤 2) 中， 还包 括腐蚀上集电极层以露出下集电极层的电极形成区域。 [0017] Preferably, the collector layer comprises a high impurity concentration n-type lower collector layer and a low impurity concentration n-type upper collector layer, and the collector electrode is formed on the lower collector layer And in the step 2), further comprising etching the upper collector layer to expose the electrode formation region of the lower collector layer.
[0018] 优选的， 还包括腐蚀器件间的下集电极层以使各个器件之间相互隔离的步骤。 [0018] Preferably, a step of etching the lower collector layer between the devices to isolate the respective devices from each other is further included.
[0019] 优选的， 所述基极电极是 Ti/Pt/Au金属层， 与基极层形成欧姆接触。 [0019] Preferably, the base electrode is a Ti/Pt/Au metal layer, which forms an ohmic contact with the base layer.
[0020] 优选的， 所述集电极电极的制作是形成 AuGe/Ni/Ag/Au金属层， 并于 350°C~400[0020] Preferably, the collector electrode is formed by forming a AuGe/Ni/Ag/Au metal layer and is at 350 ° C to 400
°C下退火 30~90s以使集电极电极与所述集电极层形成欧姆接触。 Annealing at ° C for 30 to 90 s to form an ohmic contact between the collector electrode and the collector layer.
[0021] 优选的， 所述介质层是 SiO 2或& 3N 4。
发明的有益效果 [0021] Preferably, the dielectric layer is SiO 2 or & 3 N 4 . Advantageous effects of the invention
有益效果 Beneficial effect
[0022] 相较于现有技术， 本发明将发射极电极、 基极电极引出线以及集电极电极引出 线于同一工序中同吋制作， 省却了单独的发射极电极制作这一工序， 从而降低 了制造成本， 提高生产效率。 [0022] Compared with the prior art, the present invention produces the emitter electrode, the base electrode lead-out line and the collector electrode lead-out line in the same process, eliminating the need for a separate emitter electrode fabrication process, thereby reducing Manufacturing costs and increased production efficiency.
对附图的简要说明 Brief description of the drawing
附图说明 DRAWINGS
[0023] 图 1是本发明的结构流程示意图。 1 is a schematic flow chart of the structure of the present invention.
本发明的实施方式 Embodiments of the invention
[0024] 以下结合附图及实施例对本发明作进一步详细说明。 本发明的各附图仅为示意 以更容易了解本发明， 其具体比例可依照设计需求进行调整。 文中所描述的图 形中相对元件的上下关系， 在本领域技术人员应能理解是指构件的相对位置而 言， 因此皆可以翻转而呈现相同的构件， 此皆应同属本说明书所揭露的范围。 此外， 图中所示的元件及结构的个数、 层的厚度及层间的厚度对比， 均仅为示 例， 并不以此进行限制， 实际可依照设计需求进行调整。 [0024] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. The drawings of the present invention are merely illustrative for easier understanding of the present invention, and the specific proportions thereof can be adjusted according to design requirements. The above-described relative relationship of the elements in the drawings described herein will be understood by those skilled in the art to refer to the relative positions of the members, and therefore, the same members may be turned over and the like, which are all within the scope of the present disclosure. In addition, the number of components and structures shown in the drawings, the thickness of the layers, and the thickness comparison between the layers are merely examples, and are not limited thereto, and may be actually adjusted according to design requirements.
[0025] 以下以 GaAs/ InGaP型 HBT的制程为例进行具体说明。 参考图 1， 首先是提供半 导体基片。 半导体基片通过常规的 MBE外延或 MOCVD法形成由下至上依次层叠 的衬底 1、 下集电极层 2、 上集电极层 3、 p型基极层 4、 n型发射极层 5、 发射极盖 层 6以及发射极接触层 7。 上集电极层 3的惨杂浓度小于下集电极层 2的惨杂浓度 ， 发射极层 5的能带隙大于基极层 4的能带隙， 发射极接触层 7的能带隙小于发射 极盖层 6的能带隙。 举例来说， 衬底是 GaAs、 Si、 SiC、 GaN或蓝宝石； 下集电 极层 2和上集电极层 3是不同惨杂浓度的 n型 GaAs; 基极层 4是 p型 GaAs ; 发射极 层 5是 n型 InGaP, 厚度为 30nm~60nm; 发射极盖层 6是 n型 GaAs , 厚度为 100nm~l 50nm; 发射极接触层 7是 n型 InGaAs , 厚度为 70nm~100nm， 惨杂浓度大于 1x10 18 cm - 3。 [0025] Hereinafter, a process of a GaAs/InGaP type HBT will be specifically described as an example. Referring to Figure 1, the first is to provide a semiconductor substrate. The semiconductor substrate is formed by a conventional MBE epitaxy or MOCVD method to form a substrate 1, a lower collector layer 2, an upper collector layer 3, a p-type base layer 4, an n-type emitter layer 5, and an emitter which are sequentially stacked from bottom to top. The cap layer 6 and the emitter contact layer 7. The impurity concentration of the upper collector layer 3 is smaller than the impurity concentration of the lower collector layer 2, the energy band gap of the emitter layer 5 is larger than the energy band gap of the base layer 4, and the energy band gap of the emitter contact layer 7 is smaller than that of the emitter. The band gap of the cap layer 6. For example, the substrate is GaAs, Si, SiC, GaN or sapphire; the lower collector layer 2 and the upper collector layer 3 are different types of n-type GaAs; the base layer 4 is p-type GaAs; the emitter layer 5 is n-type InGaP, thickness is 30nm~60nm; emitter cap layer 6 is n-type GaAs, thickness is 100nm~l 50nm ; emitter contact layer 7 is n-type InGaAs, thickness is 70nm~100nm, and the impurity concentration is greater than 1x10 1 8 cm - 3 .
[0026] 其次， 直接对半导体基片进行发射极台面腐蚀以留出发射极的电极形成区域并
露出基极层的电极形成区域， 于基极层的电极形成区域上制作基极电极。 具体 ， 以保护发射极形成区域的光刻胶图案作为掩膜， 依次采用柠檬酸加 H 20 2 腐蚀 InGaAs、 NH 4OH加 H 20 2腐蚀 GaAs层以及 HC1加 H 3PO 4腐蚀 InGaP， 从而 形成发射极， 并露出发射极之外的基极层 4， 其中， 发射极接触层 7上表面即为 发射极电极形成区域。 然后， 以对基极电极形成区域幵口的光刻胶图案作为掩 膜， 通过蒸发 Ti/Pt/Au金属层， 并通过金属剥离技术去除光刻胶以及光刻胶之上 的金属层， 从而在基极电极形成区域形成了基极电极 8， 基极电极 8与基极层 4之 间形成欧姆接触。 [0026] Secondly, the epitaxial etching of the semiconductor substrate is performed directly to leave the electrode formation region of the emitter and An electrode formation region of the base layer is exposed, and a base electrode is formed on the electrode formation region of the base layer. Specifically, in order to protect the emitter region forming a photoresist pattern as a mask, successively citric acid plus H 2 0 2 etching InGaAs, NH 4 OH was added H 2 0 2 etch the GaAs layer, and H 3 PO 4 was added HC1 etching InGaP, Thereby, an emitter is formed, and the base layer 4 other than the emitter is exposed, wherein the upper surface of the emitter contact layer 7 is an emitter electrode forming region. Then, the photoresist pattern on the base electrode formation region is used as a mask, the Ti/Pt/Au metal layer is evaporated, and the metal layer on the photoresist and the photoresist is removed by a metal lift-off technique. A base electrode 8 is formed in the base electrode formation region, and an ohmic contact is formed between the base electrode 8 and the base layer 4.
[0027] 基极电极 8制作完成后， 进行基极层以及上集电极层台面腐蚀以露出下集电极 层的电极形成区域， 于下集电极层的电极形成区域上制作集电极电极。 具体， 以保护含发射极的基极形成区域的光刻胶图案作为掩膜， 通过柠檬酸和 H 20 2腐 蚀基极层以及上集电极层从而形成基极， 同吋露出下集电极层的电极形成区域 。 以保护各 HBT器件形成区域的光刻胶图案作为掩膜， 腐蚀掉器件间的下集电 极层 2以使各个器件之间相互隔离。 以对集电极电极形成区域幵口的光刻胶图案 作为掩膜， 蒸发 AuGe/Ni/Ag/Au金属层， 并通过金属剥离技术去除光刻胶以及光 刻胶之上的金属层， 从而在集电极电极形成区域形成了集电极电极 9， 然后于 35 0°C~400°C下退火 30~90s以使集电极电极 9与下集电极层 2形成欧姆接触。 [0027] After the base electrode 8 is completed, the base layer and the upper collector layer are mesa-etched to expose the electrode formation region of the lower collector layer, and the collector electrode is formed on the electrode formation region of the lower collector layer. Specifically, a photoresist pattern for protecting a base-forming region of the emitter is used as a mask, and the base layer and the upper collector layer are etched by citric acid and H 2 0 2 to form a base, and the lower collector layer is exposed at the same time. The electrode formation area. The lower collector layer 2 between the devices is etched away to isolate the respective devices from each other by using a photoresist pattern for protecting the regions in which the respective HBT devices are formed as a mask. The AuGe/Ni/Ag/Au metal layer is evaporated by using a photoresist pattern on the collector electrode formation region as a mask, and the photoresist and the metal layer on the photoresist are removed by a metal lift-off technique, thereby The collector electrode forming region is formed with the collector electrode 9, and then annealed at 35 0 ° C to 400 ° C for 30 to 90 s to form the ohmic contact between the collector electrode 9 and the lower collector layer 2.
[0028] 以保护发射极电极形成区域的光刻胶图案作为掩膜， 沉积介质层 10。 介质层 10 可以是810 2或 ^ 4。 腐蚀介质层 10以对基极电极、 集电极电极相应的区域幵孔 。 此后， 以对发射极电极形成区域、 基极电极 8以及集电极电极 9幵口的光刻胶 图案作为掩膜， 蒸发 Pt/Ti/Pt/Au金属层， 并通过金属剥离去除光刻胶及其之上的 金属层， 从而同吋形成位于发射极接触层 7之上的发射极电极 11， 介质层 10幵孔 之中并与集电极电极 9相接的集电极电极引出线 12、 位于介质层幵孔之中并与基 极电极 8相接的基极电极引出线 13， 然后根据集成电路结构及功能的设计进行器 件间的金属互联布线。 其中， 金属层底材 Pt的厚度为 5nm~60nm。 在另一实施例 中， 金属层是 Ti/Pt/Au且 Ti厚度为 40nm~60nm。 在又一实施例中， 金属层是 AuGe /Ti/Pt/Au且 AuGe厚度为 30nm~100nm。 上述三次金属蒸发， 均可采用例如电子束 蒸发、 溅射或电镀的方法。
[0029] 发射极接触层 7是高惨杂的 n型 InGaAs, 与金属之间的接触势垒低， 发射极电极 11与发射极接触层 7之间可以直接形成欧姆接触。 发射极电极 11、 集电极电极引 出线 12以及基极电极引出线 13图形同吋定义， 并于同道工序中同吋制作， 可省 去现有技术中发射极电极制作这一工序， 从而达到节省生产成本的目的。 [0028] The dielectric layer 10 is deposited with a photoresist pattern that protects the emitter electrode formation region as a mask. The dielectric layer 10 can be 810 2 or ^ 4 . The dielectric layer 10 is etched in a region corresponding to the base electrode and the collector electrode. Thereafter, a photoresist pattern of the emitter electrode formation region, the base electrode 8 and the collector electrode 9 is used as a mask to evaporate the Pt/Ti/Pt/Au metal layer, and the photoresist is removed by metal stripping. a metal layer thereon, thereby forming an emitter electrode 11 on the emitter contact layer 7, a collector electrode lead line 12 in the pupil of the dielectric layer 10 and contacting the collector electrode 9, located in the medium The base electrode of the layer pupil and which is in contact with the base electrode 8 leads the line 13, and then the metal interconnection wiring between the devices is performed according to the design of the integrated circuit structure and function. The metal layer substrate Pt has a thickness of 5 nm to 60 nm. In another embodiment, the metal layer is Ti/Pt/Au and the Ti has a thickness of 40 nm to 60 nm. In still another embodiment, the metal layer is AuGe /Ti/Pt/Au and the AuGe has a thickness of 30 nm to 100 nm. For the above three metal evaporations, for example, electron beam evaporation, sputtering or electroplating may be employed. [0029] The emitter contact layer 7 is a highly cumbersome n-type InGaAs, and the contact barrier with the metal is low, and an ohmic contact can be directly formed between the emitter electrode 11 and the emitter contact layer 7 . The emitter electrode 11, the collector electrode lead-out line 12, and the base electrode lead-out line 13 are similarly defined and fabricated in the same process, which eliminates the prior art process of fabricating the emitter electrode, thereby saving The purpose of production costs.
[0030] 上述实施例仅用来进一步说明本发明的一种 HBT制造方法， 但本发明并不局限 于实施例， 凡是依据本发明的技术实质对以上实施例所作的任何简单修改、 等 同变化与修饰， 均落入本发明技术方案的保护范围内。
The above embodiments are only used to further illustrate an HBT manufacturing method of the present invention, but the present invention is not limited to the embodiments, and any simple modifications and equivalent changes made to the above embodiments in accordance with the technical essence of the present invention are Modifications are all within the scope of protection of the technical solutions of the present invention.
Claims
[权利要求 1] 一种 HBT制造方法， 包括提供或形成半导体基片， 所述半导体基片包 括由下至上依次层叠的衬底、 n型集电极层、 p型基极层、 n型发射极 层以及发射极接触层， 其特征在于还包括以下步骤： [Claim 1] A method of manufacturing an HBT, comprising providing or forming a semiconductor substrate, the semiconductor substrate including a substrate stacked in order from bottom to top, an n-type collector layer, a p-type base layer, and an n-type emitter The layer and the emitter contact layer are further characterized by the following steps:
1 ) 对所述半导体基片进行发射极台面腐蚀以留出发射极的电极形成 区域并露出基极层的电极形成区域， 于基极层的电极形成区域上制作 基极电极； 1) performing epitaxial etching on the semiconductor substrate to leave an electrode formation region of the emitter and exposing an electrode formation region of the base layer, and forming a base electrode on the electrode formation region of the base layer;
2) 进行基极台面腐蚀以露出集电极层的电极形成区域， 于集电极层 的电极形成区域上制作集电极电极； 2) performing base mesa etching to expose an electrode formation region of the collector layer, and forming a collector electrode on the electrode formation region of the collector layer;
3) 于发射极的电极形成区域之外沉积介质层， 腐蚀介质层以对基极 电极、 集电极电极相应的区域幵孔； 3) depositing a dielectric layer outside the electrode formation region of the emitter, and etching the dielectric layer to punctate the corresponding region of the base electrode and the collector electrode;
4) 同吋制作集电极电极引出线、 基极电极引出线以及发射极电极， 其中发射极电极与发射极接触层形成欧姆接触； 4) producing a collector electrode lead-out line, a base electrode lead-out line, and an emitter electrode, wherein the emitter electrode forms an ohmic contact with the emitter contact layer;
5) 进行电极互联布线。 5) Perform electrode interconnection wiring.
[权利要求 2] 根据权利要求 1所述的制备方法， 其特征在于： 所述集电极层是 n型 G aAs , 所述基极层是 p型 GaAs， 所述发射极层是 n型 InGaP。 [Claim 2] The preparation method according to claim 1, wherein the collector layer is n-type G aAs , the base layer is p-type GaAs, and the emitter layer is n-type InGaP.
[权利要求 3] 根据权利要求 1所述的制备方法， 其特征在于： 步骤 4) 是于介质层幵 孔区域以及发射极的电极形成区域之外覆盖光阻层， 进行金属蒸发形 成金属层， 并通过金属剥离去除光阻层及其之上的金属层， 从而形成 位于介质层幵孔之中并与集电极电极相接的集电极电极引出线、 位于 介质层幵孔之中并与基极电极相接的基极电极引出线以及位于发射极 接触层之上的发射极电极。 [Claim 3] The preparation method according to claim 1, wherein: step 4) is to cover the photoresist layer outside the pupil formation region of the dielectric layer and the electrode formation region of the emitter, and evaporate the metal to form a metal layer. And removing the photoresist layer and the metal layer thereon by metal stripping, thereby forming a collector electrode lead line located in the pupil of the dielectric layer and contacting the collector electrode, located in the pupil of the dielectric layer and with the base A base electrode lead line to which the electrodes are connected and an emitter electrode located above the emitter contact layer.
[权利要求 4] 根据权利要求 3所述的制备方法， 其特征在于： 所述金属蒸发包括电 子束蒸发、 溅射或电镀。 [Claim 4] The preparation method according to claim 3, wherein the metal evaporation includes electron beam evaporation, sputtering, or electroplating.
[权利要求 5] 根据权利要求 3所述的制备方法， 其特征在于： 所述金属层是由下至 上为 Ti/Pt/Au且 Ti厚度为 40nm~60nm、 或 Pt/Ti/Pt/Au且底层 Pt厚度为 5n m~60nm、 或 AuGe/Ti/Pt/Au且 AuGe厚度为 30nm~100nm的叠层结构。 [Claim 5] The preparation method according to claim 3, wherein the metal layer is Ti/Pt/Au from bottom to top and has a thickness of 40 nm to 60 nm, or Pt/Ti/Pt/Au. The underlayer Pt has a thickness of 5 nm to 60 nm, or AuGe/Ti/Pt/Au, and AuGe has a thickness of 30 nm to 100 nm.
[权利要求 6] 根据权利要求 1或 5所述的制备方法， 其特征在于： 所述发射极接触层
是 n型 InGaAs , 厚度为 70nm~100nm， 惨杂浓度大于 1x10 18 cm -3。 [Claim 6] The preparation method according to claim 1 or 5, wherein: the emitter contact layer It is an n-type InGaAs with a thickness of 70 nm to 100 nm and a bulk concentration of more than 1 x 10 18 cm - 3 .
[权利要求 7] 根据权利要求 1所述的制备方法， 其特征在于： 还包括一发射极盖层 ， 所述发射极盖层是 n型 GaAs， 形成于发射极接触层以及发射极层之 间。 [Claim 7] The preparation method according to claim 1, further comprising: an emitter cap layer, wherein the emitter cap layer is n-type GaAs, formed between the emitter contact layer and the emitter layer .
[权利要求 8] 根据权利要求 1所述的制备方法， 其特征在于： 所述集电极层包括一 高惨杂浓度的 n型下集电极层以及一低惨杂浓度的 n型上集电极层， 所 述集电极电极形成于下集电极层之上； 步骤 2) 中， 还包括腐蚀上集 电极层以露出下集电极层的电极形成区域。 [Claim 8] The preparation method according to claim 1, wherein: the collector layer comprises a high impurity concentration n-type lower collector layer and a low impurity concentration n-type upper collector layer The collector electrode is formed on the lower collector layer; and in the step 2), further includes etching the upper collector layer to expose the electrode formation region of the lower collector layer.
[权利要求 9] 根据权利要求 8所述的制备方法， 其特征在于： 还包括腐蚀器件间的 下集电极层以使各个器件之间相互隔离的步骤。 [Claim 9] The preparation method according to claim 8, further comprising the step of etching the lower collector layer between the devices to isolate the respective devices from each other.
[权利要求 10] 根据权利要求 1所述的制备方法， 其特征在于： 所述基极电极是 Ti/Pt/ [Claim 10] The preparation method according to claim 1, wherein: the base electrode is Ti/Pt/
Au金属层， 与基极层形成欧姆接触。 The Au metal layer forms an ohmic contact with the base layer.
[权利要求 11] 根据权利要求 1所述的制备方法， 其特征在于： 所述集电极电极的制 作是形成 AuGe/Ni/Ag/Au金属层， 并于 350°C~400°C下退火 30~90s以使 集电极电极与所述集电极层形成欧姆接触。 [Claim 11] The preparation method according to claim 1, wherein: the collector electrode is formed by forming an AuGe/Ni/Ag/Au metal layer and annealing at 350 ° C to 400 ° C. ~90s to make the collector electrode form an ohmic contact with the collector layer.
[权利要求 12] 根据权利要求 1所述的制备方法， 其特征在于： 所述介质层是 Si0 2 或 Si 3N 4。
[Claim 12] The preparation method according to claim 1, wherein the dielectric layer is SiO 2 or Si 3 N 4 .
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