WO2018032754A1 - Dispositif de circuit réglable et dispositif de mesure de tension - Google Patents

Dispositif de circuit réglable et dispositif de mesure de tension Download PDF

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Publication number
WO2018032754A1
WO2018032754A1 PCT/CN2017/076396 CN2017076396W WO2018032754A1 WO 2018032754 A1 WO2018032754 A1 WO 2018032754A1 CN 2017076396 W CN2017076396 W CN 2017076396W WO 2018032754 A1 WO2018032754 A1 WO 2018032754A1
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Prior art keywords
regulating circuit
capacitor
signal
buffer
input
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PCT/CN2017/076396
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English (en)
Chinese (zh)
Inventor
周立功
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广州致远电子股份有限公司
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Priority claimed from CN201610667922.7A external-priority patent/CN106353549B/zh
Priority claimed from CN201620880722.5U external-priority patent/CN206208961U/zh
Application filed by 广州致远电子股份有限公司 filed Critical 广州致远电子股份有限公司
Publication of WO2018032754A1 publication Critical patent/WO2018032754A1/fr

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R15/00—Details of measuring arrangements of the types provided for in groups G01R17/00 - G01R29/00, G01R33/00 - G01R33/26 or G01R35/00
    • G01R15/04—Voltage dividers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof

Definitions

  • the voltage dividing resistor Since the operating voltage of the semiconductor electronic circuit is low, the voltage dividing resistor is usually used to divide and attenuate the high voltage input signal. However, after the buffer is divided, the input capacitor Cin is present, and the voltage dividing resistor and the buffer input capacitor Cin form a low pass filter network. As the frequency of the input signal increases, the capacitive reactance of the buffer input capacitor decreases, and the voltage entering the buffer is attenuated, limiting the bandwidth of the input signal. To increase the bandwidth, the capacitor is shunted across the voltage dividing resistor, and the high frequency passes through the capacitor. Dividing the voltage, as shown in Figure 1, the voltage divider resistor includes an upper divider resistor for R1 and a lower divider resistor for R2.
  • the adjustable capacitor has a semi-circular fixed metal electrode and a movable semi-circular metal electrode, and ceramic or film or air is used as a dielectric in the middle, and the degree of overlap between the movable electrode and the fixed electrode is manually adjusted by the tool to adjust Capacity, but with this manual adjustment, it is time consuming and laborious.
  • the present invention provides a tunable circuit device that realizes automatic adjustment of a voltage dividing capacitor, which can reduce manpower input and greatly improve work efficiency.
  • the present invention provides the following technical solutions:
  • a tunable circuit device comprising: a first signal input terminal N1, a second signal input terminal N2, a first voltage dividing resistor R1, a second voltage dividing resistor R2, a first voltage dividing capacitor C1, a buffer input capacitor Cin, a stray capacitance C2', a buffer 1, a first adjustment circuit 5, a second adjustment circuit 6, a signal conditioner 2, an analog-to-digital converter 3, and a processor 4;
  • a first end of the first adjusting circuit 5 is connected to an input end of the buffer 1, and a second end of the first adjusting circuit 5 is connected to an output end of the buffer 1, the first adjusting circuit The third end of 5 is grounded;
  • a first end of the second adjusting circuit 6 is connected to an input end of the buffer 1, and a second end of the second adjusting circuit 6 is connected to an output end of the buffer 1, the second adjusting circuit The third end of 6 is grounded;
  • An output end of the buffer 1 is sequentially connected to an input end of the processor 4 through the signal conditioner 2 and the analog-to-digital converter 3;
  • the signal conditioner 2 modulates an output signal of the buffer 1 and transmits the conditioned signal to the analog-to-digital converter 3, and the analog-to-digital converter 3 digitally converts the received signal And transmitting the converted digital signal to the processor 4, the processor 4 analyzes the received digital signal according to a preset rule, and sends the analysis result to the first through the control harness L2
  • the control terminal of each switch in the regulating circuit 5 is sent to the address input of the multiplexer 61 in the second regulating circuit 6 via the control harness (L1).
  • the first adjusting circuit 5 includes: a plurality of branches having the same structure, each of the branches being connected in parallel with each other, wherein each of the branches includes: a first capacitor C11, a first switch Q11, and a first a first end of the first capacitor C11 is connected to the input end of the buffer 1, and a second end of the first capacitor C11 is connected to the first end of the first switch Q11.
  • the second end of the first switch Q11 is grounded, the first capacitor C11 and the first switch Q11 A connection point between the terminals is connected to the output of the buffer 1 via the first protection resistor R11.
  • the second adjusting circuit 6 includes: a fixed capacitor C21, a multiplexer 61 and a resistor network 62; a first end of the fixed capacitor C21 is connected to an input end of the buffer 1 A second end of the fixed capacitor C21 is coupled to the output terminal N3 of the multiplexer 61; a first end of the resistor network 62 is coupled to an output of the buffer 1, and a second of the resistor network 62
  • the terminal network is grounded, the resistor network 62 includes a plurality of resistors, and the resistors are sequentially connected in series;
  • the multiplexer 61 includes a first input end and a plurality of second input ends, the first input end is grounded, and The second input terminals are in one-to-one correspondence with the first ends of the plurality of resistors in sequence.
  • the processor 4 includes: a plurality of outputs, wherein the output end corresponding to the first adjusting circuit 5 is respectively controlled by the switch control harness L2 and each of the switches in the first adjusting circuit 5 The control terminals are connected, and the output terminal corresponding to the second regulating circuit 6 is connected to the address input terminal of the multiplexer 61 in the second regulating circuit 6 via the multiplexer control harness L1.
  • each branch capacitor in the first adjusting circuit 5 is sequentially increased in binary.
  • the switch on each branch in the first adjustment circuit 5 is a mechanical relay, a low capacitance photorelay or a junction field effect transistor.
  • the electrode of each branch capacitor in the first adjusting circuit 5 is a circuit board copper, and the dielectric is a board substrate; or the capacitance of each branch in the first adjusting circuit 5 is a fixed capacitor.
  • the processor 4 includes: a first analyzing unit 41, configured to receive low-frequency and high-frequency digital signals with the same amplitude, and measure amplitudes of low-frequency and high-frequency signals, and compare and analyze a difference between the amplitude of the high frequency signal and the amplitude of the low frequency signal.
  • a first analyzing unit 41 configured to receive low-frequency and high-frequency digital signals with the same amplitude, and measure amplitudes of low-frequency and high-frequency signals, and compare and analyze a difference between the amplitude of the high frequency signal and the amplitude of the low frequency signal.
  • the processor 4 includes: a second analyzing unit 42 configured to perform FFT analysis on the received digital signal to obtain a fundamental wave and a harmonic amplitude of the digital signal.
  • the value and phase ratio information is compared and analyzed according to the proportional information and the proportional information calculated by the theoretical FFT in advance by the digital signal.
  • a voltage measuring device includes: the adjustable circuit device.
  • the present invention discloses a tunable circuit device, which comprises: a first signal input terminal N1, a second signal input terminal N2, a first voltage dividing resistor R1, and a second Voltage dividing resistor R2, first voltage dividing capacitor C1, buffer input capacitor Cin, stray capacitance C2', buffer 1, first regulating circuit 5, second adjusting circuit 6, signal conditioner 2, analog-to-digital converter 3 and the processor 4; the processor 4 receives the output signal modulated by the signal conditioner 2 and the analog-to-digital converter 3, and analyzes the output signal according to a preset rule; Controlling the harness to send a control signal to control the open and closed states of each switch in the first regulating circuit 5, to achieve input or cutoff of the adjustable capacitor, thereby adjusting the equivalent capacitance of the first adjusting circuit 5; and controlling In the second adjusting circuit 6, the gear position connection state of the multiplexer 61 changes the connection relationship between the fixed capacitor C21 and the tap position of the voltage dividing resistor network, thereby adjusting the voltage
  • FIG. 1 is a schematic circuit diagram of a conventional circuit device provided by the present invention.
  • FIG. 2 is a schematic circuit diagram of a tunable circuit device according to an embodiment of the present invention.
  • FIG. 3 is a schematic circuit diagram of another adjustable circuit device according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a processor in FIG. 3 corresponding to Embodiment 2 of the present invention.
  • FIG. 2 is a schematic circuit diagram of an embodiment of a tunable circuit device according to the present invention.
  • the tunable circuit device includes: a first signal input terminal N1, a second signal input terminal N2, a first voltage dividing resistor R1, a second voltage dividing resistor R2, and a first component. a piezoelectric capacitor C1, a buffer input capacitor Cin, a stray capacitance C2', a buffer 1, a first regulating circuit 5, a second regulating circuit 6, a signal conditioner 2, an analog-to-digital converter 3, and a processor 4;
  • a first end of the first adjusting circuit 5 is connected to an input end of the buffer 1, and a second end of the first adjusting circuit 5 is connected to an output end of the buffer 1, the first adjusting circuit The third end of 5 is grounded;
  • a first end of the second adjusting circuit 6 is connected to an input end of the buffer 1, and a second end of the second adjusting circuit 6 is connected to an output end of the buffer 1, the second adjusting circuit The third end of 6 is grounded;
  • An output end of the buffer 1 is sequentially connected to an input end of the processor 4 through the signal conditioner 2 and the analog-to-digital converter 3;
  • the signal conditioner 2 modulates an output signal of the buffer 1 and transmits the conditioned signal to the analog-to-digital converter 3, and the analog-to-digital converter 3 digitally converts the received signal And transmitting the converted digital signal to the processor 4, the processor 4 analyzes the received digital signal according to a preset rule, and sends the analysis result to the first through the control harness L2
  • the control terminal of each switch in the regulating circuit 5 is sent to the address input of the multiplexer 61 in the second regulating circuit 6 via the control harness L1.
  • each switch in the first adjusting circuit 5 and the address input end of the multiplexer 61 in the second adjusting circuit 6 control the first adjustment according to the received analysis result. Opening or closing of each switch in the circuit 5; and controlling a gear connection line of the multiplexer 61 in the second regulating circuit 6 to be connected to an input terminal in the multiplexer 61, thereby changing The equivalent capacitance value of the first adjustment circuit 5 and the second adjustment circuit 6 is described.
  • the processor 4 can control the opening and closing states of each switch in the first adjusting circuit 5 by controlling the wire harness transmission control signal to implement Turning on or off the adjustable capacitor in series, thereby adjusting the equivalent capacitance of the first regulating circuit 5; and controlling the gear connection state of the multiplexer 61 in the second regulating circuit 6, changing the connection
  • the voltage divider resistor network 62 taps the position, thereby adjusting the voltage across the fixed capacitor, so that the fixed capacitor is simulated as a tunable capacitor, which can realize automatic adjustment of the voltage dividing capacitor, reduce human intervention, improve work efficiency, and improve adjustment. Precision.
  • FIG. 3 is a schematic structural view of another embodiment of a tunable circuit device according to the present invention.
  • the first adjusting circuit 5 includes: a plurality of branches having the same structure, each of the branches being connected in parallel with each other, wherein each of the branches includes: a first capacitor C11 a first switch Q11 and a first protection resistor R11, a first end of the first capacitor C11 is connected to an input end of the buffer 1, a second end of the first capacitor C11 and the first switch Q11 The first end of the first switch Q11 is connected to the ground, and the connection point between the first capacitor C11 and the first switch Q11 passes through the first protection resistor R11 and the buffer 1 The outputs are connected.
  • each branch in the first adjusting circuit 5 can be increased in binary order, assuming that the lowest bit is C, the high order is 2C, 4C, 8C, 16C, etc., and the smallest component can be used according to binary increment.
  • 1pF, 2pF, 4pF three capacitors can be composed of 8 different capacities of 1pF, 0pF (3 are not connected), 1pF, 2pF, 3pF (1pF and 2pF in parallel) , 4pF, 5pF (1pF and 4pF in parallel), 6pF (2pF and 4pF in parallel), 7pF (3 in parallel) and so on.
  • the capacitance of each branch in the first adjustment circuit 5 may be one or more Cascade and parallel connection;
  • the capacitor may be a capacitor formed by using a circuit board copper as an electrode and a board substrate as a dielectric, wherein a copper-clad area as a capacitor electrode is set in a binary manner, and a ground plane is covered with copper as a common electrode to realize a binary capacitor;
  • the capacitor can also be a fixed capacitor.
  • the switch on each branch in the first adjusting circuit 5 may be a mechanical relay, a low-capacitance optical relay or a junction field effect transistor, and the switch can be connected in series with the switch by controlling the open and closed states of the switch. The input and the cutoff of the capacitance are adjusted to adjust the capacitance of the first adjustment circuit 5.
  • the first protection resistor R11 is configured to maintain a connection point voltage between the first adjustable capacitor C11 and the first switch Q11 and the first voltage dividing resistor R1 and the first switch Q11 when the first switch Q11 is turned off.
  • the voltage at the connection point between the second voltage dividing resistors R2 is the same, and the stray capacitance at both ends of the switch is prevented from generating a leakage current.
  • the second adjusting circuit 6 includes a fixed capacitor C21, a multiplexer 61 and a resistor network 62.
  • the first end of the fixed capacitor C21 is connected to the input end of the buffer 1.
  • the second end of the fixed capacitor C21 is connected to the output terminal N3 of the multiplexer 61;
  • the first end of the resistor network 62 is connected to the output end of the buffer 1, the resistor network 62
  • the second end is grounded, the resistor network 62 includes a plurality of resistors, each of the resistors being sequentially connected in series;
  • the multiplexer 61 includes a first input terminal and a plurality of second input terminals, the first input terminal is grounded And the plurality of second input terminals are in one-to-one correspondence with the first ends of the plurality of resistors in sequence.
  • the multiplexer 61 includes a first input end and a plurality of second input ends, the first input end is grounded, and the plurality of the second input ends are sequentially and in sequence with the plurality of the resistors One-to-one correspondence.
  • the resistor network 62 is composed of a plurality of resistors in series. The two ends of the resistor are grounded at one end and the other end is connected to a signal source to be divided.
  • the first ends of the plurality of groups are Different taps or lead points, different taps correspond to different partial pressure ratios.
  • a voltage divider resistor network consisting of five resistors in series, the 0 to 5 tap divider ratios are 0/5, 1/5, 2/5, 3/5, 4/5, 5/5, set the signal voltage to Vs, the output voltage of 0 ⁇ 5 taps is 0, 1/5Vs, 2/5Vs, 3 /5Vs, 4/5Vs, Vs.
  • the multiplexer selects one of the taps to obtain a voltage division ratio.
  • the capacity of the fixed capacitor C21 is ⁇ the capacity of the lowest bit capacitance in the first adjustment circuit to cover the error of the lowest bit capacitance of the first adjustment circuit 5, so that the adjustment can be smoothly continuous, by controlling the multiplexer 61 In the gear state, the connected tapping resistor network 62 tap position is changed, thereby adjusting the voltage across the fixed capacitor C21, thereby simulating the fixed capacitor C21 as a variable capacitor.
  • the processor 4 includes: a plurality of outputs, wherein an output corresponding to the first adjustment circuit 5 passes through each of the first adjustment circuits 5 through the switch control harness L2 The control terminals of the switches are connected, and the output terminals corresponding to the second regulating circuit 6 are connected to the address inputs of the multiplexers 61 in the second regulating circuit 6 via the multiplexer control harness L1.
  • the processor 4 includes:
  • a first analyzing unit 41 configured to receive low frequency and high frequency digital signals of the same amplitude, measure amplitudes of low frequency and high frequency signals, compare and analyze amplitudes of the high frequency signals and the low frequency The difference in signal amplitude.
  • the processor 4 includes:
  • a second analyzing unit 42 configured to perform FFT analysis on the received digital signal, acquire amplitude and phase ratio information of a fundamental wave and each harmonic of the digital signal, according to the ratio information and The digital signal is previously compared and analyzed by the ratio information calculated by the theoretical FFT.
  • the processor has two adjustment schemes, one of which is that the first analyzing unit 41 of the processor 4 receives the same amplitude output by the analog-to-digital converter 3 respectively.
  • the low frequency and high frequency signals the processor 4 first measures the amplitude of the low frequency signal, and then measures the amplitude of the output high frequency signal, and compares and analyzes the difference between the amplitude of the high frequency signal and the amplitude of the low frequency signal,
  • a control signal is sent to the control terminal of the switch on each branch in the first regulating circuit 5 through the switch control harness L2 to adjust the first regulated power a switching state in the way 5, coarsely adjusting the equivalent capacitance value of the first regulating circuit 5; transmitting a control signal to the address input end of the multiplexer through the multiplexer control harness L1, the plurality
  • the multiplexer parses the control signal and selects data corresponding to one of the input terminals for output, that is, the multiplexer 61 gear position in the second
  • the position of the multiplexer can control the ratio of the voltage across the fixed capacitor to the voltage of the divided voltage to ground, thereby changing the current flowing through the fixed capacitor, and simulating the fixed capacitor as a variable capacitor, through the first regulating circuit 5 and
  • the capacitance and the buffer input capacitance and the stray capacitance minimize the difference between the final high-frequency signal amplitude and the low-frequency signal, that is, the matching state, and the processor 4 simultaneously records the high-frequency and low-frequency signal amplitude matching states.
  • the second analyzing unit 42 of the processor 4 performs FFT analysis on the input square wave signal converted by the voltage division attenuation, the buffer 1, the signal conditioner 2, and the analog-to-digital converter 3.
  • the signal conditioner 2 is for adjusting the input signal to a signal satisfying the input voltage range of the analog-to-digital converter 3, the analog-to-digital converter 3 for converting its input signal into a digital signal, and the processor 4 for analogizing the digital signal to the digital signal
  • the sampled value of the converter 3 is subjected to FFT analysis to obtain the amplitude and phase information of the fundamental wave and each harmonic of the input square wave signal.
  • the simulation is performed.
  • the digital signal converted by the digitizer 3 is subjected to FFT to find the ratio of the fundamental wave and each harmonic, which is compared with the theoretical calculation of the input square wave signal.
  • the fundamental state and each harmonic of the digital signal converted by the final analog-to-digital converter 3 are adjusted by controlling the wiring harness to adjust the switching state of the first regulating circuit and the multiplexer gear state of the second regulating circuit.
  • the wave ratio is closest to the case when the input square wave is theoretically decomposed.
  • the switching state is the matching state
  • the processor 4 records the switching state of the first adjusting circuit 5 in the matching state and the second adjusting circuit 6 Multiplexer 61 gear status, each The first adjustment circuit 5 switch and the multiplexer 61 position of the second adjustment circuit 6 are configured in accordance with this code.
  • the processor 4 passes the first analysis unit by receiving the digital signal converted by the signal conditioner 2 and the analog-to-digital converter 3. Or the second analyzing unit analyzes the received digital signal, and sends the analysis result to the control end of each switch in the first adjusting circuit 5 through the control harness L2 and sends the same to the control through the control harness L1.
  • the voltage across the fixed capacitor C21 is such that the fixed capacitor C21 is simulated as a tunable capacitor to match the upper and lower voltage divider capacitors.
  • the program control can realize the automatic adjustment of the upper and lower voltage division resistance time constant matching, obtain the flat amplitude frequency characteristic, improve the production efficiency, and at the same time avoid the influence of vibration on the stability of the voltage dividing capacitor because there is no mechanical capacitance adjustable device.
  • the present invention also provides a specific embodiment of a voltage measuring device comprising: the tunable circuit device described above.
  • the voltage measuring device can be any voltage measuring device for measuring DC, AC or AC/DC mixed signals, such as an oscilloscope; or a module of the voltage measuring device is used for measuring the above voltage signal, such as a multimeter, power Meter, power analyzer, etc.
  • the voltage measuring device may convert the continuous analog signal into a discrete digital sequence by using an analog-to-digital converter 3 according to a sampling principle, and then recover and reconstruct the waveform, thereby achieving the purpose of measuring the waveform.
  • the buffer 1 is used for buffering the received input signal to isolate the measured object from the voltage measuring device.
  • the change of the operating state of the voltage measuring device does not affect the input signal, and the amplitude of the signal is The value is switched to the appropriate level range, ie the range that the voltage measuring device can handle, that is to say the signals of different amplitudes are converted into signals in the same voltage range after passing through the input buffer amplifier;
  • the signal conditioner 2 is configured to modulate an output analog signal to be tested of the buffer 1 to a range suitable for conversion by the analog to digital converter 3;
  • the analog-to-digital converter 3 is configured to convert a continuous analog signal output by the signal conditioner 2 into a discrete digital sequence, and then reconstruct a waveform according to a sequence of digital sequences, the analog-to-digital converter 3 serving as a sampling
  • the role of the sampling clock, the amplitude of the signal at the moment of arrival of the sampling pulse is converted into a numerical value, this point is called the sampling point;
  • the processor 4 receives the digital signal converted by the analog-to-digital converter 3, and analyzes the received digital signal according to a preset rule, and sends the analysis result to the first through the control harness L2.
  • the control terminal of each switch in the adjusting circuit 5 and the address input terminal of the multiplexer 61 in the second adjusting circuit 6 are controlled by the control harness L1, and each switch in the first adjusting circuit 5 can be controlled.
  • connection state changes the tap position of the connected voltage divider resistor network 62, thereby adjusting the voltage across the fixed capacitor C21, so that the fixed capacitor C21 is simulated as a tunable capacitor, and the process control can realize the automatic adjustment of the upper and lower voltage division resistance time constant matching. , to obtain a flat amplitude frequency characteristic.
  • the voltage measuring device adopts the adjustable circuit device as its internal circuit structure, can realize automatic adjustment of upper and lower voltage-dividing resistance-capacitance time constant matching, obtains flat amplitude-frequency characteristics, and ensures accuracy of high-frequency signal data measurement. , effectively avoiding measurement errors.
  • the device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be Physical units can be located in one place or distributed to multiple network elements. You can choose some of them according to actual needs or All units are used to achieve the objectives of the solution of this embodiment.
  • the connection relationship between the units indicates that there is a communication connection between them, and specifically may be implemented as one or more communication buses or signal lines.

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  • General Physics & Mathematics (AREA)
  • Measurement Of Current Or Voltage (AREA)

Abstract

La présente invention concerne un dispositif de circuit réglable, comprenant : un premier circuit de réglage (5), un second circuit de réglage (6), un conditionneur de signal (2), un convertisseur analogique-numérique (3) et un processeur (4). Le processeur (4) reçoit un signal de sortie converti par le conditionneur de signal (2) et le convertisseur analogique-numérique (3), analyse le signal numérique selon des règles préétablies, et envoie, selon les résultats d'analyse, des signaux de commande : en vue de commander les états de marche et d'arrêt de chaque commutateur du premier circuit de réglage (5), afin de réaliser l'incorporation ou la coupure d'un condensateur réglable, ce qui permet de régler la capacité équivalente du premier circuit de réglage (5) ; et en vue de commander l'état de connexion de position de prise du multiplexeur dans le second circuit de réglage (6), afin de modifier la position d'une prise d'un réseau de résistances de diviseur de tension connecté, ce qui permet de régler la tension à travers le condensateur fixe, de sorte que le condensateur fixe simule qu'il est un condensateur réglable. L'invention réalise le réglage automatique du condensateur diviseur de tension au moyen d'une commande de programme, réduit le besoin d'entrée humaine et améliore considérablement l'efficacité de travail.
PCT/CN2017/076396 2016-08-15 2017-03-13 Dispositif de circuit réglable et dispositif de mesure de tension WO2018032754A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
CN201610667922.7 2016-08-15
CN201610667922.7A CN106353549B (zh) 2016-08-15 2016-08-15 一种可调电路装置及电压测量装置
CN201620880722.5U CN206208961U (zh) 2016-08-15 2016-08-15 一种可调电路装置
CN201620880722.5 2016-08-15

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CN113992021A (zh) * 2021-10-20 2022-01-28 广东电网有限责任公司 多电压等级输出装置
CN114264870A (zh) * 2021-12-21 2022-04-01 北京航天测控技术有限公司 交流信号调理***及方法
CN114637356A (zh) * 2020-12-16 2022-06-17 浙江驰拓科技有限公司 参考电压调节电路以及参考电阻调节电路

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CN114264870A (zh) * 2021-12-21 2022-04-01 北京航天测控技术有限公司 交流信号调理***及方法

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