WO2018032754A1 - Adjustable circuit device and voltage measuring device - Google Patents

Adjustable circuit device and voltage measuring device Download PDF

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Publication number
WO2018032754A1
WO2018032754A1 PCT/CN2017/076396 CN2017076396W WO2018032754A1 WO 2018032754 A1 WO2018032754 A1 WO 2018032754A1 CN 2017076396 W CN2017076396 W CN 2017076396W WO 2018032754 A1 WO2018032754 A1 WO 2018032754A1
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Prior art keywords
regulating circuit
capacitor
signal
buffer
input
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PCT/CN2017/076396
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French (fr)
Chinese (zh)
Inventor
周立功
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广州致远电子股份有限公司
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Priority claimed from CN201620880722.5U external-priority patent/CN206208961U/en
Priority claimed from CN201610667922.7A external-priority patent/CN106353549B/en
Application filed by 广州致远电子股份有限公司 filed Critical 广州致远电子股份有限公司
Publication of WO2018032754A1 publication Critical patent/WO2018032754A1/en

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R15/00—Details of measuring arrangements of the types provided for in groups G01R17/00 - G01R29/00, G01R33/00 - G01R33/26 or G01R35/00
    • G01R15/04—Voltage dividers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof

Definitions

  • the voltage dividing resistor Since the operating voltage of the semiconductor electronic circuit is low, the voltage dividing resistor is usually used to divide and attenuate the high voltage input signal. However, after the buffer is divided, the input capacitor Cin is present, and the voltage dividing resistor and the buffer input capacitor Cin form a low pass filter network. As the frequency of the input signal increases, the capacitive reactance of the buffer input capacitor decreases, and the voltage entering the buffer is attenuated, limiting the bandwidth of the input signal. To increase the bandwidth, the capacitor is shunted across the voltage dividing resistor, and the high frequency passes through the capacitor. Dividing the voltage, as shown in Figure 1, the voltage divider resistor includes an upper divider resistor for R1 and a lower divider resistor for R2.
  • the adjustable capacitor has a semi-circular fixed metal electrode and a movable semi-circular metal electrode, and ceramic or film or air is used as a dielectric in the middle, and the degree of overlap between the movable electrode and the fixed electrode is manually adjusted by the tool to adjust Capacity, but with this manual adjustment, it is time consuming and laborious.
  • the present invention provides a tunable circuit device that realizes automatic adjustment of a voltage dividing capacitor, which can reduce manpower input and greatly improve work efficiency.
  • the present invention provides the following technical solutions:
  • a tunable circuit device comprising: a first signal input terminal N1, a second signal input terminal N2, a first voltage dividing resistor R1, a second voltage dividing resistor R2, a first voltage dividing capacitor C1, a buffer input capacitor Cin, a stray capacitance C2', a buffer 1, a first adjustment circuit 5, a second adjustment circuit 6, a signal conditioner 2, an analog-to-digital converter 3, and a processor 4;
  • a first end of the first adjusting circuit 5 is connected to an input end of the buffer 1, and a second end of the first adjusting circuit 5 is connected to an output end of the buffer 1, the first adjusting circuit The third end of 5 is grounded;
  • a first end of the second adjusting circuit 6 is connected to an input end of the buffer 1, and a second end of the second adjusting circuit 6 is connected to an output end of the buffer 1, the second adjusting circuit The third end of 6 is grounded;
  • An output end of the buffer 1 is sequentially connected to an input end of the processor 4 through the signal conditioner 2 and the analog-to-digital converter 3;
  • the signal conditioner 2 modulates an output signal of the buffer 1 and transmits the conditioned signal to the analog-to-digital converter 3, and the analog-to-digital converter 3 digitally converts the received signal And transmitting the converted digital signal to the processor 4, the processor 4 analyzes the received digital signal according to a preset rule, and sends the analysis result to the first through the control harness L2
  • the control terminal of each switch in the regulating circuit 5 is sent to the address input of the multiplexer 61 in the second regulating circuit 6 via the control harness (L1).
  • the first adjusting circuit 5 includes: a plurality of branches having the same structure, each of the branches being connected in parallel with each other, wherein each of the branches includes: a first capacitor C11, a first switch Q11, and a first a first end of the first capacitor C11 is connected to the input end of the buffer 1, and a second end of the first capacitor C11 is connected to the first end of the first switch Q11.
  • the second end of the first switch Q11 is grounded, the first capacitor C11 and the first switch Q11 A connection point between the terminals is connected to the output of the buffer 1 via the first protection resistor R11.
  • the second adjusting circuit 6 includes: a fixed capacitor C21, a multiplexer 61 and a resistor network 62; a first end of the fixed capacitor C21 is connected to an input end of the buffer 1 A second end of the fixed capacitor C21 is coupled to the output terminal N3 of the multiplexer 61; a first end of the resistor network 62 is coupled to an output of the buffer 1, and a second of the resistor network 62
  • the terminal network is grounded, the resistor network 62 includes a plurality of resistors, and the resistors are sequentially connected in series;
  • the multiplexer 61 includes a first input end and a plurality of second input ends, the first input end is grounded, and The second input terminals are in one-to-one correspondence with the first ends of the plurality of resistors in sequence.
  • the processor 4 includes: a plurality of outputs, wherein the output end corresponding to the first adjusting circuit 5 is respectively controlled by the switch control harness L2 and each of the switches in the first adjusting circuit 5 The control terminals are connected, and the output terminal corresponding to the second regulating circuit 6 is connected to the address input terminal of the multiplexer 61 in the second regulating circuit 6 via the multiplexer control harness L1.
  • each branch capacitor in the first adjusting circuit 5 is sequentially increased in binary.
  • the switch on each branch in the first adjustment circuit 5 is a mechanical relay, a low capacitance photorelay or a junction field effect transistor.
  • the electrode of each branch capacitor in the first adjusting circuit 5 is a circuit board copper, and the dielectric is a board substrate; or the capacitance of each branch in the first adjusting circuit 5 is a fixed capacitor.
  • the processor 4 includes: a first analyzing unit 41, configured to receive low-frequency and high-frequency digital signals with the same amplitude, and measure amplitudes of low-frequency and high-frequency signals, and compare and analyze a difference between the amplitude of the high frequency signal and the amplitude of the low frequency signal.
  • a first analyzing unit 41 configured to receive low-frequency and high-frequency digital signals with the same amplitude, and measure amplitudes of low-frequency and high-frequency signals, and compare and analyze a difference between the amplitude of the high frequency signal and the amplitude of the low frequency signal.
  • the processor 4 includes: a second analyzing unit 42 configured to perform FFT analysis on the received digital signal to obtain a fundamental wave and a harmonic amplitude of the digital signal.
  • the value and phase ratio information is compared and analyzed according to the proportional information and the proportional information calculated by the theoretical FFT in advance by the digital signal.
  • a voltage measuring device includes: the adjustable circuit device.
  • the present invention discloses a tunable circuit device, which comprises: a first signal input terminal N1, a second signal input terminal N2, a first voltage dividing resistor R1, and a second Voltage dividing resistor R2, first voltage dividing capacitor C1, buffer input capacitor Cin, stray capacitance C2', buffer 1, first regulating circuit 5, second adjusting circuit 6, signal conditioner 2, analog-to-digital converter 3 and the processor 4; the processor 4 receives the output signal modulated by the signal conditioner 2 and the analog-to-digital converter 3, and analyzes the output signal according to a preset rule; Controlling the harness to send a control signal to control the open and closed states of each switch in the first regulating circuit 5, to achieve input or cutoff of the adjustable capacitor, thereby adjusting the equivalent capacitance of the first adjusting circuit 5; and controlling In the second adjusting circuit 6, the gear position connection state of the multiplexer 61 changes the connection relationship between the fixed capacitor C21 and the tap position of the voltage dividing resistor network, thereby adjusting the voltage
  • FIG. 1 is a schematic circuit diagram of a conventional circuit device provided by the present invention.
  • FIG. 2 is a schematic circuit diagram of a tunable circuit device according to an embodiment of the present invention.
  • FIG. 3 is a schematic circuit diagram of another adjustable circuit device according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a processor in FIG. 3 corresponding to Embodiment 2 of the present invention.
  • FIG. 2 is a schematic circuit diagram of an embodiment of a tunable circuit device according to the present invention.
  • the tunable circuit device includes: a first signal input terminal N1, a second signal input terminal N2, a first voltage dividing resistor R1, a second voltage dividing resistor R2, and a first component. a piezoelectric capacitor C1, a buffer input capacitor Cin, a stray capacitance C2', a buffer 1, a first regulating circuit 5, a second regulating circuit 6, a signal conditioner 2, an analog-to-digital converter 3, and a processor 4;
  • a first end of the first adjusting circuit 5 is connected to an input end of the buffer 1, and a second end of the first adjusting circuit 5 is connected to an output end of the buffer 1, the first adjusting circuit The third end of 5 is grounded;
  • a first end of the second adjusting circuit 6 is connected to an input end of the buffer 1, and a second end of the second adjusting circuit 6 is connected to an output end of the buffer 1, the second adjusting circuit The third end of 6 is grounded;
  • An output end of the buffer 1 is sequentially connected to an input end of the processor 4 through the signal conditioner 2 and the analog-to-digital converter 3;
  • the signal conditioner 2 modulates an output signal of the buffer 1 and transmits the conditioned signal to the analog-to-digital converter 3, and the analog-to-digital converter 3 digitally converts the received signal And transmitting the converted digital signal to the processor 4, the processor 4 analyzes the received digital signal according to a preset rule, and sends the analysis result to the first through the control harness L2
  • the control terminal of each switch in the regulating circuit 5 is sent to the address input of the multiplexer 61 in the second regulating circuit 6 via the control harness L1.
  • each switch in the first adjusting circuit 5 and the address input end of the multiplexer 61 in the second adjusting circuit 6 control the first adjustment according to the received analysis result. Opening or closing of each switch in the circuit 5; and controlling a gear connection line of the multiplexer 61 in the second regulating circuit 6 to be connected to an input terminal in the multiplexer 61, thereby changing The equivalent capacitance value of the first adjustment circuit 5 and the second adjustment circuit 6 is described.
  • the processor 4 can control the opening and closing states of each switch in the first adjusting circuit 5 by controlling the wire harness transmission control signal to implement Turning on or off the adjustable capacitor in series, thereby adjusting the equivalent capacitance of the first regulating circuit 5; and controlling the gear connection state of the multiplexer 61 in the second regulating circuit 6, changing the connection
  • the voltage divider resistor network 62 taps the position, thereby adjusting the voltage across the fixed capacitor, so that the fixed capacitor is simulated as a tunable capacitor, which can realize automatic adjustment of the voltage dividing capacitor, reduce human intervention, improve work efficiency, and improve adjustment. Precision.
  • FIG. 3 is a schematic structural view of another embodiment of a tunable circuit device according to the present invention.
  • the first adjusting circuit 5 includes: a plurality of branches having the same structure, each of the branches being connected in parallel with each other, wherein each of the branches includes: a first capacitor C11 a first switch Q11 and a first protection resistor R11, a first end of the first capacitor C11 is connected to an input end of the buffer 1, a second end of the first capacitor C11 and the first switch Q11 The first end of the first switch Q11 is connected to the ground, and the connection point between the first capacitor C11 and the first switch Q11 passes through the first protection resistor R11 and the buffer 1 The outputs are connected.
  • each branch in the first adjusting circuit 5 can be increased in binary order, assuming that the lowest bit is C, the high order is 2C, 4C, 8C, 16C, etc., and the smallest component can be used according to binary increment.
  • 1pF, 2pF, 4pF three capacitors can be composed of 8 different capacities of 1pF, 0pF (3 are not connected), 1pF, 2pF, 3pF (1pF and 2pF in parallel) , 4pF, 5pF (1pF and 4pF in parallel), 6pF (2pF and 4pF in parallel), 7pF (3 in parallel) and so on.
  • the capacitance of each branch in the first adjustment circuit 5 may be one or more Cascade and parallel connection;
  • the capacitor may be a capacitor formed by using a circuit board copper as an electrode and a board substrate as a dielectric, wherein a copper-clad area as a capacitor electrode is set in a binary manner, and a ground plane is covered with copper as a common electrode to realize a binary capacitor;
  • the capacitor can also be a fixed capacitor.
  • the switch on each branch in the first adjusting circuit 5 may be a mechanical relay, a low-capacitance optical relay or a junction field effect transistor, and the switch can be connected in series with the switch by controlling the open and closed states of the switch. The input and the cutoff of the capacitance are adjusted to adjust the capacitance of the first adjustment circuit 5.
  • the first protection resistor R11 is configured to maintain a connection point voltage between the first adjustable capacitor C11 and the first switch Q11 and the first voltage dividing resistor R1 and the first switch Q11 when the first switch Q11 is turned off.
  • the voltage at the connection point between the second voltage dividing resistors R2 is the same, and the stray capacitance at both ends of the switch is prevented from generating a leakage current.
  • the second adjusting circuit 6 includes a fixed capacitor C21, a multiplexer 61 and a resistor network 62.
  • the first end of the fixed capacitor C21 is connected to the input end of the buffer 1.
  • the second end of the fixed capacitor C21 is connected to the output terminal N3 of the multiplexer 61;
  • the first end of the resistor network 62 is connected to the output end of the buffer 1, the resistor network 62
  • the second end is grounded, the resistor network 62 includes a plurality of resistors, each of the resistors being sequentially connected in series;
  • the multiplexer 61 includes a first input terminal and a plurality of second input terminals, the first input terminal is grounded And the plurality of second input terminals are in one-to-one correspondence with the first ends of the plurality of resistors in sequence.
  • the multiplexer 61 includes a first input end and a plurality of second input ends, the first input end is grounded, and the plurality of the second input ends are sequentially and in sequence with the plurality of the resistors One-to-one correspondence.
  • the resistor network 62 is composed of a plurality of resistors in series. The two ends of the resistor are grounded at one end and the other end is connected to a signal source to be divided.
  • the first ends of the plurality of groups are Different taps or lead points, different taps correspond to different partial pressure ratios.
  • a voltage divider resistor network consisting of five resistors in series, the 0 to 5 tap divider ratios are 0/5, 1/5, 2/5, 3/5, 4/5, 5/5, set the signal voltage to Vs, the output voltage of 0 ⁇ 5 taps is 0, 1/5Vs, 2/5Vs, 3 /5Vs, 4/5Vs, Vs.
  • the multiplexer selects one of the taps to obtain a voltage division ratio.
  • the capacity of the fixed capacitor C21 is ⁇ the capacity of the lowest bit capacitance in the first adjustment circuit to cover the error of the lowest bit capacitance of the first adjustment circuit 5, so that the adjustment can be smoothly continuous, by controlling the multiplexer 61 In the gear state, the connected tapping resistor network 62 tap position is changed, thereby adjusting the voltage across the fixed capacitor C21, thereby simulating the fixed capacitor C21 as a variable capacitor.
  • the processor 4 includes: a plurality of outputs, wherein an output corresponding to the first adjustment circuit 5 passes through each of the first adjustment circuits 5 through the switch control harness L2 The control terminals of the switches are connected, and the output terminals corresponding to the second regulating circuit 6 are connected to the address inputs of the multiplexers 61 in the second regulating circuit 6 via the multiplexer control harness L1.
  • the processor 4 includes:
  • a first analyzing unit 41 configured to receive low frequency and high frequency digital signals of the same amplitude, measure amplitudes of low frequency and high frequency signals, compare and analyze amplitudes of the high frequency signals and the low frequency The difference in signal amplitude.
  • the processor 4 includes:
  • a second analyzing unit 42 configured to perform FFT analysis on the received digital signal, acquire amplitude and phase ratio information of a fundamental wave and each harmonic of the digital signal, according to the ratio information and The digital signal is previously compared and analyzed by the ratio information calculated by the theoretical FFT.
  • the processor has two adjustment schemes, one of which is that the first analyzing unit 41 of the processor 4 receives the same amplitude output by the analog-to-digital converter 3 respectively.
  • the low frequency and high frequency signals the processor 4 first measures the amplitude of the low frequency signal, and then measures the amplitude of the output high frequency signal, and compares and analyzes the difference between the amplitude of the high frequency signal and the amplitude of the low frequency signal,
  • a control signal is sent to the control terminal of the switch on each branch in the first regulating circuit 5 through the switch control harness L2 to adjust the first regulated power a switching state in the way 5, coarsely adjusting the equivalent capacitance value of the first regulating circuit 5; transmitting a control signal to the address input end of the multiplexer through the multiplexer control harness L1, the plurality
  • the multiplexer parses the control signal and selects data corresponding to one of the input terminals for output, that is, the multiplexer 61 gear position in the second
  • the position of the multiplexer can control the ratio of the voltage across the fixed capacitor to the voltage of the divided voltage to ground, thereby changing the current flowing through the fixed capacitor, and simulating the fixed capacitor as a variable capacitor, through the first regulating circuit 5 and
  • the capacitance and the buffer input capacitance and the stray capacitance minimize the difference between the final high-frequency signal amplitude and the low-frequency signal, that is, the matching state, and the processor 4 simultaneously records the high-frequency and low-frequency signal amplitude matching states.
  • the second analyzing unit 42 of the processor 4 performs FFT analysis on the input square wave signal converted by the voltage division attenuation, the buffer 1, the signal conditioner 2, and the analog-to-digital converter 3.
  • the signal conditioner 2 is for adjusting the input signal to a signal satisfying the input voltage range of the analog-to-digital converter 3, the analog-to-digital converter 3 for converting its input signal into a digital signal, and the processor 4 for analogizing the digital signal to the digital signal
  • the sampled value of the converter 3 is subjected to FFT analysis to obtain the amplitude and phase information of the fundamental wave and each harmonic of the input square wave signal.
  • the simulation is performed.
  • the digital signal converted by the digitizer 3 is subjected to FFT to find the ratio of the fundamental wave and each harmonic, which is compared with the theoretical calculation of the input square wave signal.
  • the fundamental state and each harmonic of the digital signal converted by the final analog-to-digital converter 3 are adjusted by controlling the wiring harness to adjust the switching state of the first regulating circuit and the multiplexer gear state of the second regulating circuit.
  • the wave ratio is closest to the case when the input square wave is theoretically decomposed.
  • the switching state is the matching state
  • the processor 4 records the switching state of the first adjusting circuit 5 in the matching state and the second adjusting circuit 6 Multiplexer 61 gear status, each The first adjustment circuit 5 switch and the multiplexer 61 position of the second adjustment circuit 6 are configured in accordance with this code.
  • the processor 4 passes the first analysis unit by receiving the digital signal converted by the signal conditioner 2 and the analog-to-digital converter 3. Or the second analyzing unit analyzes the received digital signal, and sends the analysis result to the control end of each switch in the first adjusting circuit 5 through the control harness L2 and sends the same to the control through the control harness L1.
  • the voltage across the fixed capacitor C21 is such that the fixed capacitor C21 is simulated as a tunable capacitor to match the upper and lower voltage divider capacitors.
  • the program control can realize the automatic adjustment of the upper and lower voltage division resistance time constant matching, obtain the flat amplitude frequency characteristic, improve the production efficiency, and at the same time avoid the influence of vibration on the stability of the voltage dividing capacitor because there is no mechanical capacitance adjustable device.
  • the present invention also provides a specific embodiment of a voltage measuring device comprising: the tunable circuit device described above.
  • the voltage measuring device can be any voltage measuring device for measuring DC, AC or AC/DC mixed signals, such as an oscilloscope; or a module of the voltage measuring device is used for measuring the above voltage signal, such as a multimeter, power Meter, power analyzer, etc.
  • the voltage measuring device may convert the continuous analog signal into a discrete digital sequence by using an analog-to-digital converter 3 according to a sampling principle, and then recover and reconstruct the waveform, thereby achieving the purpose of measuring the waveform.
  • the buffer 1 is used for buffering the received input signal to isolate the measured object from the voltage measuring device.
  • the change of the operating state of the voltage measuring device does not affect the input signal, and the amplitude of the signal is The value is switched to the appropriate level range, ie the range that the voltage measuring device can handle, that is to say the signals of different amplitudes are converted into signals in the same voltage range after passing through the input buffer amplifier;
  • the signal conditioner 2 is configured to modulate an output analog signal to be tested of the buffer 1 to a range suitable for conversion by the analog to digital converter 3;
  • the analog-to-digital converter 3 is configured to convert a continuous analog signal output by the signal conditioner 2 into a discrete digital sequence, and then reconstruct a waveform according to a sequence of digital sequences, the analog-to-digital converter 3 serving as a sampling
  • the role of the sampling clock, the amplitude of the signal at the moment of arrival of the sampling pulse is converted into a numerical value, this point is called the sampling point;
  • the processor 4 receives the digital signal converted by the analog-to-digital converter 3, and analyzes the received digital signal according to a preset rule, and sends the analysis result to the first through the control harness L2.
  • the control terminal of each switch in the adjusting circuit 5 and the address input terminal of the multiplexer 61 in the second adjusting circuit 6 are controlled by the control harness L1, and each switch in the first adjusting circuit 5 can be controlled.
  • connection state changes the tap position of the connected voltage divider resistor network 62, thereby adjusting the voltage across the fixed capacitor C21, so that the fixed capacitor C21 is simulated as a tunable capacitor, and the process control can realize the automatic adjustment of the upper and lower voltage division resistance time constant matching. , to obtain a flat amplitude frequency characteristic.
  • the voltage measuring device adopts the adjustable circuit device as its internal circuit structure, can realize automatic adjustment of upper and lower voltage-dividing resistance-capacitance time constant matching, obtains flat amplitude-frequency characteristics, and ensures accuracy of high-frequency signal data measurement. , effectively avoiding measurement errors.
  • the device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be Physical units can be located in one place or distributed to multiple network elements. You can choose some of them according to actual needs or All units are used to achieve the objectives of the solution of this embodiment.
  • the connection relationship between the units indicates that there is a communication connection between them, and specifically may be implemented as one or more communication buses or signal lines.

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  • Measurement Of Current Or Voltage (AREA)

Abstract

An adjustable circuit device, comprising: a first adjustment circuit (5), a second adjustment circuit (6), a signal conditioner (2), an analog-to-digital converter (3) and a processor (4). The processor (4) receives an output signal converted by the signal conditioner (2) and the analog-to-digital converter (3), analyzes the digital signal according to preset rules, and sends, according to the analysis results, control signals to control the on and off states of each switch in the first adjustment circuit (5), so as to achieve the incorporation or cut off of an adjustable capacitor, thereby adjusting the equivalent capacitance of the first adjustment circuit (5); and to control the tap-position connection state of the multiplexer in the second adjustment circuit (6), so as to change the position of a tap of a connected voltage divider resistor network, thereby adjusting the voltage across the fixed capacitor, such that the fixed capacitor is simulated to be an adjustable capacitor. The invention achieves the automatic adjustment of the voltage divider capacitor by means of program control, reducing the need for human input and greatly improving work efficiency.

Description

一种可调电路装置及电压测量装置Adjustable circuit device and voltage measuring device 技术领域Technical field
本申请要求于2016年8月15日提交中国专利局、申请号为201610667922.7、发明名称为“一种可调电路装置及电压测量装置”的国内申请的优先权，其全部内容通过引用结合在本申请中。This application claims the priority of the domestic application filed on August 15, 2016, the Chinese Patent Office, the application number is 201610667922.7, and the invention is entitled "a tunable circuit device and a voltage measuring device", the entire contents of which are incorporated herein by reference. In the application.
本申请要求于2016年8月15日提交中国专利局、申请号为201620880722.5、发明名称为“一种可调电路装置”的国内申请的优先权，其全部内容通过引用结合在本申请中。The present application claims priority to the Chinese Patent Application No. PCT-A No. No. No. No. No. No. No. No. No. No. No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No
背景技术Background technique
由于半导体电子电路工作电压较低，通常使用分压电阻将高压输入信号进行分压衰减，然而缓冲器分压后存在输入电容Cin，分压电阻与缓冲器输入电容Cin构成了低通滤波器网络，随着输入信号频率的增大，缓冲器输入电容的容抗减少，进入缓冲器的电压被衰减，限制了输入信号的带宽，为了提高带宽，在分压电阻上并联电容，高频通过电容进行分压，如图1所示，分压电阻包括上分压电阻为R1、下分压电阻为R2，分压电容包括上分压电容为C1、总下分压电容(包括杂散电容和缓冲器输入电容)为C2，若电阻电容取值满足R1×C1＝R2×C2，即上分压阻容的时间常数与下分压阻容的时间常数相等，对于任何频率电容分压比与电阻分压比相同，可以得到平坦的幅频响应。Since the operating voltage of the semiconductor electronic circuit is low, the voltage dividing resistor is usually used to divide and attenuate the high voltage input signal. However, after the buffer is divided, the input capacitor Cin is present, and the voltage dividing resistor and the buffer input capacitor Cin form a low pass filter network. As the frequency of the input signal increases, the capacitive reactance of the buffer input capacitor decreases, and the voltage entering the buffer is attenuated, limiting the bandwidth of the input signal. To increase the bandwidth, the capacitor is shunted across the voltage dividing resistor, and the high frequency passes through the capacitor. Dividing the voltage, as shown in Figure 1, the voltage divider resistor includes an upper divider resistor for R1 and a lower divider resistor for R2. The divider capacitor includes an upper divider capacitor for C1 and a total lower divider capacitor (including stray capacitance and The buffer input capacitance is C2. If the value of the resistor and capacitor satisfies R1×C1=R2×C2, the time constant of the upper voltage-dividing resistor is equal to the time constant of the lower voltage-dependent resistor, and the voltage-divider ratio of any frequency is The resistor divider ratio is the same, and a flat amplitude-frequency response can be obtained.
实际上由于分压电容存在误差，缓冲器输入电容、安装结构等都会存在差异，导致上下分压阻容时间常数不相等，造成幅频特性不平坦，所以需要对每个产品的分压电容进行微调，目前使用可调电容进行匹配，可调电容有半圆固定金属电极和可动半圆金属电极，中间用陶瓷或薄膜或空气作为电介质，通过工具手动调整可动电极与固定电极的重叠程度从而调整容量，但是采用这种手动调整的方式，比较费时费力。 In fact, due to the error of the voltage dividing capacitor, the buffer input capacitance, the mounting structure, etc. will be different, resulting in unequal time constants of the upper and lower voltage dividers, resulting in uneven amplitude frequency characteristics, so the voltage dividing capacitor of each product needs to be performed. Fine-tuning, currently using a tunable capacitor for matching, the adjustable capacitor has a semi-circular fixed metal electrode and a movable semi-circular metal electrode, and ceramic or film or air is used as a dielectric in the middle, and the degree of overlap between the movable electrode and the fixed electrode is manually adjusted by the tool to adjust Capacity, but with this manual adjustment, it is time consuming and laborious.
发明内容Summary of the invention
有鉴于此，本发明提供了一种可调电路装置，实现分压电容的自动调整，可以减小人力的投入，大大提高了工作效率。In view of this, the present invention provides a tunable circuit device that realizes automatic adjustment of a voltage dividing capacitor, which can reduce manpower input and greatly improve work efficiency.
为实现上述目的，本发明提供如下技术方案：To achieve the above object, the present invention provides the following technical solutions:
一种可调电路装置，包括：第一信号输入端N1、第二信号输入端N2、第一分压电阻R1、第二分压电阻R2、第一分压电容C1、缓冲器输入电容Cin、杂散电容C2'、缓冲器1、第一调节电路5、第二调节电路6、信号调理器2、模拟-数字转换器3和处理器4；A tunable circuit device comprising: a first signal input terminal N1, a second signal input terminal N2, a first voltage dividing resistor R1, a second voltage dividing resistor R2, a first voltage dividing capacitor C1, a buffer input capacitor Cin, a stray capacitance C2', a buffer 1, a first adjustment circuit 5, a second adjustment circuit 6, a signal conditioner 2, an analog-to-digital converter 3, and a processor 4;
所述第一调节电路5的第一端与所述缓冲器1的输入端相连，所述第一调节电路5的第二端与所述缓冲器1的输出端相连，所述第一调节电路5的第三端接地；a first end of the first adjusting circuit 5 is connected to an input end of the buffer 1, and a second end of the first adjusting circuit 5 is connected to an output end of the buffer 1, the first adjusting circuit The third end of 5 is grounded;
所述第二调节电路6的第一端与所述缓冲器1的输入端相连，所述第二调节电路6的第二端与所述缓冲器1的输出端相连，所述第二调节电路6的第三端接地；a first end of the second adjusting circuit 6 is connected to an input end of the buffer 1, and a second end of the second adjusting circuit 6 is connected to an output end of the buffer 1, the second adjusting circuit The third end of 6 is grounded;
所述缓冲器1的输出端依次通过所述信号调理器2和所述模拟-数字转换器3与所述处理器4的输入端相连；An output end of the buffer 1 is sequentially connected to an input end of the processor 4 through the signal conditioner 2 and the analog-to-digital converter 3;
所述信号调理器2对所述缓冲器1的输出信号进行调理，并将调理后的信号发送到所述模拟-数字转换器3，所述模拟-数字转换器3对接收的信号进行数字转换，并将转换后的数字信号发送到所述处理器4，所述处理器4按照预先设置的规则对接收的所述数字信号进行分析，并将分析结果通过控制线束L2发送给所述第一调节电路5内每个开关的控制端以及通过控制线束(L1)发送给所述第二调节电路6内多路复用器61的地址输入端。The signal conditioner 2 modulates an output signal of the buffer 1 and transmits the conditioned signal to the analog-to-digital converter 3, and the analog-to-digital converter 3 digitally converts the received signal And transmitting the converted digital signal to the processor 4, the processor 4 analyzes the received digital signal according to a preset rule, and sends the analysis result to the first through the control harness L2 The control terminal of each switch in the regulating circuit 5 is sent to the address input of the multiplexer 61 in the second regulating circuit 6 via the control harness (L1).
可选的，所述第一调节电路5包括：多个结构相同的支路，各个所述支路相互并联，其中每个所述支路包括：第一电容C11、第一开关Q11和第一保护电阻R11，所述第一电容C11的第一端与所述缓冲器1的输入端相连，所述第一电容C11的第二端与所述第一开关Q11的第一端相连，所述第一开关Q11的第二端接地，所述第一电容C11与所述第一开关Q11 之间的连接点通过所述第一保护电阻R11与所述缓冲器1的输出端相连。Optionally, the first adjusting circuit 5 includes: a plurality of branches having the same structure, each of the branches being connected in parallel with each other, wherein each of the branches includes: a first capacitor C11, a first switch Q11, and a first a first end of the first capacitor C11 is connected to the input end of the buffer 1, and a second end of the first capacitor C11 is connected to the first end of the first switch Q11. The second end of the first switch Q11 is grounded, the first capacitor C11 and the first switch Q11 A connection point between the terminals is connected to the output of the buffer 1 via the first protection resistor R11.
可选的，所述第二调节电路6包括：固定电容C21、多路复用器61和电阻网络62；所述固定电容C21的第一端与所述缓冲器1的输入端相连，所述固定电容C21的第二端与所述多路复用器61的输出端N3相连；所述电阻网络62的第一端与所述缓冲器1的输出端相连，所述电阻网络62的第二端接地，所述电阻网络62包括多个电阻，各个所述电阻依次串联；所述多路复用器61包括第一输入端和多个第二输入端，所述第一输入端接地，多个所述第二输入端按顺序与多个所述电阻的第一端一一对应。Optionally, the second adjusting circuit 6 includes: a fixed capacitor C21, a multiplexer 61 and a resistor network 62; a first end of the fixed capacitor C21 is connected to an input end of the buffer 1 A second end of the fixed capacitor C21 is coupled to the output terminal N3 of the multiplexer 61; a first end of the resistor network 62 is coupled to an output of the buffer 1, and a second of the resistor network 62 The terminal network is grounded, the resistor network 62 includes a plurality of resistors, and the resistors are sequentially connected in series; the multiplexer 61 includes a first input end and a plurality of second input ends, the first input end is grounded, and The second input terminals are in one-to-one correspondence with the first ends of the plurality of resistors in sequence.
可选的，所述处理器4包括：多个输出端，其中与所述第一调节电路5相对应的输出端通过开关控制线束L2分别与所述第一调节电路5内的每一个开关的控制端相连，与所述第二调节电路6相对应的输出端通过多路复用器控制线束L1与所述第二调节电路6内多路复用器61的地址输入端相连。Optionally, the processor 4 includes: a plurality of outputs, wherein the output end corresponding to the first adjusting circuit 5 is respectively controlled by the switch control harness L2 and each of the switches in the first adjusting circuit 5 The control terminals are connected, and the output terminal corresponding to the second regulating circuit 6 is connected to the address input terminal of the multiplexer 61 in the second regulating circuit 6 via the multiplexer control harness L1.
可选的，所述第一调节电路5内每条支路上电容的容量按照二进制依次递增。Optionally, the capacity of each branch capacitor in the first adjusting circuit 5 is sequentially increased in binary.
可选的，所述第一调节电路5内每条支路上的开关为机械继电器、低电容光继电器或者结型场效应管。Optionally, the switch on each branch in the first adjustment circuit 5 is a mechanical relay, a low capacitance photorelay or a junction field effect transistor.
可选的，所述第一调节电路5内每条支路上电容的电极为电路板覆铜，电介质为板基材；或者所述第一调节电路5内每条支路上的电容为固定电容器。Optionally, the electrode of each branch capacitor in the first adjusting circuit 5 is a circuit board copper, and the dielectric is a board substrate; or the capacitance of each branch in the first adjusting circuit 5 is a fixed capacitor.
可选的，所述处理器4包括：第一分析单元41，所述第一分析单元41用于接收幅值相同的低频和高频数字信号，测量低频和高频信号的幅值，比较分析所述高频信号的幅值与所述低频信号幅值的差值。Optionally, the processor 4 includes: a first analyzing unit 41, configured to receive low-frequency and high-frequency digital signals with the same amplitude, and measure amplitudes of low-frequency and high-frequency signals, and compare and analyze a difference between the amplitude of the high frequency signal and the amplitude of the low frequency signal.
可选的，所述处理器4包括：第二分析单元42，所述第二分析单元42用于对接收的数字信号进行FFT分析，获取所述数字信号的基波和各次谐波的幅值和相位比例信息，依据所述比例信息与所述数字信号预先通过理论FFT计算的比例信息进行比较分析。Optionally, the processor 4 includes: a second analyzing unit 42 configured to perform FFT analysis on the received digital signal to obtain a fundamental wave and a harmonic amplitude of the digital signal. The value and phase ratio information is compared and analyzed according to the proportional information and the proportional information calculated by the theoretical FFT in advance by the digital signal.
一种电压测量装置，包括：所述可调电路装置。 A voltage measuring device includes: the adjustable circuit device.
经由上述的技术方案可知，与现有技术相比，本发明公开了一种可调电路装置，包括：第一信号输入端N1、第二信号输入端N2、第一分压电阻R1、第二分压电阻R2、第一分压电容C1、缓冲器输入电容Cin、杂散电容C2'、缓冲器1、第一调节电路5、第二调节电路6、信号调理器2、模拟-数字转换器3和处理器4；所述处理器4接收经信号调理器2调理以及模拟-数字转换器3转换后的输出信号，并按照预先设置的规则对所述输出信号进行分析；依据分析结果，通过控制线束发送控制信号以控制所述第一调节电路5内每个开关的断开与闭合状态，实现可调电容的投入或切断，从而调整所述第一调节电路5的等效电容；以及控制所述第二调节电路6内多路复用器61的档位连接状态，改变固定电容C21与分压电阻网络抽头位置的连接关系，从而调整所述固定电容C21两端的电压，使固定电容C21模拟成可调电容。本发明通过程控实现分压电容的自动调整，可以减小人力的投入，大大提高了工作效率。According to the above technical solution, the present invention discloses a tunable circuit device, which comprises: a first signal input terminal N1, a second signal input terminal N2, a first voltage dividing resistor R1, and a second Voltage dividing resistor R2, first voltage dividing capacitor C1, buffer input capacitor Cin, stray capacitance C2', buffer 1, first regulating circuit 5, second adjusting circuit 6, signal conditioner 2, analog-to-digital converter 3 and the processor 4; the processor 4 receives the output signal modulated by the signal conditioner 2 and the analog-to-digital converter 3, and analyzes the output signal according to a preset rule; Controlling the harness to send a control signal to control the open and closed states of each switch in the first regulating circuit 5, to achieve input or cutoff of the adjustable capacitor, thereby adjusting the equivalent capacitance of the first adjusting circuit 5; and controlling In the second adjusting circuit 6, the gear position connection state of the multiplexer 61 changes the connection relationship between the fixed capacitor C21 and the tap position of the voltage dividing resistor network, thereby adjusting the voltage across the fixed capacitor C21, so that the voltage across the fixed capacitor C21 is adjusted. Given capacitance modeled as variable capacitor C21. The invention realizes the automatic adjustment of the voltage dividing capacitor through the process control, can reduce the input of manpower, and greatly improves the working efficiency.
附图说明DRAWINGS
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据提供的附图获得其他的附图。In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below. Obviously, the drawings in the following description are only It is an embodiment of the present invention, and those skilled in the art can obtain other drawings according to the provided drawings without any creative work.
图1为本发明提供的一种现有电路装置的电路示意图；1 is a schematic circuit diagram of a conventional circuit device provided by the present invention;
图2为本发明实施例中提供的一种可调电路装置的电路示意图；2 is a schematic circuit diagram of a tunable circuit device according to an embodiment of the present invention;
图3为本发明实施例中提供的另一种可调电路装置的电路示意图；3 is a schematic circuit diagram of another adjustable circuit device according to an embodiment of the present invention;
图4为本发明实施例二对应的图3中处理器的结构示意图。FIG. 4 is a schematic structural diagram of a processor in FIG. 3 corresponding to Embodiment 2 of the present invention.
具体实施方式detailed description
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没 有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, those of ordinary skill in the art are not All other embodiments obtained under the premise of creative work are within the scope of the present invention.
本发明的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的术语在适当情况下可以互换，这仅仅是描述本发明的实施例中对相同属性的对象在描述时所采用的区分方式。The terms "first", "second" and the like in the specification and claims of the present invention and the above drawings are used to distinguish similar objects, and are not necessarily used to describe a particular order or order. It is to be understood that the terms so used are interchangeable as appropriate, and are merely illustrative of the manner in which the objects of the same.
为使本发明的上述目的、特征和优点能够更加明显易懂，下面结合附图和具体实施方式对本发明作进一步详细的说明。The present invention will be further described in detail with reference to the accompanying drawings and specific embodiments.
请参阅附图2，为本发明提供的一种可调电路装置的一实施例电路示意图。2 is a schematic circuit diagram of an embodiment of a tunable circuit device according to the present invention.
所述一种可调电路装置，如图2所示，该装置包括：第一信号输入端N1、第二信号输入端N2、第一分压电阻R1、第二分压电阻R2、第一分压电容C1、缓冲器输入电容Cin、杂散电容C2'、缓冲器1、第一调节电路5、第二调节电路6、信号调理器2、模拟-数字转换器3和处理器4；The tunable circuit device, as shown in FIG. 2, includes: a first signal input terminal N1, a second signal input terminal N2, a first voltage dividing resistor R1, a second voltage dividing resistor R2, and a first component. a piezoelectric capacitor C1, a buffer input capacitor Cin, a stray capacitance C2', a buffer 1, a first regulating circuit 5, a second regulating circuit 6, a signal conditioner 2, an analog-to-digital converter 3, and a processor 4;
所述第一调节电路5的第一端与所述缓冲器1的输入端相连，所述第一调节电路5的第二端与所述缓冲器1的输出端相连，所述第一调节电路5的第三端接地；a first end of the first adjusting circuit 5 is connected to an input end of the buffer 1, and a second end of the first adjusting circuit 5 is connected to an output end of the buffer 1, the first adjusting circuit The third end of 5 is grounded;
所述第二调节电路6的第一端与所述缓冲器1的输入端相连，所述第二调节电路6的第二端与所述缓冲器1的输出端相连，所述第二调节电路6的第三端接地；a first end of the second adjusting circuit 6 is connected to an input end of the buffer 1, and a second end of the second adjusting circuit 6 is connected to an output end of the buffer 1, the second adjusting circuit The third end of 6 is grounded;
所述缓冲器1的输出端依次通过所述信号调理器2和所述模拟-数字转换器3与所述处理器4的输入端相连；An output end of the buffer 1 is sequentially connected to an input end of the processor 4 through the signal conditioner 2 and the analog-to-digital converter 3;
所述信号调理器2对所述缓冲器1的输出信号进行调理，并将调理后的信号发送到所述模拟-数字转换器3，所述模拟-数字转换器3对接收的信号进行数字转换，并将转换后的数字信号发送到所述处理器4，所述处理器4按照预先设置的规则对接收的所述数字信号进行分析，并将分析结果通过控制线束L2发送给所述第一调节电路5内每个开关的控制端以及通过控制线束L1发送给所述第二调节电路6内多路复用器61的地址输入端。 The signal conditioner 2 modulates an output signal of the buffer 1 and transmits the conditioned signal to the analog-to-digital converter 3, and the analog-to-digital converter 3 digitally converts the received signal And transmitting the converted digital signal to the processor 4, the processor 4 analyzes the received digital signal according to a preset rule, and sends the analysis result to the first through the control harness L2 The control terminal of each switch in the regulating circuit 5 is sent to the address input of the multiplexer 61 in the second regulating circuit 6 via the control harness L1.
其中，所述第一调节电路5内每个开关的控制端以及所述第二调节电路6内多路复用器61的地址输入端，依据接收的所述分析结果，控制所述第一调节电路5内每个开关的断开或者闭合；以及控制所述第二调节电路6内多路复用器61的档位连接线与多路复用器61内的一个输入端相连，从而改变所述第一调节电路5与所述第二调节电路6的等效电容值。The control end of each switch in the first adjusting circuit 5 and the address input end of the multiplexer 61 in the second adjusting circuit 6 control the first adjustment according to the received analysis result. Opening or closing of each switch in the circuit 5; and controlling a gear connection line of the multiplexer 61 in the second regulating circuit 6 to be connected to an input terminal in the multiplexer 61, thereby changing The equivalent capacitance value of the first adjustment circuit 5 and the second adjustment circuit 6 is described.
根据本发明实施例一中公开的技术方案，所述处理器4通过控制线束发送控制信号可以控制所述第一调节电路5内每个开关的断开与闭合状态，以实现与每个所述开关串联的可调电容的投入或切断，从而调整所述第一调节电路5的等效电容；以及控制所述第二调节电路6内多路复用器61的档位连接状态，改变连接的分压电阻网络62抽头位置，从而调整所述固定电容两端的电压，使固定电容模拟成可调电容，可以实现分压电容的自动调整，减小人为的干预，提高工作效率，同时提高了调整精度。According to the technical solution disclosed in Embodiment 1 of the present invention, the processor 4 can control the opening and closing states of each switch in the first adjusting circuit 5 by controlling the wire harness transmission control signal to implement Turning on or off the adjustable capacitor in series, thereby adjusting the equivalent capacitance of the first regulating circuit 5; and controlling the gear connection state of the multiplexer 61 in the second regulating circuit 6, changing the connection The voltage divider resistor network 62 taps the position, thereby adjusting the voltage across the fixed capacitor, so that the fixed capacitor is simulated as a tunable capacitor, which can realize automatic adjustment of the voltage dividing capacitor, reduce human intervention, improve work efficiency, and improve adjustment. Precision.
请参阅附图3，为本发明提供的一种可调电路装置的另一实施例结构示意图。3 is a schematic structural view of another embodiment of a tunable circuit device according to the present invention.
如图3所示，在本实施例中，所述第一调节电路5包括：多个结构相同的支路，各个所述支路相互并联，其中每个所述支路包括：第一电容C11、第一开关Q11和第一保护电阻R11，所述第一电容C11的第一端与所述缓冲器1的输入端相连，所述第一电容C11的第二端与所述第一开关Q11的第一端相连，所述第一开关Q11的第二端接地，所述第一电容C11与所述第一开关Q11之间的连接点通过所述第一保护电阻R11与所述缓冲器1的输出端相连。As shown in FIG. 3, in the embodiment, the first adjusting circuit 5 includes: a plurality of branches having the same structure, each of the branches being connected in parallel with each other, wherein each of the branches includes: a first capacitor C11 a first switch Q11 and a first protection resistor R11, a first end of the first capacitor C11 is connected to an input end of the buffer 1, a second end of the first capacitor C11 and the first switch Q11 The first end of the first switch Q11 is connected to the ground, and the connection point between the first capacitor C11 and the first switch Q11 passes through the first protection resistor R11 and the buffer 1 The outputs are connected.
其中，所述第一调节电路5内每条支路上电容的容量可以按照二进制依次递增，假设最低位为C，高位依次为2C，4C，8C，16C等等，按照二进制递增可以用最小的元件实现最多等间隔的档位，例如用1pF、2pF、4pF三个电容即可组成刻度为1pF的8种不同容量，0pF(3个都不接)，1pF，2pF，3pF(1pF与2pF并联)，4pF，5pF(1pF与4pF并联)，6pF(2pF与4pF并联)，7pF(3个并联)等。The capacity of each branch in the first adjusting circuit 5 can be increased in binary order, assuming that the lowest bit is C, the high order is 2C, 4C, 8C, 16C, etc., and the smallest component can be used according to binary increment. To achieve the most equally spaced gears, for example, 1pF, 2pF, 4pF three capacitors can be composed of 8 different capacities of 1pF, 0pF (3 are not connected), 1pF, 2pF, 3pF (1pF and 2pF in parallel) , 4pF, 5pF (1pF and 4pF in parallel), 6pF (2pF and 4pF in parallel), 7pF (3 in parallel) and so on.
其中，所述第一调节电路5内每条支路上的电容可以为一个或多个电 容串并联构成；The capacitance of each branch in the first adjustment circuit 5 may be one or more Cascade and parallel connection;
或者所述电容可以为利用电路板覆铜作为电极，板基材作为电介质构成的电容，其中作为电容电极的覆铜面积按照二进制设置，地平面覆铜作为公共电极，以实现二进制电容；或者所述电容也可以为固定电容器。Alternatively, the capacitor may be a capacitor formed by using a circuit board copper as an electrode and a board substrate as a dielectric, wherein a copper-clad area as a capacitor electrode is set in a binary manner, and a ground plane is covered with copper as a common electrode to realize a binary capacitor; The capacitor can also be a fixed capacitor.
所述第一调节电路5内每个支路上的开关可以为机械继电器、低电容的光继电器或者结型场效应管，通过控制所述开关的断开与闭合状态实现与所述开关串联的可调电容的投入和切断，从而调整所述第一调节电路5的电容量。The switch on each branch in the first adjusting circuit 5 may be a mechanical relay, a low-capacitance optical relay or a junction field effect transistor, and the switch can be connected in series with the switch by controlling the open and closed states of the switch. The input and the cutoff of the capacitance are adjusted to adjust the capacitance of the first adjustment circuit 5.
所述第一保护电阻R11用来在所述第一开关Q11断开时维持所述第一可调电容C11与所述第一开关Q11连接点电压与所述第一分压电阻R1和所述第二分压电阻R2之间的连接点电压相同，避免开关两端杂散电容产生泄露电流。The first protection resistor R11 is configured to maintain a connection point voltage between the first adjustable capacitor C11 and the first switch Q11 and the first voltage dividing resistor R1 and the first switch Q11 when the first switch Q11 is turned off. The voltage at the connection point between the second voltage dividing resistors R2 is the same, and the stray capacitance at both ends of the switch is prevented from generating a leakage current.
如图3所示，所述第二调节电路6包括：固定电容C21、多路复用器61和电阻网络62；所述固定电容C21的第一端与所述缓冲器1的输入端相连，所述固定电容C21的第二端与所述多路复用器61的输出端N3相连；所述电阻网络62的第一端与所述缓冲器1的输出端相连，所述电阻网络62的第二端接地，所述电阻网络62包括多个电阻，各个所述电阻依次串联；所述多路复用器61包括第一输入端和多个第二输入端，所述第一输入端接地，多个所述第二输入端按顺序与多个所述电阻的第一端一一对应。As shown in FIG. 3, the second adjusting circuit 6 includes a fixed capacitor C21, a multiplexer 61 and a resistor network 62. The first end of the fixed capacitor C21 is connected to the input end of the buffer 1. The second end of the fixed capacitor C21 is connected to the output terminal N3 of the multiplexer 61; the first end of the resistor network 62 is connected to the output end of the buffer 1, the resistor network 62 The second end is grounded, the resistor network 62 includes a plurality of resistors, each of the resistors being sequentially connected in series; the multiplexer 61 includes a first input terminal and a plurality of second input terminals, the first input terminal is grounded And the plurality of second input terminals are in one-to-one correspondence with the first ends of the plurality of resistors in sequence.
其中，所述多路复用器61包括第一输入端和多个第二输入端，所述第一输入端接地，多个所述第二输入端按顺序与多个所述电阻的第一端一一对应。通过控制多路复用器61的档位与输入端的连接状态，可以实现利用多个所述电阻对缓冲器1的输出进行平均分压，即可控制固定电容C21两端电压占分压点对地电压的比例，从而将固定电容C21模拟为可变电容。Wherein the multiplexer 61 includes a first input end and a plurality of second input ends, the first input end is grounded, and the plurality of the second input ends are sequentially and in sequence with the plurality of the resistors One-to-one correspondence. By controlling the connection state of the gear position and the input end of the multiplexer 61, it is possible to achieve an average voltage division of the output of the buffer 1 by using the plurality of the resistors, thereby controlling the voltage across the fixed capacitor C21. The ratio of the ground voltage is such that the fixed capacitor C21 is modeled as a variable capacitor.
其中，所述电阻网络62由多个电阻串联组成的分压电阻网络，整串电阻的两端，一端接地，另一端接要分压的信号源，多个所述电组的第一端为不同的抽头或者引出点，不同的抽头对应不同的分压比。The resistor network 62 is composed of a plurality of resistors in series. The two ends of the resistor are grounded at one end and the other end is connected to a signal source to be divided. The first ends of the plurality of groups are Different taps or lead points, different taps correspond to different partial pressure ratios.
例如，由5个电阻串联组成的分压电阻网络，0～5抽头分压比分别为 0/5、1/5、2/5、3/5、4/5、5/5，设信号电压为Vs，0～5抽头的输出电压分别为0、1/5Vs、2/5Vs、3/5Vs、4/5Vs、Vs。所述多路复用器选择其中一个抽头，即可得到一个分压比。For example, a voltage divider resistor network consisting of five resistors in series, the 0 to 5 tap divider ratios are 0/5, 1/5, 2/5, 3/5, 4/5, 5/5, set the signal voltage to Vs, the output voltage of 0~5 taps is 0, 1/5Vs, 2/5Vs, 3 /5Vs, 4/5Vs, Vs. The multiplexer selects one of the taps to obtain a voltage division ratio.
所述固定电容C21的容量≥第一调节电路中最低位电容的容量，以覆盖所述第一调节电路5最低位电容的误差，使调整能够平滑连续，通过控制所述多路复用器61的档位状态，改变连接的分压电阻网络62抽头位置，从而调整所述固定电容C21两端的电压，从而将固定电容C21模拟为可变电容。The capacity of the fixed capacitor C21 is ≥ the capacity of the lowest bit capacitance in the first adjustment circuit to cover the error of the lowest bit capacitance of the first adjustment circuit 5, so that the adjustment can be smoothly continuous, by controlling the multiplexer 61 In the gear state, the connected tapping resistor network 62 tap position is changed, thereby adjusting the voltage across the fixed capacitor C21, thereby simulating the fixed capacitor C21 as a variable capacitor.
如图3所示，所述处理器4包括：多个输出端，其中与所述第一调节电路5相对应的输出端通过开关控制线束L2分别与所述第一调节电路5内的每一个开关的控制端相连，与所述第二调节电路6相对应的输出端通过多路复用器控制线束L1与所述第二调节电路6内多路复用器61的地址输入端相连。As shown in FIG. 3, the processor 4 includes: a plurality of outputs, wherein an output corresponding to the first adjustment circuit 5 passes through each of the first adjustment circuits 5 through the switch control harness L2 The control terminals of the switches are connected, and the output terminals corresponding to the second regulating circuit 6 are connected to the address inputs of the multiplexers 61 in the second regulating circuit 6 via the multiplexer control harness L1.
如图4所示，所述处理器4包括：As shown in FIG. 4, the processor 4 includes:
第一分析单元41，所述第一分析单元用于接收幅值相同的低频和高频数字信号，测量低频和高频信号的幅值，比较分析所述高频信号的幅值与所述低频信号幅值的差值。a first analyzing unit 41, configured to receive low frequency and high frequency digital signals of the same amplitude, measure amplitudes of low frequency and high frequency signals, compare and analyze amplitudes of the high frequency signals and the low frequency The difference in signal amplitude.
如图4所示，所述处理器4包括：As shown in FIG. 4, the processor 4 includes:
第二分析单元42，所述第二分析单元用于对接收的数字信号进行FFT分析，获取所述数字信号的基波和各次谐波的幅值和相位比例信息，依据所述比例信息与所述数字信号预先通过理论FFT计算的比例信息进行比较分析。a second analyzing unit 42, configured to perform FFT analysis on the received digital signal, acquire amplitude and phase ratio information of a fundamental wave and each harmonic of the digital signal, according to the ratio information and The digital signal is previously compared and analyzed by the ratio information calculated by the theoretical FFT.
其中，在进行分压电容的自动调整时，所述处理器有2种调整方案，其中一种是所述处理器4的第一分析单元41分别接收经模拟数字转换器3输出的幅值相同的低频和高频信号，处理器4先测量低频信号的幅值，再测量输出的高频信号幅值，比较分析所述高频信号的幅值与所述低频信号幅值的差值，采用递进的方式，通过开关控制线束L2发送控制信号到所述第一调节电路5内每个支路上的开关的控制端，以调整所述第一调节电 路5内的开关状态，对第一调节电路5的等效电容值进行粗调；通过多路复用器控制线束L1发送控制信号至所述多路复用器的地址输入端，所述多路复用器解析所述控制信号，选择其中一个输入端对应的数据进行输出，即所述第二调节电路6内的多路复用器61档位与其中一个输入端相连，通过控制多路复用器的档位，即可控制固定电容两端电压占分压点对地电压的比例，从而改变流过固定电容的电流，将固定电容模拟为可变电容，通过第一调节电路5和第二调节电路6的配合，实现上下阻容时间常数的自动匹配，使R1×C1＝R2×C2，所述总下分压电容C2包括：第一调节电路等效电容、第二调节电路固定电容和缓冲器输入电容和杂散电容，使最终高频信号幅值与低频信号差异最小，此时即为匹配状态，所述处理器4同时记录所述高频与低频信号幅值匹配状态下的第一调节电路5内每条支路上的开关状态和所述第二调节电路6的多路复用器61的档位状态，每一次开机都按照这个码配置第一调节电路5的开关状态和所述第二调节电路6的多路复用器61档位状态。In the automatic adjustment of the voltage dividing capacitor, the processor has two adjustment schemes, one of which is that the first analyzing unit 41 of the processor 4 receives the same amplitude output by the analog-to-digital converter 3 respectively. The low frequency and high frequency signals, the processor 4 first measures the amplitude of the low frequency signal, and then measures the amplitude of the output high frequency signal, and compares and analyzes the difference between the amplitude of the high frequency signal and the amplitude of the low frequency signal, In a progressive manner, a control signal is sent to the control terminal of the switch on each branch in the first regulating circuit 5 through the switch control harness L2 to adjust the first regulated power a switching state in the way 5, coarsely adjusting the equivalent capacitance value of the first regulating circuit 5; transmitting a control signal to the address input end of the multiplexer through the multiplexer control harness L1, the plurality The multiplexer parses the control signal and selects data corresponding to one of the input terminals for output, that is, the multiplexer 61 gear position in the second adjustment circuit 6 is connected to one of the input terminals, and the multi-channel is controlled. The position of the multiplexer can control the ratio of the voltage across the fixed capacitor to the voltage of the divided voltage to ground, thereby changing the current flowing through the fixed capacitor, and simulating the fixed capacitor as a variable capacitor, through the first regulating circuit 5 and The second adjusting circuit 6 cooperates to realize automatic matching of the upper and lower RC time constants, so that R1×C1=R2×C2, the total lower divided capacitor C2 includes: the first adjusting circuit equivalent capacitance and the second adjusting circuit fixed The capacitance and the buffer input capacitance and the stray capacitance minimize the difference between the final high-frequency signal amplitude and the low-frequency signal, that is, the matching state, and the processor 4 simultaneously records the high-frequency and low-frequency signal amplitude matching states. First Adjusting the switching state of each branch in the circuit 5 and the gear state of the multiplexer 61 of the second regulating circuit 6, the switching state of the first regulating circuit 5 and the said The multiplexer 61 of the second regulating circuit 6 has a gear state.
另一种调整方案是所述处理器4的第二分析单元42对经过分压衰减、缓冲器1、信号调理器2、模拟-数字转换器3转换后的输入方波信号进行FFT分析，其中信号调理器2用于将输入信号调整到满足模拟-数字转换器3输入电压范围的信号，模拟-数字转换器3用于将其输入信号换成为数字信号，处理器4对数字信号模拟-数字转换器3采样值进行FFT分析，得到输入方波信号的基波和各次谐波的幅值和相位信息。由于方波信号可以通过FFT运算分解为基波及其各次谐波叠加而成，幅值和周期不变则基波和各次谐波幅值比例也保持不变，根据这个特征，对模拟-数字转换器3转换的数字信号进行FFT求出基波和各次谐波比例，与输入方波信号理论计算的比例对比。根据比对结果，通过控制线束调整第一调节电路的开关状态和第二调节电路的多路复用器档位状态，使最终模拟-数字转换器3转换的数字信号的基波和各次谐波比例最接近对输入方波进行理论分解时的情况，此时开关状态即为匹配状态，处理器4记录此匹配状态下的第一调节电路5的开关状态和所述第二调节电路6的多路复用器61档位状态，每一 次开机都按照这个码配置第一调节电路5开关和所述第二调节电路6的多路复用器61档位。Another adjustment scheme is that the second analyzing unit 42 of the processor 4 performs FFT analysis on the input square wave signal converted by the voltage division attenuation, the buffer 1, the signal conditioner 2, and the analog-to-digital converter 3. The signal conditioner 2 is for adjusting the input signal to a signal satisfying the input voltage range of the analog-to-digital converter 3, the analog-to-digital converter 3 for converting its input signal into a digital signal, and the processor 4 for analogizing the digital signal to the digital signal The sampled value of the converter 3 is subjected to FFT analysis to obtain the amplitude and phase information of the fundamental wave and each harmonic of the input square wave signal. Since the square wave signal can be decomposed into the fundamental wave and its harmonics by FFT operation, the amplitude and period of the fundamental wave and the harmonic amplitude ratio remain unchanged. According to this feature, the simulation is performed. The digital signal converted by the digitizer 3 is subjected to FFT to find the ratio of the fundamental wave and each harmonic, which is compared with the theoretical calculation of the input square wave signal. According to the comparison result, the fundamental state and each harmonic of the digital signal converted by the final analog-to-digital converter 3 are adjusted by controlling the wiring harness to adjust the switching state of the first regulating circuit and the multiplexer gear state of the second regulating circuit. The wave ratio is closest to the case when the input square wave is theoretically decomposed. At this time, the switching state is the matching state, and the processor 4 records the switching state of the first adjusting circuit 5 in the matching state and the second adjusting circuit 6 Multiplexer 61 gear status, each The first adjustment circuit 5 switch and the multiplexer 61 position of the second adjustment circuit 6 are configured in accordance with this code.
通过本发明实施例二中的具体实施方式的描述，所述处理器4通过接收经所述信号调理器2以及所述模拟-数字转换器3转换后的数字信号，通过所述第一分析单元或者所述第二分析单元对接收的所述数字信号进行分析，同时将分析结果通过控制线束L2发送给所述第一调节电路5内每个开关的控制端以及通过控制线束L1发送给所述第二调节电路6内多路复用器61的地址输入端，从而有效的调整所述第一调节电路5内每个开关的断开与闭合状态，以实现可调电容的投入或切断，从而改变所述第一调节电路5的等效电容；以及调整所述第二调节电路6内多路复用器61的档位连接状态，改变连接的分压电阻网络62抽头位置，从而调整所述固定电容C21两端的电压，使固定电容C21模拟成可调电容，使上下分压电容达到匹配。通过程控可以实现上下分压阻容时间常数匹配的自动调整，得到平坦的幅频特性，提高生产效率，同时由于无机械电容可调器件，避免了振动对分压电容稳定性的影响。Through the description of the specific embodiment in the second embodiment of the present invention, the processor 4 passes the first analysis unit by receiving the digital signal converted by the signal conditioner 2 and the analog-to-digital converter 3. Or the second analyzing unit analyzes the received digital signal, and sends the analysis result to the control end of each switch in the first adjusting circuit 5 through the control harness L2 and sends the same to the control through the control harness L1. An address input end of the multiplexer 61 in the second adjusting circuit 6, thereby effectively adjusting an open and closed state of each switch in the first adjusting circuit 5, so as to realize input or cutoff of the adjustable capacitor, thereby Changing the equivalent capacitance of the first adjustment circuit 5; and adjusting the gear connection state of the multiplexer 61 in the second adjustment circuit 6, changing the tap position of the connected voltage dividing resistor network 62, thereby adjusting the The voltage across the fixed capacitor C21 is such that the fixed capacitor C21 is simulated as a tunable capacitor to match the upper and lower voltage divider capacitors. The program control can realize the automatic adjustment of the upper and lower voltage division resistance time constant matching, obtain the flat amplitude frequency characteristic, improve the production efficiency, and at the same time avoid the influence of vibration on the stability of the voltage dividing capacitor because there is no mechanical capacitance adjustable device.
本发明还提供了一种电压测量装置的具体实施方式，该电压测量装置包括：上述所述可调电路装置。The present invention also provides a specific embodiment of a voltage measuring device comprising: the tunable circuit device described above.
其中，所述电压测量装置可以为一切测量直流、交流或交直流混合信号的电压测量装置，如示波器；或者所述电压测量装置中的某一模块用于测量上述电压信号，如多用表、功率计、功率分析仪等。Wherein, the voltage measuring device can be any voltage measuring device for measuring DC, AC or AC/DC mixed signals, such as an oscilloscope; or a module of the voltage measuring device is used for measuring the above voltage signal, such as a multimeter, power Meter, power analyzer, etc.
其中，所述电压测量装置可以是按照采样原理，利用模拟-数字转换器3变换，将连续的模拟信号转变成离散的数字序列，然后进行恢复重建波形，从而达到测量波形的目的。Wherein, the voltage measuring device may convert the continuous analog signal into a discrete digital sequence by using an analog-to-digital converter 3 according to a sampling principle, and then recover and reconstruct the waveform, thereby achieving the purpose of measuring the waveform.
所述缓冲器1用于对接收的输入信号作缓冲变换，起到将被测体与所述电压测量装置隔离的作用，电压测量装置工作状态的变换不会影响输入信号，同时将信号的幅值切换至适当的电平范围，即电压测量装置可以处理的范围，也就是说不同幅值的信号在通过输入缓冲放大器后都会转变成相同电压范围内的信号； The buffer 1 is used for buffering the received input signal to isolate the measured object from the voltage measuring device. The change of the operating state of the voltage measuring device does not affect the input signal, and the amplitude of the signal is The value is switched to the appropriate level range, ie the range that the voltage measuring device can handle, that is to say the signals of different amplitudes are converted into signals in the same voltage range after passing through the input buffer amplifier;
所述信号调理器2，用于对所述缓冲器1的输出待测模拟信号调理到适合模拟数字转换器3转换的范围；The signal conditioner 2 is configured to modulate an output analog signal to be tested of the buffer 1 to a range suitable for conversion by the analog to digital converter 3;
所述模拟数字转换器3，用于将所述信号调理器2输出的连续模拟信号转变为离散的数字序列，然后按照数字序列的先后顺序重建波形，所述模拟数字转换器3起到一个采样的作用，它在采样时钟的作用下，将采样脉冲到来时刻的信号幅值的大小转化为数字表示的数值，这个点称为采样点；The analog-to-digital converter 3 is configured to convert a continuous analog signal output by the signal conditioner 2 into a discrete digital sequence, and then reconstruct a waveform according to a sequence of digital sequences, the analog-to-digital converter 3 serving as a sampling The role of the sampling clock, the amplitude of the signal at the moment of arrival of the sampling pulse is converted into a numerical value, this point is called the sampling point;
所述处理器4通过接收所述模拟-数字转换器3转换后的数字信号，并按照预先设置的规则对接收的所述数字信号进行分析，同时将分析结果通过控制线束L2发送给所述第一调节电路5内每个开关的控制端以及通过控制线束L1发送给所述第二调节电路6内多路复用器61的地址输入端，可以控制所述第一调节电路5内每个开关的断开与闭合状态，以实现可调电容的投入或切断，从而调整所述第一调节电路5的等效电容；以及控制所述第二调节电路6内多路复用器61的档位连接状态，改变连接的分压电阻网络62抽头位置，从而调整所述固定电容C21两端的电压，使固定电容C21模拟成可调电容，通过程控可以实现上下分压阻容时间常数匹配的自动调整，得到平坦的幅频特性。The processor 4 receives the digital signal converted by the analog-to-digital converter 3, and analyzes the received digital signal according to a preset rule, and sends the analysis result to the first through the control harness L2. The control terminal of each switch in the adjusting circuit 5 and the address input terminal of the multiplexer 61 in the second adjusting circuit 6 are controlled by the control harness L1, and each switch in the first adjusting circuit 5 can be controlled. Disconnected and closed state to achieve input or cutoff of the adjustable capacitance, thereby adjusting the equivalent capacitance of the first regulating circuit 5; and controlling the gear position of the multiplexer 61 in the second regulating circuit 6 The connection state changes the tap position of the connected voltage divider resistor network 62, thereby adjusting the voltage across the fixed capacitor C21, so that the fixed capacitor C21 is simulated as a tunable capacitor, and the process control can realize the automatic adjustment of the upper and lower voltage division resistance time constant matching. , to obtain a flat amplitude frequency characteristic.
所述电压测量装置通过采用该可调电路装置作为其内部电路结构，可以实现上下分压阻容时间常数匹配的自动调整，得到平坦的幅频特性，同时保证了高频信号数据测量的准确性，有效避免了测量误差。The voltage measuring device adopts the adjustable circuit device as its internal circuit structure, can realize automatic adjustment of upper and lower voltage-dividing resistance-capacitance time constant matching, obtains flat amplitude-frequency characteristics, and ensures accuracy of high-frequency signal data measurement. , effectively avoiding measurement errors.
本说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分互相参见即可。对于实施例公开的装置而言，由于其与实施例公开的方法相对应，所以描述的比较简单，相关之处参见方法部分说明即可。The various embodiments in the present specification are described in a progressive manner, and each embodiment focuses on differences from other embodiments, and the same similar parts between the various embodiments may be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.
另外需说明的是，以上所描述的装置实施例仅仅是示意性的，其中所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或 者全部单元来实现本实施例方案的目的。另外，本发明提供的装置实施例附图中，单元之间的连接关系表示它们之间具有通信连接，具体可以实现为一条或多条通信总线或信号线。本领域普通技术人员在不付出创造性劳动的情况下，即可以理解并实施。It should be further noted that the device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be Physical units can be located in one place or distributed to multiple network elements. You can choose some of them according to actual needs or All units are used to achieve the objectives of the solution of this embodiment. In addition, in the drawings of the device embodiments provided by the present invention, the connection relationship between the units indicates that there is a communication connection between them, and specifically may be implemented as one or more communication buses or signal lines. Those of ordinary skill in the art can understand and implement without any creative effort.
综上所述，以上实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照上述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对上述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围。 In conclusion, the above embodiments are only used to explain the technical solutions of the present invention, and are not limited thereto; although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still The technical solutions described in the above embodiments are modified, or equivalent to some of the technical features are included; and the modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims (10)

  1. 一种可调电路装置，其特征在于，包括：第一信号输入端(N1)、第二信号输入端(N2)、第一分压电阻(R1)、第二分压电阻(R2)、第一分压电容(C1)、缓冲器输入电容(Cin)、杂散电容(C2')、缓冲器(1)、第一调节电路(5)、第二调节电路(6)、信号调理器(2)、模拟-数字转换器(3)和处理器(4)；A tunable circuit device, comprising: a first signal input terminal (N1), a second signal input terminal (N2), a first voltage dividing resistor (R1), a second voltage dividing resistor (R2), a divided capacitor (C1), a buffer input capacitor (Cin), a stray capacitance (C2'), a buffer (1), a first regulating circuit (5), a second regulating circuit (6), a signal conditioner ( 2) analog-to-digital converter (3) and processor (4);
    所述第一调节电路(5)的第一端与所述缓冲器(1)的输入端相连，所述第一调节电路(5)的第二端与所述缓冲器(1)的输出端相连，所述第一调节电路(5)的第三端接地；a first end of the first regulating circuit (5) is connected to an input end of the buffer (1), a second end of the first regulating circuit (5) and an output end of the buffer (1) Connected, the third end of the first regulating circuit (5) is grounded;
    所述第二调节电路(6)的第一端与所述缓冲器(1)的输入端相连，所述第二调节电路(6)的第二端与所述缓冲器(1)的输出端相连，所述第二调节电路(6)的第三端接地；a first end of the second regulating circuit (6) is connected to an input end of the buffer (1), a second end of the second regulating circuit (6) and an output end of the buffer (1) Connected, the third end of the second regulating circuit (6) is grounded;
    所述缓冲器(1)的输出端依次通过所述信号调理器(2)和所述模拟-数字转换器(3)与所述处理器(4)的输入端相连；An output end of the buffer (1) is sequentially connected to an input end of the processor (4) through the signal conditioner (2) and the analog-to-digital converter (3);
    所述信号调理器(2)对所述缓冲器(1)的输出信号进行调理，并将调理后的信号发送到所述模拟-数字转换器(3)，所述模拟-数字转换器(3)对接收的信号进行数字转换，并将转换后的数字信号发送到所述处理器(4)，所述处理器(4)按照预先设置的规则对接收的所述数字信号进行分析，并将分析结果通过控制线束(L2)发送给所述第一调节电路(5)内每个开关的控制端以及通过控制线束(L1)发送给所述第二调节电路(6)内多路复用器(61)的地址输入端。The signal conditioner (2) modulates an output signal of the buffer (1) and transmits the conditioned signal to the analog-to-digital converter (3), the analog-to-digital converter (3) Transmitting the received signal digitally and transmitting the converted digital signal to the processor (4), the processor (4) analyzing the received digital signal according to a preset rule, and The analysis result is sent to the control terminal of each switch in the first regulating circuit (5) through the control harness (L2) and to the multiplexer in the second regulating circuit (6) through the control harness (L1) Address input of (61).
  2. 根据权利要求1所述的装置，其特征在于，所述第一调节电路(5)包括：多个结构相同的支路，各个所述支路相互并联，其中每个所述支路包括：第一电容(C11)、第一开关(Q11)和第一保护电阻(R11)，所述第一电容(C11)的第一端与所述缓冲器(1)的输入端相连，所述第一电容(C11)的第二端与所述第一开关(Q11)的第一端相连，所述第一开关(Q11)的第二端接地，所述第一电容(C11)与所述第一开关(Q11)之间的连接点通过所述第一保护电阻(R11)与所述缓冲器(1)的输出端相 连。The apparatus according to claim 1, wherein said first regulating circuit (5) comprises: a plurality of identically configured branches, each of said branches being connected in parallel with each other, wherein each of said branches comprises: a capacitor (C11), a first switch (Q11) and a first protection resistor (R11), the first end of the first capacitor (C11) being connected to an input end of the buffer (1), the first a second end of the capacitor (C11) is connected to the first end of the first switch (Q11), a second end of the first switch (Q11) is grounded, and the first capacitor (C11) is connected to the first a connection point between the switches (Q11) and the output end of the buffer (1) through the first protection resistor (R11) even.
  3. 根据权利要求1所述的装置，其特征在于，所述第二调节电路(6)包括：固定电容(C21)、多路复用器(61)和电阻网络(62)；所述固定电容(C21)的第一端与所述缓冲器(1)的输入端相连，所述固定电容(C21)的第二端与所述多路复用器(61)的输出端(N3)相连；所述电阻网络(62)的第一端与所述缓冲器(1)的输出端相连，所述电阻网络(62)的第二端接地，所述电阻网络(62)包括多个电阻，各个所述电阻依次串联；所述多路复用器(61)包括第一输入端和多个第二输入端，所述第一输入端接地，多个所述第二输入端按顺序与多个所述电阻的第一端一一对应。The apparatus according to claim 1, wherein said second regulating circuit (6) comprises: a fixed capacitor (C21), a multiplexer (61), and a resistor network (62); said fixed capacitor ( a first end of C21) is connected to an input end of said buffer (1), and a second end of said fixed capacitor (C21) is connected to an output end (N3) of said multiplexer (61); A first end of the resistor network (62) is coupled to an output of the buffer (1), a second end of the resistor network (62) is coupled to ground, and the resistor network (62) includes a plurality of resistors, each The resistors are connected in series; the multiplexer (61) includes a first input end and a plurality of second input ends, the first input end is grounded, and the plurality of second input ends are sequentially connected to the plurality of The first ends of the resistors are in one-to-one correspondence.
  4. 根据权利要求1所述的装置，其特征在于，所述处理器(4)包括：多个输出端，其中与所述第一调节电路(5)相对应的输出端通过开关控制线束(L2)分别与所述第一调节电路(5)内的每一个开关的控制端相连，与所述第二调节电路(6)相对应的输出端通过多路复用器控制线束(L1)与所述第二调节电路(6)内多路复用器(61)的地址输入端相连。The apparatus according to claim 1, characterized in that said processor (4) comprises: a plurality of outputs, wherein an output corresponding to said first regulating circuit (5) controls a wiring harness (L2) through a switch Connected to the control terminals of each of the switches in the first regulating circuit (5), respectively, and the output terminal corresponding to the second regulating circuit (6) controls the wire harness (L1) through the multiplexer The address inputs of the multiplexer (61) in the second regulating circuit (6) are connected.
  5. 根据权利要求2所述的装置，其特征在于，所述第一调节电路(5)内每条支路上电容的容量按照二进制依次递增。The device according to claim 2, characterized in that the capacity of the capacitance of each branch in the first regulating circuit (5) is increased in binary order.
  6. 根据权利要求2所述的装置，其特征在于，所述第一调节电路(5)内每条支路上的开关为机械继电器、低电容光继电器或者结型场效应管。The device according to claim 2, characterized in that the switch on each branch in the first regulating circuit (5) is a mechanical relay, a low capacitance photorelay or a junction field effect transistor.
  7. 根据权利要求2所述的装置，其特征在于，所述第一调节电路(5)内每条支路上电容的电极为电路板覆铜，电介质为板基材；或者所述第一调节电路(5)内每条支路上的电容为固定电容器。The device according to claim 2, wherein the electrode of each of the branches in the first regulating circuit (5) is a circuit board copper, the dielectric is a board substrate; or the first regulating circuit ( 5) The capacitance on each branch is a fixed capacitor.
  8. 根据权利要求1所述的装置，其特征在于，所述处理器(4)包括：第一分析单元(41)，所述第一分析单元(41)用于接收幅值相同的低频和高频数字信号，测量低频和高频信号的幅值，比较分析所述高频信号的幅值与所述低频信号幅值的差值。The apparatus according to claim 1, characterized in that said processor (4) comprises: a first analysis unit (41) for receiving low frequency and high frequency of the same amplitude The digital signal measures the amplitudes of the low frequency and high frequency signals, and compares and analyzes the difference between the amplitude of the high frequency signal and the amplitude of the low frequency signal.
  9. 根据权利要求1所述的装置，其特征在于，所述处理器(4)包括：第二分析单元(42)，所述第二分析单元(42)用于对接收的数字信号进行FFT分析，获取所述数字信号的基波和各次谐波的幅值和相位比例信息， 依据所述比例信息与所述数字信号预先通过理论FFT计算的比例信息进行比较分析。The apparatus according to claim 1, wherein said processor (4) comprises: a second analyzing unit (42), said second analyzing unit (42) for performing FFT analysis on the received digital signal, Obtaining amplitude and phase ratio information of a fundamental wave and each harmonic of the digital signal, And comparing and analyzing the proportional information and the digital signal calculated by the theoretical FFT in advance according to the proportional information.
  10. 一种电压测量装置，其特征在于，包括如权利要求1至9任意一项所述可调电路装置。 A voltage measuring device comprising the adjustable circuit device according to any one of claims 1 to 9.
PCT/CN2017/076396 2016-08-15 2017-03-13 Adjustable circuit device and voltage measuring device WO2018032754A1 (en)

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CN201620880722.5U CN206208961U (en) 2016-08-15 2016-08-15 A kind of conditioned circuit device
CN201610667922.7A CN106353549B (en) 2016-08-15 2016-08-15 A kind of conditioned circuit device and voltage measuring apparatus
CN201610667922.7 2016-08-15

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