WO2017206268A1 - 一种显示面板及其栅极驱动电路 - Google Patents

一种显示面板及其栅极驱动电路 Download PDF

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Publication number
WO2017206268A1
WO2017206268A1 PCT/CN2016/089600 CN2016089600W WO2017206268A1 WO 2017206268 A1 WO2017206268 A1 WO 2017206268A1 CN 2016089600 W CN2016089600 W CN 2016089600W WO 2017206268 A1 WO2017206268 A1 WO 2017206268A1
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WIPO (PCT)
Prior art keywords
thin film
film transistor
signal
gate driving
pull control
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Application number
PCT/CN2016/089600
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English (en)
French (fr)
Inventor
杜鹏
Original Assignee
深圳市华星光电技术有限公司
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Priority to US15/118,882 priority Critical patent/US10460687B2/en
Publication of WO2017206268A1 publication Critical patent/WO2017206268A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present invention relates to the field of liquid crystal display technologies, and in particular, to a display panel and a gate driving circuit thereof.
  • Array substrate row driver (GOA, Gate Driver On Array or Gate On The Array) circuit is formed by using a conventional thin film transistor display device (TFT-LCD) array (Array) process to form a gate line scan driving signal circuit on the array substrate to realize a progressive scanning operation on the gate line.
  • TFT-LCD thin film transistor display device
  • Array gate line scan driving signal circuit on the array substrate to realize a progressive scanning operation on the gate line.
  • COF flexible circuit board
  • COG glass circuit board
  • each level of GOA circuit is designed with a corresponding auxiliary pull-down circuit, usually two sets of auxiliary pull-down circuits.
  • the two sets of auxiliary pull-down circuits work alternately in different time periods to match the Q point and the gate in the GOA circuit.
  • the drive signal is pulled down.
  • the auxiliary pull-down circuit includes two switching frequencies, one switching frequency is the same as the frequency of the clock signal, and the other switching frequency is switched every time of several frames. If the switching frequency is the same as the frequency of the clock signal, the thin film transistor of the GOA circuit receives the high frequency pressure; if the switching frequency is switched every time for several frames, the thin film transistor of the GOA circuit receives the low frequency pressure, resulting in GOA The circuit is working abnormally.
  • the technical problem to be solved by the present invention is to provide a display panel and a gate driving circuit thereof to solve the above problems.
  • the present invention provides a gate driving circuit including a multi-level gate driving unit, and each stage of the gate driving unit includes:
  • a first pull control unit configured to output a first pull control signal at the first node
  • the first pull unit is coupled to the first node, receives the first clock signal, generates a gate drive signal according to the first pull control signal and the first clock signal, and outputs a gate drive signal to the gate drive signal output end;
  • a second pull control unit configured to receive the first signal, the second signal, the third signal, and the fourth signal, and output a second pull control signal according to the first signal, the second signal, the third signal, and the fourth signal;
  • a second pull unit coupled to the first node and the gate drive signal output end, receiving the second pull control signal, and pulling the level of the first node and the level of the gate drive signal output end according to the second pull control signal;
  • the frequency of the second pull control signal is smaller than the frequency of the first clock signal, and is greater than the refresh frequency of the display panel, and the second pull control signal is a square wave pulse control signal;
  • the first signal is a second clock signal, and the ratio of the frequency of the second clock signal to the frequency of the first clock signal ranges from 2 to 50.
  • the frequency of the second clock signal is four times the frequency of the first clock signal
  • the third signal is the second signal of the gate driving unit of the first two stages
  • the fourth signal is the number of the gate driving unit of the last two stages Two signals.
  • the present invention also provides a gate driving circuit comprising a multi-level gate driving unit, each stage of the gate driving unit comprising:
  • a first pull control unit configured to output a first pull control signal at the first node
  • the first pull unit is coupled to the first node, receives the first clock signal, generates a gate drive signal according to the first pull control signal and the first clock signal, and outputs a gate drive signal to the gate drive signal output end;
  • a second pull control unit configured to receive the first signal, the second signal, the third signal, and the fourth signal, and output a second pull control signal according to the first signal, the second signal, the third signal, and the fourth signal;
  • a second pull unit coupled to the first node and the gate drive signal output end, receiving the second pull control signal, and pulling the level of the first node and the level of the gate drive signal output end according to the second pull control signal;
  • the frequency of the second pull control signal is smaller than the frequency of the first clock signal and greater than the refresh frequency of the display panel.
  • the second pull control signal is a square wave pulse control signal.
  • the first signal is a second clock signal, and the ratio of the frequency of the second clock signal to the frequency of the first clock signal ranges from 2 to 50.
  • the frequency of the second clock signal is four times the frequency of the first clock signal
  • the third signal is the second signal of the gate driving unit of the first two stages
  • the fourth signal is the number of the gate driving unit of the last two stages Two signals.
  • the frequency of the second clock signal is twice the frequency of the first clock signal
  • the third signal is the second signal of the gate driving unit of the first four stages
  • the fourth signal is the number of the gate driving unit of the last four stages Two signals.
  • the first pull control unit includes a first thin film transistor, the first end of the first thin film transistor receives the first reference voltage, and the second end of the first thin film transistor receives the gate drive signal of the first two stages of the gate drive unit, The third end of the first thin film transistor is connected to the first node.
  • the first pull unit includes a second thin film transistor and a capacitor, the first end of the second thin film transistor receives the first clock signal, the second end of the second thin film transistor is connected to the first node, and the third end of the second thin film transistor is At the gate drive signal output end, one end of the capacitor is connected to the first node, and the other end of the capacitor is connected to the third end of the second thin film transistor.
  • the second pull control unit includes a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a seventh thin film transistor, an eighth thin film transistor, a ninth thin film transistor, a tenth thin film transistor, and a tenth a thin film transistor, a twelfth thin film transistor, and a thirteenth thin film transistor, the first end of the third thin film transistor and the first end of the fourth thin film transistor receive the first reference voltage, and the second end of the third thin film transistor receives the third a signal, the second end of the fourth thin film transistor receives the second signal, the third end of the third thin film transistor and the third end of the fourth thin film transistor and the first end of the fifth thin film transistor, and the second end of the seventh thin film transistor Connected to the second end of the eighth thin film transistor, the second end of the fifth thin film transistor and the second end of the twelfth thin film transistor receive the fourth signal, and the second end of the thirteenth thin film transistor is connected to the gate driving signal output
  • the second pull unit includes a fourteenth thin film transistor, a fifteenth thin film transistor, a sixteenth thin film transistor, and a seventeenth thin film transistor.
  • the first end of the fourteenth thin film transistor is connected to the first node, and the fourteenth thin film transistor
  • the second end and the second end of the fifteenth thin film transistor are connected to the third end of the eleventh thin film transistor, the third end of the fourteenth thin film transistor, the third end of the fifteenth thin film transistor, and the sixteenth thin film transistor
  • the third end and the third end of the seventeenth thin film transistor receive the second reference voltage
  • the first end of the fifteenth thin film transistor is connected to the gate driving signal output end
  • the first end of the sixteenth thin film transistor is connected to the first node a second end of the seventeenth thin film transistor and a second end of the eighteenth thin film transistor receive a gate driving signal of the gate driving unit of the second two stages, and the first end of the eighteenth thin film transistor is connected to the gate driving signal output end.
  • the present invention also provides a display panel including a gate driving circuit, the gate driving circuit includes a multi-level gate driving unit, and each stage of the gate driving unit includes:
  • a first pull control unit configured to output a first pull control signal at the first node
  • the first pull unit is coupled to the first node, receives the first clock signal, generates a gate drive signal according to the first pull control signal and the first clock signal, and outputs a gate drive signal to the gate drive signal output end;
  • a second pull control unit configured to receive the first signal, the second signal, the third signal, and the fourth signal, and output a second pull control signal according to the first signal, the second signal, the third signal, and the fourth signal;
  • a second pull unit coupled to the first node and the gate drive signal output end, receiving the second pull control signal, and pulling the level of the first node and the level of the gate drive signal output end according to the second pull control signal;
  • the frequency of the second pull control signal is smaller than the frequency of the first clock signal and greater than the refresh frequency of the display panel.
  • the second pull control signal is a square wave pulse control signal.
  • the first signal is a second clock signal, and the ratio of the frequency of the second clock signal to the frequency of the first clock signal ranges from 2 to 50.
  • the frequency of the second clock signal is four times the frequency of the first clock signal
  • the third signal is the second signal of the gate driving unit of the first two stages
  • the fourth signal is the number of the gate driving unit of the last two stages Two signals.
  • the frequency of the second clock signal is twice the frequency of the first clock signal
  • the third signal is the second signal of the gate driving unit of the first four stages
  • the fourth signal is the number of the gate driving unit of the last four stages Two signals.
  • the first pull control unit includes a first thin film transistor, the first end of the first thin film transistor receives the first reference voltage, and the second end of the first thin film transistor receives the gate drive signal of the first two stages of the gate drive unit, The third end of the first thin film transistor is connected to the first node.
  • the first pull unit includes a second thin film transistor and a capacitor, the first end of the second thin film transistor receives the first clock signal, the second end of the second thin film transistor is connected to the first node, and the third end of the second thin film transistor is At the gate drive signal output end, one end of the capacitor is connected to the first node, and the other end of the capacitor is connected to the third end of the second thin film transistor.
  • the second pull control unit includes a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a seventh thin film transistor, an eighth thin film transistor, a ninth thin film transistor, a tenth thin film transistor, and a tenth a thin film transistor, a twelfth thin film transistor, and a thirteenth thin film transistor, the first end of the third thin film transistor and the first end of the fourth thin film transistor receive the first reference voltage, and the second end of the third thin film transistor receives the third a signal, the second end of the fourth thin film transistor receives the second signal, the third end of the third thin film transistor and the third end of the fourth thin film transistor and the first end of the fifth thin film transistor, and the second end of the seventh thin film transistor Connected to the second end of the eighth thin film transistor, the second end of the fifth thin film transistor and the second end of the twelfth thin film transistor receive the fourth signal, and the second end of the thirteenth thin film transistor is connected to the gate driving signal output
  • the second pull unit includes a fourteenth thin film transistor, a fifteenth thin film transistor, a sixteenth thin film transistor, and a seventeenth thin film transistor.
  • the first end of the fourteenth thin film transistor is connected to the first node, and the fourteenth thin film transistor
  • the second end and the second end of the fifteenth thin film transistor are connected to the third end of the eleventh thin film transistor, the third end of the fourteenth thin film transistor, the third end of the fifteenth thin film transistor, and the sixteenth thin film transistor
  • the third end and the third end of the seventeenth thin film transistor receive the second reference voltage
  • the first end of the fifteenth thin film transistor is connected to the gate driving signal output end
  • the first end of the sixteenth thin film transistor is connected to the first node a second end of the seventeenth thin film transistor and a second end of the eighteenth thin film transistor receive a gate driving signal of the gate driving unit of the second two stages, and the first end of the eighteenth thin film transistor is connected to the gate driving signal output end.
  • the first aspect of the present invention provides that the first pull control unit outputs a first pull control signal at the first node, and the first pull unit is coupled to the first The node receives the first clock signal, generates a gate driving signal according to the first pulling control signal and the first clock signal, and outputs a gate driving signal to the gate driving signal output end;
  • the second pulling control unit is configured to receive the first signal, The second signal, the third signal, and the fourth signal output a second pull control signal according to the first signal, the second signal, the third signal, and the fourth signal;
  • the second pull unit is coupled to the first node and the gate drive
  • the signal output end receives the second pull control signal, and pulls the level of the first node and the level of the output of the gate drive signal according to the second pull control signal; wherein the frequency of the second pull control signal is less than the frequency of the first clock signal, And larger than the refresh frequency of the display panel; can effectively prevent the drift of the thin film transistor characteristics of the gate driving unit, and improve the gate driving unit Depend.
  • FIG. 1 is a schematic structural view of a gate driving circuit according to a first embodiment of the present invention
  • FIG. 2 is a schematic structural view of the gate driving unit of FIG. 1;
  • FIG. 3 is a circuit diagram of a gate driving unit of a second embodiment of the present invention.
  • FIG. 4 is a timing diagram of the first clock signal and the gate driving signal of FIG. 3;
  • Figure 5 is a timing diagram of the second clock signal and the second signal of Figure 3;
  • Figure 6 is a circuit diagram of a gate driving unit of a third embodiment of the present invention.
  • Figure 7 is a timing diagram of the second clock signal and the second signal of Figure 6;
  • FIG. 8 is a schematic structural view of a display panel according to a first embodiment of the present invention.
  • Fig. 9 is a view showing the configuration of a liquid crystal display device of a first embodiment of the present invention.
  • FIG. 1 is a schematic structural diagram of a gate driving circuit according to a first embodiment of the present invention.
  • the gate driving circuit disclosed in this embodiment is applied to a display panel for driving a plurality of scanning lines of a liquid display panel to open a plurality of scanning lines.
  • the gate driving circuit 10 is connected to a plurality of scanning lines 20 for generating gate driving signals for driving a plurality of scanning lines 20.
  • the gate driving circuit 10 includes a multi-level gate driving unit 11 .
  • the first gate driving unit 11 corresponds to one scanning line 20 , and the output end of each stage of the gate driving unit 11 is connected to one scanning line 20 .
  • n is an integer greater than or equal to 1.
  • the nth stage gate driving unit 11 includes a first pull control unit 111, a first pull unit 112, a second pull control unit 113, and a second pull unit 114.
  • the first pull control unit 111 is configured to output a first pull control signal at the first node Qn.
  • the first pull unit 112 is coupled to the first node Qn, and the first pull unit 112 receives the first clock signal CK, and generates a gate drive signal Gn according to the first pull control signal and the first clock signal CK, and the gate drive signal output end
  • the gate drive signal Gn is output, that is, the gate drive signal output terminal of the first pull unit 112 outputs a gate drive signal Gn, and the gate drive signal Gn is used to drive the scan line 20.
  • the first pull unit 112 When the first pull control signal and the first clock signal CK are both at a high level, the first pull unit 112 generates the gate drive signal Gn according to the first pull control signal and the first clock signal CK to a high level.
  • the scanning line 20 corresponding to the n-stage gate driving unit 11 is turned on.
  • the second pull control unit 113 is configured to receive the first signal, the second signal, the third signal, and the fourth signal, and output a second pull control signal according to the first signal, the second signal, the third signal, and the fourth signal.
  • the second pull unit 114 is coupled to the first node Qn and the gate drive signal output end, receives the second pull control signal, and pulls the level of the first node Qn and the level of the gate drive signal output end according to the second pull control signal.
  • the second pull unit 114 pulls the level of the first node Qn and the level of the gate drive signal output to a low level according to the second pull control signal, and the nth stage gate
  • the scan line 20 corresponding to the pole drive unit 11 is turned on and off.
  • the frequency of the second pull control signal is smaller than the frequency of the first clock signal CK and greater than the refresh frequency of the display panel; the refresh frequency of the display panel is the number of times the display panel displays the image per second.
  • the second pull control unit 113 controls the frequency of the second pull control signal according to the first signal, the second signal, and the third signal, so that the frequency of the second pull control signal is smaller than the frequency of the first clock signal CK, and is greater than the display.
  • the refresh rate of the panel is controlled by the second pull control unit 113 according to the first signal, the second signal, and the third signal, so that the frequency of the second pull control signal is smaller than the frequency of the first clock signal CK, and is greater than the display.
  • This embodiment can effectively prevent the drift of the thin film transistor characteristics of the gate driving unit 11 and improve the reliability of the gate driving unit 11.
  • the present invention also provides a gate driving unit of the second embodiment, which is described on the basis of the gate driving unit 11 disclosed in the first embodiment.
  • the first pull control unit 111 includes a first thin film transistor T1.
  • the first end of the first thin film transistor T1 receives the first reference voltage VDD, and the second end of the first thin film transistor T1 receives the first two stages of the gate.
  • the gate driving signal Gn-2 of the pole driving unit 11 and the third end of the first thin film transistor T1 are connected to the first node Qn.
  • the first pull unit 112 includes a second thin film transistor T2 and a capacitor C.
  • the first end of the second thin film transistor T2 receives the first clock signal CK, and the second end of the second thin film transistor T2 is connected to the first node Qn, and the second thin film transistor
  • the third end of the T2 is a gate driving signal output terminal Gn for outputting the gate driving signal Gn; one end of the capacitor C is connected to the first node Qn, and the other end of the capacitor C is connected to the third end of the second thin film transistor T2.
  • the second pull control unit 113 includes a third thin film transistor T3, a fourth thin film transistor T4, a fifth thin film transistor T5, a sixth thin film transistor T6, a seventh thin film transistor T7, an eighth thin film transistor T8, and a ninth thin film transistor T9, a first thin film transistor T10, an eleventh thin film transistor T11, a twelfth thin film transistor T12, and a thirteenth thin film transistor T13, the first end of the third thin film transistor T3 and the first end of the fourth thin film transistor T4 receive the first reference voltage VDD, the second end of the third thin film transistor T3 receives the third signal, the second end of the fourth thin film transistor T4 receives the second signal, the third end of the third thin film transistor T3 and the third end of the fourth thin film transistor T4 The first end of the fifth thin film transistor T5, the second end of the seventh thin film transistor T7 and the second end of the eighth thin film transistor T8 are connected, the second end of the fifth thin film transistor T5 and the second end of the twelf
  • the second pull unit 114 includes a fourteenth thin film transistor T14, a fifteenth thin film transistor T15, a sixteenth thin film transistor T16, and a seventeenth thin film transistor T17.
  • the first end of the fourteenth thin film transistor T14 is connected to the first node
  • the second end of the fourteenth thin film transistor T14 and the second end of the fifteenth thin film transistor T15 are connected to the third end of the eleventh thin film transistor T11, the third end of the fourteenth thin film transistor T14, and the fifteenth thin film transistor T15
  • the third end, the third end of the sixteenth thin film transistor T16, and the third end of the seventeenth thin film transistor T17 receive the second reference voltage VSS, and the first end of the fifteenth thin film transistor T15 is connected to the gate driving signal output terminal Gn.
  • the first end of the sixteenth thin film transistor T16 is connected to the first node, and the second end of the seventeenth thin film transistor T17 and the second end of the eighteenth thin film transistor T18 receive the gate driving of the gate driving units of the latter two stages.
  • the signal Gn-2, the first end of the eighteenth thin film transistor T17 is connected to the gate driving signal output terminal Gn.
  • the second reference voltage VSS is at a low level.
  • the second pull control signal is a square wave pulse control signal.
  • the first signal is preferably a second clock signal CKH, wherein the ratio of the frequency of the second clock signal CKH to the frequency of the first clock signal CK ranges from 2 to 50.
  • the frequency of the second clock signal CKH is four times the frequency of the first clock signal CK.
  • the second signal is PDn
  • the third signal PDn-2 is the second signal of the gate driving unit of the first two stages
  • the fourth signal PDn+2 is the second signal of the gate driving unit of the last two stages, that is,
  • the second pull control unit 113 outputs a second pull control signal according to the second clock signal CKH, the second signal PDn, the third signal PDn-2, and the fourth signal PDn+2.
  • the operation of the gate driving unit will be described in detail in conjunction with the timing diagrams shown in FIGS. 4-5.
  • the gate driving signal Gn-2 of the gate driving unit of the first two stages when the gate driving signal Gn-2 of the gate driving unit of the first two stages is at a high level, the first thin film transistor T1 is turned on, and the third end of the first thin film transistor T1 is at the first node Qn.
  • the output first pull control signal is at a high level; the second thin film transistor T2 is turned on, and the gate drive signal Gn is the same as the first clock signal CK.
  • the gate driving signal Gn-2 of the first two stages of the gate driving unit When the gate driving signal Gn-2 of the first two stages of the gate driving unit is at a low level, the first thin film transistor T1 is turned off, and the third terminal of the first thin film transistor T1 does not output the first pulling control signal; The charging and discharging functions, the first node Qn is at a high level, the second thin film transistor T2 is turned on, and the gate driving signal Gn is the same as the first clock signal CK.
  • the sixteenth thin film transistor T16 and the seventeenth thin film transistor T17 are turned on, and the sixteenth thin film transistor T16 is to be the first node Qn.
  • the level is pulled from the high level to the low level, and the second thin film transistor T2 is turned off; the seventeenth thin film transistor T17 pulls the level of the gate drive signal Gn from the high level to the low level.
  • the third signal PDn-2 is at a high level
  • the second clock signal CKH is at a low level
  • the fourth signal PDn+2 is at a low level
  • the eighth thin film transistor T8, the tenth thin film transistor T10, and the eleventh thin film transistor T11 are all turned on.
  • the second signal PDn is the same as the second clock signal CKH, that is, the second signal PDn is at a low level; the fourth thin film transistor T4, the fifth thin film transistor T5, the ninth thin film transistor T9, and the twelfth thin film transistor T12 are all turned off, and the third end of the eleventh thin film transistor T11 outputs a second pull control signal to a low level.
  • the thirteenth thin film transistor T13 is turned off, and the fourteenth thin film transistor T14 and the fifteenth thin film transistor T15 are both turned off; when the gate driving signal Gn is at a high level, the tenth The three thin film transistors T13 are turned on, and the fourteenth thin film transistor T14 and the fifteenth thin film transistor T15 are both turned off.
  • the third thin film transistor T3 is turned off,
  • the fourth thin film transistor T4, the seventh thin film transistor T7, the eighth thin film transistor T8, the tenth thin film transistor T10, and the eleventh thin film transistor T11 are all turned on.
  • the second signal PDn is the same as the second clock signal CKH, that is, the second The signal PDn is at a high level; the fifth thin film transistor T5, the ninth thin film transistor T9, and the twelfth thin film transistor T12 are both turned off, and the third end of the eleventh thin film transistor T11 outputs a second pull control signal to a high level.
  • the gate driving signal Gn is at a low level, the thirteenth thin film transistor T13 is turned off, the fourteenth thin film transistor T14 and the fifteenth thin film transistor T15 are both turned on, and the fourteenth thin film transistor T14 pulls the electric power of the first node Qn.
  • the fifteenth thin film transistor T15 pulls the level of the gate driving signal output terminal Gn to a low level; when the gate driving signal Gn is at a high level, the thirteenth thin film transistor T13 is turned on, the tenth The four thin film transistors T14 and the fifteenth thin film transistor T15 are both turned off.
  • the third signal PDn-2 is at a low level
  • the second clock signal CKH is at a low level
  • the second signal PDn is at a low level
  • the fourth signal PDn+2 is at a high level
  • the transistor T4, the seventh thin film transistor T7, the eighth thin film transistor T8, the tenth thin film transistor T10, and the eleventh thin film transistor T11 are all turned off, and the fifth thin film transistor T5, the sixth thin film transistor T6, the ninth thin film transistor T9, and the The twelve thin film transistor T12 is turned on, and the third end of the eleventh thin film transistor T11 outputs a second pull control signal to a low level.
  • the thirteenth thin film transistor T13 is turned off, and the fourteenth thin film transistor T14 and the fifteenth thin film transistor T15 are both turned off; when the gate driving signal Gn is at a high level, the tenth The three thin film transistors T13 are turned on, and the fourteenth thin film transistor T14 and the fifteenth thin film transistor T15 are both turned off.
  • the thirteenth thin film transistor T13 is configured to ensure that the third pull control signal of the third end of the eleventh thin film transistor T11 is maintained at a low level when the gate drive signal Gn at the output end of the gate drive signal is at a high level.
  • the fourteen thin film transistor T14 and the fifteenth thin film transistor T15 are kept turned off to ensure the normal operation of the gate driving circuit 10.
  • the second signal PDn has a pulse width of w1.
  • the fourteenth thin film transistor T14 is used to pull down the first node Qn
  • the fifteenth thin film transistor T15 is used to pull down the gate driving signal Gn of the gate driving signal output end, tenth
  • the four thin film transistors T14 and the fifteenth thin film transistor T15 are turned on four times, that is, the fourteenth thin film transistor T14 pulls down the first node Qn four times, and the fifteenth thin film transistor T15 pulls down the gate driving signal Gn four times to ensure the gate.
  • the normal operation of the driving circuit 10 prevents the fourteenth thin film transistor T14 and the fifteenth thin film transistor T15 from being subjected to excessively high frequency or excessively low frequency, which can effectively prevent the drift of the thin film transistor characteristics of the gate driving unit and improve the gate driving.
  • the reliability of unit 11. Furthermore, by adjusting the frequency of the second clock signal CKH, the frequency of the second preferred pull control signal is obtained.
  • the present invention further provides a gate driving unit of the third embodiment, which is different from the gate driving unit disclosed in the second embodiment in that the frequency of the second clock signal CKH is twice the frequency of the first clock signal.
  • the second clock signal CKH uses eight clock signals.
  • the second signal is PDn
  • the third signal PDn-4 is the second signal of the first four stages of the gate driving unit
  • the fourth signal PDn+4 is the second of the last four stages of the gate driving unit. signal.
  • the pulse width w2 of the second signal PDn of the present embodiment is twice the pulse width w1 shown in FIG.
  • the power consumption of the gate driving unit of the present embodiment is reduced with respect to the gate driving unit disclosed in the second embodiment. Therefore, the number of the second clock signal CKH including the clock signal can be set according to actual conditions.
  • the second clock signal CKH includes 4, 6 or 8 clock signals, and the number of clock signals included in the second clock signal CKH is When h (h is an even number), the second pull control signal is controlled by the second clock signal CKH, the third signal P(nh/2), and the fourth signal P(n+h/2).
  • the second clock signal CKH includes the number of clock signals, the lower the frequency of the second clock signal CKH, the smaller the corresponding power consumption, and the gate drive circuit occupies more wiring space.
  • the frequency of the second clock signal CKH is higher, the corresponding power consumption is larger, and the wiring space occupied by the gate driving circuit is less, which is advantageous for the display design of the narrow frame. .
  • the present invention further provides a display panel.
  • the display panel 80 disclosed in this embodiment includes a gate driving circuit 81, and the gate driving circuit 81 is the gate driving circuit and the gate driving circuit of the above embodiment. 81 is used to drive the plurality of scanning lines 82 of the liquid display panel 80 to open the plurality of scanning lines 82, and details are not described herein again.
  • the present invention also provides a liquid crystal display device.
  • the liquid crystal display device disclosed in the embodiment includes a backlight module 91 and a display panel 92.
  • the display panel 92 is disposed above the light emitting surface of the backlight module 91.
  • the backlight module 91 is configured to provide a light source for the display panel 92.
  • the display panel 92 includes the gate driving circuit of the above embodiment, and the gate driving circuit is configured to drive a plurality of scanning lines of the liquid display panel 92 to enable a plurality of scanning lines. Open, no longer repeat them here.
  • each stage of the gate driving unit of the present invention includes a first pull control unit for outputting a first pull control signal at the first node, and a first pull unit coupled to the first node to receive the first clock.
  • a signal, a gate driving signal is generated according to the first pull control signal and the first clock signal, a gate drive signal output end outputs a gate drive signal
  • a second pull control unit is configured to receive the first signal, the second signal, and the third The signal and the fourth signal output a second pull control signal according to the first signal, the second signal, the third signal, and the fourth signal;
  • the second pull unit is coupled to the first node and the gate drive signal output end, and receives the first Pulling the control signal to pull the level of the first node and the level of the output of the gate driving signal according to the second pulling control signal; wherein, the frequency of the second pulling control signal is smaller than the frequency of the first clock signal, and is greater than the refresh of the display panel The frequency can effectively prevent the drift of the thin film transistor characteristics of the gate driving

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Abstract

一种显示面板（92）及其栅极驱动电路（10）。该栅极驱动电路（10）包括多级栅极驱动单元（11），每级栅极驱动单元（11）包括：第一拉动控制单元（111），用于在第一节点（Qn）输出第一拉动控制信号；第一拉动单元（112），根据第一拉动控制信号和第一时钟信号（CK）生成栅极驱动信号（Gn）；第二拉动控制单元（113），根据第一信号、第二信号、第三信号和第四信号输出第二拉动控制信号；第二拉动单元（114），根据第二拉动控制信号拉动第一节点（Qn）的电平和栅极驱动信号输出端的电平；其中第二拉动控制信号的频率小于第一时钟信号（CK）的频率，并且大于显示面板（92）的刷新频率。该栅极驱动电路（10）能够有效防止栅极驱动单元（11）的薄膜晶体管特性的漂移，提高栅极驱动单元（11）的信赖性。

Description

一种显示面板及其栅极驱动电路
【技术领域】
本发明涉及液晶显示技术领域，特别是涉及一种显示面板及其栅极驱动电路。
【背景技术】
阵列基板行驱动（GOA，Gate Driver On Array 或Gate On Array）电路，是利用现有薄膜晶体管显示装置（TFT-LCD）阵列（Array）制程将栅线（Gate）行扫描驱动信号电路制作在阵列基板上，以实现对栅线逐行扫描的驱动方式的一项技术。其与传统的柔性电路板（COF）和玻璃电路板（COG）工艺相比，不仅节省了制作成本，而且还可以省去栅极方向邦定（Bonding）的工艺，对提升产能极为有利，并提高了显示装置的集成度。
在实际使用时，每级GOA电路均设计相应的辅助下拉电路，通常为两组辅助下拉电路，两组辅助下拉电路在不同的时间段内交替工作，以对GOA电路中的Q点和栅极驱动信号进行下拉。目前辅助下拉电路包括两种切换频率，一种切换频率与时钟信号的频率相同，另一种切换频率为每隔若干帧的时间切换一次。若切换频率与时钟信号的频率相同，则GOA电路的薄膜晶体管收到高频的压力；若切换频率为每隔若干帧的时间切换一次，则GOA电路的薄膜晶体管收到低频的压力，造成GOA电路工作异常。
【发明内容】
本发明主要解决的技术问题是提供一种显示面板及其栅极驱动电路，以解决上述问题。
本发明提供一种栅极驱动电路，其包括多级栅极驱动单元，每级栅极驱动单元包括：
第一拉动控制单元，用于在第一节点输出第一拉动控制信号；
第一拉动单元，其耦接第一节点，接收第一时钟信号，根据第一拉动控制信号和第一时钟信号生成栅极驱动信号，栅极驱动信号输出端输出栅极驱动信号；
第二拉动控制单元，用于接收第一信号、第二信号、第三信号和第四信号，根据第一信号、第二信号、第三信号和第四信号输出第二拉动控制信号；
第二拉动单元，其耦接第一节点和栅极驱动信号输出端，接收第二拉动控制信号，根据第二拉动控制信号拉动第一节点的电平和栅极驱动信号输出端的电平；
其中，第二拉动控制信号的频率小于第一时钟信号的频率，并且大于显示面板的刷新频率，第二拉动控制信号为方波脉冲控制信号；
第一信号为第二时钟信号，第二时钟信号的频率与第一时钟信号的频率的比例范围为2-50。
其中，第二时钟信号的频率为第一时钟信号的频率的4倍，第三信号为前两级的栅极驱动单元的第二信号，第四信号为后两级的栅极驱动单元的第二信号。
本发明还提供一种栅极驱动电路，其包括多级栅极驱动单元，每级栅极驱动单元包括：
第一拉动控制单元，用于在第一节点输出第一拉动控制信号；
第一拉动单元，其耦接第一节点，接收第一时钟信号，根据第一拉动控制信号和第一时钟信号生成栅极驱动信号，栅极驱动信号输出端输出栅极驱动信号；
第二拉动控制单元，用于接收第一信号、第二信号、第三信号和第四信号，根据第一信号、第二信号、第三信号和第四信号输出第二拉动控制信号；
第二拉动单元，其耦接第一节点和栅极驱动信号输出端，接收第二拉动控制信号，根据第二拉动控制信号拉动第一节点的电平和栅极驱动信号输出端的电平；
其中，第二拉动控制信号的频率小于第一时钟信号的频率，并且大于显示面板的刷新频率。
其中，第二拉动控制信号为方波脉冲控制信号。
其中，第一信号为第二时钟信号，第二时钟信号的频率与第一时钟信号的频率的比例范围为2-50。
其中，第二时钟信号的频率为第一时钟信号的频率的4倍，第三信号为前两级的栅极驱动单元的第二信号，第四信号为后两级的栅极驱动单元的第二信号。
其中，第二时钟信号的频率为第一时钟信号的频率的2倍，第三信号为前四级的栅极驱动单元的第二信号，第四信号为后四级的栅极驱动单元的第二信号。
其中，第一拉动控制单元包括第一薄膜晶体管，第一薄膜晶体管的第一端接收第一参考电压，第一薄膜晶体管的第二端接收前两级的栅极驱动单元的栅极驱动信号，第一薄膜晶体管的第三端连接第一节点。
其中，第一拉动单元包括第二薄膜晶体管和电容，第二薄膜晶体管的第一端接收第一时钟信号，第二薄膜晶体管的第二端连接第一节点，第二薄膜晶体管的第三端为栅极驱动信号输出端，电容的一端连接第一节点，电容的另一端连接第二薄膜晶体管的第三端。
其中，第二拉动控制单元包括第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管、第十薄膜晶体管、第十一薄膜晶体管、第十二薄膜晶体管以及第十三薄膜晶体管，第三薄膜晶体管的第一端和第四薄膜晶体管的第一端接收第一参考电压，第三薄膜晶体管的第二端接收第三信号，第四薄膜晶体管的第二端接收第二信号，第三薄膜晶体管的第三端和第四薄膜晶体管的第三端与第五薄膜晶体管的第一端、第七薄膜晶体管的第二端和第八薄膜晶体管的第二端连接，第五薄膜晶体管的第二端和第十二薄膜晶体管的第二端接收第四信号，第十三薄膜晶体管的第二端连接栅极驱动信号输出端，第五薄膜晶体管的第三端、第七薄膜晶体管的第三端、第九薄膜晶体管的第三端、第十二薄膜晶体管的第三端和第十三薄膜晶体管的第三端接收第二参考电压，第六薄膜晶体管的第一端和第二端接收第一参考电压，第六薄膜晶体管的第三端与第七薄膜晶体管的第一端和第九薄膜晶体管的第二端连接，第八薄膜晶体管的第一端接收第一参考电压，第八薄膜晶体管的第三端与第九薄膜晶体管的第一端、第十薄膜晶体管的第二端和第十一薄膜晶体管的第二端连接，第十薄膜晶体管的第一端接收第一信号，第十薄膜晶体管的第三端输出第二信号，第十一薄膜晶体管的第一端接收第一信号，第十一薄膜晶体管的第三端连接第十二薄膜晶体管的第一端和第十三薄膜晶体管的第一端，第十一薄膜晶体管的第三端输出第二拉动控制信号。
其中，第二拉动单元包括第十四薄膜晶体管、第十五薄膜晶体管、第十六薄膜晶体管以及第十七薄膜晶体管，第十四薄膜晶体管的第一端连接第一节点，第十四薄膜晶体管的第二端和第十五薄膜晶体管的第二端连接第十一薄膜晶体管的第三端，第十四薄膜晶体管的第三端、第十五薄膜晶体管的第三端、第十六薄膜晶体管的第三端以及第十七薄膜晶体管的第三端接收第二参考电压，第十五薄膜晶体管的第一端连接栅极驱动信号输出端，第十六薄膜晶体管的第一端连接第一节点，第十七薄膜晶体管的第二端和第十八薄膜晶体管的第二端接收后两级的栅极驱动单元的栅极驱动信号，第十八薄膜晶体管的第一端连接栅极驱动信号输出端。
本发明还提供一种显示面板，其包括栅极驱动电路，栅极驱动电路包括多级栅极驱动单元，每级栅极驱动单元包括：
第一拉动控制单元，用于在第一节点输出第一拉动控制信号；
第一拉动单元，其耦接第一节点，接收第一时钟信号，根据第一拉动控制信号和第一时钟信号生成栅极驱动信号，栅极驱动信号输出端输出栅极驱动信号；
第二拉动控制单元，用于接收第一信号、第二信号、第三信号和第四信号，根据第一信号、第二信号、第三信号和第四信号输出第二拉动控制信号；
第二拉动单元，其耦接第一节点和栅极驱动信号输出端，接收第二拉动控制信号，根据第二拉动控制信号拉动第一节点的电平和栅极驱动信号输出端的电平；
其中，第二拉动控制信号的频率小于第一时钟信号的频率，并且大于显示面板的刷新频率。
其中，第二拉动控制信号为方波脉冲控制信号。
其中，第一信号为第二时钟信号，第二时钟信号的频率与第一时钟信号的频率的比例范围为2-50。
其中，第二时钟信号的频率为第一时钟信号的频率的4倍，第三信号为前两级的栅极驱动单元的第二信号，第四信号为后两级的栅极驱动单元的第二信号。
其中，第二时钟信号的频率为第一时钟信号的频率的2倍，第三信号为前四级的栅极驱动单元的第二信号，第四信号为后四级的栅极驱动单元的第二信号。
其中，第一拉动控制单元包括第一薄膜晶体管，第一薄膜晶体管的第一端接收第一参考电压，第一薄膜晶体管的第二端接收前两级的栅极驱动单元的栅极驱动信号，第一薄膜晶体管的第三端连接第一节点。
其中，第一拉动单元包括第二薄膜晶体管和电容，第二薄膜晶体管的第一端接收第一时钟信号，第二薄膜晶体管的第二端连接第一节点，第二薄膜晶体管的第三端为栅极驱动信号输出端，电容的一端连接第一节点，电容的另一端连接第二薄膜晶体管的第三端。
其中，第二拉动控制单元包括第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管、第十薄膜晶体管、第十一薄膜晶体管、第十二薄膜晶体管以及第十三薄膜晶体管，第三薄膜晶体管的第一端和第四薄膜晶体管的第一端接收第一参考电压，第三薄膜晶体管的第二端接收第三信号，第四薄膜晶体管的第二端接收第二信号，第三薄膜晶体管的第三端和第四薄膜晶体管的第三端与第五薄膜晶体管的第一端、第七薄膜晶体管的第二端和第八薄膜晶体管的第二端连接，第五薄膜晶体管的第二端和第十二薄膜晶体管的第二端接收第四信号，第十三薄膜晶体管的第二端连接栅极驱动信号输出端，第五薄膜晶体管的第三端、第七薄膜晶体管的第三端、第九薄膜晶体管的第三端、第十二薄膜晶体管的第三端和第十三薄膜晶体管的第三端接收第二参考电压，第六薄膜晶体管的第一端和第二端接收第一参考电压，第六薄膜晶体管的第三端与第七薄膜晶体管的第一端和第九薄膜晶体管的第二端连接，第八薄膜晶体管的第一端接收第一参考电压，第八薄膜晶体管的第三端与第九薄膜晶体管的第一端、第十薄膜晶体管的第二端和第十一薄膜晶体管的第二端连接，第十薄膜晶体管的第一端接收第一信号，第十薄膜晶体管的第三端输出第二信号，第十一薄膜晶体管的第一端接收第一信号，第十一薄膜晶体管的第三端连接第十二薄膜晶体管的第一端和第十三薄膜晶体管的第一端，第十一薄膜晶体管的第三端输出第二拉动控制信号。
其中，第二拉动单元包括第十四薄膜晶体管、第十五薄膜晶体管、第十六薄膜晶体管以及第十七薄膜晶体管，第十四薄膜晶体管的第一端连接第一节点，第十四薄膜晶体管的第二端和第十五薄膜晶体管的第二端连接第十一薄膜晶体管的第三端，第十四薄膜晶体管的第三端、第十五薄膜晶体管的第三端、第十六薄膜晶体管的第三端以及第十七薄膜晶体管的第三端接收第二参考电压，第十五薄膜晶体管的第一端连接栅极驱动信号输出端，第十六薄膜晶体管的第一端连接第一节点，第十七薄膜晶体管的第二端和第十八薄膜晶体管的第二端接收后两级的栅极驱动单元的栅极驱动信号，第十八薄膜晶体管的第一端连接栅极驱动信号输出端。
通过上述方案，本发明的有益效果是：本发明的每级栅极驱动单元包括第一拉动控制单元，用于在第一节点输出第一拉动控制信号；第一拉动单元，其耦接第一节点，接收第一时钟信号，根据第一拉动控制信号和第一时钟信号生成栅极驱动信号，栅极驱动信号输出端输出栅极驱动信号；第二拉动控制单元，用于接收第一信号、第二信号、第三信号和第四信号，根据第一信号、第二信号、第三信号和第四信号输出第二拉动控制信号；第二拉动单元，其耦接第一节点和栅极驱动信号输出端，接收第二拉动控制信号，根据第二拉动控制信号拉动第一节点的电平和栅极驱动信号输出端的电平；其中，第二拉动控制信号的频率小于第一时钟信号的频率，并且大于显示面板的刷新频率；能够有效防止栅极驱动单元的薄膜晶体管特性的漂移，提高栅极驱动单元的信赖性。
【附图说明】
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。其中：
图1是本发明第一实施例的栅极驱动电路的结构示意图；
图2是图1中栅极驱动单元的结构示意图；
图3是本发明第二实施例的栅极驱动单元的电路图；
图4是图3中第一时钟信号和栅极驱动信号的时序图；
图5是图3中第二时钟信号和第二信号的时序图；
图6是本发明第三实施例的栅极驱动单元的电路图；
图7是图6中第二时钟信号和第二信号的时序图；
图8是本发明第一实施例的显示面板的结构示意图；
图9是本发明第一实施例的液晶显示装置的结构示意图。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性的劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参见图1所示，图1是本发明第一实施例的栅极驱动电路的结构示意图。本实施例所揭示的栅极驱动电路应用于显示面板，用于驱动液显示面板的多条扫描线，以使多条扫描线打开。
如图1所示，栅极驱动电路10与多条扫描线20连接，栅极驱动电路10用于产生栅极驱动信号，用于驱动多条扫描线20。该栅极驱动驱动电路10包括多级栅极驱动单元11，一级栅极驱动单元11对应一条扫描线20，每级栅极驱动单元11的输出端均与一条扫描线20连接。
以下以第n级栅极驱动单元11进行详细说明，其中n为大于或等于1的整数。
如图2所示，第n级栅极驱动单元11包括第一拉动控制单元111、第一拉动单元112、第二拉动控制单元113以及第二拉动单元114。其中，第一拉动控制单元111用于在第一节点Qn输出第一拉动控制信号。第一拉动单元112耦接第一节点Qn，第一拉动单元112接收第一时钟信号CK，并根据第一拉动控制信号和第一时钟信号CK生成栅极驱动信号Gn，栅极驱动信号输出端输出栅极驱动信号Gn，即第一拉动单元112的栅极驱动信号输出端输出栅极驱动信号Gn，栅极驱动信号Gn用于驱动扫描线20。
在第一拉动控制信号和第一时钟信号CK均为高电平时，第一拉动单元112根据第一拉动控制信号和第一时钟信号CK生成栅极驱动信号Gn为高电平，此时与第n级栅极驱动单元11对应的扫描线20打开。
第二拉动控制单元113用于接收第一信号、第二信号、第三信号和第四信号，并根据第一信号、第二信号、第三信号和第四信号输出第二拉动控制信号。第二拉动单元114耦接第一节点Qn和栅极驱动信号输出端，接收第二拉动控制信号，并根据第二拉动控制信号拉动第一节点Qn的电平和栅极驱动信号输出端的电平。
在第二拉动控制信号为高电平时，第二拉动单元114根据第二拉动控制信号拉动第一节点Qn的电平和栅极驱动信号输出端的电平至低电平，此时与第n级栅极驱动单元11对应的扫描线20打开关闭。
在本实施例中，第二拉动控制信号的频率小于第一时钟信号CK的频率，并且大于显示面板的刷新频率；显示面板的刷新频率为显示面板每秒显示图像的次数。
其中，第二拉动控制单元113根据第一信号、第二信号和第三信号控制第二拉动控制信号的频率，以使第二拉动控制信号的频率小于第一时钟信号CK的频率，并且大于显示面板的刷新频率。
本实施例能够有效防止栅极驱动单元11的薄膜晶体管特性的漂移，提高栅极驱动单元11的信赖性。
本发明还提供第二实施例的栅极驱动单元，其在第一实施例所揭示的栅极驱动单元11的基础上进行描述。如图3所示，第一拉动控制单元111包括第一薄膜晶体管T1，第一薄膜晶体管T1的第一端接收第一参考电压VDD，第一薄膜晶体管T1的第二端接收前两级的栅极驱动单元11的栅极驱动信号Gn-2，第一薄膜晶体管T1的第三端连接第一节点Qn。
第一拉动单元112包括第二薄膜晶体管T2和电容C，第二薄膜晶体管T2的第一端接收第一时钟信号CK，第二薄膜晶体管T2的第二端连接第一节点Qn，第二薄膜晶体管T2的第三端为栅极驱动信号输出端Gn，用于输出栅极驱动信号Gn；电容C的一端连接第一节点Qn，电容C的另一端连接第二薄膜晶体管T2的第三端。
第二拉动控制单元113包括第三薄膜晶体管T3、第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6、第七薄膜晶体管T7、第八薄膜晶体管T8、第九薄膜晶体管T9、第十薄膜晶体管T10、第十一薄膜晶体管T11、第十二薄膜晶体管T12以及第十三薄膜晶体管T13，第三薄膜晶体管T3的第一端和第四薄膜晶体管T4的第一端接收第一参考电压VDD，第三薄膜晶体管T3的第二端接收第三信号，第四薄膜晶体管T4的第二端接收第二信号，第三薄膜晶体管T3的第三端和第四薄膜晶体管T4的第三端与第五薄膜晶体管T5的第一端、第七薄膜晶体管T7的第二端和第八薄膜晶体管T8的第二端连接，第五薄膜晶体管T5的第二端和第十二薄膜晶体管T10的第二端接收第四信号，第十三薄膜晶体管T13的第二端连接栅极驱动信号输出端Gn，第五薄膜晶体管T5的第三端、第七薄膜晶体管T7的第三端、第九薄膜晶体管T9的第三端、第十二薄膜晶体管T12的第三端和第十三薄膜晶体管T13的第三端接收第二参考电压VSS，第六薄膜晶体管T6的第一端和第二端接收第一参考电压VDD，第六薄膜晶体管T6的第三端与第七薄膜晶体管T7的第一端和第九薄膜晶体管T9的第二端连接，第八薄膜晶体管T8的第一端接收第一参考电压VDD，第八薄膜晶体管T8的第三端与第九薄膜晶体管T9的第一端、第十薄膜晶体管T10的第二端和第十一薄膜晶体管T11的第二端连接，第十薄膜晶体管T10的第一端接收第一信号，第十薄膜晶体管T10的第三端输出第二信号，第十一薄膜晶体管T11的第一端接收第一信号，第十一薄膜晶体管T11的第三端连接第十二薄膜晶体管T12的第一端和第十三薄膜晶体管T13的第一端，第十一薄膜晶体管T11的第三端输出第二拉动控制信号。
第二拉动单元114包括第十四薄膜晶体管T14、第十五薄膜晶体管T15、第十六薄膜晶体管T16以及第十七薄膜晶体管T17，第十四薄膜晶体管T14的第一端连接第一节点，第十四薄膜晶体管T14的第二端和第十五薄膜晶体管T15的第二端连接第十一薄膜晶体管T11的第三端，第十四薄膜晶体管T14的第三端、第十五薄膜晶体管T15的第三端、第十六薄膜晶体管T16的第三端以及第十七薄膜晶体管T17的第三端接收第二参考电压VSS，第十五薄膜晶体管T15的第一端连接栅极驱动信号输出端Gn，第十六薄膜晶体管T16的第一端连接第一节点，第十七薄膜晶体管T17的第二端和第十八薄膜晶体管T18的第二端接收后两级的栅极驱动单元的栅极驱动信号Gn-2，第十八薄膜晶体管T17的第一端连接栅极驱动信号输出端Gn。其中，第二参考电压VSS为低电平。
优选地，第二拉动控制信号为方波脉冲控制信号。第一信号优选为第二时钟信号CKH，其中第二时钟信号CKH的频率与第一时钟信号CK的频率的比例范围为2-50。
优选地，第二时钟信号CKH的频率为第一时钟信号CK的频率的4倍。此时，第二信号为PDn，第三信号PDn-2为前两级的栅极驱动单元的第二信号，第四信号PDn+2为后两级的栅极驱动单元的第二信号，即第二拉动控制单元113根据第二时钟信号CKH、第二信号PDn、第三信号PDn-2和第四信号PDn+2输出第二拉动控制信号。结合图4-5所示的时序图详细描述该栅极驱动单元的工作原理。
如图4所示，在前两级的栅极驱动单元的栅极驱动信号Gn-2为高电平时，第一薄膜晶体管T1导通，第一薄膜晶体管T1的第三端在第一节点Qn输出的第一拉动控制信号为高电平；第二薄膜晶体管T2导通，栅极驱动信号Gn与第一时钟信号CK相同。
在前两级的栅极驱动单元的栅极驱动信号Gn-2为低电平时，第一薄膜晶体管T1断开，第一薄膜晶体管T1的第三端没有输出第一拉动控制信号；由于电容C充放电的作用，第一节点Qn为高电平，第二薄膜晶体管T2导通，栅极驱动信号Gn与第一时钟信号CK相同。
在后两级的栅极驱动单元的栅极驱动信号Gn+2为高电平时，第十六薄膜晶体管T16和第十七薄膜晶体管T17导通，第十六薄膜晶体管T16将第一节点Qn的电平由高电平拉到低电平，第二薄膜晶体管T2断开；第十七薄膜晶体管T17将栅极驱动信号Gn的电平由高电平拉到低电平。
如图5所示，当第三信号PDn-2为高电平、第二时钟信号CKH为低电平和第四信号PDn+2为低电平时，第三薄膜晶体管T3、第七薄膜晶体管T7、第八薄膜晶体管T8、第十薄膜晶体管T10以及第十一薄膜晶体管T11均导通，此时第二信号PDn与第二时钟信号CKH相同，即第二信号PDn为低电平；第四薄膜晶体管T4、第五薄膜晶体管T5、第九薄膜晶体管T9以及第十二薄膜晶体管T12均断开，第十一薄膜晶体管T11的第三端输出第二拉动控制信号为低电平。在栅极驱动信号Gn为低电平时，第十三薄膜晶体管T13断开，第十四薄膜晶体管T14和第十五薄膜晶体管T15均断开；在栅极驱动信号Gn为高电平时，第十三薄膜晶体管T13导通，第十四薄膜晶体管T14和第十五薄膜晶体管T15均断开。
当第三信号PDn-2为低电平、第二时钟信号CKH为高电平、第二信号PDn为高电平和第四信号PDn+2为低电平时，第三薄膜晶体管T3断开，第四薄膜晶体管T4、第七薄膜晶体管T7、第八薄膜晶体管T8、第十薄膜晶体管T10以及第十一薄膜晶体管T11均导通，此时第二信号PDn与第二时钟信号CKH相同，即第二信号PDn为高电平；第五薄膜晶体管T5、第九薄膜晶体管T9以及第十二薄膜晶体管T12均断开，第十一薄膜晶体管T11的第三端输出第二拉动控制信号为高电平。在栅极驱动信号Gn为低电平时，第十三薄膜晶体管T13断开，第十四薄膜晶体管T14和第十五薄膜晶体管T15均导通，第十四薄膜晶体管T14拉动第一节点Qn的电平到低电平，第十五薄膜晶体管T15拉动栅极驱动信号输出端Gn的电平到低电平；在栅极驱动信号Gn为高电平时，第十三薄膜晶体管T13导通，第十四薄膜晶体管T14和第十五薄膜晶体管T15均断开。
当第三信号PDn-2为低电平、第二时钟信号CKH为低电平、第二信号PDn为低电平和第四信号PDn+2为高电平时，第三薄膜晶体管T3、第四薄膜晶体管T4、第七薄膜晶体管T7、第八薄膜晶体管T8、第十薄膜晶体管T10以及第十一薄膜晶体管T11均断开，第五薄膜晶体管T5、第六薄膜晶体管T6、第九薄膜晶体管T9以及第十二薄膜晶体管T12导通，第十一薄膜晶体管T11的第三端输出第二拉动控制信号为低电平。在栅极驱动信号Gn为低电平时，第十三薄膜晶体管T13断开，第十四薄膜晶体管T14和第十五薄膜晶体管T15均断开；在栅极驱动信号Gn为高电平时，第十三薄膜晶体管T13导通，第十四薄膜晶体管T14和第十五薄膜晶体管T15均断开。
第十三薄膜晶体管T13用于保证在栅极驱动信号输出端的栅极驱动信号Gn为高电平时，将第十一薄膜晶体管T11的第三端输出第二拉动控制信号维持在低电平，第十四薄膜晶体管T14和第十五薄膜晶体管T15保持断开，以保证栅极驱动电路10的正常工作。
如图5所示，第二信号PDn每个脉冲宽度为w1。在显示面板的一帧周期内，第十四薄膜晶体管T14用于对第一节点Qn进行下拉，第十五薄膜晶体管T15用于对栅极驱动信号输出端的栅极驱动信号Gn进行下拉，第十四薄膜晶体管T14和第十五薄膜晶体管T15导通四次，即第十四薄膜晶体管T14下拉第一节点Qn四次，第十五薄膜晶体管T15下拉栅极驱动信号Gn四次，保证了栅极驱动电路10的正常工作，避免第十四薄膜晶体管T14和第十五薄膜晶体管T15受到过高频率或者过低频率的压力，能够有效防止栅极驱动单元的薄膜晶体管特性的漂移，提高栅极驱动单元11的信赖性。此外，通过对第二时钟信号CKH的频率进行调节，以获取较优的第二拉动控制信号的频率。
本发明还提供第三实施例的栅极驱动单元，其与第二实施例所揭示的栅极驱动单元不同之处在于：第二时钟信号CKH的频率为第一时钟信号的频率的2倍，例如第二时钟信号CKH采用8个时钟信号。如图6所示，第二信号为PDn，第三信号PDn-4为前四级的栅极驱动单元的第二信号，第四信号PDn+4为后四级的栅极驱动单元的第二信号。
如图7所示的时序图，与图5所示的时序图比较可知，本实施例的第二信号PDn的脉冲宽度w2为图5所示的脉冲宽度w1的两倍。
相对于第二实施例所揭示的栅极驱动单元，本实施例的栅极驱动单元的功耗降低。因此，第二时钟信号CKH包括时钟信号的数量可以根据实际情况进行设置，通常第二时钟信号CKH包括时钟信号的数量为4，6或者8个，当第二时钟信号CKH包括时钟信号的数量为h（h为偶数）时，第二拉动控制信号由第二时钟信号CKH、第三信号P（n-h/2）和第四信号P（n+h/2）控制。当第二时钟信号CKH包括时钟信号的数量越多，则第二时钟信号CKH的频率越低，相应的功耗越小，栅极驱动电路所占用的布线空间多。当第二时钟信号CKH包括时钟信号的数量越少，则第二时钟信号CKH的频率越高，相应的功耗越大，栅极驱动电路所占用的布线空间少，利于窄边框的显示面板设计。
本发明还提供一种显示面板，如图8所示，本实施例所揭示的显示面板80包括栅极驱动电路81，该栅极驱动电路81上述实施例的栅极驱动电路，栅极驱动电路81用于驱动液显示面板80的多条扫描线82，以使多条扫描线82打开，在此不再赘述。
本发明还提供一种液晶显示装置，如图9所示，本实施例所揭示的液晶显示装置包括背光模组91和显示面板92，显示面板92设置在背光模组91的出光面的上方，背光模组91用于为显示面板92提供光源，该显示面板92包括上述实施例的栅极驱动电路，栅极驱动电路用于驱动液显示面板92的多条扫描线，以使多条扫描线打开，在此不再赘述。
综上所述，本发明的每级栅极驱动单元包括第一拉动控制单元，用于在第一节点输出第一拉动控制信号；第一拉动单元，其耦接第一节点，接收第一时钟信号，根据第一拉动控制信号和第一时钟信号生成栅极驱动信号，栅极驱动信号输出端输出栅极驱动信号；第二拉动控制单元，用于接收第一信号、第二信号、第三信号和第四信号，根据第一信号、第二信号、第三信号和第四信号输出第二拉动控制信号；第二拉动单元，其耦接第一节点和栅极驱动信号输出端，接收第二拉动控制信号，根据第二拉动控制信号拉动第一节点的电平和栅极驱动信号输出端的电平；其中，第二拉动控制信号的频率小于第一时钟信号的频率，并且大于显示面板的刷新频率；能够有效防止栅极驱动单元的薄膜晶体管特性的漂移，提高栅极驱动单元的信赖性。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种栅极驱动电路，其中，所述栅极驱动电路包括多级栅极驱动单元，每级所述栅极驱动单元包括：
    第一拉动控制单元，用于在第一节点输出第一拉动控制信号；
    第一拉动单元，其耦接所述第一节点，接收第一时钟信号，根据所述第一拉动控制信号和第一时钟信号生成栅极驱动信号，栅极驱动信号输出端输出所述栅极驱动信号；
    第二拉动控制单元，用于接收第一信号、第二信号、第三信号和第四信号，根据所述第一信号、第二信号、第三信号和第四信号输出第二拉动控制信号；
    第二拉动单元，其耦接所述第一节点和所述栅极驱动信号输出端，接收所述第二拉动控制信号，根据所述第二拉动控制信号拉动所述第一节点的电平和所述栅极驱动信号输出端的电平；
    其中，所述第二拉动控制信号的频率小于所述第一时钟信号的频率，并且大于显示面板的刷新频率，所述第二拉动控制信号为方波脉冲控制信号；
    所述第一信号为第二时钟信号，所述第二时钟信号的频率与所述第一时钟信号的频率的比例范围为2-50。
  2. 根据权利要求1所述的栅极驱动电路，其中，所述第二时钟信号的频率为所述第一时钟信号的频率的4倍，所述第三信号为前两级的栅极驱动单元的第二信号，所述第四信号为后两级的栅极驱动单元的第二信号。
  3. 一种栅极驱动电路，其中，所述栅极驱动电路包括多级栅极驱动单元，每级所述栅极驱动单元包括：
    第一拉动控制单元，用于在第一节点输出第一拉动控制信号；
    第一拉动单元，其耦接所述第一节点，接收第一时钟信号，根据所述第一拉动控制信号和第一时钟信号生成栅极驱动信号，栅极驱动信号输出端输出所述栅极驱动信号；
    第二拉动控制单元，用于接收第一信号、第二信号、第三信号和第四信号，根据所述第一信号、第二信号、第三信号和第四信号输出第二拉动控制信号；
    第二拉动单元，其耦接所述第一节点和所述栅极驱动信号输出端，接收所述第二拉动控制信号，根据所述第二拉动控制信号拉动所述第一节点的电平和所述栅极驱动信号输出端的电平；
    其中，所述第二拉动控制信号的频率小于所述第一时钟信号的频率，并且大于显示面板的刷新频率。
  4. 根据权利要求3所述的栅极驱动电路，其中，所述第二拉动控制信号为方波脉冲控制信号。
  5. 根据权利要求3所述的栅极驱动电路，其中，所述第一信号为第二时钟信号，所述第二时钟信号的频率与所述第一时钟信号的频率的比例范围为2-50。
  6. 根据权利要求5所述的栅极驱动电路，其中，所述第二时钟信号的频率为所述第一时钟信号的频率的4倍，所述第三信号为前两级的栅极驱动单元的第二信号，所述第四信号为后两级的栅极驱动单元的第二信号。
  7. 根据权利要求5所述的栅极驱动电路，其中，所述第二时钟信号的频率为所述第一时钟信号的频率的2倍，所述第三信号为前四级的栅极驱动单元的第二信号，所述第四信号为后四级的栅极驱动单元的第二信号。
  8. 根据权利要求3所述的栅极驱动电路，其中，所述第一拉动控制单元包括第一薄膜晶体管，所述第一薄膜晶体管的第一端接收第一参考电压，所述第一薄膜晶体管的第二端接收前两级的栅极驱动单元的栅极驱动信号，所述第一薄膜晶体管的第三端连接所述第一节点。
  9. 根据权利要求8所述的栅极驱动电路，其中，所述第一拉动单元包括第二薄膜晶体管和电容，所述第二薄膜晶体管的第一端接收所述第一时钟信号，所述第二薄膜晶体管的第二端连接所述第一节点，所述第二薄膜晶体管的第三端为所述栅极驱动信号输出端，所述电容的一端连接所述第一节点，所述电容的另一端连接所述第二薄膜晶体管的第三端。
  10. 根据权利要求9所述的栅极驱动电路，其中，所述第二拉动控制单元包括第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管、第十薄膜晶体管、第十一薄膜晶体管、第十二薄膜晶体管以及第十三薄膜晶体管，所述第三薄膜晶体管的第一端和所述第四薄膜晶体管的第一端接收所述第一参考电压，所述第三薄膜晶体管的第二端接收所述第三信号，所述第四薄膜晶体管的第二端接收所述第二信号，所述第三薄膜晶体管的第三端和所述第四薄膜晶体管的第三端与所述第五薄膜晶体管的第一端、所述第七薄膜晶体管的第二端和所述第八薄膜晶体管的第二端连接，所述第五薄膜晶体管的第二端和所述第十二薄膜晶体管的第二端接收所述第四信号，所述第十三薄膜晶体管的第二端连接所述栅极驱动信号输出端，所述第五薄膜晶体管的第三端、所述第七薄膜晶体管的第三端、所述第九薄膜晶体管的第三端、所述第十二薄膜晶体管的第三端和所述第十三薄膜晶体管的第三端接收第二参考电压，所述第六薄膜晶体管的第一端和第二端接收所述第一参考电压，所述第六薄膜晶体管的第三端与所述第七薄膜晶体管的第一端和所述第九薄膜晶体管的第二端连接，所述第八薄膜晶体管的第一端接收所述第一参考电压，所述第八薄膜晶体管的第三端与所述第九薄膜晶体管的第一端、所述第十薄膜晶体管的第二端和所述第十一薄膜晶体管的第二端连接，所述第十薄膜晶体管的第一端接收所述第一信号，所述第十薄膜晶体管的第三端输出所述第二信号，所述第十一薄膜晶体管的第一端接收所述第一信号，所述第十一薄膜晶体管的第三端连接所述第十二薄膜晶体管的第一端和所述第十三薄膜晶体管的第一端，所述第十一薄膜晶体管的第三端输出所述第二拉动控制信号。
  11. 根据权利要求10所述的栅极驱动电路，其中，所述第二拉动单元包括第十四薄膜晶体管、第十五薄膜晶体管、第十六薄膜晶体管以及第十七薄膜晶体管，所述第十四薄膜晶体管的第一端连接所述第一节点，所述第十四薄膜晶体管的第二端和所述第十五薄膜晶体管的第二端连接所述第十一薄膜晶体管的第三端，所述第十四薄膜晶体管的第三端、所述第十五薄膜晶体管的第三端、所述第十六薄膜晶体管的第三端以及所述第十七薄膜晶体管的第三端接收第二参考电压，所述第十五薄膜晶体管的第一端连接所述栅极驱动信号输出端，所述第十六薄膜晶体管的第一端连接所述第一节点，所述第十七薄膜晶体管的第二端和所述第十八薄膜晶体管的第二端接收后两级的栅极驱动单元的栅极驱动信号，所述第十八薄膜晶体管的第一端连接所述栅极驱动信号输出端。
  12. 一种显示面板，其中，所述显示面板包括栅极驱动电路，所述栅极驱动电路包括多级栅极驱动单元，每级所述栅极驱动单元包括：
    第一拉动控制单元，用于在第一节点输出第一拉动控制信号；
    第一拉动单元，其耦接所述第一节点，接收第一时钟信号，根据所述第一拉动控制信号和第一时钟信号生成栅极驱动信号，栅极驱动信号输出端输出所述栅极驱动信号；
    第二拉动控制单元，用于接收第一信号、第二信号、第三信号和第四信号，根据所述第一信号、第二信号、第三信号和第四信号输出第二拉动控制信号；
    第二拉动单元，其耦接所述第一节点和所述栅极驱动信号输出端，接收所述第二拉动控制信号，根据所述第二拉动控制信号拉动所述第一节点的电平和所述栅极驱动信号输出端的电平；
    其中，所述第二拉动控制信号的频率小于所述第一时钟信号的频率，并且大于显示面板的刷新频率。
  13. 根据权利要求12所述的显示面板，其中，所述第二拉动控制信号为方波脉冲控制信号。
  14. 根据权利要求12所述的显示面板，其中，所述第一信号为第二时钟信号，所述第二时钟信号的频率与所述第一时钟信号的频率的比例范围为2-50。
  15. 根据权利要求14所述的显示面板，其中，所述第二时钟信号的频率为所述第一时钟信号的频率的4倍，所述第三信号为前两级的栅极驱动单元的第二信号，所述第四信号为后两级的栅极驱动单元的第二信号。
  16. 根据权利要求14所述的显示面板，其中，所述第二时钟信号的频率为所述第一时钟信号的频率的2倍，所述第三信号为前四级的栅极驱动单元的第二信号，所述第四信号为后四级的栅极驱动单元的第二信号。
  17. 根据权利要求12所述的显示面板，其中，所述第一拉动控制单元包括第一薄膜晶体管，所述第一薄膜晶体管的第一端接收第一参考电压，所述第一薄膜晶体管的第二端接收前两级的栅极驱动单元的栅极驱动信号，所述第一薄膜晶体管的第三端连接所述第一节点。
  18. 根据权利要求17所述的显示面板，其中，所述第一拉动单元包括第二薄膜晶体管和电容，所述第二薄膜晶体管的第一端接收所述第一时钟信号，所述第二薄膜晶体管的第二端连接所述第一节点，所述第二薄膜晶体管的第三端为所述栅极驱动信号输出端，所述电容的一端连接所述第一节点，所述电容的另一端连接所述第二薄膜晶体管的第三端。
  19. 根据权利要求18所述的显示面板，其中，所述第二拉动控制单元包括第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管、第十薄膜晶体管、第十一薄膜晶体管、第十二薄膜晶体管以及第十三薄膜晶体管，所述第三薄膜晶体管的第一端和所述第四薄膜晶体管的第一端接收所述第一参考电压，所述第三薄膜晶体管的第二端接收所述第三信号，所述第四薄膜晶体管的第二端接收所述第二信号，所述第三薄膜晶体管的第三端和所述第四薄膜晶体管的第三端与所述第五薄膜晶体管的第一端、所述第七薄膜晶体管的第二端和所述第八薄膜晶体管的第二端连接，所述第五薄膜晶体管的第二端和所述第十二薄膜晶体管的第二端接收所述第四信号，所述第十三薄膜晶体管的第二端连接所述栅极驱动信号输出端，所述第五薄膜晶体管的第三端、所述第七薄膜晶体管的第三端、所述第九薄膜晶体管的第三端、所述第十二薄膜晶体管的第三端和所述第十三薄膜晶体管的第三端接收第二参考电压，所述第六薄膜晶体管的第一端和第二端接收所述第一参考电压，所述第六薄膜晶体管的第三端与所述第七薄膜晶体管的第一端和所述第九薄膜晶体管的第二端连接，所述第八薄膜晶体管的第一端接收所述第一参考电压，所述第八薄膜晶体管的第三端与所述第九薄膜晶体管的第一端、所述第十薄膜晶体管的第二端和所述第十一薄膜晶体管的第二端连接，所述第十薄膜晶体管的第一端接收所述第一信号，所述第十薄膜晶体管的第三端输出所述第二信号，所述第十一薄膜晶体管的第一端接收所述第一信号，所述第十一薄膜晶体管的第三端连接所述第十二薄膜晶体管的第一端和所述第十三薄膜晶体管的第一端，所述第十一薄膜晶体管的第三端输出所述第二拉动控制信号。
  20. 根据权利要求19所述的显示面板，其中，所述第二拉动单元包括第十四薄膜晶体管、第十五薄膜晶体管、第十六薄膜晶体管以及第十七薄膜晶体管，所述第十四薄膜晶体管的第一端连接所述第一节点，所述第十四薄膜晶体管的第二端和所述第十五薄膜晶体管的第二端连接所述第十一薄膜晶体管的第三端，所述第十四薄膜晶体管的第三端、所述第十五薄膜晶体管的第三端、所述第十六薄膜晶体管的第三端以及所述第十七薄膜晶体管的第三端接收第二参考电压，所述第十五薄膜晶体管的第一端连接所述栅极驱动信号输出端，所述第十六薄膜晶体管的第一端连接所述第一节点，所述第十七薄膜晶体管的第二端和所述第十八薄膜晶体管的第二端接收后两级的栅极驱动单元的栅极驱动信号，所述第十八薄膜晶体管的第一端连接所述栅极驱动信号输出端。
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