WO2017202188A1 - 显示基板的制作方法、显示基板和显示装置 - Google Patents

显示基板的制作方法、显示基板和显示装置 Download PDF

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Publication number
WO2017202188A1
WO2017202188A1 PCT/CN2017/083125 CN2017083125W WO2017202188A1 WO 2017202188 A1 WO2017202188 A1 WO 2017202188A1 CN 2017083125 W CN2017083125 W CN 2017083125W WO 2017202188 A1 WO2017202188 A1 WO 2017202188A1
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pattern
conductive
insulating layer
insulating
layer
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PCT/CN2017/083125
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English (en)
French (fr)
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崔承镇
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京东方科技集团股份有限公司
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Priority to US15/574,350 priority Critical patent/US10109654B2/en
Publication of WO2017202188A1 publication Critical patent/WO2017202188A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices

Definitions

  • At least one embodiment of the present disclosure is directed to a method of fabricating a display substrate, a display substrate, and a display device.
  • a plurality of insulating layers are included in the display substrate, and when an insulating layer pattern (via holes of the insulating layer) is formed, static electricity is easily generated, and static electricity is liable to cause a defect to the metal structure.
  • At least one embodiment of the present disclosure is directed to a method of fabricating a display substrate, a display substrate, and a display device to avoid occurrence of defects caused by static charge during fabrication of the display substrate.
  • At least one embodiment of the present disclosure provides a method of fabricating a display substrate, including:
  • An orthographic projection of the first metal pattern on the substrate substrate and an orthographic projection of the second metal pattern on the substrate substrate have overlapping portions
  • an orthographic projection of the first conductive pattern on the substrate substrate covers at least the overlapping portion.
  • At least one embodiment of the present disclosure provides a display substrate formed using a method provided by at least one embodiment of the present disclosure.
  • At least one embodiment of the present disclosure provides a display device including a display substrate provided by at least one embodiment of the present disclosure.
  • 1A is a display substrate area division
  • 1B is a partial schematic view showing a peripheral region of a substrate
  • FIG. 2 is a flow chart of a method for fabricating a display substrate according to Embodiment 1 of the present disclosure
  • 3A-3M are schematic diagrams showing a method of fabricating a display substrate according to Embodiment 1 of the present disclosure, the left side is a cross-sectional view along A-B in FIG. 1B, and the right side is a cross-sectional view along C-D in FIG. 1B;
  • 4A, 4B, and 4C are schematic views showing a part of steps of a method for fabricating a display substrate including a fourth insulating pattern according to Embodiment 2 of the present disclosure
  • FIG. 5 is a schematic view showing a display area of a substrate and a display substrate
  • 6A-6L are schematic diagrams showing a method of fabricating a display substrate according to Embodiment 3 of the present disclosure, the left side is a cross-sectional view taken along E-F in FIG. 5, and the right side is a cross-sectional view along G-H in FIG.
  • FIG. 7 is a display substrate provided with a fourth insulating layer formed by the method provided in Embodiment 4 of the present disclosure
  • FIG. 8 is another display substrate formed by the method provided in Embodiment 6 of the present disclosure.
  • a general display substrate may include a plurality of metal layers formed on a base substrate, and a metal pattern among the plurality of metal layers may have an overlapping region in a direction perpendicular to the substrate substrate, and a via hole in a subsequent insulating layer
  • the generated static electricity can affect existing metal structures, especially overlapping regions, such as insulating layers between two metal layers, such as metal layers of overlapping regions, resulting in defects.
  • the plurality of metal layers includes an SD layer and a gate layer.
  • the SD layer includes, for example, at least one of a data line, a source and a drain, or a metal structure formed in the same layer as at least one of the data line, the source and the drain, and the gate layer includes, for example, at least one of a gate and a gate line. Or a metal structure formed in the same layer as at least one of the gate electrode and the gate line, but is not limited thereto.
  • the above overlapping regions exist in the SD layer and the gate layer, so that it is liable to cause defects due to static electricity.
  • At least one embodiment of the present disclosure provides a method of fabricating a display substrate, including:
  • An orthographic projection of the first metal pattern on the substrate substrate and an orthographic projection of the second metal pattern on the substrate substrate have overlapping portions
  • the orthographic projection of the first conductive pattern on the substrate substrate covers at least the overlapping portion.
  • At least one embodiment of the present disclosure provides a method of fabricating a display substrate that avoids the occurrence of defects caused by static charges during fabrication of the display substrate.
  • the display substrate generally includes a display area 001 and a peripheral area 002 disposed on at least one side of the display area 001.
  • the peripheral area 002 is disposed around the display area 001 in FIG. 1A as an example, but is not limited thereto.
  • the method of this embodiment is applicable to at least one of the display area 001 and the peripheral area 002. Due to the denser wiring in the peripheral area, static electricity is more likely to occur during the manufacturing process of the insulating pattern (insulating layer via), and the effect is more obvious.
  • FIG. 1B A schematic plan view of a partial region in the peripheral region 002 is shown in FIG. 1B, and a first metal pattern 101 and a second metal pattern 102, a first metal pattern 101 and a second metal pattern are disposed on the base substrate 100 in FIG. 1B.
  • An insulating arrangement between 102 for example, an insulating layer may be disposed between the first metal pattern 101 and the second metal pattern 102.
  • the projection of the first metal pattern 101 on the base substrate 100 and the projection of the second metal pattern 102 on the base substrate 100 have overlapping portions 103. In the method of manufacturing the display substrate, the position of the overlapping portion 103 is liable to be caused by static electricity.
  • the embodiment provides a method for manufacturing a display substrate, which includes the following steps.
  • a first metal pattern 101 is formed on the base substrate 100; a first insulating layer 111 is formed on the first metal pattern 101; a second metal pattern 102 is formed on the first insulating layer 111; A second insulating layer 112 is formed on the metal pattern 102; a first conductive layer 113 is formed on the second insulating layer 112.
  • the first conductive layer 113 is patterned to form a first conductive pattern 1130.
  • the second insulating layer 112 is patterned to form a second insulating pattern 1120.
  • the orthographic projection of the first metal pattern 101 on the base substrate 100 and the orthographic projection of the second metal pattern 102 on the base substrate 100 have overlapping portions 103.
  • the orthographic projection of the first conductive pattern 1130 on the substrate substrate 100 covers at least the overlapping portion 103.
  • the orthographic projection of the first conductive pattern 1130 on the substrate substrate 100 covers at least the overlapping portion 103, so that the first conductive pattern 1130 can be dispersed to pattern the second insulating layer 112.
  • the static charge generated during the process avoids the disadvantages caused by static charges.
  • the first insulating layer 111 is patterned to form a first insulating pattern 1110.
  • the first conductive pattern 1130 is on the substrate substrate 100.
  • the upper orthographic projection covers at least the overlapping portion 103. Also, since the overlapping portion 103 is covered by the first conductive pattern 1130 during the fabrication of the first insulating pattern 1110, the first conductive pattern 1130 can disperse the static charge generated during the patterning of the first insulating layer 111, thereby avoiding generation. Bad due to static charge.
  • the first metal pattern 101 further includes a first end 1011
  • the second metal pattern 102 further includes a second end 1021
  • the first conductive pattern 1130 includes a first cover portion that is independent of each other.
  • the first conductive pattern 1130, the second insulating pattern 1120, and the first insulating pattern 1110 include the first through
  • the conductive layer 113, the second insulating layer 112 and the first insulating layer 111 expose the first via 121 of the first end 1011 and the second via extending through the first conductive layer 113 and the second insulating layer 112 and exposing the second end 1021. Hole 122.
  • patterning the first conductive layer 113 to form the first conductive pattern 1130 includes the following steps.
  • a first photoresist layer 114 is formed on the first conductive layer 113.
  • the first photoresist layer 114 is exposed and developed to form a first photoresist pattern 1140.
  • the removed regions in the first photoresist pattern 1140 include corresponding first vias 121 and second vias. The area at the location of the aperture 122.
  • the first conductive layer 113 is engraved with the first photoresist pattern 1140 as a mask.
  • the first conductive pattern 1130 is formed by etching.
  • patterning the second insulating layer 112 to form the second insulating pattern 1120 and patterning the first insulating layer 111 to form the first insulating pattern 1110 includes the following steps.
  • the second insulating layer 112 is etched by using the first photoresist pattern 1140 as a mask to form a second insulating pattern 1120.
  • the first insulating layer 111 is etched by using the first photoresist pattern 1140 as a mask to form a first insulating pattern 1110.
  • the first photoresist pattern 1140 is removed to form a structure as shown in FIG. 3G.
  • the second photoresist pattern 1150 is formed (as shown in FIG. 3H), and the second photoresist pattern 1150 is used.
  • the first conductive pattern 1130 is patterned by the mask to remove the first cover portion 1131 of the first conductive pattern 1130, and the first conductive portion 1132 of the first conductive pattern 1130 is retained (as shown in FIG. 3I).
  • forming the second photoresist pattern 1150 includes forming a second photoresist layer (forming a second photoresist layer on the structure shown in FIG. 3G), exposing and developing the second photoresist layer to form a first Two photoresist patterns 1150.
  • the removal of the second photoresist pattern 1150 is also included.
  • the third insulating layer 116 is formed (as shown in FIG. 3K) and the third insulating layer 116 is patterned. Forming a third insulating pattern 1160 (shown in FIG.
  • the third insulating pattern 1160, the first conductive pattern 1130, the second insulating pattern 1120, and the first insulating pattern 1110 include: a portion corresponding to the first via 121
  • the third insulating layer 116, the first conductive layer 113, the second insulating layer 112, and the first insulating layer 111 expose the third via 123 of the first end 1011, and penetrate the third insulating layer 116 at a position corresponding to the second via 122.
  • the first conductive layer 113 and the second insulating layer 112 expose the fourth via hole 124 of the second end 1021.
  • the second conductive pattern 1170 is further formed, and the second conductive pattern 1170 includes a first connection structure 1171, and the first connection structure 1171 passes through the third via 123.
  • the fourth via 124 electrically connects the first end 1011 and the second end 1021.
  • forming the second conductive pattern 1170 includes forming a second conductive layer (the junction shown in FIG.
  • the first connection structure 1171 electrically connects the first conductive portions 1132 that are broken at the positions of the third via 123 and the fourth via 124.
  • the first conductive portion 1132 electrically connects the first end 1011 and the second end 1021 through the first connection structure 1171 at the third via 123 and the fourth via 124, and the first end 1011 and the second end 1021 may be added.
  • the stability of the electrical connection may be added.
  • the material of the first conductive pattern 1130 includes at least one of a transparent conductive metal oxide and a metal.
  • the transparent conductive metal oxide includes, for example, Indium Tin Oxide (ITO), but is not limited thereto.
  • the material of the second conductive pattern 1170 includes a transparent conductive metal oxide, but is not limited thereto.
  • the material of at least one of the first insulating layer 111, the second insulating layer 112, and the third insulating layer 116 includes silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiNxOy), and aluminum oxide. At least one, but not limited to this.
  • the first metal pattern 101 may be formed by patterning a first metal layer by forming a first metal layer
  • the second metal pattern 102 may be formed by patterning a second metal layer by forming a second metal layer.
  • the first metal pattern 101 and the second metal pattern 102 include any one of molybdenum (Mo), molybdenum-niobium alloy, aluminum (Al), aluminum-niobium alloy (AlNd), titanium (Ti), and copper (Cu).
  • the single-layer structure is a laminated structure obtained by forming a sub-layer of molybdenum/aluminum/molybdenum (Mo/Al/Mo), titanium/aluminum/titanium (Ti/Al/Ti), but is not limited thereto.
  • the patterning or patterning process may include only a photolithography process, or a photolithography process and an etching process, or may include other processes for forming a predetermined pattern, such as printing, inkjet, and the like.
  • the photolithography process refers to a process including film formation, exposure, development, and the like, and forms a pattern by using a photoresist, a mask, an exposure machine, or the like.
  • the corresponding patterning process can be selected in accordance with the structure formed in the embodiments of the present disclosure.
  • the manufacturing method of the display substrate provided in this embodiment is different from that in the first embodiment in that, as shown in FIG. 4A, the fourth insulating pattern 1180 is formed on the second insulating layer 112, and the fourth insulating pattern 1180 is formed.
  • a resin further including, for example, an acrylic resin or a polyimide resin, But it is not limited to this.
  • forming the fourth insulating pattern 1180 includes: forming a fourth insulating layer, forming a fourth photoresist layer on the fourth insulating layer, exposing and developing the fourth photoresist layer to form a fourth photoresist pattern, The fourth insulating layer is etched using the fourth photoresist pattern as a mask to form a fourth insulating pattern 1180.
  • FIG. 4B shows the first via 121 and the second via 122 formed.
  • FIG. 4C shows the formed third insulating pattern and the first connection structure 1171.
  • 4A of the present embodiment may correspond to the step of FIG. 3A
  • FIG. 4B may correspond to the step of FIG. 3G
  • FIG. 4C may correspond to the step of FIG. 3M, except that the fourth insulating pattern 1180 is disposed, which may be correspondingly referred to FIG. 3M.
  • the material of the first conductive pattern 1130 may be a transparent conductive metal oxide, but is not limited thereto.
  • Fig. 5 is a view showing the structure of a display substrate and a display area.
  • the manufacturing method of the display substrate provided in this embodiment includes the following steps.
  • a first metal pattern 101 is formed on the base substrate 100; a first insulating layer 111 is formed on the first metal pattern 101; a second metal pattern 102 is formed on the first insulating layer 111; A second insulating layer 112 is formed on the metal pattern 102; a first conductive layer 113 is formed on the second insulating layer 112.
  • the first metal pattern 101 includes a gate electrode 1013
  • the second metal pattern 102 includes a source electrode 1023 and a drain electrode 1024, which are further formed at a position corresponding to the gate electrode 1013 between the first insulating layer 111 and the second metal pattern 102.
  • a pattern of the active layer 119 is formed on the base substrate 100; a first insulating layer 111 is formed on the first metal pattern 101; a second metal pattern 102 is formed on the first insulating layer 111; A second insulating layer 112 is formed on the metal pattern 102; a first conductive layer 113 is formed on the second insulating layer 112.
  • the first conductive layer 113 is patterned to form a first conductive pattern 1130.
  • the second insulating layer 112 is patterned to form a second insulating pattern 1120.
  • the orthogonal projection of the first metal pattern 101 on the base substrate 100 and the orthographic projection of the second metal pattern 102 on the base substrate 100 have overlapping portions 1030.
  • the orthographic projection of the first conductive pattern 1130 on the substrate substrate 100 covers at least the overlapping portion 103.
  • the orthographic projection of the first conductive pattern 1130 on the substrate substrate 100 covers at least the overlapping portion 1030, so that the first conductive pattern 1130 can be dispersed to pattern the second insulating layer 112.
  • the static charge generated during the process avoiding the generation of static charge Bad coming.
  • the first metal pattern 101, the second metal pattern 102, and the first conductive pattern 1130 and the second conductive pattern 1170 are located in the display area 001, and the display area 001 includes a gate line 1012 and a data line 1022.
  • One of the first metal pattern 101 and the second metal pattern 102 includes a gate line 1012, the other includes a data line 1022, an orthographic projection of the gate line 1012 on the base substrate 100, and an orthographic projection of the data line 1022 on the base substrate 100
  • a plurality of gate lines 1012 are parallel to each other, and a plurality of data lines 1022 are parallel to each other.
  • the plurality of gate lines 1012 and the plurality of data lines 1022 cross each other and are insulated from each other, and define a plurality of sub-pixels 0010. It should be noted that, here is only an example, and the display area may also be other structures.
  • the thin film transistor can be divided into a top gate and a bottom gate structure according to the position of the gate with respect to the active layer, and can be divided into a top contact and a bottom contact structure according to the position of the source/drain electrode relative to the active layer.
  • the embodiment of the present disclosure is described by taking a thin film transistor of a bottom gate structure as an example, but a thin film transistor of a top gate structure may also be used.
  • the embodiment of the present disclosure is described by taking a thin film transistor of a top contact structure as an example.
  • the bottom contact thin film transistor can also be used, which is not limited by the embodiment of the present disclosure.
  • the first conductive pattern 1130 of the display region includes a second cover portion 1133 and a second conductive portion 1134, and during the patterning of the second insulating layer 112, the second cover portion
  • the orthographic projection of 1133 on the base substrate 100 covers at least the overlapping portion 1030.
  • the orthographic projection of the second cover portion 1133 on the base substrate 100 covers at least the overlapping portion 1030.
  • the method further includes forming a third insulating layer 116 and patterning the third insulating layer 116 to form a third insulating pattern 1160, the first metal pattern 101 and One of the second metal patterns 102 further includes a drain 1024, and at least two of the first insulating layer 111, the second insulating layer 112, and the third insulating layer 116 include a fifth portion corresponding to the drain 1024 and exposing the drain 1024. Via 125.
  • the second conductive pattern 1170 includes a second connection structure 1172 and a second electrode 1173.
  • the second connection structure 1172 electrically connects the drain 1024 and the first electrode 1134 to form a structure in which the pixel electrode 131 and the drain 1024 are electrically connected, and the second electrode 1173 is a common electrode 132.
  • the portion of the second conductive pattern in FIG. 6L other than the second connection structure 1172 is the common electrode 132.
  • the number of insulating layers through which the fifth via hole penetrates depends on the number of insulating layers provided between the pixel electrode and the drain.
  • the present disclosure does not limit the number of insulating layers provided, and the number of insulating layers may be determined as needed.
  • patterning the first conductive layer 113 to form the first conductive pattern 1130 includes:
  • a first photoresist layer 114 is formed on the first conductive layer 113;
  • the first photoresist layer 114 is exposed and developed to form a first photoresist pattern 1140.
  • the removed region of the first photoresist pattern 1140 includes a region corresponding to the position of the fifth via 121. ;
  • the first conductive layer 113 is etched by using the first photoresist pattern 1140 as a mask to form a first conductive pattern 1130.
  • patterning the second insulating layer 112 to form the second insulating pattern 1120 includes: etching the second insulating layer 112 by using the first photoresist pattern 1140 as a mask to form a second Insulation pattern 1120.
  • the removal of the first photoresist pattern 1140 also includes forming a structure as shown in FIG. 6F.
  • the method further includes forming a second photoresist pattern 1150 and using the second photoresist pattern 1150 as a mask to the first conductive pattern.
  • 1130 performs patterning to remove the second cover portion 1133 in the first conductive pattern 1130, leaving the second conductive portion 1134 in the first conductive pattern 1130.
  • forming the second photoresist pattern 1150 includes forming a second photoresist layer (forming a second photoresist layer on the structure shown in FIG. 6F), exposing and developing the second photoresist layer to form a first Two photoresist patterns 1150.
  • the second photoresist pattern 1150 is also removed.
  • the material of the first conductive pattern 1130, the second conductive pattern 1170, the first metal pattern 101, and the second metal pattern 102 refer to Embodiment 1, and details are not described herein again.
  • the material of the active layer 119 of the thin film transistor includes amorphous silicon, polycrystalline silicon, an oxide semiconductor, etc.
  • Further oxide semiconductors include, for example, Indium Gallium Zinc Oxide (IGZO) and Indium Zinc (Indium Zinc). Oxide, IZO), but not limited to this.
  • IGZO Indium Gallium Zinc Oxide
  • Oxide IZO
  • an etch stop layer may be disposed between the layer where the source and drain are located and the active layer to avoid the etchant to the active layer during the wet etching process of the source and drain electrodes. Damage, but Embodiments of the present disclosure are not limited thereto. The embodiment of the present disclosure does not limit the material of the active layer 119.
  • the present embodiment is different from Embodiment 3 in that the display substrate includes a fourth insulating pattern 1180.
  • the fifth insulating pattern 1180 includes a fifth via 125 penetrating through the fourth insulating layer.
  • both the display area 001 and the peripheral area adopt the method of the present disclosure, and the first conductive pattern is used to disperse the static charge generated in the manufacturing process.
  • the first metal pattern 101, the second metal pattern 102, the first conductive pattern 1130, and the second conductive pattern 1170 described in Embodiment 1 and/or Embodiment 2 are located in the peripheral region 002, and combined with Embodiment 3 or 4 That is the content of this embodiment.
  • the display area includes a plurality of gate lines 1012, a plurality of data lines 1022, a gate 1013, a source 1023, and a drain 1024.
  • the gate electrode 1013 is formed in the same layer as one of the first metal pattern 101 and the second metal pattern 102
  • the drain electrode 1024 is formed in the same layer as the other of the first metal pattern 101 and the second metal pattern 102
  • the first electrode 1134 and the first electrode A conductive pattern 1130 is formed in the same layer
  • the second electrode 1173 is formed in the same layer as the second conductive pattern 1170.
  • FIG. 6A-6E corresponds to the steps of FIG. 3A-3E
  • FIG. 6F-6L respectively corresponds to the steps of FIG. 3G-3M as an example. That is, FIG. 6A corresponds to FIG. 3A, FIG. 6B corresponds to FIG. 3B, and so on.
  • the previous forming steps are slightly different (the active layer 119 in which the thin film transistor is formed in FIG. 6A), in the subsequent steps, the display region does not need to be patterned for the first insulating layer, and may correspond to each other (first The insulating layer is patterned only in the peripheral area). Please refer to Figures 3A-3M and Figures 6A-6L for specific steps.
  • the second cover portion 1133 may not be provided in this embodiment. Only the overlapping portion of the peripheral area may be covered by the first conductive pattern.
  • the difference between this embodiment and the embodiment 5 is that the pattern structure of the first conductive pattern and the second conductive pattern of the display area is adjusted, and the fourth insulating pattern 1180 is provided.
  • the fourth insulation pattern 1180 reference may be made to the previous description.
  • the first electrode 1134 is a common electrode 132 and the second electrode 1173 is a pixel electrode 131.
  • the display substrate provided in this embodiment is formed by any of the methods described in Embodiments 1-6.
  • the display substrate can be, for example, an array substrate.
  • the display device provided in this embodiment includes any of the display substrates described in Embodiment 7.
  • the display device may be a display device such as a liquid crystal display, an electronic paper, an OLED (Organic Light-Emitting Diode) display, and a television, a digital camera, a mobile phone, a watch, a tablet, a notebook computer, and a navigation device including the display device. Any product or component that has a display function.
  • a display device such as a liquid crystal display, an electronic paper, an OLED (Organic Light-Emitting Diode) display, and a television, a digital camera, a mobile phone, a watch, a tablet, a notebook computer, and a navigation device including the display device. Any product or component that has a display function.

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Abstract

提供一种显示基板的制作方法、显示基板和显示装置。该显示基板的制作方法，包括：在衬底基板(100)上形成第一金属图形(101)；在第一金属图形(101)上形成第一绝缘层(111)；在第一绝缘层(111)上形成第二金属图形(102)；在第二金属图形(102)上形成第二绝缘层(112)；在第二绝缘层(112)上形成第一导电层(113)；对第一导电层(113)进行构图形成第一导电图形(1130)；在形成第一导电图形后，对第二绝缘层(112)进行构图形成第二绝缘图形(1120)；第一金属图形(101)在衬底基板(100)上的正投影和第二金属图形(102)在衬底基板(100)上的正投影具有重叠部分(103)；在对第二绝缘层(112)进行构图的过程中，第一导电图形(1130)在衬底基板(100)上的正投影至少覆盖重叠部分(103)。该显示基板的制作方法、显示基板和显示装置，可以避免在显示基板的制作过程中静电荷导致的不良的发生。

Description

显示基板的制作方法、显示基板和显示装置 技术领域
本公开至少一实施例涉及一种显示基板的制作方法、显示基板和显示装置。
背景技术
通常技术中，显示基板中包括多个绝缘层，在制作绝缘层图形(绝缘层的过孔)时，容易产生静电，而静电易对金属结构造成不良。
发明内容
本公开的至少一实施例涉及一种显示基板的制作方法、显示基板和显示装置，以避免在显示基板的制作过程中静电荷导致的不良的发生。
本公开的至少一实施例提供一种显示基板的制作方法，包括：
在衬底基板上形成第一金属图形；
在所述第一金属图形上形成第一绝缘层；
在所述第一绝缘层上形成第二金属图形；
在所述第二金属图形上形成第二绝缘层；
在所述第二绝缘层上形成第一导电层；
对所述第一导电层进行构图形成第一导电图形；
在形成所述第一导电图形后，对所述第二绝缘层进行构图形成第二绝缘图形；其中，
所述第一金属图形在所述衬底基板上的正投影和所述第二金属图形在所述衬底基板上的正投影具有重叠部分；
在对所述第二绝缘层进行构图的过程中，所述第一导电图形在所述衬底基板上的正投影至少覆盖所述重叠部分。
本公开的至少一实施例提供一种显示基板，采用本公开至少一实施例提供的方法形成。
本公开的至少一实施例提供一种显示装置，包括本公开至少一实施例提供的显示基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A为一种显示基板区域划分；
图1B为显示基板的周边区域的局部示意图；
图2为本公开实施例1提供的一种显示基板的制作方法流程图；
图3A-3M为本公开实施例1提供的一种显示基板的制作方法示意图，左边为沿图1B中A-B的剖视图，右边为沿图1B中C-D的剖视图；
图4A、4B、4C为本公开实施例2提供的包括第四绝缘图形的显示基板的制作方法部分步骤的示意图；
图5为显示基板以及显示基板的显示区示意图；
图6A-6L为本公开实施例3提供的一种显示基板的制作方法示意图，左边为沿图5中E-F的剖视图，右边为沿图5中G-H的剖视图；
图7为本公开实施例4提供的方法形成的设置有第四绝缘层的显示基板；
图8为本公开实施例6提供的方法形成的另一种显示基板。
附图标记：
001-显示区；002-周边区；100-衬底基板；101-第一金属图形；102-第二金属图形；103-(周边区域的)重叠部分；1030-(显示区域的)重叠部分；1011-第一端；1021-第二端；111-栅极绝缘层；111-第一绝缘层；112-第二绝缘层；113-第一导电层；114-第一光刻胶层；1140-第一光刻胶图形；1130-第一导电图形；1131-第一导电图形中的第一覆盖部；1132-第一导电图形中的第一导电部；1120-第二绝缘图形；1110-第一绝缘图形；1150-第二光刻胶图形；116-第三绝缘层；1160-第三绝缘图形；1170-第二导电图形；1171-第一连接结构；1180-第四绝缘图形；119-有源层；1012-栅线；1013-栅极；1022-数据线；119-有源层；1023-源极；1024-漏极；1172-第二连接结构；1173-第二电极；1133-第二覆盖部；1134-第一电极；131-像素电极；132-公共电极；0010-子像素。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
例如，通常的显示基板可包括形成在衬底基板的多个金属层，多个金属层中的金属图形中在垂直于衬底基板的方向上会具有重叠区域，而在后续的绝缘层过孔的制作过程中，产生的静电会对已有的金属结构尤其是重叠区域造成影响，例如击穿两个金属层例如重叠区域的金属层之间的绝缘层，从而产生不良。例如，多个金属层包括SD层和gate层。SD层例如包括数据线、源极和漏极中的至少一个或与数据线、源极和漏极中的至少一个同层形成的金属结构，gate层例如包括栅极和栅线中的至少一个或与栅极和栅线中的至少一个同层形成的金属结构，但不限于此。SD层和gate层中存在上述重叠区域，从而易有因静电带来的不良产生。
本公开的至少一实施例提供一种显示基板的制作方法，包括：
在衬底基板上形成第一金属图形；
在第一金属图形上形成第一绝缘层；
在第一绝缘层上形成第二金属图形；
在第二金属图形上形成第二绝缘层；
在第二绝缘层上形成第一导电层；
对第一导电层进行构图形成第一导电图形；
在形成第一导电图形后，对第二绝缘层进行构图形成第二绝缘图形；其中，
第一金属图形在衬底基板上的正投影和第二金属图形在衬底基板上的正投影具有重叠部分；
在对第二绝缘层进行构图的过程中，第一导电图形在衬底基板上的正投影至少覆盖重叠部分。
本公开的至少一实施例提供一种显示基板的制作方法，可以避免在显示基板的制作过程中静电荷导致的不良的发生。
如图1A所示，通常显示基板包括显示区001和设置在显示区001至少一侧的周边区002，图1A中以周边区002围绕显示区001设置为例进行说明，但不限于此。本实施例的方法适用于显示区001和周边区002至少之一。周边区因为布线更加密集，在绝缘图形(绝缘层过孔)制作过程中更易产生静电，效果也更明显。
以下根据几个具体的实施例进行说明。
实施例1
图1B中示出了周边区域002内的部分区域的平面示意图，图1B中在衬底基板100上设置有第一金属图形101和第二金属图形102，第一金属图形101和第二金属图形102之间绝缘设置，例如可在第一金属图形101和第二金属图形102之间设置有绝缘层。第一金属图形101在衬底基板100上的投影和第二金属图形102在衬底基板100上的投影存在重叠部分103。在显示基板的制作方法中，重叠部分103位置处易因静电引起不良产生。
如图2、图3A、3D-3E所示，本实施例提供一种显示基板的制作方法，包括如下步骤。
如图3A所示，在衬底基板100上形成第一金属图形101；在第一金属图形101上形成第一绝缘层111；在第一绝缘层111上形成第二金属图形102；在第二金属图形102上形成第二绝缘层112；在第二绝缘层112上形成第一导电层113。
如图3D所示，对第一导电层113进行构图形成第一导电图形1130。
如图3E所示，对第二绝缘层112进行构图形成第二绝缘图形1120。
如图3E所示，第一金属图形101在衬底基板100上的正投影和第二金属图形102在衬底基板100上的正投影具有重叠部分103。
在对第二绝缘层112进行构图的过程中，第一导电图形1130在衬底基板100上的正投影至少覆盖重叠部分103。
因在对第二绝缘层112进行构图的过程中，第一导电图形1130在衬底基板100上的正投影至少覆盖重叠部分103，从而第一导电图形1130可以分散对第二绝缘层112进行构图的过程中产生的静电荷，避免产生因静电荷带来的不良。
如图3F所示，一些示例中，还包括对第一绝缘层111进行构图形成第一绝缘图形1110，在对第一绝缘层111进行构图的过程中，第一导电图形1130在衬底基板100上的正投影至少覆盖重叠部分103。同样，因在第一绝缘图形1110制作过程中，重叠部分103被第一导电图形1130覆盖，第一导电图形1130可以分散对第一绝缘层111进行构图的过程中产生的静电荷，可避免产生因静电荷带来的不良。
如图1B和图3F所示，一些示例中，第一金属图形101还包括第一端1011，第二金属图形102还包括第二端1021，第一导电图形1130包括相互独立的第一覆盖部1131和第一导电部1132，第一覆盖部1131在衬底基板100上的正投影至少覆盖重叠部分103；第一导电图形1130、第二绝缘图形1120和第一绝缘图形1110中包括贯穿第一导电层113、第二绝缘层112和第一绝缘层111并暴露第一端1011的第一过孔121以及贯穿第一导电层113、第二绝缘层112并暴露第二端1021的第二过孔122。相互独立的第一覆盖部1131和第一导电部1132例如是指第一覆盖部1131和第一导电部1132不电连接，彼此绝缘。
如图3B-3D所示，一些示例中，对第一导电层113进行构图形成第一导电图形1130包括如下步骤。
如图3B所示，在第一导电层113上形成第一光刻胶层114。
如图3C所示，对第一光刻胶层114进行曝光、显影，形成第一光刻胶图形1140，第一光刻胶图形1140中被去除区域包括对应第一过孔121和第二过孔122位置处的区域。
如图3D所示，以第一光刻胶图形1140为掩膜对第一导电层113进行刻 蚀，形成第一导电图形1130。
如图3E-3F所示，一些示例中，对第二绝缘层112进行构图形成第二绝缘图形1120以及对第一绝缘层111进行构图形成第一绝缘图形1110包括如下步骤。
如图3E所示，以第一光刻胶图形1140为掩膜对第二绝缘层112进行刻蚀，形成第二绝缘图形1120。
如图3F所示，以第一光刻胶图形1140为掩膜对第一绝缘层111进行刻蚀，形成第一绝缘图形1110。
一些示例中，形成第一绝缘图形1110后，还包括去除第一光刻胶图形1140，形成如图3G所示的结构。
如图3H-3I所示，一些示例中，去除第一光刻胶图形1140之后，还包括形成第二光刻胶图形1150(如图3H所示)，并以第二光刻胶图形1150为掩膜对第一导电图形1130进行构图，去除第一导电图形1130中的第一覆盖部1131，保留第一导电图形1130中的第一导电部1132(如图3I所示)。例如，形成第二光刻胶图形1150包括形成第二光刻胶层(在图3G所示的结构上形成第二光刻胶层)，对第二光刻胶层进行曝光、显影，形成第二光刻胶图形1150。
如图3J所示，一些示例中，还包括去除第二光刻胶图形1150。
如图3K-3L所示，一些示例中，形成第二绝缘图形1120和第一绝缘图形1110之后，还包括形成第三绝缘层116(如图3K所示)并对第三绝缘层116进行构图形成第三绝缘图形1160(如图3L所示)，第三绝缘图形1160、第一导电图形1130、第二绝缘图形1120以及第一绝缘图形1110中包括：对应第一过孔121位置处贯通第三绝缘层116、第一导电层113、第二绝缘层112以及第一绝缘层111并暴露第一端1011的第三过孔123，以及对应第二过孔122位置处贯通第三绝缘层116、第一导电层113、第二绝缘层112并暴露第二端1021的第四过孔124。
如图3M所示，一些示例中，形成第三绝缘图形1160后，还包括形成第二导电图形1170，第二导电图形1170包括第一连接结构1171，第一连接结构1171通过第三过孔123和第四过孔124将第一端1011和第二端1021电连接。例如，形成第二导电图形1170包括：形成第二导电层(在图3L所示结 构的基础上形成第二导电层)，在第二导电层上形成第三光刻胶层，对第三光刻胶层进行曝光、显影，形成第三光刻胶图形，以第三光刻胶图形为掩膜对第二导电层进行刻蚀，形成第二导电图形。
如图3M所示，一些示例中，第一连接结构1171将在第三过孔123和第四过孔124位置处断开的第一导电部1132电连接。从而，第一导电部1132经第三过孔123和第四过孔124处的第一连接结构1171将第一端1011和第二端1021电连接，可增加第一端1011和第二端1021电连接的稳定性。
一些示例中，第一导电图形1130的材质包括透明导电金属氧化物、金属中至少之一。透明导电金属氧化物例如包括氧化铟锡(Indium Tin Oxide，ITO)，但不限于此。
一些示例中，第二导电图形1170的材质包括透明导电金属氧化物，但不限于此。
一些示例中，第一绝缘层111、第二绝缘层112和第三绝缘层116至少一个的材质包括氮化硅(SiNx)、氧化硅(SiOx)、氮氧化硅(SiNxOy)、氧化铝中的至少一个，但不限于此。
一些示例中，第一金属图形101可通过形成第一金属层，对第一金属层进行构图工艺形成，第二金属图形102可通过形成第二金属层，对第二金属层进行构图工艺形成，但不限于此。例如，第一金属图形101和第二金属图形102包括钼(Mo)、钼铌合金、铝(Al)、铝钕合金(AlNd)、钛(Ti)和铜(Cu)中的任一种形成的单层结构，或为采用钼/铝/钼(Mo/Al/Mo)、钛/铝/钛(Ti/Al/Ti)形成子层得到的叠层结构，但不限于此。
在本公开的实施例中，构图或构图工艺可只包括光刻工艺，或包括光刻工艺以及刻蚀步骤，或者可以包括打印、喷墨等其他用于形成预定图形的工艺。光刻工艺是指包括成膜、曝光、显影等工艺过程，利用光刻胶、掩模板、曝光机等形成图形。可根据本公开的实施例中所形成的结构选择相应的构图工艺。
实施例2
本实施例提供的显示基板的制作方法与实施例1的不同之处在于：如图4A所示，还包括形成位于第二绝缘层112之上的第四绝缘图形1180，第四绝缘图形1180材质包括树脂，进一步例如包括亚克力树脂或聚酰亚胺树脂， 但不限于此。
例如，形成第四绝缘图形1180包括：形成第四绝缘层，在第四绝缘层上形成第四光刻胶层，对第四光刻胶层进行曝光、显影，形成第四光刻胶图形，以第四光刻胶图形为掩膜对第四绝缘层进行刻蚀，形成第四绝缘图形1180。
图4B示出了形成的第一过孔121和第二过孔122。图4C示出了形成的第三绝缘图形以及第一连接结构1171。本实施例的图4A可与图3A的步骤对应，图4B可与图3G的步骤对应，图4C可与图3M的步骤对应，只是多设置了第四绝缘图形1180，可对应参照图3A-3M。
其余可参照实施例1，在此不再赘述。
实施例3
本实施例提供的显示基板的制作方法中，只显示区采用本公开的方法。此情况下，第一导电图形1130的材质可选用透明导电金属氧化物，但不限于此。图5示出了显示基板以及显示区的结构示意图。
如图5、6A-6L所示，本实施例提供的显示基板的制作方法包括如下步骤。
如图6A所示，在衬底基板100上形成第一金属图形101；在第一金属图形101上形成第一绝缘层111；在第一绝缘层111上形成第二金属图形102；在第二金属图形102上形成第二绝缘层112；在第二绝缘层112上形成第一导电层113。一些示例中，第一金属图形101包括栅极1013，第二金属图形102包括源极1023和漏极1024，在第一绝缘层111和第二金属图形102之间对应栅极1013位置处还形成有源层119的图形。
如图6D所示，对第一导电层113进行构图形成第一导电图形1130。
如图6E所示，对第二绝缘层112进行构图形成第二绝缘图形1120。
如图5、图6E所示，第一金属图形101在衬底基板100上的正投影和第二金属图形102在衬底基板100上的正投影具有重叠部分1030。
如图6D、6E所示，在对第二绝缘层112进行构图的过程中，第一导电图形1130在衬底基板100上的正投影至少覆盖重叠部分103。
因在对第二绝缘层112进行构图的过程中，第一导电图形1130在衬底基板100上的正投影至少覆盖重叠部分1030，从而第一导电图形1130可以分散对第二绝缘层112进行构图的过程中产生的静电荷，避免产生因静电荷带 来的不良。
一些示例中，如图5所示，第一金属图形101、第二金属图形102和第一导电图形1130和第二导电图形1170位于显示区001，显示区001包括栅线1012和数据线1022，第一金属图形101和第二金属图形102之一包括栅线1012，另一个包括数据线1022，栅线1012在衬底基板100上的正投影和数据线1022在衬底基板100上的正投影具有重叠部分1030。例如，如图5所示，多条栅线1012相互平行，多条数据线1022相互平行。多条栅线1012和多条数据线1022相互交叉且彼此绝缘，并限定出多个子像素0010。需要说明的是，此处只是例举，显示区亦可为其他结构。
薄膜晶体管按照栅极相对于有源层位置可以分为顶栅和底栅结构，按照源漏电极相对于有源层位置可分为顶接触和底接触结构。需要说明的是，本公开的实施例以底栅结构的薄膜晶体管为例进行说明，但亦可采用顶栅结构的薄膜晶体管，本公开的实施例以顶接触结构的薄膜晶体管为例进行说明，但亦可采用底接触的薄膜晶体管，本公开的实施例对此不作限定。
一些示例中，如图6D、6E所示，显示区的第一导电图形1130包括第二覆盖部1133和第二导电部1134，在对第二绝缘层112进行构图的过程中，第二覆盖部1133在衬底基板100上的正投影至少覆盖重叠部分1030。在对第二绝缘层112进行构图的过程中，第二覆盖部1133在衬底基板100上的正投影至少覆盖重叠部分1030。
如图6J-6L所示，一些示例中，形成第二绝缘图形1120之后，还包括形成第三绝缘层116并对第三绝缘层116进行构图形成第三绝缘图形1160，第一金属图形101和第二金属图形102之一还包括漏极1024，第一绝缘层111、第二绝缘层112和第三绝缘层116中至少两层中包括对应漏极1024位置处并暴露漏极1024的第五过孔125。
如图6L所示，一些示例中，形成第三绝缘图形1160后，还包括形成第二导电图形1170，第二导电图形1170包括第二连接结构1172和第二电极1173。通过第五过孔125，第二连接结构1172将漏极1024和第一电极1134电连接，形成像素电极131与漏极1024电连接的结构，第二电极1173为公共电极132。图6L中的第二导电图形除了第二连接结构1172外的部分为公共电极132。
需要说明的是，第五过孔贯穿的绝缘层的个数依照像素电极与漏极之间设置的绝缘层的个数而定。本公开对设置的绝缘层的个数不做限定，绝缘层的个数可依据需要而定。
如图6B-6D所示，一些示例中，对第一导电层113进行构图形成第一导电图形1130包括：
如图6B所示，在第一导电层113上形成第一光刻胶层114；
如图6C所示，对第一光刻胶层114进行曝光、显影，形成第一光刻胶图形1140，第一光刻胶图形1140中被去除区域包括对应第五过孔121位置处的区域；
如图6D所示，以第一光刻胶图形1140为掩膜对第一导电层113进行刻蚀，形成第一导电图形1130。
如图6E所示，一些示例中，对第二绝缘层112进行构图形成第二绝缘图形1120包括：以第一光刻胶图形1140为掩膜对第二绝缘层112进行刻蚀，形成第二绝缘图形1120。
一些示例中，还包括去除第一光刻胶图形1140，形成如图6F所示的结构。
如图6G-6H所示，一些示例中，去除第一光刻胶图形1140之后，还包括形成第二光刻胶图形1150，并以第二光刻胶图形1150为掩膜对第一导电图形1130进行构图，去除第一导电图形1130中的第二覆盖部1133，保留第一导电图形1130中的第二导电部1134。例如，形成第二光刻胶图形1150包括形成第二光刻胶层(在图6F所示的结构上形成第二光刻胶层)，对第二光刻胶层进行曝光、显影，形成第二光刻胶图形1150。
如图6I所示，一些示例中，还包括去除第二光刻胶图形1150。
有关第一导电图形1130、第二导电图形1170、第一金属图形101、第二金属图形102的材质可参见实施例1，在此不再赘述。
一些示例中，薄膜晶体管的有源层119的材质包括非晶硅、多晶硅、氧化物半导体等，进一步氧化物半导体例如包括氧化铟镓锌(Indium Gallium Zinc Oxide，IGZO)和氧化铟锌(Indium Zinc Oxide，IZO)，但不限于此。例如，有源层采用氧化物半导体时，源漏极所在的层和有源层之间可以设置刻蚀阻挡层，以避免在源漏极的湿法刻蚀过程中刻蚀液对有源层的损伤，但 本公开的实施例并不限于此。本公开的实施例对于有源层119的材质不作限定。
实施例4
如图7所示，本实施例与实施例3的不同之处在于：显示基板包括第四绝缘图形1180。第四绝缘图形1180中包括贯穿第四绝缘层的第五过孔125。
实施例5
在实施例1和/或实施例2的基础上，本实施例中显示区001和周边区均采用本公开的方法，采用第一导电图形来分散在制作过程中产生的静电荷。
例如，实施例1和/或实施例2中所述的第一金属图形101、第二金属图形102、第一导电图形1130和第二导电图形1170位于周边区002，并结合实施例3或4，即为本实施例的内容。如图6A-6L所示，显示区包括多条栅线1012、多条数据线1022、栅极1013、源极1023和漏极1024。
例如，栅极1013与第一金属图形101和第二金属图形102之一同层形成，漏极1024与第一金属图形101和第二金属图形102中另一个同层形成，第一电极1134与第一导电图形1130同层形成，第二电极1173与第二导电图形1170同层形成。
需要说明的是，本实施例中的以图6A-6E分别对应图3A-3E的步骤，图6F-6L分别对应图3G-3M的步骤为例进行说明。即图6A对应图3A，图6B对应图3B，以此类推。虽然在之前形成步骤稍有不同(图6A中形成有薄膜晶体管的有源层119)，但在后续的步骤中除了显示区域不需要对第一绝缘层进行图形化外均可相互对应(第一绝缘层进行图形化仅在周边区进行)。具体步骤请参照图3A-3M、图6A-6L。
需要说明的是，本实施例也可以不设置第二覆盖部1133。仅周边区域的重叠部分被第一导电图形覆盖即可。
实施例6
本实施例与实施例5的区别在于：调整了显示区的第一导电图形和第二导电图形的图形结构，并且设置了第四绝缘图形1180。有关第四绝缘图形1180可参照之前描述。
如图8所示，一些示例中，第一电极1134为公共电极132，第二电极1173为像素电极131。
实施例7
本实施例提供的显示基板，采用实施例1-6中所述的任一方法形成。显示基板例如可为阵列基板。
实施例8
本实施例提供的显示装置，包括实施例7所述的任一显示基板。
例如，显示装置可以为液晶显示器、电子纸、OLED(Organic Light-Emitting Diode，有机发光二极管)显示器等显示器件以及包括这些显示器件的电视、数码相机、手机、手表、平板电脑、笔记本电脑、导航仪等任何具有显示功能的产品或者部件。
有以下几点需要说明：
(1)除非另作定义，本公开的实施例以及附图中同一标号代表同一含义。
(2)本公开实施例附图中，只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(3)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
(4)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。
本专利申请要求于2016年5月27日递交的中国专利申请第201610366137.8号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (22)

  1. 一种显示基板的制作方法，包括：
    在衬底基板上形成第一金属图形；
    在所述第一金属图形上形成第一绝缘层；
    在所述第一绝缘层上形成第二金属图形；
    在所述第二金属图形上形成第二绝缘层；
    在所述第二绝缘层上形成第一导电层；
    对所述第一导电层进行构图形成第一导电图形；
    在形成所述第一导电图形后，对所述第二绝缘层进行构图形成第二绝缘图形；其中，
    所述第一金属图形在所述衬底基板上的正投影和所述第二金属图形在所述衬底基板上的正投影具有重叠部分；
    在对所述第二绝缘层进行构图的过程中，所述第一导电图形在所述衬底基板上的正投影至少覆盖所述重叠部分。
  2. 根据权利要求1所述的显示基板的制作方法，还包括对所述第一绝缘层进行构图形成第一绝缘图形，其中，在对所述第一绝缘层进行构图的过程中，所述第一导电图形在所述衬底基板上的正投影至少覆盖所述重叠部分。
  3. 根据权利要求2所述的显示基板的制作方法，其中，所述第一金属图形还包括第一端，所述第二金属图形还包括第二端，所述第一导电图形包括相互独立的第一覆盖部和第一导电部，所述第一覆盖部在所述衬底基板上的正投影至少覆盖所述重叠部分；所述第一导电图形、所述第二绝缘图形和所述第一绝缘图形中包括贯穿所述第一导电层、所述第二绝缘层和所述第一绝缘层并暴露所述第一端的第一过孔以及贯穿所述第一导电层、所述第二绝缘层并暴露所述第二端的第二过孔。
  4. 根据权利要求3所述的显示基板的制作方法，其中，对所述第一导电层进行构图形成第一导电图形包括：
    在所述第一导电层上形成第一光刻胶层；
    对所述第一光刻胶层进行曝光、显影，形成第一光刻胶图形，其中，所述第一光刻胶图形中被去除区域包括对应所述第一过孔和所述第二过孔位置 处的区域；
    以所述第一光刻胶图形为掩膜对所述第一导电层进行刻蚀，形成所述第一导电图形。
  5. 根据权利要求4所述的显示基板的制作方法，对所述第二绝缘层进行构图形成所述第二绝缘图形以及对所述第一绝缘层进行构图形成所述第一绝缘图形包括：
    以所述第一光刻胶图形为掩膜对所述第二绝缘层进行刻蚀，形成所述第二绝缘图形；
    以所述第一光刻胶图形为掩膜对所述第一绝缘层进行刻蚀，形成所述第一绝缘图形。
  6. 根据权利要求5所述的显示基板的制作方法，形成所述第一绝缘图形后，还包括去除所述第一光刻胶图形。
  7. 根据权利要求6所述的显示基板的制作方法，去除所述第一光刻胶图形之后，还包括形成第二光刻胶图形，并以所述第二光刻胶图形为掩膜对所述第一导电图形进行构图，去除所述第一导电图形中的所述第一覆盖部，保留所述第一导电图形中的第一导电部。
  8. 根据权利要求7所述的显示基板的制作方法，还包括去除所述第二光刻胶图形。
  9. 根据权利要求3-8任一项所述的显示基板的制作方法，形成所述第二绝缘图形和所述第一绝缘图形之后，还包括形成第三绝缘层并对所述第三绝缘层进行构图形成第三绝缘图形，其中，所述第三绝缘图形、所述第一导电图形、所述第二绝缘图形以及所述第一绝缘图形中包括：对应所述第一过孔位置处贯通所述第三绝缘层、所述第一导电层、所述第二绝缘层以及所述第一绝缘层并暴露所述第一端的第三过孔，以及对应所述第二过孔位置处贯通所述第三绝缘层、所述第一导电层、所述第二绝缘层并暴露所述第二端的第四过孔。
  10. 根据权利要求9所述的显示基板的制作方法，形成所述第三绝缘图形后，还包括形成第二导电图形，其中，所述第二导电图形包括第一连接结构，所述第一连接结构通过所述第三过孔和所述第四过孔将所述第一端和所述第二端电连接。
  11. 根据权利要求10所述的显示基板的制作方法，其中，所述第一连接结构将在所述第三过孔和所述第四过孔位置处断开的所述第一导电部电连接，从而所述第一导电部经所述第三过孔和所述第四过孔处的所述第一连接结构将所述第一端和所述第二端电连接。
  12. 根据权利要求10所述的显示基板的制作方法，其中，所述显示基板包括显示区和设置在所述显示区至少一侧的周边区，所述第一金属图形、所述第二金属图形、所述第一导电图形和所述第二导电图形位于所述周边区，所述显示区包括栅极、漏极、第一电极和第二电极，所述栅极与所述第一金属图形和所述第二金属图形之一同层形成，所述漏极与所述第一金属图形和所述第二金属图形中另一个同层形成，所述第一电极与所述第一导电图形同层形成，所述第二电极与所述第二导电图形同层形成。
  13. 根据权利要求12所述的显示基板的制作方法，其中，所述第一电极和所述第二电极之一为像素电极，另一个为公共电极。
  14. 根据权利要求12所述的显示基板的制作方法，其中，所述显示区还包括与所述第二导电图形同层形成的第二连接结构，所述第二连接结构将所述漏极和所述第一电极电连接，形成像素电极与所述漏极电连接的结构，所述第二电极为公共电极。
  15. 根据权利要求1所述的显示基板的制作方法，其中，所述显示基板包括显示区和设置在所述显示区至少一侧的周边区，所述第一金属图形、所述第二金属图形和所述第一导电图形位于所述显示区，所述显示区包括栅线和数据线，所述第一金属图形和所述第二金属图形之一包括所述栅线，另一个包括所述数据线，所述栅线在所述衬底基板上的正投影和所述数据线在所述衬底基板上的正投影具有所述重叠部分。
  16. 根据权利要求15所述的显示基板的制作方法，形成所述第二绝缘图形之后，还包括形成第三绝缘层并对所述第三绝缘层进行构图形成第三绝缘图形，其中，所述第一金属图形和所述第二金属图形之一还包括漏极，所述第一绝缘层、所述第二绝缘层和所述第三绝缘层中至少两层中包括对应所述漏极位置处并暴露所述漏极的第五过孔。
  17. 根据权利要求16所述的显示基板的制作方法，形成所述第三绝缘图形后，还包括形成第二导电图形；所述第一导电图形包括公共电极，所述第 二导电图形包括像素电极，所述像素电极经所述第五过孔与所述漏极电连接。
  18. 根据权利要求16所述的显示基板的制作方法，其中，形成所述第三绝缘图形后，还包括形成第二导电图形，所述第二导电图形包括第二连接结构和公共电极；所述第一导电图形包括第二覆盖部和第二导电部，在对所述第二绝缘层进行构图的过程中，所述第二覆盖部在所述衬底基板上的正投影至少覆盖所述重叠部分；通过所述第五过孔，所述第二连接结构将所述漏极和所述第二导电部电连接，形成像素电极与所述漏极电连接的结构。
  19. 根据权利要求1-18任一项所述的显示基板的制作方法，其中，所述第一导电图形的材质包括导电金属氧化物、金属中至少之一。
  20. 根据权利要求1-18任一项所述的显示基板的制作方法，还包括形成位于所述第二绝缘层之上的第四绝缘图形，其中，所述第四绝缘图形材质包括树脂。
  21. 一种显示基板，采用权利要求1-20任一项所述的方法形成。
  22. 一种显示装置，包括权利要求21所述的显示基板。
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