WO2017202035A1 - 像素单元及其制备方法、阵列基板和显示装置 - Google Patents

像素单元及其制备方法、阵列基板和显示装置 Download PDF

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Publication number
WO2017202035A1
WO2017202035A1 PCT/CN2017/070258 CN2017070258W WO2017202035A1 WO 2017202035 A1 WO2017202035 A1 WO 2017202035A1 CN 2017070258 W CN2017070258 W CN 2017070258W WO 2017202035 A1 WO2017202035 A1 WO 2017202035A1
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Prior art keywords
pixel
layer
pixel electrode
electrode
defining layer
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PCT/CN2017/070258
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English (en)
French (fr)
Inventor
董向丹
李坤
代磊
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to EP17737196.0A priority Critical patent/EP3282483A4/en
Priority to US15/544,666 priority patent/US20180158886A1/en
Publication of WO2017202035A1 publication Critical patent/WO2017202035A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/81—Anodes
    • H10K50/813—Anodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/82—Cathodes
    • H10K50/822—Cathodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H10K59/80515—Anodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8052—Cathodes
    • H10K59/80521—Cathodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes

Definitions

  • the present invention relates to the field of technical display technologies, and in particular, to a pixel unit in an organic light emitting diode display device, a method for fabricating the same, an array substrate, and a display device.
  • An organic light emitting diode display device is a novel light emitting technology that emits light by exciting radiation of organic matter.
  • the OLED driving method is divided into active driving and passive driving.
  • the active driving uses a thin film transistor (TFT) as a driving device, and the pixel unit is driven by a corresponding TFT to form a TFT driving array, wherein a low temperature polysilicon thin film transistor (LTPS) is used.
  • TFT thin film transistor
  • LTPS low temperature polysilicon thin film transistor
  • the -TFT)-driven OLED has the advantages of faster electron migration rate, smaller film circuit area, higher resolution, simple structure and high stability.
  • At least one object of the present invention is to provide a pixel unit capable of avoiding color mixing, and the preparation method thereof is simple in flow, low in cost, and does not affect the illuminating effect.
  • Another object of the present invention is to provide a method for preparing a pixel unit, wherein the pixel unit can avoid color mixing, and the preparation method has a simple flow and a low cost, and does not affect the illuminating effect.
  • Still another object of the present invention is to provide an array substrate in which pixel units can avoid color mixing, and the preparation method has a simple flow and low cost, and does not affect the illuminating effect.
  • the element can avoid the occurrence of color mixing, and the preparation method has a simple process and a low cost, and does not affect the luminous effect.
  • a pixel unit includes: a pixel defining layer, a pixel electrode, a light emitting layer, and a common electrode; wherein the pixel defining layer has a first via, and the pixel electrode, the light emitting layer, and the common electrode are stacked on a first via hole; the pixel electrode includes a bottom surface and a side surface extending along a sidewall of the first via hole to a top portion of the sidewall of the first via hole; a light emitting layer is formed on the pixel electrode and covering the pixel electrode, and the common electrode is formed on On the luminescent layer, the luminescent layer is covered and extends along the top surface of the pixel defining layer.
  • the sidewalls of the first via of the pixel defining layer are formed as a planar surface, an outwardly convex curved convex surface, an inwardly concave curved concave surface or a stepped shape.
  • the pixel electrode extends to a top surface of the pixel defining layer, the end of the pixel electrode is on a top surface of the pixel defining layer, and the ends of the light emitting layer and the common electrode are both stepped.
  • the pixel unit further includes a protective layer formed on the pixel defining layer and covering the end of the pixel electrode, the luminescent layer covering the protective layer.
  • the pixel unit further includes: a planarization layer having a second via hole at a position corresponding to an output end of the driving thin film transistor, the pixel defining layer being formed on the planarization layer, the first via hole Located directly above the second via and through the second via.
  • an array substrate comprising any of the above pixel units is provided.
  • a display device including the above array substrate is provided.
  • a method for fabricating a pixel unit for preparing the pixel unit includes: forming a pixel defining layer, and opening a first via in the pixel defining layer; Forming a pixel electrode in the via hole, wherein the pixel electrode is formed with a bottom surface and a side surface extending along a sidewall of the first via hole to a top portion of the sidewall of the first via hole; forming a light emitting layer covering the pixel electrode; and forming a cover light A common electrode of the layer and extending along the top surface of the pixel defining layer.
  • forming the pixel defining layer and opening the first via in the pixel defining layer comprises: depositing two layers of organic materials in sequence, forming a second via of the planarization layer and a first of the pixel defining layer by one patterning process Through hole.
  • the pixel electrode and the formation via are formed in the first via of the pixel defining layer
  • the light-emitting layer covering the pixel electrode further includes: depositing an organic material in the pixel defining layer, forming a pad spacer layer and a protective layer covering the end of the pixel electrode by one patterning process; forming the light-emitting layer covering the pixel electrode comprises: on the pixel electrode A light emitting layer covering the pixel electrode and the protective layer is formed.
  • FIG. 1 is a schematic structural view of a pixel unit of a conventional low temperature polysilicon thin film transistor organic light emitting diode (LTPS-TFT OLED) display device;
  • LTPS-TFT OLED organic light emitting diode
  • FIG. 2 is a schematic structural diagram of a pixel unit according to a first embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a pixel unit according to a second embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a pixel unit according to a third embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a pixel unit according to a fourth embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of a pixel unit according to a fifth embodiment of the present invention.
  • FIG. 7 is a flow chart of a method for fabricating a pixel unit according to an eighth embodiment of the present invention.
  • a pixel unit of a conventional low temperature polysilicon thin film transistor organic light emitting diode (LTPS-TFT OLED) display device is as shown in FIG. 1.
  • the pixel unit generally includes a low temperature polysilicon thin film transistor as a driving thin film transistor 100, a planarization layer 200, and a pixel defining layer. 300, the pixel electrode 400, the light-emitting layer 500, the common electrode 600, and the like, the two sides of the light-emitting layer 500 directly contact the pixel defining layer 300, and the light emitted by the light-emitting layer 500 will be scattered around the pixel defining layer 300, and other pixel units around it The scattered light is mixed, which seriously affects the display effect.
  • LTPS-TFT OLED organic light emitting diode
  • the fabrication sequence in the process of fabricating the pixel unit shown in FIG. 1 is generally polysilicon, gate insulating layer (Gatel), gate (Gate 2), inter-layer deposited layer (ILD), and source drain.
  • planarization layer 200 via hole and the pixel defining layer 300 via hole are sequentially prepared by two processes, so To have two sets of masks, the process is more complicated and the cost is higher.
  • the pixel electrode 400 is formed first to form the pixel defining layer 300, and the pixel electrode material residue after the process of forming the pixel defining layer 300 contaminates the pixel electrode 400, thereby affecting the light emitting effect. Therefore, there is an urgent need in the art for a pixel electrode preparation method capable of avoiding the occurrence of a color mixture phenomenon and having a simple pixel flow and a low cost without affecting the light-emitting effect.
  • FIG. 2 is a schematic structural view of a pixel unit according to a first embodiment of the present invention.
  • the pixel unit is formed on the driving thin film transistor, and includes a planarization layer (PLN layer) 200, a pixel defining layer (PDL layer) 300, a pixel electrode 400, a light emitting layer 500, and a common electrode 600.
  • PNL layer planarization layer
  • PDL layer pixel defining layer
  • a pixel electrode 400 a light emitting layer 500
  • a common electrode 600 common electrode 600.
  • the driving thin film transistor may be a low temperature polysilicon thin film transistor including a substrate 101, a buffer layer 102 formed on the substrate 101, an output electrode 103 formed on the buffer layer 102, a channel 104, and an input electrode 105.
  • a gate insulating layer 106 formed on the buffer layer 102 and the output electrode 103, the channel 104 and the input electrode 105, and a control terminal 107 formed on the gate insulating layer 106, formed on the control terminal 107 and the gate insulating layer 106
  • the upper inter-layer deposited layer 108 (ILD layer), the output via 103 and the input electrode 105 respectively have a third via 111 and a fourth via 112 extending through the inter-layer deposited layer 108 and the gate insulating layer 106, respectively.
  • One end of the terminal 109 and the input end 110 are respectively connected to the output electrode 103 and the input pole 105, and are respectively led out by the third via hole 111 and the fourth via hole 112, and the other end is exposed on the interlayer deposition layer 108.
  • the control terminal 107 is the gate of the driving thin film transistor, the input terminal 105 is the drain thereof, the input terminal 110 is the drain metal, and the output terminal 103 is the source thereof.
  • the output terminal 109 is a source metal; if a P-type thin film transistor is selected, the control terminal 107 is a gate of the driving thin film transistor, the input electrode 105 is a source thereof, the input terminal 110 is a source metal, and the output terminal 103 is The drain, the output terminal 109 is a drain metal.
  • the planarization layer 200 is formed on the interlayer deposition layer 108 and the output terminal 109 of the driving thin film transistor, and on the input terminal 110, and has a second via 201 directly above the output terminal 109.
  • the pixel defining layer 300 is formed on the planarization layer 200, and a first via hole 301 is formed directly above the second via hole 201.
  • the first via hole 301 is larger in size than the second via hole 201, and is connected to the second via hole 201. .
  • the pixel electrode 400, the light emitting layer 500 and the common electrode 600 are sequentially formed on the pixel defining layer 300.
  • the pixel electrode 400 includes a bottom surface portion and a side surface portion. The bottom surface portion covers the bottom of the first via hole 301 and passes through the second via hole 201 and the output.
  • the terminal 109 is connected, the side portion extends along the sidewall 302 of the first via 301 to the top of the sidewall 302 of the first via 301, and the light emitting layer 500 is formed on the pixel electrode.
  • the common electrode 600 is formed on the light emitting layer 500, and covers the light emitting layer 500 and extends along the top surface of the pixel defining layer 300.
  • the pixel electrode 400 is a reflective electrode formed of an indium tin oxide/silver/indium tin oxide (ITO/Ag/ITO) material, or is formed of an opaque conductive material.
  • ITO/Ag/ITO indium tin oxide/silver/indium tin oxide
  • the pixel electrode 400 since the pixel electrode 400 exists between the pixel defining layer 300 and the light emitting layer 500, the light portion emitted by the light emitting layer 500 is reflected by the reflective electrode formed of the ITO/Ag/ITO material, or is opaque.
  • the conductive material is blocked, so that the light scattered by the light-emitting layer 500 to the surroundings is greatly reduced, so that the color mixing phenomenon between the pixel units is greatly improved, and the color mixing problem caused by light scattering is effectively solved.
  • the pixel electrode 400 has a side portion, which increases the area of the pixel electrode 400, so that the contact area of the pixel electrode 400 with the light-emitting layer 500 is increased, and the light-emitting area of the pixel unit is increased without changing the aperture ratio of the pixel unit. Increases overall brightness.
  • the substrate 101 is a glass material
  • the buffer layer 102 is silicon nitride (SiN x ) or silicon dioxide (SiO 2 ) or aluminum (Al) or aluminum oxide (Al 2 O 3 ) material
  • 103, the channel 104 and the input electrode 105 are polysilicon (P-Si) materials
  • the gate insulating layer 106 is silicon dioxide (SiO 2 ) or silicon dioxide (SiO 2 ) / silicon nitride (SiN x ) double-layer material Or TEOS material
  • the control terminal 107 is a molybdenum crucible material
  • the output terminal 109 and the input terminal 110 are Ti-Al-Ti materials
  • the interlayer deposition layer 108 is a silicon nitride (SiN x ) or silicon dioxide (SiO 2 ) material.
  • the planarization layer 200 is an organic film material; the pixel defining layer 300 is a polyimide (PI) material; the light emitting layer 500 is an organic light emitting material such as Alq, Balq, and DPVBi; and the common electrode 600 is a metal alloy such as Mg- Ag.
  • PI polyimide
  • the pixel electrode 400 may further extend to the top surface of the pixel defining layer 300, the end of the pixel electrode 400 is located on the top surface of the pixel defining layer 300; and the light emitting layer end portion 501 is stepped.
  • the end of the pixel electrode 400 is covered; the common electrode end portion 601 is stepped and covers the light emitting layer end portion 501 and extends along the top surface of the pixel defining layer 300.
  • This further increases the area of the pixel electrode 400 and the light-emitting layer 500, so that the contact area of the pixel electrode 400 and the light-emitting layer 500 is further increased, and the color mixing problem caused by light scattering is prevented without changing the aperture ratio of the pixel unit.
  • the overall brightness is further improved.
  • FIG. 3 is a pixel unit according to a second embodiment of the present invention.
  • any technical features of the above-described first embodiment that can be used for the same application are all described herein, and the same description is not required. Only the technical features different from the first embodiment in the second embodiment will be described below.
  • the sidewall 302 of the first via 301 of the pixel defining layer 300 has an outwardly convex curved convex surface, and the side of the pixel electrode 400 extends along the curved convex sidewall 302 of the first via 301 to the sidewall of the first via 301
  • a light-emitting layer 500 is formed on the pixel electrode 400 and covered by the pixel defining layer 300.
  • the common electrode 600 is formed on the light-emitting layer 500, and covers the light-emitting layer 500 and extends along the top surface of the pixel defining layer 300.
  • the area of the sidewall 302 of the first via 301 of the pixel unit of the second embodiment is larger than the area of the sidewall 302 of the first via 301 of the pixel unit of the first embodiment, further increasing the area of the pixel electrode 400 and the luminescent layer 500, so that the pixel The contact area between the electrode 400 and the light-emitting layer 500 is further increased, and the overall brightness is further improved while preventing the color mixing problem caused by light scattering without changing the aperture ratio of the pixel unit.
  • the pixel electrode 400 may further extend to the top surface of the pixel defining layer 300, the end of the pixel electrode 400 is located on the top surface of the pixel defining layer 300; and the light emitting layer end portion 501 is stepped.
  • the end of the pixel electrode 400 is covered; the common electrode end portion 601 is stepped and covers the light emitting layer end portion 501 and extends along the top surface of the pixel defining layer 300, which further increases the pixel electrode 400 and the light emitting layer 500.
  • the area is such that the contact area of the pixel electrode 400 and the light-emitting layer 500 is further increased, and the overall brightness is further improved while preventing the color mixing problem caused by light scattering without changing the aperture ratio of the pixel unit.
  • FIG. 4 is a pixel unit according to a third embodiment of the present invention.
  • any technical features that can be used in the same application in any of the above embodiments are the same, and the same description is not required. Only the technical features different from the other embodiments in the third embodiment will be described below.
  • the sidewall 302 of the first via 301 of the pixel defining layer 300 has an arcuate concave surface recessed inwardly, and the side of the pixel electrode 400 extends along the curved concave sidewall 302 of the first via 301 to the sidewall 302 of the first via 301
  • the light emitting layer 500 is formed on the pixel electrode 400 and covers the pixel defining layer 300.
  • the common electrode 600 is formed on the light emitting layer 500, and covers the light emitting layer 500 and extends along the top surface of the pixel defining layer 300.
  • the area of the sidewall 302 of the first via 301 of the pixel unit of the third embodiment is larger than the area of the sidewall 302 of the first via 301 of the pixel unit of the first embodiment, further increasing the area of the pixel electrode 400 and the luminescent layer 500, so that the pixel The contact area between the electrode 400 and the light-emitting layer 500 is further increased, and the overall brightness is further improved while preventing the color mixing problem caused by light scattering without changing the aperture ratio of the pixel unit.
  • the pixel electrode 400 may further extend to a top surface of the pixel defining layer 300, and an end of the pixel electrode 400 is located on a top surface of the pixel defining layer 300;
  • the light layer end portion 501 is stepped and covers the end of the pixel electrode;
  • the common electrode end portion 601 is stepped and covers the light emitting layer end portion 501 and extends along the top surface of the pixel defining layer 300, which further increases the pixel
  • the area of the electrode 400 and the light-emitting layer 500 is such that the contact area between the pixel electrode 400 and the light-emitting layer 500 is further increased, and the color mixing problem caused by light scattering is prevented, and the overall color is further improved without changing the aperture ratio of the pixel unit. brightness.
  • FIG. 5 is a pixel unit according to a fourth embodiment of the present invention.
  • any technical features that can be used in the same application in any of the above embodiments are the same, and the same description is not required. Only the technical features different from the other embodiments in the fourth embodiment will be described below.
  • the upper half of the first via hole 301 of the pixel defining layer 300 is expanded to form a step, and a stepped side wall 302 is formed.
  • the side surface of the pixel electrode 400 extends along the stepped side wall 302 of the first via hole 301 to the first portion.
  • a light emitting layer 500 is formed on the pixel electrode 400 and covers the pixel defining layer 300.
  • the common electrode 600 is formed on the light emitting layer 500, and the light emitting layer 500 is covered and along the pixel defining layer 300.
  • the top surface extends.
  • the area of the sidewall 302 of the first via 301 of the pixel unit of the fourth embodiment is larger than the area of the sidewall 302 of the first via 301 of the pixel unit of the first embodiment, further increasing the area of the pixel electrode 400 and the luminescent layer 500, so that the pixel The contact area between the electrode 400 and the light-emitting layer 500 is further increased, and the overall brightness is further improved while preventing the color mixing problem caused by light scattering.
  • the pixel electrode 400 may further extend to the top surface of the pixel defining layer 300, the end of the pixel electrode 400 is located on the top surface of the pixel defining layer 300; and the light emitting layer end portion 501 is stepped. And covering the end of the pixel electrode; the common electrode end portion 601 is stepped and covers the light emitting layer end portion 501 and extends along the top surface of the pixel defining layer 300, which further increases the area of the pixel electrode 400 and the light emitting layer 500. The contact area between the pixel electrode 400 and the light-emitting layer 500 is further increased, and the overall brightness is further improved while preventing the color mixing problem caused by light scattering.
  • FIG. 6 is a diagram showing a pixel unit according to a fifth embodiment of the present invention.
  • any technical features that can be used in the same application in any of the above embodiments are the same, and the same description is not required. Only the technical features different from the other embodiments in the fifth embodiment will be described below.
  • the pixel unit further includes: a protective layer 800.
  • the protective layer 800 is formed on the pixel defining layer 300 and covers the end of the pixel electrode 400; the light emitting layer 500 is formed on the pixel electrode and covers the protective layer 800; the common electrode 600 is formed on the light emitting layer At 500, the luminescent layer 500 is covered and extends along the top surface of the pixel defining layer 300.
  • the protective layer of this embodiment can be formed on the pixel unit described in any of the above first to fourth embodiments of the present invention.
  • the pixel unit shown in FIG. 1 including a protective layer is taken as an example.
  • the protective layer 800 covers the end of the pixel electrode 400, so that the end of the pixel electrode 400 and the common electrode 600 are isolated from each other, thereby preventing pixels.
  • the tip discharge phenomenon between the electrode 400 and the common electrode 600 occurs, improving the display stability and display effect of the pixel unit.
  • a sixth embodiment of the present invention provides an array substrate including a gate line, a data line, and a pixel unit in any of the above embodiments.
  • the gate line is connected to the control terminal 107 of the pixel unit driving thin film transistor, and the data line is connected and driven.
  • a seventh embodiment of the present invention provides a display device including the array substrate and the cover plate in the sixth embodiment.
  • An eighth embodiment of the present invention provides a method for fabricating a pixel unit, as shown in FIG. 7, for preparing the pixel unit according to any one of the first to fifth embodiments.
  • the preparation method may specifically include the following steps.
  • Step 101 sequentially forming a planarization layer and a pixel defining layer on the driving thin film transistor, and forming a second via hole and a first via hole by a patterning process.
  • the above patterning process may be, but not limited to, a Half Tone Mask process as long as the second via hole and the first via hole can be processed.
  • step 101 specifically includes: coating an organic film material, depositing a polyimide (PI) material on the organic film material, using a halftone mask lithography process, using a halftone mask A Half Tone Mask, the second via of the planarization layer and the first via of the pixel defining layer are inscribed at one time.
  • the halftone mask is a multi-tone mask. The entire mask is divided into an opaque portion, a semi-transmissive portion and a light-transmitting portion. The halftone mask can be used to expose the exposed portion and half after one exposure. Three exposure levels for the exposed portion and the unexposed portion. Specifically, the second via is exposed using the light transmissive portion of the halftone mask, and the semi via is exposed to expose the first via, thereby etching the second via and pixel defining of the planarization layer at one time The first via of the layer.
  • PI polyimide
  • the second via hole and the first via hole are sequentially prepared by two processes, and two sets of mask plates are required.
  • the second via hole and the first via hole are formed by the halftone mask process, only one set of half is needed.
  • the mask is used to prepare the second via and the first via in a single photolithography process, which simplifies the process, shortens the production time, reduces the mask cost, and greatly reduces the cost of the entire process. Capacity.
  • the pixel electrode is formed into a pixel defining layer, and the pixel electrode material residue after the process of forming the pixel defining layer contaminates the pixel electrode, thereby affecting the light emitting effect, and the process provided by the present invention first forms a pixel definition.
  • the pixel electrode is formed after the layer, thereby avoiding the above problem and greatly improving the light-emitting effect.
  • Step 201 Form a pixel electrode.
  • the step 201 may specifically include: sequentially performing ITO coating, Ag plating, and ITO coating, forming a pixel electrode in the first via of the pixel defining layer by photolithography, wet etching, stripping, and degrading, the pixel electrode having a bottom portion and a side portion The side portion extends along the sidewall of the first via to the top of the first via sidewall.
  • Step 301 forming a spacer layer.
  • Step 301 can specifically include depositing a polyimide (PI) material on the pixel defining layer and forming a spacer layer by photolithography.
  • PI polyimide
  • step 301 may further include depositing a polyimide (PI) material on the pixel defining layer, forming a pad spacer and a protective layer covering the end of the pixel electrode by one patterning process.
  • PI polyimide
  • Step 301 of the embodiment can synchronously process the spacer layer and the protective layer by one deposition and patterning process, and does not increase the process steps due to the protective layer, which is advantageous for simplifying the process flow and controlling the cost.
  • Step 401 Forming a light-emitting layer and a common electrode.
  • Step 401 can specifically include:
  • Sub-step 4011 depositing an organic light-emitting material by a vacuum thermal evaporation process and forming a light-emitting layer covering the pixel electrode on the pixel electrode by a patterning process.
  • the sub-step 4011 may further include: depositing the organic light-emitting material by a vacuum thermal evaporation process and forming a light-emitting layer covering the pixel electrode and the protective layer on the pixel electrode by a patterning process.
  • Sub-step 4012 depositing a metal alloy by a vacuum thermal evaporation process and forming a common electrode covering the light-emitting layer and extending along the top surface of the pixel defining layer on the light-emitting layer by a patterning process.
  • the driving thin film transistor is a low temperature polysilicon thin film transistor, and the step includes:
  • Sub-step 011 A buffer layer and an active layer are sequentially formed on the substrate.
  • Sub-step 011 may specifically include:
  • a buffer layer on the glass substrate Forming a buffer layer on the glass substrate, forming an active layer, the active layer is a-Si material, and performing dehydrogenation treatment; wherein a buffer enhanced layer and a active layer are formed by a plasma enhanced chemical vapor deposition (PECVD) process ;
  • PECVD plasma enhanced chemical vapor deposition
  • the active layer is spin cleaned, and polycrystalline silicon is crystallized by an excimer laser crystallization (ELA) process to form polycrystalline silicon P-Si.
  • ELA excimer laser crystallization
  • Sub-step 012 Polysilicon etching to form an output pole, an input pole, and a channel.
  • Sub-step 012 may specifically include: etching the polysilicon P-Si by a photolithography process to obtain a patterned output pole, an input pole, and a channel.
  • Sub-step 013 forming a gate insulating layer.
  • Sub-step 013 may specifically include: first spin clean, deposition of silicon dioxide (SiO 2 ) or silicon dioxide (SiO 2 ) / silicon nitride (SiN x ) by plasma enhanced chemical vapor deposition (PECVD) process. A two-layer material is formed and a gate insulating layer is formed by a patterning process.
  • PECVD plasma enhanced chemical vapor deposition
  • Sub-step 014 forming a control terminal on the gate insulating layer.
  • Sub-step 014 may specifically include: first spin clean, depositing molybdenum tantalum material into film, photolithography, enhanced capacitive coupling plasma dry etching (ECCP), and degumming to obtain a graphical control end.
  • first spin clean depositing molybdenum tantalum material into film
  • photolithography depositing molybdenum tantalum material into film
  • ECCP enhanced capacitive coupling plasma dry etching
  • Sub-step 015 forming an interlayer deposition layer and etching the third via and the fourth via of the interlayer deposition layer and the gate insulating layer.
  • Sub-step 015 may specifically include: firstly cleaning with hydrofluoric acid (BHF), forming a silicon nitride (SiN x ) or silicon dioxide (SiO 2 ) material into a film and hydrogenating, and then performing photolithography and inductively coupled plasma (ICP).
  • BHF hydrofluoric acid
  • SiN x silicon nitride
  • SiO 2 silicon dioxide
  • the third via and the fourth via are formed by etching and stripping.
  • Sub-step 016 Forming an output and an input.
  • Sub-step 016 may specifically include: firstly cleaning with hydrofluoric acid (BHF), forming a film of Ti-Al-Ti material, and forming an output by photolithography, enhanced capacitive coupling plasma dry etching (ECCP), degumming and metal annealing. And input.
  • BHF hydrofluoric acid
  • ECCP enhanced capacitive coupling plasma dry etching
  • the pixel unit in the organic light emitting diode display device and the method for fabricating the same, the array substrate and the display device provided by the embodiments of the present invention have at least one of the following beneficial effects.
  • the side surface portion of the pixel electrode extends along the sidewall of the first via hole to the top of the first via hole, The light scattered by the luminescent layer is greatly reduced, and the color mixing phenomenon between the pixel units is greatly improved, and the color mixing problem caused by light scattering is effectively solved.
  • the area of the pixel electrode is increased, so that the contact area of the pixel electrode and the light-emitting layer is increased, and the light-emitting area of the pixel unit is increased without changing the aperture ratio of the pixel unit, thereby improving the overall brightness.
  • the stepped ends of the light-emitting layer and the common electrode further increase the light-emitting area, further improving the overall brightness.
  • the second via hole and the first via hole can be prepared by one-time photolithography process using a halftone mask, which simplifies the process flow, shortens the production time, reduces the mask cost and costs the whole process. Significantly reduced and increased production capacity.
  • the protective layer covers the end of the pixel electrode, so that the pixel electrode end portion and the common electrode are isolated from each other, which prevents the tip discharge phenomenon between the pixel electrode and the common electrode from occurring, and improves the display stability and display effect of the pixel unit.
  • the first via sidewall may also adopt other shapes

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Abstract

一种像素单元，包括：像素限定层(300)、像素电极(400)、发光层(500)和公共电极(600)，像素电极(400)包括底面和侧面，侧面沿第一过孔(301)的侧壁(302)延伸至第一过孔(301)的侧壁(302)的顶部，发光层(500)形成于像素电极(400)上，并将像素限定层(300)覆盖，公共电极(600)形成于发光层(500)上，并将发光层(500)覆盖并沿像素限定层(300)顶面延伸。还提供了一种像素单元的制备方法。该像素单元使得发光层(500)向周围散射的光大为减少，像素单元之间的混色现象大为改善，有效地解决了光散射带来的混色问题，增大了像素单元的发光面积，提升了整体亮度，减少了掩膜成本并使整个工艺的成本大幅降低。

Description

像素单元及其制备方法、阵列基板和显示装置
相关申请的交叉引用
本申请要求于2016年5月27日向中国国家知识产权局递交的中国专利申请201610364630.6的权益，该申请的公开内容通过引用整体并入本文中。
技术领域
本发明涉及技术显示技术领域，尤其涉及有机发光二极管显示装置中的像素单元及其制备方法、阵列基板和显示装置。
背景技术
有机发光二极管显示装置(OLED)是一种新型发光技术，其利用有机物受激辐射而发光。OLED驱动方式分为有源驱动与无源驱动两种，其中有源驱动采用薄膜晶体管(TFT)作为驱动装置，像素单元由对应的TFT驱动，形成TFT驱动阵列，其中采用低温多晶硅薄膜晶体管(LTPS-TFT)驱动的OLED具有电子迁移速率更快、薄膜电路面积更小、分辨率更高以及结构简单、稳定性高的优点。
发明内容
本发明的至少一个目的在于提供一种像素单元，该像素单元能够避免混色发生，并且其制备方法流程简单、成本较低，不影响发光效果。
本发明的另一个目的在于提供一种像素单元的制备方法，其中该像素单元能够避免混色发生，并且制备方法流程简单、成本较低，不影响发光效果。
本发明的又一个目的在于提供一种阵列基板，该阵列基板中的像素单元能够避免混色发生，并且制备方法流程简单、成本较低，不影响发光效果。
本发明的还一个目的在于提供一种显示装置，该显示装置中的像素单 元能够避免混色发生，并且制备方法流程简单、成本较低，不影响发光效果。
根据本发明的一个方面，提供了一种像素单元，包括：像素限定层、像素电极、发光层和公共电极；其中，像素限定层具有第一过孔，像素电极、发光层和公共电极层叠于第一过孔内；像素电极包括底面和侧面，侧面沿第一过孔的侧壁延伸至第一过孔的侧壁的顶部；发光层形成于像素电极上并覆盖像素电极，公共电极形成于发光层上，将发光层覆盖并沿像素限定层的顶面延伸。
在一些实施例中，像素限定层的第一过孔的侧壁形成为平面、向外凸出的弧形凸面、向内凹陷的弧形凹面或阶梯状。
在一些实施例中，像素电极延伸至像素限定层的顶面，像素电极的端部位于像素限定层的顶面上，发光层和公共电极的端部均为阶梯状。
在一些实施例中，像素单元还包括：保护层，保护层形成于像素限定层上并将像素电极的端部覆盖，发光层覆盖保护层。
在一些实施例中，像素单元还包括：平坦化层，平坦化层在与驱动薄膜晶体管的输出端对应位置处开有第二过孔，像素限定层形成于平坦化层上，第一过孔位于第二过孔正上方并与第二过孔贯通。
根据本发明的另一个方面，提供了一种阵列基板，包括上述任一种像素单元。
根据本发明的又一个方面，提供了一种显示装置，包括上述阵列基板。
根据本发明的再一个方面，提供了一种像素单元的制备方法，用于制备上述像素单元，包括：形成像素限定层，并在像素限定层开设第一过孔；在像素限定层的第一过孔内形成像素电极，其中，像素电极形成有底面和侧面，侧面沿第一过孔的侧壁延伸至第一过孔的侧壁的顶部；形成覆盖像素电极的发光层；以及形成覆盖发光层并沿像素限定层的顶面延伸的公共电极。
在一些实施例中，形成像素限定层，并在像素限定层开设第一过孔包括：依次沉积两层有机材料，通过一次构图工艺形成平坦化层的第二过孔和像素限定层的第一过孔。
在一些实施例中，在像素限定层的第一过孔内形成像素电极和形成覆 盖像素电极的发光层之间还包括：在像素限定层沉积有机材料，通过一次构图工艺形成垫隔层和覆盖像素电极端部的保护层；形成覆盖像素电极的发光层包括：在像素电极上形成覆盖像素电极和保护层的发光层。
附图说明
图1为普通低温多晶硅薄膜晶体管有机发光二极管(LTPS-TFT OLED)显示装置的像素单元的结构示意图；
图2为本发明第一实施例的像素单元的结构示意图；
图3为本发明第二实施例的像素单元的结构示意图；
图4为本发明第三实施例的像素单元的结构示意图；
图5为本发明第四实施例的像素单元的结构示意图；
图6为本发明第五实施例的像素单元的结构示意图；以及
图7为本发明第八实施例的像素单元制备方法流程图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本发明进一步详细说明。
普通低温多晶硅薄膜晶体管有机发光二极管(LTPS-TFT OLED)显示装置的像素单元如图1所示，所述像素单元一般包括作为驱动薄膜晶体管100的低温多晶硅薄膜晶体管、平坦化层200、像素限定层300、像素电极400、发光层500和公共电极600等，发光层500的两侧面直接接触像素限定层300，发光层500发出的光将通过像素限定层300向四周散射，与其四周的其他像素单元的散射光发生混色，严重影响显示效果。而且，发光层500只有底面与像素电极400接触，发光面积有限，影响整体亮度。另外，制造如图1所示的像素单元的工艺流程中的制作顺序一般为多晶硅(Poly)、栅极绝缘层(Gatel)、栅极(Gate2)、层间沉积层(ILD)、源极漏极(SD)、平坦化层(PLN)、像素电极(Anode)、像素限定层(PDL)、垫隔层(PS)、发光层蒸镀(EL)以及公共电极(Vcom)，该流程中通常采用两道工艺先后制备平坦化层200过孔和像素限定层300过孔，因此需 要两套掩膜板，流程较复杂，成本较高。而且该流程中先形成像素电极400再形成像素限定层300的方式，会使形成像素限定层300过程后的像素电极材料残留物污染像素电极400，进而影响发光效果。因此，本领域迫切需要一种能够避免混色现象发生的像素单元和流程简单、成本较高低，不影响发光效果的像素电极制备方法。
参见图2，图2示出了本发明第一实施例的像素单元的结构示意图。像素单元形成于驱动薄膜晶体管上，包括：平坦化层(PLN层)200、像素限定层(PDL层)300、像素电极400、发光层500和公共电极600。
在此实施例中，驱动薄膜晶体管可以是低温多晶硅薄膜晶体管，包括衬底101，形成于衬底101上的缓冲层102，形成于缓冲层102上的输出极103、沟道104和输入极105，形成于缓冲层102以及输出极103、沟道104和输入极105上的栅极绝缘层106，形成于栅极绝缘层106上的控制端107，形成于控制端107和栅极绝缘层106上的层间沉积层108(ILD层)，输出极103和输入极105正上方分别开有贯穿层间沉积层108和栅极绝缘层106的第三过孔111和第四过孔112，输出端109和输入端110一端分别连接输出极103和输入极105，分别由第三过孔111和第四过孔112引出，另一端露出于层间沉积层108上。
对于本实施例的驱动薄膜晶体管，若选用N型薄膜晶体管，则控制端107为驱动薄膜晶体管的栅极，输入极105为其漏极，输入端110为漏极金属，输出极103为其源极，输出端109为源极金属；若选用P型薄膜晶体管，则控制端107为驱动薄膜晶体管的栅极，输入极105为其源极，输入端110为源极金属，输出极103为其漏极，输出端109为漏极金属。
平坦化层200形成于驱动薄膜晶体管的层间沉积层108和输出端109、输入端110上，并在输出端109正上方开有第二过孔201。像素限定层300形成于平坦化层200上，并在第二过孔201正上方开有第一过孔301，第一过孔301尺寸大于第二过孔201，并与第二过孔201贯通。
像素限定层300上依次形成像素电极400、发光层500和公共电极600，其中，像素电极400包括底面部分与侧面部分，底面部分铺满第一过孔301底部并经第二过孔201与输出端109连接，侧面部分沿第一过孔301的侧壁302延伸至第一过孔301侧壁302的顶部，发光层500形成于像素电极 400上，并将像素电极层400覆盖，公共电极600形成于发光层500上，并将发光层500覆盖并沿像素限定层300顶面延伸。此外，在像素限定层300上形成垫隔层700。本发明实施例中，像素电极400为氧化铟锡/银/氧化铟锡(ITO/Ag/ITO)材料形成的反射电极，或由不透光导电材料形成。本发明实施例中的像素单元，由于像素限定层300与发光层500之间存在像素电极400，发光层500发出的光部分被ITO/Ag/ITO材料形成的反射电极反射，或被不透光导电材料阻挡，使得发光层500向周围散射的光大为减少，因而像素单元之间的混色现象大为改善，有效地解决了光散射带来的混色问题。像素电极400具有侧面部分，增大了像素电极400的面积，使得像素电极400与发光层500的接触面积增大，而且在不改变像素单元开口率的情况下，增大了像素单元的发光面积，提升了整体亮度。
本发明实施例中，衬底101为玻璃材料；缓冲层102为氮化硅(SiNx)或二氧化硅(SiO2)或铝(Al)或氧化铝(Al2O3)材料；输出极103、沟道104和输入极105为多晶硅(P-Si)材料；栅极绝缘层106为二氧化硅(SiO2)或二氧化硅(SiO2)/氮化硅(SiNx)双层材料，或TEOS材料；控制端107为钼铌材料；输出端109和输入端110为Ti-Al-Ti材料；层间沉积层108为氮化硅(SiNx)或二氧化硅(SiO2)材料；平坦化层200为有机膜材料；像素限定层300为聚酰亚胺(PI)材料；发光层500为有机发光材料，例如Alq、Balq和DPVBi等；公共电极600为金属合金，例如Mg-Ag。
在一些实施例中，如图2所示，像素电极400可以进一步延伸至像素限定层300的顶面，像素电极400的端部位于像素限定层300顶面上；发光层端部501为阶梯状并将像素电极400的端部覆盖；公共电极端部601为阶梯状并将发光层端部501覆盖，并沿像素限定层300顶面延伸。这进一步增大了像素电极400和发光层500的面积，使得像素电极400与发光层500的接触面积进一步增大，在不改变像素单元开口率的情况下，在防止光散射带来的混色问题同时，进一步提升了整体亮度。
图3为本发明的第二实施例的像素单元，为了达到简要说明的目的，上述第一实施例中任何可作相同应用的技术特征叙述皆并于此，无需再重复相同叙述。以下仅描述第二实施例中与第一实施例不同的技术特征。
像素限定层300的第一过孔301侧壁302具有向外凸出的弧形凸面，像素电极400侧面沿第一过孔301的弧形凸面状侧壁302延伸至第一过孔301侧壁302的顶部，发光层500形成于像素电极400上，并将像素限定层300覆盖，公共电极600形成于发光层500上，并将发光层500覆盖并沿像素限定层300顶面延伸。第二实施例像素单元的第一过孔301侧壁302面积大于第一实施例像素单元的第一过孔301侧壁302面积，进一步增大了像素电极400和发光层500的面积，使得像素电极400与发光层500的接触面积进一步增大，在不改变像素单元开口率的情况下，在防止光散射带来的混色问题同时，进一步提升了整体亮度。
在一些实施例中，如图3所示，像素电极400可以进一步延伸至像素限定层300的顶面，像素电极400的端部位于像素限定层300顶面上；发光层端部501为阶梯状并将像素电极400的端部覆盖；公共电极端部601为阶梯状并将发光层端部501覆盖，并沿像素限定层300顶面延伸，这进一步增大了像素电极400和发光层500的面积，使得像素电极400与发光层500的接触面积进一步增大，在不改变像素单元开口率的情况下，在防止光散射带来的混色问题同时，进一步提升了整体亮度。
图4为本发明的第三实施例的像素单元，为了达到简要说明的目的，上述任一实施例中任何可作相同应用的技术特征叙述皆并于此，无需再重复相同叙述。以下仅描述第三实施例中与其它实施例不同的技术特征。
像素限定层300的第一过孔301侧壁302具有向内凹陷的弧形凹面，像素电极400侧面沿第一过孔301的弧形凹面状侧壁302延伸至第一过孔301侧壁302的顶部，发光层500形成于像素电极400上，并将像素限定层300覆盖，公共电极600形成于发光层500上，并将发光层500覆盖并沿像素限定层300顶面延伸。第三实施例像素单元的第一过孔301侧壁302面积大于第一实施例像素单元的第一过孔301侧壁302面积，进一步增大了像素电极400和发光层500的面积，使得像素电极400与发光层500的接触面积进一步增大，在不改变像素单元开口率的情况下，在防止光散射带来的混色问题同时，进一步提升了整体亮度。
在一些实施例中，如图4所示，像素电极400可以进一步延伸至像素限定层300的顶面，像素电极400的端部位于像素限定层300顶面上；发 光层端部501为阶梯状并将像素电极的端部覆盖；公共电极端部601为阶梯状并将发光层端部501覆盖，并沿像素限定层300顶面延伸，这进一步增大了像素电极400和发光层500的面积，使得像素电极400与发光层500的接触面积进一步增大，在不改变像素单元开口率的情况下，在防止光散射带来的混色问题同时，进一步提升了整体亮度。
图5为本发明的第四实施例的像素单元，为了达到简要说明的目的，上述任一实施例中任何可作相同应用的技术特征叙述皆并于此，无需再重复相同叙述。以下仅描述第四实施例中与其它实施例不同的技术特征。
像素限定层300的第一过孔301的上半部分外扩，形成一台阶，构成一阶梯状的侧壁302，像素电极400侧面沿第一过孔301的阶梯状的侧壁302延伸至第一过孔301侧壁302的顶部，发光层500形成于像素电极400上，并将像素限定层300覆盖，公共电极600形成于发光层500上，并将发光层500覆盖并沿像素限定层300顶面延伸。第四实施例像素单元的第一过孔301侧壁302面积大于第一实施例像素单元的第一过孔301侧壁302面积，进一步增大了像素电极400和发光层500的面积，使得像素电极400与发光层500的接触面积进一步增大，在防止光散射带来的混色问题同时，进一步提升了整体亮度。
在一些实施例中，如图5所示，像素电极400可以进一步延伸至像素限定层300的顶面，像素电极400的端部位于像素限定层300顶面上；发光层端部501为阶梯状并将像素电极的端部覆盖；公共电极端部601为阶梯状并将发光层端部501覆盖，并沿像素限定层300顶面延伸，这进一步增大了像素电极400和发光层500的面积，使得像素电极400与发光层500的接触面积进一步增大，在防止光散射带来的混色问题同时，进一步提升了整体亮度。
图6为本发明的第五实施例的像素单元，为了达到简要说明的目的，上述任一实施例中任何可作相同应用的技术特征叙述皆并于此，无需再重复相同叙述。以下仅描述第五实施例中与其它实施例不同的技术特征。
作为本发明的另一个可选实施例，像素单元还包括：保护层800。保护层800形成于像素限定层300上并将像素电极400的端部覆盖；发光层500形成于像素电极上并将保护层800覆盖；公共电极600形成于发光层 500上，将发光层500覆盖并沿像素限定层300顶面延伸。
本实施例的保护层可形成于本发明上述第一至第四实施例中的任一实施例所述的像素单元上。以包含保护层的图1所示的像素单元为例进行说明，如图6所示，保护层800将像素电极400端部覆盖，使得像素电极400端部和公共电极600相互隔离，可防止像素电极400和公共电极600之间的尖端放电现象发生，提高了像素单元的显示稳定性和显示效果。
本发明的第六实施例提供了一种阵列基板，阵列基板包括栅线、数据线和上述任一实施例中的像素单元，栅线连接像素单元驱动薄膜晶体管的控制端107，数据线连接驱动薄膜晶体管的输入端110。
本发明的第七实施例提供了一种显示装置，显示装置包括第六实施例中的阵列基板以及盖板。
本发明第八实施例提供了一种像素单元的制备方法，如图7所示，用于制备上述第一至第五实施例中任一实施例所述的像素单元。制备方法可以具体包括如下步骤。
步骤101：在驱动薄膜晶体管上依次形成平坦化层和像素限定层，并通过构图工艺形成第二过孔和第一过孔。
上述构图工艺可以但不限于半色调掩膜(Half Tone Mask)工艺，只要能加工出第二过孔和第一过孔即可。
当采用半色调掩膜工艺时，步骤101具体包括：涂布有机膜材料，在有机膜材料上沉积聚酰亚胺(PI)材料，采用半色调掩膜光刻工艺，使用一张半色调掩膜版(Half Tone Mask)，一次性刻出平坦化层的第二过孔和像素限定层第一过孔。半色调掩膜版是一种多灰度掩膜，整个掩膜分为不透光部分、半透光部分和透光部分，使用半色调掩膜版可以在一次曝光后呈现出曝光部分、半曝光部分和未曝光部分三种曝光层次。具体来说，使用半色调掩膜版的透光部分曝光出第二过孔，半透光部分曝光出第一过孔，从而在一次性光刻出平坦化层的第二过孔和像素限定层的第一过孔。
现有技术通过两道工艺先后制备第二过孔和第一过孔，需要两套掩膜板，当采用半色调掩膜工艺形成第二过孔和第一过孔时，只需一套半色调掩膜版，一次光刻工艺就制备出第二过孔和第一过孔，简化了工艺流程，缩短了生产时间，减少了掩膜成本并使整个工艺的成本大幅降低，提高了 产能。现有技术的先形成像素电极再形成像素限定层的方式，会使形成像素限定层过程后的像素电极材料残留物污染像素电极，进而影响发光效果，而本发明提供的工艺流程先形成像素限定层后形成像素电极，从而避免了上述问题，极大提升了发光效果。
步骤201：形成像素电极。
步骤201可以具体包括：依次进行ITO镀膜、Ag镀膜、ITO镀膜，经光刻、湿刻、去胶和退化在像素限定层的第一过孔内形成像素电极，像素电极具有底面部分和侧面部分，其侧面部分沿第一过孔的侧壁延伸至第一过孔侧壁的顶部。
步骤301：形成垫隔层。
步骤301可以具体包括：在像素限定层上沉积聚酰亚胺(PI)材料，经光刻形成垫隔层。
在本发明的另一个实施例中，步骤301还可以具体包括：在像素限定层上沉积聚酰亚胺(PI)材料，通过一次构图工艺形成垫隔层和覆盖像素电极端部的保护层。
本实施例的步骤301可以通过一次沉积和构图工艺同步加工出垫隔层和保护层，并不会因保护层而增加工艺步骤，有利于简化工艺流程和控制成本。
步骤401：形成发光层和公共电极。
步骤401可以具体包括：
子步骤4011：采用真空热蒸镀工艺，沉积有机发光材料并通过构图工艺在像素电极上形成覆盖像素电极的发光层。
在本发明的另一个实施例中，子步骤4011也可以具体包括：采用真空热蒸镀工艺，沉积有机发光材料并通过构图工艺在像素电极上形成覆盖像素电极和保护层的发光层。
子步骤4012：采用真空热蒸镀工艺，沉积金属合金并通过构图工艺在发光层上形成覆盖发光层并沿像素限定层顶面延伸的公共电极。
在一些实施例中，在制备像素单元前还包括制备驱动薄膜晶体管的步骤，该驱动薄膜晶体管是低温多晶硅薄膜晶体管，所述步骤包括：
子步骤011：在衬底上依次形成缓冲层和有源层。
子步骤011可以具体包括：
清洗玻璃衬底并对进行预处理；
在玻璃衬底上形成缓冲层，再形成有源层，有源层为a-Si材料，并进行去氢处理；其中，选用等离子体增强化学气相沉积(PECVD)工艺形成缓冲层、有源层；
对有源层旋转清洗(spin clean)，并利用准分子激光晶化(ELA)工艺进行多晶硅晶化，生成多晶硅P-Si。
子步骤012：多晶硅刻蚀，形成输出极、输入极和沟道。
子步骤012可以具体包括：利用光刻工艺刻蚀多晶硅P-Si，得到图形化的输出极、输入极和沟道。
子步骤013：形成栅极绝缘层。
子步骤013可以具体包括：先旋转清洗(spin clean)，利用等离子体增强化学气相沉积(PECVD)工艺沉积二氧化硅(SiO2)或二氧化硅(SiO2)/氮化硅(SiNx)双层材料，并通过构图工艺形成栅极绝缘层。
子步骤014：在栅极绝缘层上形成控制端。
子步骤014可以具体包括：先旋转清洗(spin clean)，将钼铌材料沉积成膜、光刻、增强电容耦合等离子干刻(ECCP)、去胶得到图形化的控制端。
子步骤015：形成层间沉积层并刻蚀层间沉积层和栅极绝缘层的第三过孔和第四过孔。
子步骤015可以具体包括：先经氢氟酸(BHF)清洗，将氮化硅(SiNx)或二氧化硅(SiO2)材料成膜并氢化，再经光刻、感应耦合等离子(ICP)刻蚀和去胶形成第三过孔和第四过孔。
子步骤016：形成输出端和输入端。
子步骤016可以具体包括：先经氢氟酸(BHF)清洗，将Ti-Al-Ti材料成膜，并经光刻、增强电容耦合等离子干刻(ECCP)、去胶和金属退火形成输出端和输入端。
由上可知，本发明实施例提供的有机发光二极管显示装置中的像素单元及其制备方法、阵列基板和显示装置至少具有以下有益效果之一。
(1)像素电极侧面部分沿第一过孔的侧壁延伸至第一过孔顶部，使 得发光层向周围散射的光大为减少，像素单元之间的混色现象大为改善，有效地解决了光散射带来的混色问题。
(2)像素电极面积增大，使得像素电极与发光层的接触面积增大，在不改变像素单元开口率的情况下，增大了像素单元的发光面积，提升了整体亮度。
(3)发光层和公共电极的阶梯状端部进一步增大了发光面积，进一步提升了整体亮度。
(4)制备方法可利用半色调掩膜版，一次光刻工艺制备出第二过孔和第一过孔，简化了工艺流程，缩短了生产时间，减少了掩膜成本并使整个工艺的成本大幅降低，提高了产能。
(5)先形成像素限定层后形成像素电极，从而避免了形成像素限定层过程后的像素电极材料残留物污染像素电极，提升了发光效果。
(6)保护层将像素电极的端部覆盖，使得像素电极端部和公共电极相互隔离，可防止像素电极和公共电极间的尖端放电现象发生，提高了像素单元的显示稳定性和显示效果。
至此，已经结合附图对本实施例进行了详细描述。依据以上描述，本领域技术人员应当对本发明提供的像素单元及其制备方法、阵列基板和显示装置有了清楚的认识。
需要说明的是，在附图或说明书正文中，未绘示或描述的实现方式，均为所属技术领域中普通技术人员所知的形式，并未进行详细说明。此外，上述对各元件的定义并不仅限于实施例中提到的各种具体结构、形状或方式，本领域普通技术人员可对其进行简单地更改或替换，例如：
(1)第一过孔侧壁还可以采用其他形状；
(2)实施例中提到的方向用语，例如“上”、“下”、“前”、“后”、“左”、“右”等，仅是参考附图的方向，并非用来限制本发明的保护范围；
(3)上述实施例可基于设计及可靠度的考虑，彼此混合搭配使用或与其他实施例混合搭配使用，即不同实施例中的技术特征可以自由组合形成更多的实施例。
以上所述的具体实施例，对本发明的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本发明的具体实施例而 已，并不用于限制本发明，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (10)

  1. 一种像素单元，其特征在于，包括：像素限定层、像素电极、发光层和公共电极；其中，
    所述像素限定层具有第一过孔，像素电极、发光层和公共电极层叠于所述第一过孔内；
    所述像素电极包括底面部分和侧面部分，所述侧面部分沿第一过孔的侧壁延伸至第一过孔的侧壁的顶部；
    所述发光层形成于像素电极上并覆盖像素电极，所述公共电极形成于发光层上，覆盖发光层并沿像素限定层的顶面延伸。
  2. 如权利要求1所述的像素单元，其特征在于，所述像素限定层的第一过孔的侧壁形成为平面、向外凸出的弧形凸面、向内凹陷的弧形凹面或阶梯状。
  3. 如权利要求1所述的像素单元，其特征在于，所述像素电极延伸至像素限定层的顶面，所述像素电极的端部位于像素限定层的顶面上，所述发光层和公共电极的端部均为阶梯状。
  4. 如权利要求1所述的像素单元，其特征在于，还包括：保护层，所述保护层形成于所述像素限定层上并将所述像素电极的端部覆盖，所述发光层覆盖所述保护层。
  5. 如权利要求1所述的像素单元，其特征在于，还包括：平坦化层，所述平坦化层在与驱动薄膜晶体管的输出端对应位置处开有第二过孔，所述像素限定层形成于平坦化层上，所述第一过孔位于所述第二过孔正上方并与所述第二过孔贯通。
  6. 一种阵列基板，其特征在于，包括如权利要求1-5中任一项权利要求所述的像素单元。
  7. 一种显示装置，其特征在于，包括如权利要求6所述的阵列基板。
  8. 一种像素单元的制备方法，其特征在于，用于制备如权利要求1所述的像素单元，包括：
    形成像素限定层，并在所述像素限定层开设第一过孔；
    在所述像素限定层的第一过孔内形成像素电极，其中，所述像素电极 形成有底面和侧面，所述侧面沿第一过孔的侧壁延伸至第一过孔的侧壁的顶部；
    形成覆盖像素电极的发光层；以及
    形成覆盖发光层并沿像素限定层的顶面延伸的公共电极。
  9. 如权利要求8所述的制备方法，其特征在于，所述形成像素限定层，并在所述像素限定层开设第一过孔包括：
    依次沉积两层有机材料，通过一次构图工艺形成平坦化层的第二过孔和像素限定层的第一过孔。
  10. 如权利要求8所述的制备方法，其特征在于，所述在像素限定层的第一过孔内形成像素电极之后和所述形成覆盖像素电极的发光层之前还包括：
    在像素限定层沉积有机材料，通过一次构图工艺形成垫隔层和覆盖像素电极端部的保护层；以及
    所述形成覆盖像素电极的发光层还包括：
    在像素电极上形成覆盖像素电极和保护层的发光层。
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