WO2017197915A1 - 光刻掩膜板及其制作方法、光刻方法 - Google Patents
光刻掩膜板及其制作方法、光刻方法 Download PDFInfo
- Publication number
- WO2017197915A1 WO2017197915A1 PCT/CN2017/070816 CN2017070816W WO2017197915A1 WO 2017197915 A1 WO2017197915 A1 WO 2017197915A1 CN 2017070816 W CN2017070816 W CN 2017070816W WO 2017197915 A1 WO2017197915 A1 WO 2017197915A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- mask
- pattern
- conductive connection
- photolithography
- conductive
- Prior art date
Links
- 238000000206 photolithography Methods 0.000 title claims abstract description 32
- 238000000034 method Methods 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 238000001459 lithography Methods 0.000 claims description 30
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 12
- 239000011787 zinc oxide Substances 0.000 claims description 6
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 3
- CXKCTMHTOKXKQT-UHFFFAOYSA-N cadmium oxide Inorganic materials [Cd]=O CXKCTMHTOKXKQT-UHFFFAOYSA-N 0.000 claims description 3
- CFEAAQFZALKQPA-UHFFFAOYSA-N cadmium(2+);oxygen(2-) Chemical compound [O-2].[Cd+2] CFEAAQFZALKQPA-UHFFFAOYSA-N 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 2
- 229910052738 indium Inorganic materials 0.000 claims 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims 2
- 229910052782 aluminium Inorganic materials 0.000 claims 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims 1
- 238000009825 accumulation Methods 0.000 description 6
- 238000000926 separation method Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 239000011521 glass Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000002508 contact lithography Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
- G03F1/40—Electrostatic discharge [ESD] related features, e.g. antistatic coatings or a conductive metal layer around the periphery of the mask substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
Definitions
- the present disclosure relates generally to the field of display, and in particular to a lithographic mask, a lithography method using a lithography mask, and a method of fabricating a lithography mask.
- a photolithography process is often used to make the pattern layer on the display panel.
- the use of a photolithographic mask in a lithography process inevitably introduces an electrostatic charge during production, testing, and transportation. Since the photolithography mask usually uses an organic material such as insulating glass as the substrate, it is not conducive to the discharge of electrostatic charges. When the electrostatic charge on the lithographic mask is accumulated to some extent, electrostatic discharge may occur between the separated portions of the mask pattern on the lithographic mask.
- the high voltage or high current generated in an instant may cause the performance of the semiconductor layer or the metal trace on the display panel to be degraded or even destroyed, thereby seriously affecting the performance and products of the produced display panel. Yield.
- a photolithography mask comprising a substrate substrate and a mask pattern disposed on a surface of the substrate substrate, and a conductive connection pattern disposed on the surface, Wherein the conductive connection pattern is used to electrically connect the separated portions of the mask pattern together.
- a "surface" of a substrate substrate refers to a mask pattern formed thereon. And the surface of the substrate substrate that electrically connects the patterns, and does not necessarily refer to the exposed surface of the lithography mask.
- the lithography mask may further include an encapsulation layer encapsulating the substrate substrate and the mask pattern and the conductive connection pattern thereon for protecting the mask pattern and the conductive connection pattern from damage.
- the electrically conductive connection pattern includes a plurality of electrically conductive connecting lines that intersect each other.
- the spacing between the electrically conductive connecting lines can be selected to be less than the minimum spacing between the separated portions of the mask pattern, thereby ensuring that any two separate portions of the mask pattern can be electrically connected together by the electrically conductive connecting lines.
- the plurality of conductive connecting lines crossing each other may cross horizontally or vertically, or may intersect each other at any angle.
- a universal conductive connection pattern is provided.
- the conductive connection pattern is suitable for any mask pattern, and does not require the designer to design different conductive connection patterns for different mask patterns, which is very simple and efficient, and greatly reduces the workload of the designer.
- the electrically conductive connection pattern comprises a transparent conductive layer that is electrically connected to the mask pattern.
- the transparent conductive layer may cover the mask pattern.
- the transparent conductive layer may be sandwiched between the mask pattern and the substrate.
- the term "transparent" means that the light emitted by the source of the lithography machine used in conjunction with the lithographic mask is transparent, and thus the transparent conductive layer is ultimately applied to the display panel produced by the lithography process. The pattern on it has no effect.
- the design and fabrication of the lithography mask is simpler and more efficient due to the use of a transparent conductive layer to serve as a conductive connection pattern.
- the transparent conductive layer is made of a conductive oxide.
- the conductive oxide may include one or more of indium tin oxide (ITO), aluminum-doped zinc oxide (AZO), indium-doped zinc oxide (IZO), or indium-doped cadmium oxide.
- ITO indium tin oxide
- AZO aluminum-doped zinc oxide
- IZO indium-doped zinc oxide
- indium-doped cadmium oxide indium tin oxide or tin-doped indium oxide is the best known and most widely used transparent conductive oxide, which is widely used due to its ease of deposition as a film.
- the conductive connection pattern is formed of the same material as the mask pattern.
- the conductive connection pattern and the mask pattern can be simultaneously formed in one patterning process, and thus the design and fabrication of the lithography mask sheet is simpler and more efficient.
- the maximum line width of the conductive connection lines is less than the resolution of the lithography machine used in conjunction with the lithographic mask.
- the resolution of the lithography machine means the size of the thinnest lines that can be formed by the lithography machine, and is limited by various aspects such as the light source, the lithography system, the photoresist, and the process parameters.
- the resolution of common contact lithography machines is on the order of micrometers. Therefore, for example, the conductive line has a maximum line width of less than 0.5 ⁇ m.
- the maximum line width of the conductive connection line is smaller than the resolution of the lithography machine, only the pattern corresponding to the mask pattern exists on the display panel after the lithography process, and there is no conductive connection line. Corresponding pattern. Therefore, arranging the conductive connection lines on the photolithography mask does not affect the pattern on the finally obtained display panel, and can prevent the occurrence of electrostatic discharge.
- the conductive connection pattern and the mask pattern are made of chrome.
- a photolithography method using the above photolithographic mask Therefore, by arranging the conductive connection patterns on the photolithography mask to electrically connect the respective separated portions of the mask pattern, electrostatic discharge can be prevented from occurring between the separated portions of the mask pattern due to electrostatic charge accumulation, thereby protecting The display panel is not affected by electrostatic discharge during the photolithography process, improving the performance and yield of the display panel.
- a method of fabricating a photolithography mask comprising: providing a substrate; forming a mask pattern on a surface of the substrate; making a conductive connection on the surface a pattern, wherein the conductive connection pattern is used to electrically connect separate portions of the mask pattern together.
- electrostatic discharge can be prevented from occurring between the separated portions of the mask pattern due to electrostatic charge accumulation, thereby protecting the display panel It is not affected by electrostatic discharge, improving the performance and yield of the display panel.
- fabricating a conductive connection pattern on the surface includes forming a plurality of electrically conductive connecting lines that intersect each other on the surface.
- the spacing between the electrically conductive connecting lines can be selected to be less than the minimum spacing between the separated portions of the mask pattern, thereby ensuring that any two separate portions of the mask pattern can be electrically connected together by the electrically conductive connecting lines.
- the plurality of conductive connecting lines crossing each other may cross horizontally or vertically, or may intersect each other at any angle.
- a common conductive connection pattern is fabricated on the lithographic mask.
- the conductive connection pattern is suitable for any mask pattern, and does not require the designer to design different conductive connection patterns for different mask patterns, so it is very simple and efficient, greatly reducing The workload of the designer.
- fabricating a conductive connection pattern on the surface includes forming a transparent conductive layer on the surface that is electrically connected to the mask pattern. For example, a transparent conductive layer is first formed on a base substrate, and then a mask pattern is formed on the transparent conductive layer. Alternatively, the transparent conductive layer is covered on the substrate substrate on which the mask pattern is disposed. The transparent conductive layer has no effect on the pattern on the display panel that is ultimately produced by the photolithography process. The design and fabrication of the lithography mask is simpler and more efficient due to the use of a transparent conductive layer to serve as a conductive connection pattern.
- the conductive connection pattern and the mask pattern are simultaneously fabricated during a patterning process, and thus the design and fabrication of the lithography mask is simpler and more efficient.
- FIG. 1 is a top plan view of a photolithography mask in accordance with an embodiment of the present disclosure
- FIG. 2 is a top plan view of a photolithography mask in accordance with another embodiment of the present disclosure.
- FIG. 3 is a cross-sectional view of a photolithographic mask in accordance with yet another embodiment of the present disclosure.
- FIG. 4 is a cross-sectional view of a lithographic mask in accordance with yet another embodiment of the present disclosure.
- FIG. 5 is a flow chart of a method of fabricating a lithography mask in accordance with an embodiment of the present disclosure.
- FIG. 1 illustrates a top view of a lithographic mask in accordance with an embodiment of the present disclosure.
- the photolithography mask includes a mask pattern disposed on a top surface of a base substrate (not shown), and a conductive connection pattern 2 disposed on the top surface.
- conductive The connection pattern 2 electrically connects the separated portions 1a, 1b, 1c, 1d of the mask pattern together.
- the present disclosure proposes a general conductive connection pattern.
- 2 illustrates a top view of a lithographic mask in accordance with another embodiment of the present disclosure.
- the conductive connection pattern 2 includes a plurality of conductive connecting lines crossing each other. The spacing between the conductive connecting lines is selected to be smaller than the minimum spacing between the separated portions of the mask pattern, thereby ensuring that any two separate portions of the mask pattern 1 can be electrically connected together through the conductive connecting lines.
- the plurality of conductive connecting lines crossing each other may cross horizontally and vertically as shown in FIG. 2 or may cross each other at any angle.
- a general conductive connection pattern is provided.
- the conductive connection pattern is suitable for any mask pattern, and does not require the designer to design different conductive connection patterns for different mask patterns, which is very simple and efficient, and greatly reduces the workload of the designer.
- the conductive connecting lines are illustrated as being evenly spaced from each other and having the same width in FIG. 2, the arrangement of the conductive connecting lines can be designed by those skilled in the art according to actual needs as long as the mask pattern can be separated. Part of the electrical connection can be.
- the electrically conductive connection pattern comprises a transparent conductive layer that is electrically connected to the mask pattern.
- the transparent conductive layer 21 covers the mask pattern to electrically connect the separated portions 1a, 1b, and 1c of the mask pattern.
- the transparent conductive layer 22 is sandwiched between the mask pattern and the base substrate 3 to electrically connect the separated portions 1a, 1b and 1c of the mask pattern.
- the design and fabrication of the lithographic mask is simpler and more efficient due to the use of a transparent conductive layer to act as a conductive connection pattern.
- the transparent conductive layer may be made of a conductive oxide.
- the conductive oxide may include one or more of indium tin oxide (ITO), aluminum-doped zinc oxide (AZO), indium-doped zinc oxide (IZO), or indium-doped cadmium oxide.
- the conductive connection pattern is formed in the same layer as the mask pattern.
- the conductive connection pattern and the mask pattern are made of chrome, and thus the design and fabrication of the lithography mask is simpler and more efficient.
- the maximum line width of the conductive connection lines is less than the resolution of the lithography machine used in conjunction with the lithographic mask.
- the conductive line has a maximum line width of less than 0.5 ⁇ m.
- the maximum line width of the conductive connection line is smaller than the resolution of the lithography machine, only the pattern corresponding to the mask pattern exists on the display panel after the lithography process, and there is no conductive connection line. Corresponding pattern. Therefore, arranging the conductive connection lines on the photolithography mask does not affect the pattern on the finally obtained display panel, and can prevent the occurrence of electrostatic discharge.
- the present disclosure also provides a photolithography method using the photolithographic mask described above. Therefore, by arranging the conductive connection patterns on the photolithography mask to electrically connect the respective separated portions of the mask pattern, electrostatic discharge can be prevented from occurring between the separated portions of the mask pattern due to electrostatic charge accumulation, thereby protecting The display panel is not affected by electrostatic discharge during the photolithography process, improving the performance and yield of the display panel.
- FIG. 5 illustrates a flow chart of a method of fabricating a lithographic mask in accordance with an embodiment of the present disclosure.
- a base substrate is provided.
- the base substrate may be a transparent substrate such as a glass substrate or a sapphire substrate which is common in the art.
- a mask pattern is formed on the surface of the base substrate, the mask pattern corresponding to a lithographic pattern to be formed on the display panel.
- a conductive connection pattern is formed on the same surface of the base substrate, wherein the conductive connection pattern is used to electrically connect the separated portions of the mask pattern together.
- steps S502 and S503 may be sequentially performed in any order, or simultaneously.
- step S502 and step S503 are simultaneously performed, the conductive connection pattern and the mask pattern can be simultaneously fabricated in one patterning process, so that the design and fabrication of the lithography mask is simpler and more efficient.
- electrostatic discharge can be prevented from occurring between the separated portions of the mask pattern due to electrostatic charge accumulation, thereby protecting the display panel It is not affected by electrostatic discharge, improving the performance and yield of the display panel.
- Making the conductive connection pattern on the surface specifically includes making a cross on the surface Strip conductive wire.
- the spacing between the electrically conductive connecting lines can be selected to be less than the minimum spacing between the separated portions of the mask pattern, thereby ensuring that any two separate portions of the mask pattern can be electrically connected together by the electrically conductive connecting lines.
- the plurality of conductive connecting lines crossing each other may cross horizontally or vertically, or may intersect each other at any angle.
- fabricating the conductive connection pattern on the surface specifically includes forming a transparent conductive layer electrically connected to the mask pattern on the surface.
- a transparent conductive layer is first formed on a base substrate, and then a mask pattern is formed on the transparent conductive layer.
- the transparent conductive layer is covered on the substrate substrate on which the mask pattern is disposed.
- the transparent conductive layer has no effect on the pattern on the display panel that is ultimately produced by the photolithography process.
- the design and fabrication of the lithography mask is simpler and more efficient due to the use of a transparent conductive layer to serve as a conductive connection pattern.
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Preparing Plates And Mask In Photomechanical Process (AREA)
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- Electroluminescent Light Sources (AREA)
Abstract
Description
Claims (16)
- 一种光刻掩膜板,包括衬底基板和布置在所述衬底基板的表面上的掩膜图案,以及布置在所述表面上的导电连接图案,其中,所述导电连接图案用于将所述掩膜图案的分离部分电气连接在一起。
- 根据权利要求1所述的光刻掩膜板,其中,所述导电连接图案包括相互交叉的多条导电连接线。
- 根据权利要求1所述的光刻掩膜板,其中,所述导电连接图案包括与所述掩膜图案电气连接的透明导电层。
- 根据权利要求3所述的光刻掩膜板,其中,所述透明导电层覆盖所述掩膜图案。
- 根据权利要求3所述的光刻掩膜板,其中,所述透明导电层夹在所述掩膜图案与所述衬底基板之间。
- 根据权利要求3-5中任一项所述的光刻掩膜板,其中,所述透明导电层由导电氧化物制成。
- 根据权利要求6所述的光刻掩膜板,其中,所述导电氧化物包括铟锡氧化物、铝掺杂的氧化锌、铟掺杂的氧化锌或铟掺杂的氧化镉中的一个或多个。
- 根据权利要求1所述的光刻掩膜板,其中,所述导电连接图案与所述掩膜图案同层同材料形成。
- 根据权利要求2所述的光刻掩膜板,其中,所述导电连接线的最大线宽小于与所述光刻掩膜板配合使用的光刻机的分辨率。
- 根据权利要求9所述的光刻掩膜板,其中,所述导电连接线的最大线宽小于0.5μm。
- 根据权利要求8所述的光刻掩膜板,其中,所述导电连接图案和所述掩膜图案由铬制成。
- 一种光刻方法,使用根据权利要求1至11中任一项所述的光刻掩膜板。
- 一种光刻掩膜板的制作方法,包括:提供衬底基板;在所述衬底基板的表面上制作掩膜图案;在所述表面上制作导电连接图案,其中,所述导电连接图案用于将所述掩膜图案的分离部分电气连接在一起。
- 根据权利要求13所述的方法,其中,在所述表面上制作导电连接图案,包括在所述表面上制作相互交叉的多条导电连接线。
- 根据权利要求13所述的方法,其中,在所述表面上制作导电连接图案,包括在所述表面上制作与掩膜图案电气连接的透明导电层。
- 根据权利要求13所述的方法,其中,在一个图案化工艺过程中同时制作所述导电连接图案和所述掩膜图案。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/533,456 US10466584B2 (en) | 2016-05-18 | 2017-01-11 | Photoetching mask plate, manufacture method thereof, and photoetching method |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201610329420.3 | 2016-05-18 | ||
CN201610329420.3A CN105759562B (zh) | 2016-05-18 | 2016-05-18 | 光刻掩膜板及其制作方法、光刻方法 |
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Publication Number | Publication Date |
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WO2017197915A1 true WO2017197915A1 (zh) | 2017-11-23 |
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PCT/CN2017/070816 WO2017197915A1 (zh) | 2016-05-18 | 2017-01-11 | 光刻掩膜板及其制作方法、光刻方法 |
Country Status (3)
Country | Link |
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US (1) | US10466584B2 (zh) |
CN (1) | CN105759562B (zh) |
WO (1) | WO2017197915A1 (zh) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
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CN105759562B (zh) | 2016-05-18 | 2019-11-12 | 京东方科技集团股份有限公司 | 光刻掩膜板及其制作方法、光刻方法 |
CN109270786B (zh) * | 2018-12-10 | 2022-03-15 | 长江存储科技有限责任公司 | 一种掩膜板 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW200625000A (en) * | 2005-01-10 | 2006-07-16 | Taiwan Semiconductor Mfg Co Ltd | Anti-ESD photomask blank |
KR20130044393A (ko) * | 2011-09-23 | 2013-05-03 | (주)마이크로이미지 | 대전 방지 포토 마스크 및 그 제조 방법 |
CN203164592U (zh) * | 2012-07-03 | 2013-08-28 | 上海大学 | 一种接触式曝光掩膜版 |
CN103941540A (zh) * | 2014-04-11 | 2014-07-23 | 京东方科技集团股份有限公司 | 一种掩模板 |
CN203759422U (zh) * | 2014-04-11 | 2014-08-06 | 京东方科技集团股份有限公司 | 一种掩模板 |
CN204374607U (zh) * | 2015-01-23 | 2015-06-03 | 山西大同大学 | 一种掩模板 |
CN105759562A (zh) * | 2016-05-18 | 2016-07-13 | 京东方科技集团股份有限公司 | 光刻掩膜板及其制作方法、光刻方法 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003248294A (ja) * | 2002-02-26 | 2003-09-05 | Oki Degital Imaging:Kk | フォトマスクの製造方法 |
JP2009128558A (ja) * | 2007-11-22 | 2009-06-11 | Hoya Corp | フォトマスク及びフォトマスクの製造方法、並びにパターン転写方法 |
-
2016
- 2016-05-18 CN CN201610329420.3A patent/CN105759562B/zh not_active Expired - Fee Related
-
2017
- 2017-01-11 US US15/533,456 patent/US10466584B2/en not_active Expired - Fee Related
- 2017-01-11 WO PCT/CN2017/070816 patent/WO2017197915A1/zh active Application Filing
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW200625000A (en) * | 2005-01-10 | 2006-07-16 | Taiwan Semiconductor Mfg Co Ltd | Anti-ESD photomask blank |
KR20130044393A (ko) * | 2011-09-23 | 2013-05-03 | (주)마이크로이미지 | 대전 방지 포토 마스크 및 그 제조 방법 |
CN203164592U (zh) * | 2012-07-03 | 2013-08-28 | 上海大学 | 一种接触式曝光掩膜版 |
CN103941540A (zh) * | 2014-04-11 | 2014-07-23 | 京东方科技集团股份有限公司 | 一种掩模板 |
CN203759422U (zh) * | 2014-04-11 | 2014-08-06 | 京东方科技集团股份有限公司 | 一种掩模板 |
CN204374607U (zh) * | 2015-01-23 | 2015-06-03 | 山西大同大学 | 一种掩模板 |
CN105759562A (zh) * | 2016-05-18 | 2016-07-13 | 京东方科技集团股份有限公司 | 光刻掩膜板及其制作方法、光刻方法 |
Also Published As
Publication number | Publication date |
---|---|
US10466584B2 (en) | 2019-11-05 |
CN105759562B (zh) | 2019-11-12 |
US20190094681A1 (en) | 2019-03-28 |
CN105759562A (zh) | 2016-07-13 |
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