WO2017193469A1 - 用于阵列基板栅极驱动电路的电平转换器 - Google Patents

用于阵列基板栅极驱动电路的电平转换器 Download PDF

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WO2017193469A1
WO2017193469A1 PCT/CN2016/089789 CN2016089789W WO2017193469A1 WO 2017193469 A1 WO2017193469 A1 WO 2017193469A1 CN 2016089789 W CN2016089789 W CN 2016089789W WO 2017193469 A1 WO2017193469 A1 WO 2017193469A1
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voltage
resistor
level shifter
input terminal
received
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PCT/CN2016/089789
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English (en)
French (fr)
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张先明
曹丹
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深圳市华星光电技术有限公司
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Publication of WO2017193469A1 publication Critical patent/WO2017193469A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present invention generally relates to the field of liquid crystal display technology, and more particularly to a level shifter for an array substrate gate drive circuit.
  • the Gate Driver On Array (GOA) technology is a method of fabricating a gate scan driving circuit of a Thin Film Transistor (TFT) on an array substrate instead of an external silicon chip.
  • the gate voltage of each row of TFTs in the liquid crystal display can be provided by a GOA circuit.
  • a level shifter Level Shifter
  • the existing level shifting circuit for a GOA-structured liquid crystal display generally includes: a timing controller disposed on the circuit driving board, the timing controller is configured to generate and transmit a logic control signal (Logic Control); A level shifter on the driver board that converts the level of the logic control signal sent by the timing controller. The level-converted control signal is input to the gate driving circuit to drive the TFT in the liquid crystal display to operate.
  • a timing controller disposed on the circuit driving board, the timing controller is configured to generate and transmit a logic control signal (Logic Control);
  • a level shifter on the driver board that converts the level of the logic control signal sent by the timing controller.
  • the level-converted control signal is input to the gate driving circuit to drive the TFT in the liquid crystal display to operate.
  • the difference between the maximum voltage and the minimum voltage of the voltages used by the GOA circuit is 35V or more. Therefore, the level converter can easily cause voltage changes during the voltage change. Too fast, the ripple of the output current of the level shifter is too large, resulting in worse output electromagnetic interference (EMI).
  • EMI output electromagnetic interference
  • the present invention provides a level shifter for an array substrate gate drive circuit, including: a first input terminal, a second input terminal, a third input terminal, a fourth input terminal, and an output terminal.
  • the method further includes: a first resistor and a second resistor; the first input receiving a logic control signal; the second input receiving a reference voltage; and one end of the first resistor receiving a first voltage, the first a three input terminal connected to the other end of the first resistor to receive a voltage from the first resistor; one end of the second resistor receiving a second voltage, and the fourth input terminal being coupled to the second
  • the other end of the resistor receives a voltage from the second resistor; the output is in accordance with the logic control signal and the reference The voltage alternately outputs a voltage received by the third input terminal and a voltage received by the fourth input terminal.
  • the output terminal If the voltage value of the logic control signal is greater than a voltage value of the reference voltage, the output terminal outputs a voltage received by the third input terminal; if a voltage value of the logic control signal is less than a voltage of the reference voltage And the output outputs the voltage received by the fourth input.
  • the first resistor is a first variable resistor and the second resistor is a second variable resistor.
  • the first variable resistor changes a resistance according to the received first control parameter
  • the second variable resistor changes the resistance according to the received second control parameter
  • the first variable resistor includes a plurality of resistors and a first selection switch for selecting one of the plurality of resistors.
  • the first selection switch selects one of the plurality of resistors according to a first control parameter such that the third input is coupled to a resistor selected by the first selection switch to be selected from the first selection switch
  • the resistor receives the voltage.
  • the second variable resistor includes a plurality of resistors and a second selection switch for selecting one of the plurality of resistors.
  • the second selection switch selects one of the plurality of resistors according to a second control parameter such that the fourth input is coupled to a resistor selected by the second selection switch to be selected from the second selection switch
  • the resistor receives the voltage.
  • the logic control signal is a periodic logic level.
  • the period at which the output terminal outputs the voltage received by the third input terminal and the voltage received by the fourth input terminal is the same as the period of the logic control signal.
  • the present invention provides a level shifter for an array substrate gate drive circuit, which alternately outputs a third input terminal via a first according to a logic control signal received by the first input terminal and a reference voltage received by the second input terminal.
  • the voltage received by the resistor and the voltage received by the fourth input via the second resistor effectively reduces the ripple of the output current of the level shifter by increasing the slope of the output voltage change of the variable resistor control output, while reducing the effect of electromagnetic interference.
  • FIG. 1 is a circuit diagram showing a level shifter for an array substrate gate drive circuit in accordance with an embodiment of the present invention.
  • FIG. 2 shows a specific example of the circuit of the level shifter of FIG. 1.
  • a level shifter for an array substrate gate drive circuit according to an embodiment of the present invention will be described below with reference to FIGS. 1 through 2.
  • FIG. 1 shows a circuit schematic of a level shifter for an array substrate gate drive circuit in accordance with an embodiment of the present invention.
  • an embodiment of the present invention provides a level shifter for an array substrate gate driving circuit, including: a first input terminal 10, a second input terminal 20, a third input terminal 30, and a fourth input.
  • the terminal 40 and the output terminal 50 further include: a first resistor R 10 and a second resistor R 20 ; the first input terminal 10 receives the logic control signal V in ; the second input terminal 20 receives the reference voltage V ref ; one end of a resistor R 10 receives a first voltage V GH, the third input terminal 30 is connected to the other end of said first resistor R 10 to R 10 receives a voltage from the first resistor; the first One end of two resistors R 20 receives the second voltage V GL, the fourth input terminal 40 is connected to the other terminal of the second resistor 20 to R 20 received from the second voltage resistor R; the output The terminal 50 alternately outputs the voltage received by the third input terminal 30 and the voltage received by the fourth input terminal 40 according to the logic control signal V in and the reference voltage V ref .
  • a logic control signal V in may be a timing controller generates the logic level periodically. Specifically, when the logic control signal V in is a high level signal, that is, the voltage value of the high level signal is greater than the voltage value of the reference voltage V ref , the output terminal 50 outputs the voltage received by the third input terminal 30, further, the high voltage as the gate voltage (voltage gate high) input to the gate drive circuit to drive the TFT liquid crystal display device is turned on; when the logic control signal V in a low level signal, i.e., the low-level The voltage value of the signal is less than the voltage value of the reference voltage V ref , and the output terminal 50 outputs the voltage received by the fourth input terminal 40. Further, the voltage is input to the gate driving circuit as a gate low voltage (Voltage Gate Low) to The TFT in the driving liquid crystal display is turned off.
  • a gate low voltage Voltage Gate Low
  • the period at which the output terminal 50 outputs the voltage received by the third input terminal 30 and the voltage received by the fourth input terminal 40 is the same as the period of the logic control signal V in .
  • the first input 10 is a non-inverting input of the level shifter and the second input 20 is an inverting input of the level shifter.
  • both the first voltage V GH and the second voltage V GL may be generated by the power management chip, and the first voltage V GH is greater than the second voltage V GL .
  • the first resistor R 10 is a first variable resistor R 100 and the second resistor R 20 is a second variable resistor R 200 .
  • the first variable resistor R 100 changes the resistance according to the received first control parameter
  • the second variable resistor R 200 changes the resistance according to the received second control parameter.
  • FIG. 2 shows a specific example of the circuit of the level shifter of FIG. 1.
  • the first variable resistor R 100 includes a plurality of resistors (R 1 , R 2 . . . R n , n is an integer greater than 2) and is used to select the plurality of resistors One of the first selection switches K 1 .
  • the plurality of resistors (R 1 , R 2 . . . R n ) are fixed resistors of different resistance values.
  • the first selection switch K 1 may select one of the plurality of resistors according to the first control parameter.
  • the first control parameter may be preset in a register.
  • each of the first variable resistors R 100 is connected to the third input terminal 30, and the other end of each of the first variable resistors R 100 is a free end, which may be K 1 according to the first selection switch to select a control parameter of the first free end of the resistor, so that the third input terminal 30 is connected to a first selection switch K 1 is selected from the resistor to the first resistor selection switch K 1 selected Receive voltage.
  • the second variable resistor R 200 includes a plurality of resistors (R 1 ', R 2 '...R n ', n is an integer greater than 2) and is used to select the plurality of resistors A second selection switch K 2 .
  • the plurality of resistors (R 1 ', R 2 '...R n ') are fixed resistors of different resistance values.
  • the second selection switch K 2 may select one of the plurality of resistors according to the second control parameter.
  • the second control parameter may be preset in another register.
  • each of the second variable resistors R 200 is connected to the fourth input terminal 40, and the other end of each of the second variable resistors R 200 is a free end, which may be
  • the second selection switch K 2 selects the free end of a certain resistor according to the second control parameter, such that the fourth input 40 is connected to the resistor selected by the second selection switch K 2 to select the resistor from the second selection switch K 2 Receive voltage.
  • the reference voltage V ref signal periodically changes the control logic 10 receives a first input terminal of the level converter input V in and a second end 20 received by the level shifter outputs a corresponding cycle of the output terminal V out 50 changes, and through the first resistor and the second resistor R 10 R 20 may control the slope of the rise of the output voltage V out of the 50 / decrease output.
  • the level converter output terminal 50 when the voltage value of the logic control signal V in is greater than the reference voltage V ref , the level converter output terminal 50 outputs the voltage received by the third input terminal 30; when the voltage value of the logic control signal V in is less than the reference voltage V ref
  • the level shifter output 50 outputs the voltage received by the fourth input 40.
  • the level shifter output terminal V 50 out of the respective fourth input voltage received by the input terminal 40 becomes a third receiving terminal 30 voltage
  • the level shifter output terminal V out 50 in the process of change the output current of the level shifter is increased, limiting the role of the first resistor R 10 to the output current to hinder, thereby impeding the output terminal V out 50 of the voltage received from the fourth input terminal 40 becomes a third input voltage 30 received voltage received 40 first resistor R and the size of the resistance 10 becomes a fourth input of the third time proportional to the input voltage terminal 30 receives, thus, may control the voltage output terminal V out of the slope 50 rising through a first resistor R 10, effectively prevent the output current ripple output from the output terminal of the voltage rise caused by excessive The problem of excessive wave and electromagnetic interference; as the logic control signal V in received by the first input terminal 10 continues to be high, the output current of the increased level shifter falls close to zero, thus flowing through the first resistor R 10 is connected to the current To zero, so that
  • the logic control signal V in changes from a high level to a low level
  • the voltage received by the third input terminal 30 of the output V out of the level shifter output terminal 50 becomes the voltage received by the fourth input terminal 40.
  • the level shifter output terminal V out 50 in the process of change the output current level of the converter is reduced, limiting the role of the second resistor R 20 to reduce the output current is hindered, thereby impeding the output terminal 50
  • the voltage of the output V out received by the third input terminal 30 becomes the voltage received by the fourth input terminal 40, and the magnitude of the resistance of the second resistor R 20 and the voltage received by the third input terminal 30 become the fourth input terminal 40.
  • the level shifter for the array substrate gate driving circuit according to the embodiment of the present invention is used to effectively reduce the ripple of the level converter output current by increasing the slope of the output voltage variation of the variable resistor control output. At the same time reduce the effect of electromagnetic interference.

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Abstract

一种用于阵列基板栅极驱动电路的电平转换器，包括：第一输入端（10）、第二输入端（20）、第三输入端（30）、第四输入端（40）、输出端（50）、第一电阻器（R 10）和第二电阻器（R 20）；第一输入端（10）接收逻辑控制信号（V in）；第二输入端（20）接收参考电压（V ref）；第一电阻器（R 10）的一端接收第一电压（V GH），第三输入端（30）连接到第一电阻器（R 10）的另一端以从第一电阻器（R 10）接收电压；第二电阻器（R 20）的一端接收第二电压（V GL），第四输入端（40）连接到第二电阻器（R 20）的另一端以从第二电阻器（R 20）接收电压；输出端（50）根据逻辑控制信号（V in）和参考电压（V ref）交替地输出第三输入端（30）接收的电压和第四输入端（40）接收的电压。该电平转换器通过增加可变电阻器控制输出端（40）的输出电压变化的斜率，减小电平转换器输出电流的纹波，同时减少电磁干扰的效果。

Description

用于阵列基板栅极驱动电路的电平转换器 技术领域
本发明总体说来涉及液晶显示技术领域，更具体地讲，涉及一种用于阵列基板栅极驱动电路的电平转换器。
背景技术
阵列基板栅极驱动(Gate Driver On Array，GOA)技术，是一种将薄膜晶体管(Thin Film Transistor，TFT)的栅极扫描驱动电路制作在阵列基板上，以替代外接硅芯片制作的驱动芯片的一种技术。液晶显示器中的每一行TFT的栅极电压可以通过GOA电路提供，在GOA电路中，一般使用电平转换器(Level Shifter)产生时钟控制信号控制每一行TFT开启或关闭。
现有的用于GOA架构液晶显示器的电平转换电路通常包括：一设于电路驱动板上的时序控制器，所述时序控制器用于产生和发送逻辑控制信号(Logic Control)；一设于电路驱动板上的电平转换器，所述电平转换器用于转换由时序控制器发送的逻辑控制信号的电平。经电平转换后的控制信号输入到栅极驱动电路，以驱动液晶显示器中的TFT进行工作。
目前，GOA电路使用的几种电压在高低变化的过程中，最大电压与最小电压的差值会有35V甚至更大，那么，电平转换器在电压变化的过程中，很容易造成电压的变化过快，电平转换器的输出电流的纹波过大，导致输出电磁干扰(EMI)效果更差。
发明内容
本发明的目的在于提供一种用于阵列基板栅极驱动电路的电平转换器，通过增加可变电阻器控制电平转换器输出电压变化的斜率，有效减小电平转换器输出电流的纹波，同时减少电磁干扰的效果。
为实现上述发明目的，本发明提供一种用于阵列基板栅极驱动电路的电平转换器，包括：第一输入端、第二输入端、第三输入端、第四输入端和输出端，还包括：第一电阻器和第二电阻器；所述第一输入端接收逻辑控制信号；所述第二输入端接收参考电压；所述第一电阻器的一端接收第一电压，所述第三输入端连接到所述第一电阻器的另一端以从所述第一电阻器接收电压；所述第二电阻器的一端接收第二电压，所述第四输入端连接到所述第二电阻器的另一端以从所述第二电阻器接收电压；所述输出端根据所述逻辑控制信号和所述参考 电压交替地输出所述第三输入端接收的电压和所述第四输入端接收的电压。
如果所述逻辑控制信号的电压值大于所述参考电压的电压值，则所述输出端输出所述第三输入端接收的电压；如果所述逻辑控制信号的电压值小于所述参考电压的电压值，则所述输出端输出所述第四输入端接收的电压。
所述第一电阻器为第一可变电阻器，所述第二电阻器为第二可变电阻器。
所述第一可变电阻器根据接收的第一控制参数而改变阻值，所述第二可变电阻器根据接收的第二控制参数而改变阻值。
所述第一可变电阻器包括多个电阻器和用于选择所述多个电阻器之一的第一选择开关。
所述第一选择开关根据第一控制参数选择所述多个电阻器之一，从而所述第三输入端连接到所述第一选择开关选择的电阻器以从所述第一选择开关选择的电阻器接收电压。
所述第二可变电阻器包括多个电阻器和用于选择所述多个电阻器之一的第二选择开关。
所述第二选择开关根据第二控制参数选择所述多个电阻器之一，从而所述第四输入端连接到所述第二选择开关选择的电阻器以从所述第二选择开关选择的电阻器接收电压。
所述逻辑控制信号为周期性的逻辑电平。
所述输出端输出所述第三输入端接收的电压和所述第四输入端接收的电压的周期与所述逻辑控制信号的周期相同。
本发明提供一种用于阵列基板栅极驱动电路的电平转换器，根据第一输入端接收的逻辑控制信号和第二输入端接收的参考电压，周期交替地输出第三输入端经由第一电阻器接收的电压和第四输入端经由第二电阻器接收的电压。所述电平转换器通过增加可变电阻器控制输出端的输出电压变化的斜率，有效减小电平转换器输出电流的纹波，同时减少电磁干扰的效果。
附图说明
图1示出本发明实施例的用于阵列基板栅极驱动电路的电平转换器的电路示意图。
图2示出图1的电平转换器的电路一个具体示例。
具体实施方式
下面参照图1至图2描述根据本发明的实施例的用于阵列基板栅极驱动电路的电平转换器。
图1示出根据本发明实施例的用于阵列基板栅极驱动电路的电平转换器的电路示意图。参照图1，本发明的实施例中提出一种用于阵列基板栅极驱动 电路的电平转换器，包括：第一输入端10、第二输入端20、第三输入端30、第四输入端40和输出端50，还包括：第一电阻器R10和第二电阻器R20；第一输入端10接收逻辑控制信号Vin；第二输入端20接收参考电压Vref；所述第一电阻器R10的一端接收第一电压VGH，所述第三输入端30连接到所述第一电阻器R10的另一端以从所述第一电阻器R10接收电压；所述第二电阻器R20的一端接收第二电压VGL，所述第四输入端40连接到所述第二电阻器R20的另一端以从所述第二电阻器R20接收电压；所述输出端50根据所述逻辑控制信号Vin和所述参考电压Vref交替地输出所述第三输入端30接收的电压和所述第四输入端40接收的电压。
在本实施例中，逻辑控制信号Vin可以为时序控制器产生的周期性的逻辑电平。具体说来，当逻辑控制信号Vin为高电平信号时，即所述高电平信号的电压值大于参考电压Vref的电压值，则输出端50输出第三输入端30接收的电压，进一步地，该电压作为栅极高电压(Voltage Gate High)输入至栅极驱动电路，以驱动液晶显示器中的TFT开启；当逻辑控制信号Vin为低电平信号时，即所述低电平信号的电压值小于参考电压Vref的电压值，则输出端50输出第四输入端40接收的电压，进一步地，该电压作为栅极低电压(Voltage Gate Low)输入至栅极驱动电路，以驱动液晶显示器中的TFT关闭。
此外，输出端50输出第三输入端30接收的电压和第四输入端40接收的电压的周期与逻辑控制信号Vin的周期相同。
优选地，第一输入端10为电平转换器的同相输入端，第二输入端20为电平转换器的反相输入端。
在本实施例中，第一电压VGH和第二电压VGL均可以由电源管理芯片产生，第一电压VGH大于第二电压VGL。
作为示例，第一电阻器R10为第一可变电阻器R100，第二电阻器R20为第二可变电阻器R200。所述第一可变电阻器R100根据接收的第一控制参数而改变阻值，所述第二可变电阻器R200根据接收的第二控制参数而改变阻值。
图2示出图1的电平转换器的电路一个具体示例。
参照图2，在一个实施例中，第一可变电阻器R100包括多个电阻器(R1，R2…Rn，n为大于2的整数)和用于选择所述多个电阻器之一的第一选择开关K1。优选地，所述多个电阻器(R1，R2…Rn)为不同阻值的固定电阻器。其中，第一选择开关K1可以根据第一控制参数选择多个电阻器之一，优选地，所述第一控制参数可预设在一寄存器中。具体说来，第一可变电阻器R100中的每一电阻器的一端连接到第三输入端30，第一可变电阻器R100中的每一电阻器的另一端为自由端，可由第一选择开关K1根据第一控制参数选择某一电阻器的自由端，从而第三输入端30连接到第一选择开关K1选择的电阻器以从第一选择开关K1选择的电阻器接收电压。
在一个实施例中，第二可变电阻器R200包括多个电阻器(R1’，R2’…Rn’， n为大于2的整数)和用于选择所述多个电阻器之一的第二选择开关K2。优选地，所述多个电阻器(R1’，R2’…Rn’)为不同阻值的固定电阻器。其中，第二选择开关K2可以根据第二控制参数选择多个电阻器之一，优选地，所述第二控制参数可预设在另一寄存器中。具体说来，第二可变电阻器R200中的每一电阻器的一端连接到第四输入端40，第二可变电阻器R200中的每一电阻器的另一端为自由端，可由第二选择开关K2根据第二控制参数选择某一电阻器的自由端，从而第四输入端40连接到第二选择开关K2选择的电阻器以从第二选择开关K2选择的电阻器接收电压。
本实施例提供的用于阵列基板栅极驱动电路的电平转换器的工作过程为：
根据电平转换器的第一输入端10接收的逻辑控制信号Vin的周期性变化与第二输入端20接收的参考电压Vref，使电平转换器输出端50的输出Vout相应的周期性变化，并通过第一电阻器R10和第二电阻器R20可以控制输出端50的输出Vout的电压上升/下降的斜率。其中，当逻辑控制信号Vin的电压值大于参考电压Vref时，电平转换器输出端50输出第三输入端30接收的电压；当逻辑控制信号Vin的电压值小于参考电压Vref时，电平转换器输出端50输出第四输入端40接收的电压。
具体说来，当逻辑控制信号Vin由低电平变为高电平时，电平转换器输出端50的输出Vout相应地由第四输入端40接收的电压变为第三输入端30接收的电压，该电平转换器输出端50的输出Vout在变化的过程中，电平转换器的输出电流增大，第一电阻器R10的限流作用阻碍输出电流的增大，进而阻碍输出端50的输出Vout由第四输入端40接收的电压变为第三输入端30接收的电压，第一电阻器R10的阻值大小与第四输入端40接收的电压变为第三输入端30接收的电压的时间成正比，因此，通过第一电阻器R10可以控制输出端50的输出Vout的电压上升的斜率，有效避免输出端的输出的电压上升过快造成的输出电流纹波过大和电磁干扰的问题；随着第一输入端10接收的逻辑控制信号Vin持续为高电平，增大的电平转换器的输出电流回落接近于零，因此，流经第一电阻器R10的电流接近于零，故第一电压VGH经由第一电阻器R10产生的压降接近于零，可忽略不计，则第三输入端30接收的电压达到第一电压VGH，即电平转换器输出端50的输出Vout达到第一电压VGH并稳定输出。
同理，当逻辑控制信号Vin由高电平变为低电平时，电平转换器输出端50的输出Vout由第三输入端30接收的电压变为第四输入端40接收的电压，该电平转换器输出端50的输出Vout在变化的过程中，电平转换器的输出电流减小，第二电阻器R20的限流作用阻碍输出电流的减小，进而阻碍输出端50的输出Vout由第三输入端30接收的电压变为第四输入端40接收的电压，第二电阻器R20的阻值大小与第三输入端30接收的电压变为第四输入端40接收的电压的时间成正比，因此，通过第二电阻器R20可以控制输出端50的输出Vout的电压下降的斜率，避免输出的控制信号电压下降过快造成的输出电流纹波过大和电 磁干扰的问题；随着第一输入端10接收的逻辑控制信号Vin持续为低电平，减小的电平转换器的输出电流回升接近于零，因此，流经第二电阻器R20的电流接近于零，故第二电压VGL经由第二电阻器R20产生的压降接近于零，可忽略不计，则第四输入端40接收的电压达到第二电压VGL，即电平转换器输出端50的输出Vout达到第二电压VGL并稳定输出。
采用上述根据本发明实施例的用于阵列基板栅极驱动电路的电平转换器，通过增加可变电阻器控制输出端的输出电压变化的斜率，有效减小电平转换器输出电流的纹波，同时减少电磁干扰的效果。
上面已经结合具体实施例描述了本发明，但是本发明的实施不限于此。在本发明的精神和范围内，本领域技术人员可以进行各种修改和变型，这些修改和变型将落入权利要求限定的保护范围之内。

Claims (10)

  1. 一种用于阵列基板栅极驱动电路的电平转换器，包括：第一输入端、第二输入端、第三输入端、第四输入端和输出端，其中，还包括：第一电阻器和第二电阻器；
    所述第一输入端接收逻辑控制信号；
    所述第二输入端接收参考电压；
    所述第一电阻器的一端接收第一电压，所述第三输入端连接到所述第一电阻器的另一端以从所述第一电阻器接收电压；
    所述第二电阻器的一端接收第二电压，所述第四输入端连接到所述第二电阻器的另一端以从所述第二电阻器接收电压；
    所述输出端根据所述逻辑控制信号和所述参考电压交替地输出所述第三输入端接收的电压和所述第四输入端接收的电压。
  2. 如权利要求1所述的电平转换器，其中，如果所述逻辑控制信号的电压值大于所述参考电压的电压值，则所述输出端输出所述第三输入端接收的电压；
    如果所述逻辑控制信号的电压值小于所述参考电压的电压值，则所述输出端输出所述第四输入端接收的电压。
  3. 如权利要求1所述的电平转换器，其中，所述第一电阻器为第一可变电阻器，所述第二电阻器为第二可变电阻器。
  4. 如权利要求3所述的电平转换器，其中，所述第一可变电阻器根据接收的第一控制参数而改变阻值，所述第二可变电阻器根据接收的第二控制参数而改变阻值。
  5. 如权利要求4所述的电平转换器，其中，所述第一可变电阻器包括多个电阻器和用于选择所述多个电阻器之一的第一选择开关。
  6. 如权利要求5所述的电平转换器，其中，所述第一选择开关根据第一控制参数选择所述多个电阻器之一，从而所述第三输入端连接到所述第一选择开关选择的电阻器以从所述第一选择开关选择的电阻器接收电压。
  7. 如权利要求4所述的电平转换器，其中，所述第二可变电阻器包括多个电阻器和用于选择所述多个电阻器之一的第二选择开关。
  8. 如权利要求7所述的电平转换器，其中，所述第二选择开关根据第二控制参数选择所述多个电阻器之一，从而所述第四输入端连接到所述第二选择开关选择的电阻器以从所述第二选择开关选择的电阻器接收电压。
  9. 如权利要求1所述的电平转换器，其中，所述逻辑控制信号为周期性的逻辑电平。
  10. 如权利要求9所述的电平转换器，其中，所述输出端输出所述第三输入端接收的电压和所述第四输入端接收的电压的周期与所述逻辑控制信号的 周期相同。
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