WO2017177686A1 - 同时实现rsa/ecc加解密算法的装置 - Google Patents

同时实现rsa/ecc加解密算法的装置 Download PDF

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Publication number
WO2017177686A1
WO2017177686A1 PCT/CN2016/107549 CN2016107549W WO2017177686A1 WO 2017177686 A1 WO2017177686 A1 WO 2017177686A1 CN 2016107549 W CN2016107549 W CN 2016107549W WO 2017177686 A1 WO2017177686 A1 WO 2017177686A1
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module
calculation
control module
send
command
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PCT/CN2016/107549
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English (en)
French (fr)
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林先萌
王永
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深圳市中兴微电子技术有限公司
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Publication of WO2017177686A1 publication Critical patent/WO2017177686A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/30—Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/30—Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy
    • H04L9/3066—Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy involving algebraic varieties, e.g. elliptic or hyper-elliptic curves
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/30—Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy
    • H04L9/3006—Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy underlying computational problems or public-key parameters

Definitions

  • the present invention relates to public key encryption and decryption techniques, and more particularly to a simultaneous implementation of RSA (Ron Rivest, Adi Shamir, Leonard Adleman, Ronald Levist, Adi Samuel and Leonard Adelman) / ECC ( Elliptic curve cryptography, an apparatus for encryption and decryption algorithms.
  • RSA Rivest, Adi Shamir, Leonard Adleman, Ronald Levist, Adi Samuel and Leonard Adelman
  • ECC Elliptic curve cryptography
  • RSA public key encryption algorithm is currently the most influential public key encryption algorithm. It can resist most of the password attacks known so far. It has been recommended as the public key data by the International Organization for Standardization (ISO). Encryption standard.
  • the security of RSA public key encryption algorithm is based on the difficulty of large prime factorization. With the rapid development of computer processing speed and distributed computing theory, the shorter RSA key is no longer safe. Currently, a 1024-bit key can be cracked in a short period of time. Therefore, in order to improve the security strength of RSA encryption, a higher bit width key is required. However, as the key length increases, the speed of RSA encryption and decryption will be greatly reduced, which seriously affects the efficiency of use.
  • ECC Elliptic Curve Cryptography
  • the core of RSA encryption algorithm is large modulus exponentiation.
  • the core of ECC encryption algorithm is elliptic point multiplication. Because the calculation steps are very complicated, most of the encryption and decryption devices only implement one encryption algorithm at a time, but can realize two kinds of encryption algorithms at the same time. The device of the encryption algorithm is difficult to balance the operation speed, area and power consumption, and cannot be adapted to different scenarios with high requirements on speed or area respectively.
  • embodiments of the present invention are directed to providing an apparatus for simultaneously implementing an RSA/ECC encryption and decryption algorithm to simultaneously implement two RSA/ECC encryption and decryption algorithms in one apparatus.
  • An embodiment of the present invention provides an apparatus for simultaneously implementing an RSA/ECC encryption and decryption algorithm, where the apparatus includes:
  • a central processing unit CPU interface module a main control module, a complex computing control module, and a basic computing module;
  • the CPU interface module is configured to receive configuration parameters and send the configuration parameters to the main control module, and return status parameters in the main control module.
  • the main control module is configured to receive and store configuration parameters, send a calculation command to the complex computing control module according to the configuration parameter, send the status parameter to the CPU interface module, and receive the basic computing module to send a read command to send a calculation parameter to the basic calculation module;
  • the complex computing control module is configured to receive a calculation command sent by the main control module, generate an operation command according to the calculation command, and send the operation command to the basic calculation module; and receive a completion signal of the basic calculation module;
  • the basic calculation module is configured to receive the operation command, and send a read command to the main control module to obtain the calculation parameter, and complete calculation according to the operation command and the acquired calculation parameter, to the
  • the complex calculation control module sends the completion signal and the calculation result is Send to the main control module.
  • calculation command includes an RSA/ECC calculation
  • the complex calculation control module is configured to decompose the received RSA/ECC calculation in the calculation command into a series of modular multiplication operations, and generate an operation command corresponding to each modular multiplication operation to send to the basic calculation module.
  • the device further comprises:
  • the slave interface is configured to receive the configuration parameter sent by the CPU interface module, and send the configuration parameter to the main control module;
  • the host interface is configured to receive the configuration parameter sent by the main control module and store the configuration.
  • the device further comprises:
  • a storage module configured to store the plaintext parameter, the ciphertext parameter, the key parameter, and the calculated intermediate result of the basic computing module.
  • the configuration parameter is configured to configure an algorithm of the apparatus to operate as an RSA algorithm or an ECC algorithm, a key bit width, and an operation mode, the working mode including an encryption mode and a decryption mode.
  • the CPU interface module, the slave interface, and the host interface each support a peripheral bus APB protocol, a system bus AHB protocol, an on-chip bus AXI protocol, and an ACE_Lite bus protocol.
  • An apparatus for simultaneously implementing an RSA/ECC encryption and decryption algorithm comprising:
  • CPU CPU, CPU module, main control module, complex computing control module, basic computing module, direct memory access DMA controller, key generation module, true random number generation module and large multiplication processing module;
  • the CPU interface module is configured to receive configuration parameters and send the configuration parameters to the main control module. Blocking, returning a status parameter in the main control module;
  • the main control module is configured to receive and store configuration parameters, send a key generation command to the key generation module according to the configuration parameter, send a calculation command to the complex calculation control module, and send the status parameter to
  • the CPU interface module receives a read command sent by the basic calculation module, and sends a calculation parameter to the basic calculation module;
  • the complex calculation control module is configured to receive a calculation command sent by the main control module, generate an addition and subtraction operation command according to the calculation command, send the calculation command to the basic calculation module, and generate a modular multiplication operation command to send to the large a multiplication processing module; receiving a completion signal of the basic calculation module and the large multiplication processing module;
  • the basic calculation module is configured to receive the addition and subtraction operation command, and send a read command to the main control module to obtain the calculation parameter, according to the addition and subtraction operation command and the acquired calculation parameter Completing the calculation, sending the completion signal to the complex computing control module, and transmitting the calculation result to the main control module;
  • the key generation module is configured to receive the key generation command, and invoke the true random number generation module to generate a random number generation key pair, and send the key pair to the main control module for storage;
  • the true random number generating module is configured to generate a true random number and send the key to the key generation module;
  • the DMA controller is configured to receive and store data
  • the large multiplication processing module is configured to receive the modular multiplication operation command, and send a read command to the DMA controller to acquire the calculation parameter, according to the modular multiplication operation command and the acquired calculation parameter.
  • the calculation is completed, the calculated intermediate result is stored to a memory, and the completion signal is sent to the complex computing control module.
  • calculation command includes an RSA/ECC calculation
  • the complex calculation control module is configured to decompose the received RSA/ECC calculation in the calculation command into a series of modular multiplication operations and addition and subtraction operations, and generate the addition and subtraction operations
  • the command is sent to the basic calculation module, and the modular multiplication operation command is generated and sent to the large multiplication processing module.
  • the device further comprises:
  • the slave interface is configured to receive the configuration parameter sent by the CPU interface module, and send the configuration parameter to the main control module;
  • the host interface is configured to receive the configuration parameter sent by the main control module and store the configuration.
  • the CPU interface module, the host interface, and the slave interface each support a peripheral bus APB protocol, a system bus AHB protocol, an on-chip bus AXI protocol, and an ACE_Lite bus protocol.
  • the configuration parameter is configured to configure an algorithm of the apparatus to operate as an RSA algorithm or an ECC algorithm, a key bit width, and an operation mode, the working mode including an encryption mode and a decryption mode.
  • the device further comprises:
  • a storage module configured to store the plaintext parameter, the ciphertext parameter, the key parameter, the calculation intermediate result of the basic calculation module, and the calculation intermediate result of the large number multiplication processing module.
  • the storage module employs a dual port random access memory RAM.
  • the large multiplication processing module is configured to invoke a scalable cyclic pulsation array to perform a large modulus multiplication operation of any bit width.
  • An apparatus for simultaneously implementing an RSA/ECC encryption and decryption algorithm includes: the CPU interface module configured to receive a configuration parameter and send the configuration parameter to the main control module, and return a status parameter in the main control module;
  • the main control module is configured to receive and store configuration parameters, send a calculation command to the complex computing control module according to the configuration parameter, send the status parameter to the CPU interface module, and receive the basic computing module to send Read command
  • the basic calculation module sends a calculation parameter;
  • the complex calculation control module is configured to receive a calculation command sent by the main control module, generate an operation command according to the calculation command, and send the operation command to the basic calculation module; and receive the basic calculation a completion signal of the module;
  • the basic calculation module is configured to receive the operation command, and send a read command to the main control module to obtain the calculation parameter, according to the operation command and the obtained calculation parameter Calculating, sending a completion signal to the complex computing control module, and transmitting the calculation result to the main control module.
  • FIG. 1 is a schematic structural diagram of an apparatus for simultaneously implementing an RSA/ECC encryption and decryption algorithm according to an embodiment of the present invention
  • FIG. 2 is a schematic diagram 1 of a configuration for performing a public key encryption operation using a device for simultaneously implementing an RSA/ECC encryption and decryption algorithm provided by the embodiment;
  • FIG. 3 is a schematic structural diagram of an apparatus for simultaneously implementing an RSA/ECC encryption and decryption algorithm according to an embodiment of the present invention
  • FIG. 4 is a second schematic diagram of a configuration for performing a public key encryption operation using the apparatus for simultaneously implementing the RSA/ECC encryption and decryption algorithm provided by the embodiment.
  • the present invention provides an RSA/ECC public key encryption and decryption apparatus, which can simultaneously implement two RSA/ECC public key encryption and decryption algorithms.
  • the user can perform corresponding configuration according to the speed priority or the area priority scenario, and greatly improve the adaptability of the present invention in different application scenarios.
  • the device supports various bus protocols such as Advanced Peripheral Bus (APB) protocol, Advanced High Performance Bus (AHB) protocol, Advanced eXtensible Interface (AXI) protocol and ACE_Lite, and supports RSA/ECC.
  • the key generation function supports keys of any length according to the size of the storage space.
  • FIG. 1 is a schematic structural diagram of an apparatus for simultaneously implementing an RSA/ECC encryption and decryption algorithm according to an embodiment of the present invention. As shown in FIG. 1, the apparatus provided in this embodiment includes:
  • CPU Central Processing Unit
  • the CPU interface module 101 is configured to receive configuration parameters and send the configuration parameters to the main control module, and return the status parameters in the main control module.
  • the main control module 102 is configured to receive and store configuration parameters, send a calculation command to the complex computing control module according to the configuration parameter, send the status parameter to the CPU interface module, and receive the basic computing module. Sending a read command, sending a calculation parameter to the basic calculation module;
  • the complex calculation control module 103 is configured to receive a calculation command sent by the main control module, generate an operation command according to the calculation command, and send the operation command to the basic calculation module; and receive a completion signal of the basic calculation module;
  • the basic calculation module 104 is configured to receive the operation command, and send a read command to the main control module to obtain the calculation parameter, and complete calculation according to the operation command and the acquired calculation parameter,
  • the complex computing control module sends a completion signal and sends the calculation result to the main control module.
  • the calculation command includes an RSA/ECC calculation; the complex calculation control module 103 is configured to decompose the received RSA/ECC calculation in the calculation command into a series of modular multiplication operations, and generate corresponding to each modular multiplication operation.
  • the operation command is sent to the basic calculation module.
  • the complex computing control module mainly implements elliptic point multiplication, elliptic point addition operation in the ECC algorithm, large modulus exponentiation operation in the RSA algorithm, and generalized modular division and Montgomey precomputation operation control;
  • the basic calculation module mainly implements basic operations such as addition, subtraction, multiplication, modulus reduction, and modular multiplication of large numbers.
  • the apparatus further includes: a slave interface and a host interface; the slave interface configured to receive the configuration parameter sent by the CPU interface module, and send the configuration parameter
  • the host module is configured to receive the configuration parameter sent by the main control module and store the configuration parameter.
  • the apparatus further includes: a storage module configured to store the plaintext parameter, the ciphertext parameter, the key parameter, and the calculated intermediate result of the basic computing module.
  • the configuration parameter is used to configure an algorithm for running the device to be an RSA algorithm or an ECC algorithm, a key bit width, and an operation mode, where the working mode includes an encryption mode and a decryption mode;
  • the CPU interface module Both the slave interface and the host interface support an APB protocol, an AHB protocol, an AXI protocol, and an ACE_Lite bus protocol.
  • the application scenario shown in Figure 2 is in the area priority or power consumption priority scenario.
  • the workflow is as follows:
  • the processor accesses the device CPU interface via the bus and sends configuration parameters.
  • the algorithm of the device is configured as an RSA or ECC algorithm, and then the key bit width is configured, and finally the working mode is the encryption mode.
  • the bus master sends the plaintext, key and other data to the slave interface of the device, and the slave interface transmits the data to the master control module.
  • the master module transmits the data of the slave interface to the host interface and is controlled by the host interface to complete the storage.
  • the main control module sends the RSA/ECC encryption command to the complex computing control module, and the complex computing control module decomposes the RSA modular exponentiation into a series of modular multiplication operations according to the command, and decomposes the ECC point multiplication operation into a series of elliptic point addition operations, and The elliptic point addition operation is decomposed into large number modular multiplication and addition operations. All arithmetic commands are sent to the basic calculation module.
  • the basic calculation module receives the modular multiplication and addition issued by the complex calculation control module. After the command, the mode is reduced, etc., the read command is sent to the main control module, the calculation parameter is read from the memory through the main control module, and the basic operation unit such as the adder and the multiplier having a small area inside the module is called to realize the large number. Multiplication, addition, and modulus reduction. After the calculation is completed, the result is stored in the memory through the main control module, the completion signal is sent to the complex calculation control module, and the next basic operation command is awaited.
  • Encryption is completed and the ciphertext is sent.
  • the main control module controls the host interface to read the ciphertext data in the memory and send it to the bus host through the slave interface.
  • the technical solution of the embodiment can implement RSA encryption and decryption operation and ECC encryption and decryption operation at the same time, realize RSA and ECC switching by CPU to device control register configuration, realize RSA signature/verification, ECDSA signature/verification, and ECDH key exchange function.
  • Reduce software pre-calculation and other operations reduce the complexity of pre-computation, and improve the efficiency of computing.
  • it can support keys of any length.
  • FIG. 3 is a schematic structural diagram of an apparatus for implementing an RSA/ECC encryption and decryption algorithm according to an embodiment of the present invention.
  • the apparatus for simultaneously implementing the RSA/ECC encryption and decryption algorithm provided by this embodiment includes:
  • CPU interface module main control module, complex calculation control module, basic calculation module, direct memory access DMA controller, key generation module, true random number generation module and large number multiplication processing module;
  • the CPU interface module is configured to receive configuration parameters and send the configuration parameters to the main control module, and return status parameters in the main control module.
  • the main control module is configured to receive and store configuration parameters, send a key generation command to the key generation module according to the configuration parameter, send a calculation command to the complex calculation control module, and send the status parameter to
  • the CPU interface module receives a read command sent by the basic calculation module, and sends a calculation parameter to the basic calculation module;
  • the complex computing control module is configured to receive a calculation command sent by the main control module, And generating, according to the calculation command, an addition and subtraction operation command sent to the basic calculation module, generating a modular multiplication operation command, sending the macro multiplication processing module, and receiving the basic calculation module and the large multiplication processing module Complete signal
  • the basic calculation module is configured to receive the addition and subtraction operation command, and send a read command to the main control module to obtain the calculation parameter, according to the addition and subtraction operation command and the acquired calculation parameter Completing the calculation, sending the completion signal to the complex computing control module, and transmitting the calculation result to the main control module;
  • the key generation module is configured to receive the key generation command, and invoke the true random number generation module to generate a random number generation key pair, and send the key pair to the main control module for storage;
  • the true random number generating module is configured to generate a true random number and send the key to the key generation module;
  • the DMA controller is configured to receive and store data
  • the large multiplication processing module is configured to receive the modular multiplication operation command, and send a read command to the DMA controller to acquire the calculation parameter, according to the modular multiplication operation command and the acquired calculation parameter.
  • the calculation is completed, the calculated intermediate result is stored to a memory, and the completion signal is sent to the complex computing control module.
  • the large multiplication processing module is configured to invoke a scalable cyclic pulsation array to perform a large modulus multiplication operation of any bit width.
  • the calculation command includes an RSA/ECC calculation
  • the complex calculation control module is configured to decompose the received RSA/ECC calculation in the calculation command into a series of modular multiplication operations and Adding or subtracting an operation, and generating the addition and subtraction operation command to send to the basic calculation module, and generating the modular multiplication operation command to send to the large number multiplication processing module.
  • the device further includes: a slave interface and a host interface; the slave interface is configured to receive the configuration parameter sent by the CPU interface module, and send the configuration parameter to the main control module
  • the host interface is configured to receive the sending by the main control module Configure parameters and store them.
  • the CPU interface module, the host interface, and the slave interface all support an APB protocol, an AHB protocol, an AXI protocol, and an ACE_Lite bus protocol;
  • the configuration parameter is configured to configure an algorithm for running the device as An RSA algorithm or an ECC algorithm, a key bit width, and an operating mode, the working mode including an encryption mode and a decryption mode.
  • the device further includes: a storage module configured to store a plaintext parameter, a ciphertext parameter, a key parameter, a calculation intermediate result of the basic calculation module, and a calculation intermediate result of the large number multiplication processing module;
  • the storage module uses a dual port random access memory RAM.
  • FIG. 4 a process of performing a public key encryption operation using the apparatus for simultaneously implementing the RSA/ECC encryption and decryption algorithm provided by this embodiment will be described in detail.
  • the application scenario shown in Figure 4 is in the speed priority scenario.
  • the workflow is as follows:
  • the processor accesses the device CPU interface via the bus and sends configuration parameters. Firstly, the algorithm of the device is configured as an RSA or ECC algorithm, and then the key bit width is configured and the large multiplication processor is called, the enable key generation function is configured again, and finally the working mode is the encryption mode.
  • the bus master sends data to the slave interface of the device.
  • the slave interface transfers the data to the DMA controller.
  • the DMA controller transfers the slave interface data to the host interface, and the host interface controls the storage.
  • the main control module sends a key generation command to the key generation module, and the key generation module calls the true random number generation module to generate a random number, completes screening the prime factor, generates a key, and deletes the prime factor to implement key pair generation.
  • the key pair is stored in the memory through the control of the master module and the public key is issued as required.
  • the main control module sends the RSA/ECC encryption command to the complex computing control module, and the complex computing control module decomposes the RSA modular exponentiation into a series of modular multiplication operations according to the command, and decomposes the ECC point multiplication operation into a series of elliptic point addition operations, and Ellipse
  • the dot addition operation is decomposed into large modulus multiplication and addition operations.
  • the modular multiplication operation command is sent to the large multiplication processing module, and the addition operation command is sent to the basic calculation module.
  • the large multiplication processing module starts a modular multiplication operation according to a command issued by the complex computational control module. After reading the calculation parameters from the memory, the modular multiplication calculation is performed through the cyclic pulsation array inside the module, and the intermediate result is stored in the storage space specially opened for the module. After the modular multiplication calculation is completed, the large multiplication processing module sends a completion signal to the complex computation control module and waits for the next modular multiplication operation command.
  • the basic calculation module sends a read command to the main control module, reads the calculation parameters from the memory through the main control module, and calls the adder inside the module to realize the large number addition and the analog reduction. Operation. After the calculation is completed, the result is stored in the memory through the main control module, the completion signal is sent to the complex calculation control module, and the next basic operation command is awaited.
  • Encryption is completed and the ciphertext is sent.
  • the DMA controller controls the host interface to read the ciphertext data in the memory and send it to the bus master through the slave interface.
  • the technical solution of the embodiment can implement RSA encryption and decryption operation and ECC encryption and decryption operation at the same time, realize RSA and ECC switching by CPU to device control register configuration, realize RSA signature/verification, ECDSA signature/verification, and ECDH key exchange function.
  • the device includes a true random number generator and a key generation module, and the key generation function can be implemented in the device.
  • the complex calculation control module can realize ECC point multiplication, RSA modular power, general modular division, and Montgomery pre-computation, etc.
  • a variety of complex operations ; reduced software pre-computation and other operations, reduced the complexity of pre-computation, and improved operational efficiency.
  • the device can support keys of any length. It can be applied to various application scenarios such as speed priority, area priority, and power consumption priority.
  • the device includes a large number of arithmetic processing modules, which can quickly complete the modular multiplication operation and greatly improve the speed of encryption and decryption.
  • the complex computing control module in the device can select whether to call the large number arithmetic processing module according to different application scenario requirements, thereby matching various requirements.
  • embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention can take the form of a hardware embodiment, a software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.
  • the RSA encryption and decryption operation and the ECC encryption and decryption operation can be simultaneously implemented, and the RSA and ECC switching is implemented by the CPU to the device control register configuration; the RSA signature/verification, the ECDSA signature/verification, and the ECDH key exchange function are implemented; Software pre-calculation and other operations reduce the complexity of pre-calculation and improve the efficiency of the operation. At the same time, according to the size of the storage space, it can support keys of any length.

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Abstract

本发明实施例提供一种同时实现RSA/ECC加解密算法的装置，包括：CPU接口模块，配置为接收配置参数并发送给主控模块，返回状态参数；主控模块，配置为接收并存储配置参数，根据所述配置参数向复杂计算控制模块发送计算命令；将状态参数发送给所述CPU接口模块；接收读取命令并向基本计算模块发送计算参数；复杂计算控制模块，配置为接收计算命令，根据所述计算命令，生成运算命令发送给基本计算模块；接收基本计算模块的完成信号；基本计算模块，配置为接收运算命令，并向主控模块发送读取命令以获取计算参数，根据运算命令以及计算参数完成计算，向复杂计算控制模块发送完成信号，同时将计算结果发送给主控模块。

Description

同时实现RSA/ECC加解密算法的装置 技术领域
本发明涉及公钥加解密技术，尤其涉及一种同时实现RSA(Ron Rivest，Adi Shamir，Leonard Adleman，罗纳德·李维斯特、阿迪·萨莫尔和伦纳德·阿德曼)/ECC(Elliptic curve cryptography，椭圆曲线密码学)加解密算法的装置。
背景技术
RSA公钥加密算法是目前最有影响力的公钥加密算法，它能够抵抗到目前为止已知的绝大多数密码攻击，已被国际标准化组织(International Organization for Standardization，ISO)推荐为公钥数据加密标准。
RSA公钥加密算法的安全性是基于大素数因式分解的困难性，随着计算机处理速度与分布式计算等理论的飞速发展，较短的RSA密钥已不再安全。目前1024位长度的密钥也可以在较短的时间内被破解，因此，为了提高RSA加密的安全强度，需要采用更高位宽的密钥。但是，随着密钥长度的增加，RSA加解密的速度将大幅降低，严重影响使用效率。
椭圆曲线密码学(Elliptic Curve Cryptography，ECC)加密算法的安全性是基于解决椭圆曲线离散对数问题的困难性，目前已知的公钥加密体制中，ECC加密算法是对每比特所提供加密强度最高的一种体制，即在位宽相同的情况下，ECC加密算法具有最高的安全强度。因此，在对位宽，功耗，安全性等方面有更高要求的应用场景下，ECC加密算法具有极大的优势。
公钥加密算法中密钥对的生成需要若干个随机的大素数，以及一系列复杂的计算；目前绝大部分的密钥对生成是通过软件实现的；但通过软件 生成公钥密钥对耗时较长，且会有被第三方窃取素数或随机因子的风险。
RSA加密算法的核心为大数模幂运算，ECC加密算法的核心为椭圆点乘运算；由于计算步骤非常复杂，目前大部分加解密装置只是单一实现其中一种加密算法，而可以同时实现两种加密算法的装置，又很难平衡运算速度、面积和功耗，不能适配于分别对速度或面积有较高要求的不同场景。
发明内容
有鉴于此，本发明实施例期望提供一种同时实现RSA/ECC加解密算法的装置，以在一个装置中同时实现RSA/ECC两种加解密算法。
本发明实施例的技术方案是这样实现的：
本发明实施例提供一种同时实现RSA/ECC加解密算法的装置，所述装置包括：
中央处理器CPU接口模块、主控模块、复杂计算控制模块和基本计算模块；
其中，所述CPU接口模块，配置为接收配置参数并发送给所述主控模块，返回所述主控模块中的状态参数；
所述主控模块，配置为接收并存储配置参数，根据所述配置参数向所述复杂计算控制模块发送计算命令；将所述状态参数发送给所述CPU接口模块；接收所述基本计算模块发送的读取命令，向所述基本计算模块发送计算参数；
所述复杂计算控制模块，配置为接收所述主控模块发送的计算命令，根据所述计算命令，生成运算命令发送给所述基本计算模块；接收所述基本计算模块的完成信号；
所述基本计算模块，配置为接收所述运算命令，并向所述主控模块发送读取命令以获取所述计算参数，根据所述运算命令以及获取的所述计算参数完成计算，向所述复杂计算控制模块发送完成信号，同时将计算结果 发送给所述主控模块。
如上所述的装置，其中，所述计算命令中包含RSA/ECC计算；
所述复杂计算控制模块配置为，将接收到的所述计算命令中的RSA/ECC计算分解成一系列模乘运算，并生成与各模乘运算对应的运算命令发送给所述基本计算模块。
如上所述的装置，其中，所述装置还包括：
从机接口和主机接口；
所述从机接口，配置为接收所述CPU接口模块发送的所述配置参数，并将所述配置参数发送给所述主控模块；
所述主机接口，配置为接收所述主控模块发送的所述配置参数，并进行存储。
如上所述的装置，其中，所述装置还包括：
存储模块，配置为存储明文参数、密文参数、密钥参数和所述基本计算模块的计算中间结果。
如上所述的装置，其中，所述配置参数用于配置所述装置运行的算法为RSA算法或ECC算法、密钥位宽以及工作模式，所述工作模式包括加密模式和解密模式。
如上所述的装置，其中，所述CPU接口模块、所述从机接口和所述主机接口均支持***总线APB协议、***总线AHB协议、片内总线AXI协议和ACE_Lite总线协议。
一种同时实现RSA/ECC加解密算法的装置，所述装置包括：
中央处理器CPU接口模块、主控模块、复杂计算控制模块、基本计算模块、直接内存存取DMA控制器、密钥生成模块、真随机数发生模块和大数乘法处理模块；
其中，所述CPU接口模块，配置为接收配置参数并发送给所述主控模 块，返回所述主控模块中的状态参数；
所述主控模块，配置为接收并存储配置参数，根据所述配置参数向所述密钥生成模块发送密钥生成命令；向所述复杂计算控制模块发送计算命令；将所述状态参数发送给所述CPU接口模块；接收所述基本计算模块发送的读取命令，向所述基本计算模块发送计算参数；
所述复杂计算控制模块，配置为接收所述主控模块发送的计算命令，根据所述计算命令，生成加减法运算命令发送给所述基本计算模块，生成模乘运算命令发送给所述大数乘法处理模块；接收所述基本计算模块和所述大数乘法处理模块的完成信号；
所述基本计算模块，配置为接收所述加减法运算命令，并向所述主控模块发送读取命令以获取所述计算参数，根据所述加减法运算命令以及获取的所述计算参数完成计算，向所述复杂计算控制模块发送所述完成信号，同时将计算结果发送给所述主控模块；
所述密钥生成模块，配置为接收所述密钥生成命令，并调用所述真随机数发生模块生成随机数生成密钥对，并发送给所述主控模块进行存储；
所述真随机数发生模块，配置为产生真随机数并发送给所述密钥生成模块；
所述DMA控制器，配置为接收并存储数据；
所述大数乘法处理模块，配置为接收所述模乘运算命令，并向所述DMA控制器发送读取命令以获取所述计算参数，根据所述模乘运算命令以及获取的所述计算参数完成计算，将计算的中间结果存储至存储器，向所述复杂计算控制模块发送所述完成信号。
如上所述的装置，其中，所述计算命令中包含RSA/ECC计算；
所述复杂计算控制模块配置为，将接收到的所述计算命令中的RSA/ECC计算分解成一系列模乘运算和加减运算，并生成所述加减法运算 命令发送给所述基本计算模块，生成所述模乘运算命令发送给所述大数乘法处理模块。
如上所述的装置，其中，所述装置还包括：
从机接口和主机接口；
所述从机接口，配置为接收所述CPU接口模块发送的所述配置参数，并将所述配置参数发送给所述主控模块；
所述主机接口，配置为接收所述主控模块发送的所述配置参数，并进行存储。
如上所述的装置，其中，所述CPU接口模块、所述主机接口和所述从机接口均支持***总线APB协议、***总线AHB协议、片内总线AXI协议和ACE_Lite总线协议。
如上所述的装置，其中，所述配置参数用于配置所述装置运行的算法为RSA算法或ECC算法、密钥位宽以及工作模式，所述工作模式包括加密模式和解密模式。
如上所述的装置，其中，所述装置还包括：
存储模块，配置为存储明文参数、密文参数、密钥参数、所述基本计算模块的计算中间结果和所述大数乘法处理模块的计算中间结果。
如上所述的装置，其中，所述存储模块采用双口随机存取存储器RAM。
如上所述的装置，其中，所述大数乘法处理模块，配置为调用可伸缩的循环脉动阵列完成任意位宽的大数模乘运算。
本发明实施例提供的同时实现RSA/ECC加解密算法的装置，包括：所述CPU接口模块，配置为接收配置参数并发送给所述主控模块，返回所述主控模块中的状态参数；所述主控模块，配置为接收并存储配置参数，根据所述配置参数向所述复杂计算控制模块发送计算命令；将所述状态参数发送给所述CPU接口模块；接收所述基本计算模块发送的读取命令，向所 述基本计算模块发送计算参数；所述复杂计算控制模块，配置为接收所述主控模块发送的计算命令，根据所述计算命令，生成运算命令发送给所述基本计算模块；接收所述基本计算模块的完成信号；所述基本计算模块，配置为接收所述运算命令，并向所述主控模块发送读取命令以获取所述计算参数，根据所述运算命令以及获取的所述计算参数完成计算，向所述复杂计算控制模块发送完成信号，同时将计算结果发送给所述主控模块。能够同时实现RSA/ECC两种公钥加解密算法，用户可以根据速度优先或面积优先的场景进行相应的配置，大幅提高本发明在不同应用场景下的适配性。
附图说明
图1为本发明实施例提供的同时实现RSA/ECC加解密算法的装置的结构示意图；
图2为使用本实施例提供的同时实现RSA/ECC加解密算法的装置完成公钥加密运算的配置示意图一；
图3为本发明实施例提供的同时实现RSA/ECC加解密算法的装置的结构示意图；
图4为使用本实施例提供的同时实现RSA/ECC加解密算法的装置完成公钥加密运算的配置示意图二。
具体实施方式
在本发明的各实施例中，本发明提出了一种RSA/ECC公钥加解密装置，可以同时实现RSA/ECC两种公钥加解密算法。用户可以根据速度优先或面积优先的场景进行相应的配置，大幅提高本发明在不同应用场景下的适配性。该装置支持***总线(Advanced Peripheral Bus，APB)协议、***总线(Advanced High performance Bus，AHB)协议、片内总线(Advanced eXtensible Interface，AXI)协议和ACE_Lite等多种总线协议，支持RSA/ECC 密钥生成功能，根据存储空间大小，可支持任意长度的密钥。
图1为本发明实施例提供的同时实现RSA/ECC加解密算法的装置的结构示意图。如图1所示，本实施例提供的装置包括：
中央处理器(Central Processing Unit，CPU)接口模块101、主控模块102、复杂计算控制模块103和基本计算模块104；
其中，所述CPU接口模块101，配置为接收配置参数并发送给所述主控模块，返回所述主控模块中的状态参数；
所述主控模块102，配置为接收并存储配置参数，根据所述配置参数向所述复杂计算控制模块发送计算命令；将所述状态参数发送给所述CPU接口模块；接收所述基本计算模块发送的读取命令，向所述基本计算模块发送计算参数；
所述复杂计算控制模块103，配置为接收所述主控模块发送的计算命令，根据所述计算命令，生成运算命令发送给所述基本计算模块；接收所述基本计算模块的完成信号；
所述基本计算模块104，配置为接收所述运算命令，并向所述主控模块发送读取命令以获取所述计算参数，根据所述运算命令以及获取的所述计算参数完成计算，向所述复杂计算控制模块发送完成信号，同时将计算结果发送给所述主控模块。
所述计算命令中包含RSA/ECC计算；所述复杂计算控制模块103，配置为将接收到的所述计算命令中的RSA/ECC计算分解成一系列模乘运算，并生成与各模乘运算对应的运算命令发送给所述基本计算模块。
需要说明的是，所述复杂计算控制模块主要实现ECC算法中的椭圆点乘、椭圆点加运算，RSA算法中的大数模幂运算，以及通用的模除和Montgomey预计算等运算控制；所述基本计算模块主要实现大数的加法、减法、乘法、模约减和模乘等基本运算。
在本发明的其他实施例中，所述装置还包括：从机接口和主机接口；所述从机接口，配置为接收所述CPU接口模块发送的所述配置参数，并将所述配置参数发送给所述主控模块；所述主机接口，配置为接收所述主控模块发送的所述配置参数，并进行存储。
在本发明的其他实施例中，所述装置还包括：存储模块，配置为存储明文参数、密文参数、密钥参数和所述基本计算模块的计算中间结果。
需要说明的是，所述配置参数用于配置所述装置运行的算法为RSA算法或ECC算法、密钥位宽以及工作模式，所述工作模式包括加密模式和解密模式；所述CPU接口模块、所述从机接口和所述主机接口均支持APB协议、AHB协议、AXI协议和ACE_Lite总线协议。
参照图2，对使用本实施例提供的同时实现RSA/ECC加解密算法的装置完成公钥加密运算的过程进行详细说明。图2所示的应用场景为在面积优先或功耗优先场景，工作流程如下：
装置初始化。处理器通过总线访问装置CPU接口，发送配置参数。首先配置装置的算法为RSA或ECC算法，其次配置密钥位宽，最后配置工作模式为加密模式。
接收并存储数据。总线主机发送明文、密钥等数据到装置的从机接口，从机接口将数据传递给主控模块，主控模块将从机接口数据传递给主机接口由主机接口控制完成存储。
RSA/ECC加密复杂计算控制。主控模块发送RSA/ECC加密命令到复杂计算控制模块，复杂计算控制模块根据命令将RSA模幂运算分解成一系列的模乘运算，将ECC点乘运算分解成一系列的椭圆点加运算，并将椭圆点加运算分解成大数模乘和加法运算。所有的运算命令均发送至基本计算模块。
完成基本计算。基本计算模块收到复杂计算控制模块发出的模乘、加 法、模约减等命令后，发送读取命令至主控模块，通过主控模块从存储器中读取计算参数，调用模块内部的面积较小的加法器、乘法器等基本运算单元实现大数乘法、加法与模约减运算。计算完成后通过主控模块将结果存入存储器中，发送完成信号至复杂计算控制模块，并等待下一次基本运算命令。
加密完成，发送密文。主控模块控制主机接口读取存储器中的密文数据，通过从机接口发送给总线主机。
本实施例的技术方案，可以同时实现RSA加解密运算和ECC加解密运算，通过CPU对装置控制寄存器配置实现RSA与ECC的切换；实现RSA签名/验证、ECDSA签名/验证以及ECDH密钥交换功能；减少软件预计算等操作，降低预计算的复杂度，提高了运算效率。同时可以根据存储空间的大小，可支持任意长度的密钥。
图3为本发明实施例提供的同时实现RSA/ECC加解密算法的装置的结构示意图，如图3所示，本实施例提供的同时实现RSA/ECC加解密算法的装置包括：
CPU接口模块、主控模块、复杂计算控制模块、基本计算模块、直接内存存取DMA控制器、密钥生成模块、真随机数发生模块和大数乘法处理模块；
其中，所述CPU接口模块，配置为接收配置参数并发送给所述主控模块，返回所述主控模块中的状态参数；
所述主控模块，配置为接收并存储配置参数，根据所述配置参数向所述密钥生成模块发送密钥生成命令；向所述复杂计算控制模块发送计算命令；将所述状态参数发送给所述CPU接口模块；接收所述基本计算模块发送的读取命令，向所述基本计算模块发送计算参数；
所述复杂计算控制模块，配置为接收所述主控模块发送的计算命令， 根据所述计算命令，生成加减法运算命令发送给所述基本计算模块，生成模乘运算命令发送给所述大数乘法处理模块；接收所述基本计算模块和所述大数乘法处理模块的完成信号；
所述基本计算模块，配置为接收所述加减法运算命令，并向所述主控模块发送读取命令以获取所述计算参数，根据所述加减法运算命令以及获取的所述计算参数完成计算，向所述复杂计算控制模块发送所述完成信号，同时将计算结果发送给所述主控模块；
所述密钥生成模块，配置为接收所述密钥生成命令，并调用所述真随机数发生模块生成随机数生成密钥对，并发送给所述主控模块进行存储；
所述真随机数发生模块，配置为产生真随机数并发送给所述密钥生成模块；
所述DMA控制器，配置为接收并存储数据；
所述大数乘法处理模块，配置为接收所述模乘运算命令，并向所述DMA控制器发送读取命令以获取所述计算参数，根据所述模乘运算命令以及获取的所述计算参数完成计算，将计算的中间结果存储至存储器，向所述复杂计算控制模块发送所述完成信号。
在本发明的其他实施例中，所述大数乘法处理模块，配置为调用可伸缩的循环脉动阵列完成任意位宽的大数模乘运算。
在本发明的其他实施例中，所述计算命令中包含RSA/ECC计算；所述复杂计算控制模块配置为，将接收到的所述计算命令中的RSA/ECC计算分解成一系列模乘运算和加减运算，并生成所述加减法运算命令发送给所述基本计算模块，生成所述模乘运算命令发送给所述大数乘法处理模块。
进一步地，所述装置还包括：从机接口和主机接口；所述从机接口，配置为接收所述CPU接口模块发送的所述配置参数，并将所述配置参数发送给所述主控模块；所述主机接口，配置为接收所述主控模块发送的所述 配置参数，并进行存储。
需要说明的是，所述CPU接口模块、所述主机接口和所述从机接口均支持APB协议、AHB协议、AXI协议和ACE_Lite总线协议；所述配置参数配置为配置所述装置运行的算法为RSA算法或ECC算法、密钥位宽以及工作模式，所述工作模式包括加密模式和解密模式。
进一步地，所述装置还包括：存储模块，配置为存储明文参数、密文参数、密钥参数、所述基本计算模块的计算中间结果和所述大数乘法处理模块的计算中间结果；实际应用中，所述存储模块采用双口随机存取存储器RAM。
参照图4，对使用本实施例提供的同时实现RSA/ECC加解密算法的装置完成公钥加密运算的过程进行详细说明。图4所示的应用场景为在速度优先场景，工作流程如下：
装置初始化。处理器通过总线访问装置CPU接口，发送配置参数。首先配置装置的算法为RSA或ECC算法，其次配置密钥位宽以及调用大数乘法处理器，再次配置使能密钥生成功能，最后配置工作模式为加密模式。
接收并存储数据。总线主机发送数据到装置的从机接口，从机接口将数据传递给DMA控制器，DMA控制器将从机接口数据传递给主机接口，由主机接口控制完成存储。
生成密钥对。主控模块发送密钥生成命令至密钥生成模块，密钥生成模块调用真随机数产生模块生成随机数，完成筛选质数因子，生成密钥，删除质数因子等操作实现密钥对生成。密钥对通过主控模块控制存储在存储器中，并根据需求将公钥发出。
RSA/ECC加密复杂计算控制。主控模块发送RSA/ECC加密命令到复杂计算控制模块，复杂计算控制模块根据命令将RSA模幂运算分解成一系列的模乘运算，将ECC点乘运算分解成一系列的椭圆点加运算，并将椭圆 点加运算分解成大数模乘和加法运算。根据CPU配置，模乘运算命令发送至大数乘法处理模块，加法运算命令发送至基本计算模块。
模乘与加法计算。大数乘法处理模块根据复杂计算控制模块发出的命令开始一次模乘运算。从存储器中读取计算参数后，经过模块内部的循环脉动阵列完成模乘计算，中间结果存储到为该模块专门开辟的存储空间中。模乘计算完成后，大数乘法处理模块发送完成信号至复杂计算控制模块，并等待下一次模乘运算命令。基本计算模块收到复杂计算控制模块发出的加法命令后，发送读取命令至主控模块，通过主控模块从存储器中读取计算参数，调用模块内部的加法器实现大数加法与模约减运算。计算完成后通过主控模块将结果存入存储器中，发送完成信号至复杂计算控制模块，并等待下一次基本运算命令。
加密完成，发送密文。DMA控制器控制主机接口读取存储器中的密文数据，通过从机接口发送给总线主机。
本实施例的技术方案，可以同时实现RSA加解密运算和ECC加解密运算，通过CPU对装置控制寄存器配置实现RSA与ECC的切换；实现RSA签名/验证、ECDSA签名/验证以及ECDH密钥交换功能；装置中包含了真随机数发生器与密钥生成模块，可以在装置中实现密钥生成功能。与通常的软件生成密钥相比，安全性更强，密钥生成速度更快，用户操作更便捷；复杂计算控制模块能够实现ECC点乘，RSA模幂，通用的模除以及Montgomery预计算等多种复杂运算；减少了软件预计算等操作，降低了预计算的复杂度，提高了运算效率。同时可以根据存储空间的大小，可支持任意长度的密钥。可以适用于速度优先、面积优先、功耗优先等各种不同应用场景。装置中包含了大数运算处理模块，可以快速完成模乘运算，大幅提高加解密运算速度。同时，装置中的复杂计算控制模块可以根据不同的应用场景需求，选择是否调用大数运算处理模块，从而匹配各种需求。
本领域内的技术人员应明白，本发明的实施例可提供为方法、***、或计算机程序产品。因此，本发明可采用硬件实施例、软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器和光学存储器等)上实施的计算机程序产品的形式。
本发明是参照根据本发明实施例的方法、设备(***)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
以上所述，仅为本发明的较佳实施例而已，并非用于限定本发明的保护范围。
工业实用性
本实施例中，可以同时实现RSA加解密运算和ECC加解密运算，通过CPU对装置控制寄存器配置实现RSA与ECC的切换；实现RSA签名/验证、ECDSA签名/验证以及ECDH密钥交换功能；减少软件预计算等操作，降低预计算的复杂度，提高了运算效率。同时可以根据存储空间的大小，可支持任意长度的密钥。

Claims (14)

  1. 一种同时实现RSA/ECC加解密算法的装置，所述装置包括：
    中央处理器CPU接口模块、主控模块、复杂计算控制模块和基本计算模块；
    其中，所述CPU接口模块，配置为接收配置参数并发送给所述主控模块，返回所述主控模块中的状态参数；
    所述主控模块，配置为接收并存储配置参数，根据所述配置参数向所述复杂计算控制模块发送计算命令；将所述状态参数发送给所述CPU接口模块；接收所述基本计算模块发送的读取命令，向所述基本计算模块发送计算参数；
    所述复杂计算控制模块，配置为接收所述主控模块发送的计算命令，根据所述计算命令，生成运算命令发送给所述基本计算模块；接收所述基本计算模块的完成信号；
    所述基本计算模块，配置为接收所述运算命令，并向所述主控模块发送读取命令以获取所述计算参数，根据所述运算命令以及获取的所述计算参数完成计算，向所述复杂计算控制模块发送完成信号，同时将计算结果发送给所述主控模块。
  2. 根据权利要求1所述的装置，其中，所述计算命令中包含RSA/ECC计算；
    所述复杂计算控制模块配置为，将接收到的所述计算命令中的RSA/ECC计算分解成一系列模乘运算，并生成与各模乘运算对应的运算命令发送给所述基本计算模块。
  3. 根据权利要求2所述的装置，其中，所述装置还包括：
    从机接口和主机接口；
    所述从机接口，配置为接收所述CPU接口模块发送的所述配置参数， 并将所述配置参数发送给所述主控模块；
    所述主机接口，配置为接收所述主控模块发送的所述配置参数，并进行存储。
  4. 根据权利要求3所述的装置，其中，所述装置还包括：
    存储模块，配置为存储明文参数、密文参数、密钥参数和所述基本计算模块的计算中间结果。
  5. 根据权利要求4所述的装置，其中，所述配置参数用于配置所述装置运行的算法为RSA算法或ECC算法、密钥位宽以及工作模式，所述工作模式包括加密模式和解密模式。
  6. 根据权利要求5所述的装置，其中，所述CPU接口模块、所述从机接口和所述主机接口均支持***总线APB协议、***总线AHB协议、片内总线AXI协议和ACE_Lite总线协议。
  7. 一种同时实现RSA/ECC加解密算法的装置，其中，所述装置包括：
    中央处理器CPU接口模块、主控模块、复杂计算控制模块、基本计算模块、直接内存存取DMA控制器、密钥生成模块、真随机数发生模块和大数乘法处理模块；
    其中，所述CPU接口模块，配置为接收配置参数并发送给所述主控模块，返回所述主控模块中的状态参数；
    所述主控模块，配置为接收并存储配置参数，根据所述配置参数向所述密钥生成模块发送密钥生成命令；向所述复杂计算控制模块发送计算命令；将所述状态参数发送给所述CPU接口模块；接收所述基本计算模块发送的读取命令，向所述基本计算模块发送计算参数；
    所述复杂计算控制模块，配置为接收所述主控模块发送的计算命令，根据所述计算命令，生成加减法运算命令发送给所述基本计算模块，生 成模乘运算命令发送给所述大数乘法处理模块；接收所述基本计算模块和所述大数乘法处理模块的完成信号；
    所述基本计算模块，配置为接收所述加减法运算命令，并向所述主控模块发送读取命令以获取所述计算参数，根据所述加减法运算命令以及获取的所述计算参数完成计算，向所述复杂计算控制模块发送所述完成信号，同时将计算结果发送给所述主控模块；
    所述密钥生成模块，配置为接收所述密钥生成命令，并调用所述真随机数发生模块生成随机数生成密钥对，并发送给所述主控模块进行存储；
    所述真随机数发生模块，配置为产生真随机数并发送给所述密钥生成模块；
    所述DMA控制器，配置为接收并存储数据；
    所述大数乘法处理模块，配置为接收所述模乘运算命令，并向所述DMA控制器发送读取命令以获取所述计算参数，根据所述模乘运算命令以及获取的所述计算参数完成计算，将计算的中间结果存储至存储器，向所述复杂计算控制模块发送所述完成信号。
  8. 根据权利要求7所述的装置，其中，所述计算命令中包含RSA/ECC计算；
    所述复杂计算控制模块配置为，将接收到的所述计算命令中的RSA/ECC计算分解成一系列模乘运算和加减运算，并生成所述加减法运算命令发送给所述基本计算模块，生成所述模乘运算命令发送给所述大数乘法处理模块。
  9. 根据权利要求8所述的装置，其中，所述装置还包括：
    从机接口和主机接口；
    所述从机接口，配置为接收所述CPU接口模块发送的所述配置参数， 并将所述配置参数发送给所述主控模块；
    所述主机接口，配置为接收所述主控模块发送的所述配置参数，并进行存储。
  10. 根据权利要求9所述的装置，其中，所述CPU接口模块、所述主机接口和所述从机接口均支持***总线APB协议、***总线AHB协议、片内总线AXI协议和ACE_Lite总线协议。
  11. 根据权利要求9所述的装置，其中，所述配置参数用于配置所述装置运行的算法为RSA算法或ECC算法、密钥位宽以及工作模式，所述工作模式包括加密模式和解密模式。
  12. 根据权利要求7所述的装置，其中，所述装置还包括：
    存储模块，配置为存储明文参数、密文参数、密钥参数、所述基本计算模块的计算中间结果和所述大数乘法处理模块的计算中间结果。
  13. 根据权利要求12所述的装置，其中，所述存储模块采用双口随机存取存储器RAM。
  14. 根据权利要求8所述的装置，其中，所述大数乘法处理模块，配置为调用可伸缩的循环脉动阵列完成任意位宽的大数模乘运算。
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