WO2017156899A1 - 阵列基板、液晶显示面板及液晶显示装置 - Google Patents

阵列基板、液晶显示面板及液晶显示装置 Download PDF

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WO2017156899A1
WO2017156899A1 PCT/CN2016/085467 CN2016085467W WO2017156899A1 WO 2017156899 A1 WO2017156899 A1 WO 2017156899A1 CN 2016085467 W CN2016085467 W CN 2016085467W WO 2017156899 A1 WO2017156899 A1 WO 2017156899A1
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substrate
layer
gate
drain
liquid crystal
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PCT/CN2016/085467
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English (en)
French (fr)
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徐向阳
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深圳市华星光电技术有限公司
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Priority to US15/110,404 priority Critical patent/US20180108786A1/en
Publication of WO2017156899A1 publication Critical patent/WO2017156899A1/zh

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Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular to an array substrate, a liquid crystal display panel having the array substrate, and a liquid crystal display device.
  • the thin film transistor 10 of this structure includes a gate electrode 12, a gate insulating layer (GI) 13, an active layer 14, a source 15 and a drain which are sequentially formed on a substrate substrate 11. 16.
  • the channel P of the thin film transistor 10 is formed on the active layer 14.
  • the width c of the channel P is smaller than the width a of the gate 12 and the width b of the active layer 14.
  • the width a of the gate 12 is greater than the width b of the active layer 14.
  • the active layer 14 can provide a carrier of sufficient concentration to achieve conduction between the source 15 and the drain 16 when a voltage is applied to the gate 12, and prevent backlighting of the backlight module when the thin film transistor 10 is turned off Leakage occurs when the active layer 14 is present.
  • the parasitic capacitance formed by the large overlapping area of the source 15 and the drain 16 and the gate 12 is also large, so that the voltage of the pixel electrode of the liquid crystal display changes greatly when the thin film transistor 10 is switched. , affecting the display quality.
  • the present invention provides an array substrate, a liquid crystal display panel, and a liquid crystal display device, which can reduce the parasitic capacitance between the source and the drain and the gate, thereby improving display quality.
  • the invention provides an array substrate comprising: a substrate substrate; a gate formed on the substrate substrate; a gate insulating layer formed on the substrate substrate and covering the gate; and an active layer formed on the gate On the pole insulating layer and above the gate, the active layer includes a polysilicon semiconductor layer and an ohmic contact layer sequentially formed on the gate insulating layer, and a side of the polysilicon semiconductor layer facing away from the gate is formed with a channel, and the ohmic contact layer is formed a slit located above the channel and communicating with the channel, wherein the orthographic projection of the active layer on the substrate substrate covers the gate substrate and the substrate substrate on both sides thereof, and the channel is positive on the substrate substrate. The projection is located within the area where the gate is located; the protective layer is formed on the channel; the source and the drain are formed On the active layer and at the two ends of the active layer.
  • the orthographic projection of the source on the substrate substrate overlaps with the gate portion, and the orthogonal projection of the drain on the substrate substrate does not overlap with the gate.
  • the orthographic projection of the drain on the substrate substrate overlaps with the gate portion, and the orthographic projection of the source on the substrate substrate does not overlap with the gate.
  • the orthographic projection of the source and the drain on the substrate substrate does not overlap with the gate.
  • the array substrate further includes: a flat passivation layer formed on the source, the drain, and the active layer, the flat passivation layer being formed with a contact hole exposing a surface of the drain; the pixel electrode being formed on the flat passivation layer and In the contact hole, the pixel electrode is electrically connected to the drain through the contact hole.
  • the array substrate further includes: a flat passivation layer formed on the source, the drain, and the active layer, the flat passivation layer being formed with a contact hole exposing a surface of the drain; and a common electrode formed on the flat passivation layer; An insulating layer is formed on the common electrode; a pixel electrode is formed on the insulating layer and the flat passivation layer and in the contact hole, and the pixel electrode is electrically connected to the drain through the contact hole.
  • the surface of the protective layer comprises an Al 2 O 3 layer
  • the Al 2 O 3 layer is thermally annealed by an Al layer formed by magnetron sputtering in an atmosphere having an oxygen concentration higher than 21% at a temperature of 300 to 400 ° C. be made of.
  • a liquid crystal display panel includes a first substrate and a second substrate disposed at a relatively spaced interval, and a liquid crystal filled between the first substrate and the second substrate, wherein one of the first substrate and the second substrate
  • the array substrate comprises: a substrate substrate; a gate formed on the substrate substrate; a gate insulating layer formed on the substrate substrate and covering the gate; and an active layer formed on the gate
  • An insulating layer is above the gate, and a side of the active layer facing away from the gate is formed with a channel, wherein an orthographic projection of the active layer on the substrate substrate covers the gate and the substrate substrate on both sides thereof, and The orthographic projection of the channel on the substrate substrate is located within the region of the gate; the source and drain are formed on the active layer and are respectively located at opposite ends of the active layer.
  • the active layer includes a polysilicon semiconductor layer sequentially formed on the gate insulating layer, an ohmic contact layer, a side of the polysilicon semiconductor layer facing away from the gate is formed with a channel, and the ohmic contact layer is formed above the channel and with the channel Intersecting slits.
  • the array substrate further includes: a flat passivation layer formed on the source, the drain, and the active layer, the flat passivation layer being formed with a contact hole exposing a surface of the drain; the pixel electrode being formed on the flat passivation layer and In the contact hole, the pixel electrode is electrically connected to the drain through the contact hole.
  • the array substrate further includes: a flat passivation layer formed on the source, the drain, and the active layer, the flat passivation layer being formed with a contact hole exposing a surface of the drain; and a common electrode formed on the flat passivation layer; An insulating layer is formed on the common electrode; a pixel electrode is formed on the insulating layer and the flat passivation layer and in the contact hole, and the pixel electrode is electrically connected to the drain through the contact hole.
  • the present invention provides a liquid crystal display device comprising a liquid crystal display panel and a backlight module for providing light to the liquid crystal display panel
  • the array substrate of the liquid crystal display panel comprises: a substrate substrate; a gate electrode formed on the substrate substrate; a gate insulating layer formed on the substrate substrate and covering the gate; the active layer is formed on the gate insulating layer and above the gate, and the active layer is formed with a channel on a side facing away from the gate, wherein the active layer
  • the orthographic projection of the layer on the substrate substrate covers the gate substrate and the substrate substrate on both sides thereof, and the orthographic projection of the channel on the substrate substrate is located within the region where the gate is located; the source and the drain are formed On the active layer and at the two ends of the active layer.
  • the active layer includes a polysilicon semiconductor layer sequentially formed on the gate insulating layer, an ohmic contact layer, a side of the polysilicon semiconductor layer facing away from the gate is formed with a channel, and the ohmic contact layer is formed above the channel and with the channel Intersecting slits.
  • the array substrate further includes: a flat passivation layer formed on the source, the drain, and the active layer, the flat passivation layer being formed with a contact hole exposing a surface of the drain; the pixel electrode being formed on the flat passivation layer and In the contact hole, the pixel electrode is electrically connected to the drain through the contact hole.
  • the array substrate further includes: a flat passivation layer formed on the source, the drain, and the active layer, the flat passivation layer being formed with a contact hole exposing a surface of the drain; and a common electrode formed on the flat passivation layer; An insulating layer is formed on the common electrode; a pixel electrode is formed on the insulating layer and the flat passivation layer and in the contact hole, and the pixel electrode is electrically connected to the drain through the contact hole.
  • the orthographic projection of the active layer of the thin film transistor on the substrate substrate covers the gate and the substrate substrate on both sides thereof, and the channel of the thin film transistor
  • the orthographic projection on the substrate substrate is located within the region where the gate is located, that is, the width of the design gate is smaller than the width of the active layer and larger than the width of the channel, and the source and drain are reduced by shortening the width of the gate.
  • the overlap area of the gates reduces the parasitic capacitance between the source and drain and the gate, improving display quality.
  • FIG. 1 is a cross-sectional view showing the structure of a thin film transistor according to an embodiment of the prior art
  • FIG. 2 is a cross-sectional view showing the structure of an array substrate according to an embodiment of the present invention.
  • FIG. 3 is a cross-sectional view showing the structure of an array substrate according to another embodiment of the present invention.
  • FIG. 4 is a cross-sectional view showing the structure of an array substrate according to still another embodiment of the present invention.
  • Figure 5 is a cross-sectional view showing the structure of a liquid crystal display panel according to an embodiment of the present invention.
  • Fig. 6 is a cross-sectional view showing the structure of a liquid crystal display device according to an embodiment of the present invention.
  • the array substrate 20 (Array Substrate, also known as Thin Film Transistor Substrate, TFT substrate or thin film transistor substrate) includes a substrate substrate 21 and a thin film transistor 22 formed on the substrate substrate 21, and is flat.
  • An overcoat layer 23 and a pixel electrode 24 include a gate electrode 221, a gate insulating layer 222, an active layer 223, and a source 224 and a drain 225.
  • the gate electrode 221 is formed on the substrate substrate 21; the gate insulating layer 222 is formed on the substrate substrate 21 and covers the gate electrode 221; the active layer 223 is formed on the gate insulating layer 222 and located at the gate electrode 221 Above, a side of the active layer 223 facing away from the gate 221 is formed with a channel P which is a back channel of the thin film transistor 22; a source 224 and a drain 225 are formed on the active layer 223 and respectively located on the active layer Both ends of the 223; a flat passivation layer 23 is formed on the source 224, the drain 225, the active layer 223, and the gate insulating layer 222 not covered by the thin film transistor 22, and the flat passivation layer 23 is formed with the surface of the exposed drain 225
  • the contact hole O 1 ; the pixel electrode 24 is formed on the flat passivation layer 23 and in the contact hole O 1 , and the pixel electrode 24 can be electrically connected to the drain 225 of the thin film transistor 22 through the contact hole O 1
  • the orthographic projection of the active layer 223 on the substrate substrate 21 covers the gate 221 and the two sides of the gate 221.
  • the substrate substrate 21, and the orthographic projection of the channel P on the substrate substrate 21 is located within the region where the gate electrode 221 is located, wherein the orthographic projection refers to the active layer along the line of sight perpendicular to the substrate substrate 21. 223 and projection of the channel P on the substrate substrate 21.
  • a indicates a region corresponding to the gate 221
  • b indicates a region corresponding to the active layer 223
  • c indicates a region corresponding to the channel P
  • a, b, and c may respectively represent the gate 221 and the main The width of the movable layer 223 and the channel P in the horizontal direction in the drawing. That is, the width a of the gate 221 is designed to be smaller than the width b of the active layer 223 and larger than the width c of the channel P, that is, c ⁇ a ⁇ b.
  • the embodiment of the present invention reduces the overlapping area of the source 224 and the gate 221 (the orthographic projection on the substrate substrate 21) and the drain 225 and the gate by shortening the width of the gate 221 The sum of the overlapping regions of the poles 221 (the orthographic projections on the substrate substrate 21), thereby reducing the parasitic capacitance between the source 224 and the drain 225 and the gate 221, and improving the liquid crystal display panel having the array substrate 20 and The display quality of the liquid crystal display device.
  • d and e shown in FIG. 2 indicate an ohmic contact area, where d represents a backlight illumination area, and e represents a gate occlusion area.
  • the active layer 223 includes a polysilicon (a-Si) semiconductor layer 2231 and an ohmic contact layer 2232 which are sequentially formed on the gate insulating layer 222.
  • the ohmic contact layer 2232 includes a region d and a region e, and is formed after the polysilicon semiconductor layer 2231 is heavily doped.
  • the polysilicon semiconductor layer 2231 includes, but is not limited to, a metal oxide semiconductor layer, for example, including indium gallium oxide (IGO).
  • IZO Indium zinc oxide
  • IGZO indium gallium zinc oxide
  • ITO indium tin oxide
  • a side of the polysilicon semiconductor layer 2231 facing away from the gate 221 is formed with the channel P
  • the ohmic contact layer 2232 Located above the channel P and formed with a slit O2 communicating with the channel P. Since the carrier mobility of the metal oxide semiconductor layer is high, the embodiment of the present invention can be in the active layer even if the overlapping area of the source 224 and the drain 225 and the gate 221 is small in the structural design of the thin film transistor 22.
  • a conductive path is formed in 223.
  • the primary purpose of the embodiment of the present invention is to reduce the overlapping area of the source 224 and the drain 225 and the gate 221 by designing the width a of the gate 221 to be smaller than the width b of the active layer 223.
  • the core is that the width a of the gate 221 is smaller than
  • the width b of the active layer 223 is not necessarily limited to the widths of the source 224 and the drain 225.
  • the embodiment of the present invention is based on the above Other designs are also possible, such as: first, the orthographic projection of source 224 on substrate substrate 21 partially overlaps gate 221, while drain 225 The orthographic projection on the substrate substrate 21 does not overlap with the gate electrode 221; secondly, the orthographic projection of the drain electrode 225 on the substrate substrate 21 partially overlaps the gate electrode 221, and the source electrode 224 is on the substrate substrate. The orthographic projection on 21 does not overlap with the gate 221; third, the orthographic projection of the source 224 and the drain 225 on the substrate substrate 21 does not overlap with the gate 221.
  • the array substrate 20 also has other structures of the prior art, for example, further includes a common electrode formed in the array substrate 20 and a protective layer between the common electrode and the pixel electrode 24.
  • 3 is a cross-sectional view showing the structure of an array substrate according to another embodiment of the present invention. To describe the differences between the various embodiments, the same structural elements are given the same reference numerals. As shown in FIG. 3, on the basis of, but different from, the description of the embodiment shown in FIG. 2, the array substrate 20 of the present embodiment further includes a common electrode 30 formed between the flat passivation layer 23 and the pixel electrode 24.
  • the insulating layer 31, that is, the common electrode 30 is formed on the flat passivation layer 23; the insulating layer 31 is formed on the common electrode 30, wherein the insulating layer 31 is also called a PV (passivation) layer; the pixel electrode 24 is formed in the insulating layer. 23 and 31 and the upper layer 1, the pixel electrode 24 may be connected to the contact holes planar passivation layer O O 1 through the contact hole 225 and the drain electrode 22 of the thin film transistor.
  • the array substrate 20 of the present embodiment further includes a protective layer 41 formed on the channel P. Since the semiconductor forming the channel P is a material extremely sensitive to water and oxygen, water molecules and oxygen molecules are highly susceptible to their electrical properties, so in order to improve the electrical stability of the channel P, it is necessary to be on the channel P.
  • a protective layer 41 is formed, which may also be referred to as a water oxygen barrier layer or an Etch Stop Layer (ESL) layer.
  • the material of the protective layer 41 includes, but is not limited to, silicon oxide SiO 2 , silicon nitride Si 3 N 4 , and chemical vapor deposition (CVD), atomic layer epitaxy (ALD), and magnetron sputtering. Produced by means of sputtering (Sputter).
  • the surface of the protective layer 41 may further include an Al 2 O 3 layer, and the Al 2 O 3 layer is formed by an Al layer formed by magnetron sputtering in an atmosphere having an oxygen concentration higher than 21% at a temperature of 300 to 400 ° C. Prepared by thermal annealing. Specifically, the Al atom undergoes an oxidation reaction in an oxygen-rich atmosphere having an oxygen O 2 concentration higher than 21%, and can generate Al 2 O 3 to the greatest extent, while a temperature of 300 to 400 ° C can promote the oxidation reaction to cause the Al layer.
  • the thermal annealing treatment in an oxygen-rich atmosphere can simultaneously have three functions: one is to reduce the density of the defect state of the channel P, and obtain good electrical properties of the active layer; and second, to some extent repair the active layer 223.
  • the manufacturing process of magnetron sputtering or etching damages the channel P; the third is to oxidize the Al layer to a higher film of Al 2 O 3 to form a better trench. Road protection layer.
  • the embodiment of the invention further provides a liquid crystal display panel as shown in FIG.
  • the liquid crystal display panel 50 includes an array substrate 51 and a color filter substrate (Color filter, CF substrate or color filter substrate) 52 disposed at a distance, and is sandwiched between the array substrate 51 and the color filter substrate.
  • the array substrate 51 includes the array substrate 20 of any of the above embodiments, and thus has the same advantageous effects.
  • the embodiment of the present invention further provides a liquid crystal display device 60 as shown in FIG. 6 .
  • the liquid crystal display device 60 includes the liquid crystal display panel 50 and a backlight module 61 that supplies light to the liquid crystal display panel 50 . Since the liquid crystal display device 60 also has the above-described design of the array substrate 20, it also has the same advantageous effects.

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Abstract

一种阵列基板（20）、液晶显示面板（50）及液晶显示装置（60），设计栅极（221）的宽度（a）小于薄膜晶体管（22）的主动层（223）的宽度（b）且大于薄膜晶体管（22）的沟道（P）的宽度（c），通过缩短栅极（221）的宽度（a），减小源极（224）和漏极（225）与栅极（221）的重叠区域，从而缩小源极（224）和漏极（225）与栅极（221）之间的寄生电容，提升显示品质。

Description

阵列基板、液晶显示面板及液晶显示装置 【技术领域】
本发明涉及液晶显示技术领域，具体而言涉及一种阵列基板以及具有该阵列基板的液晶显示面板、液晶显示装置。
【背景技术】
随着液晶显示器(Liquid Crystal Display，LCD)尺寸和清晰度的增加，具有BCE(Back Channel Etching，背沟道刻蚀)结构的薄膜晶体管(Thin Film Transistor，TFT)已崭露头角并表现出巨大的市场应用前景。如图1所示，该结构的薄膜晶体管10包括依次形成于衬底基材11上的栅极12、栅极绝缘层(Gate Insulation Layer，GI)13、主动层14、源极15和漏极16。其中，主动层14上形成有薄膜晶体管10的沟道P，沟道P的宽度c小于栅极12的宽度a以及主动层14的宽度b，栅极12的宽度a大于主动层14的宽度b，从而使得在对栅极12施加电压时主动层14能够提供足够浓度的载子以实现源极15和漏极16之间的导通，并且在薄膜晶体管10关闭时防止背光模组的背光照射主动层14时产生漏电。但是在该结构设计中，源极15和漏极16与栅极12的重叠区域较大所形成的寄生电容也较大，从而使得液晶显示器的像素电极在薄膜晶体管10开关时的电压变化较大，影响显示品质。
【发明内容】
鉴于此，本发明提供一种阵列基板、液晶显示面板及液晶显示装置，能够缩小源极和漏极与栅极之间的寄生电容，提升显示品质。
本发明提供的一种阵列基板，包括：衬底基材；栅极，形成于衬底基材上；栅极绝缘层，形成于衬底基材上并覆盖栅极；主动层，形成于栅极绝缘层上且位于栅极的上方，主动层包括依次形成于栅极绝缘层上的多晶硅半导体层、欧姆接触层，多晶硅半导体层背向栅极的一侧形成有沟道，欧姆接触层形成有位于沟道上方且与沟道相通的狭缝，其中主动层在衬底基材上的正投影覆盖栅极及其两侧的衬底基材，且沟道在衬底基材上的正投影位于栅极所在区域之内；保护层，形成于沟道上；源极和漏极，形成 于主动层上且分别位于主动层的两端。
其中，源极在衬底基材上的正投影与栅极部分重叠，漏极在衬底基材上的正投影与栅极无重叠。
其中，漏极在衬底基材上的正投影与栅极部分重叠，源极在衬底基材上的正投影与栅极无重叠。
其中，源极和漏极在衬底基材上的正投影与栅极无重叠。
其中，阵列基板还包括：平坦钝化层，形成于源极、漏极以及主动层上，平坦钝化层形成有暴露漏极的表面的接触孔；像素电极，形成于平坦钝化层上以及接触孔内，像素电极通过接触孔与漏极电连接。
其中，阵列基板还包括：平坦钝化层，形成于源极、漏极以及主动层上，平坦钝化层形成有暴露漏极的表面的接触孔；公共电极，形成于平坦钝化层上；绝缘层，形成于公共电极上；像素电极，形成于绝缘层和平坦钝化层上以及接触孔内，像素电极通过接触孔与漏极电连接。
其中，保护层的表面包括Al2O3层，Al2O3层由采用磁控溅射法形成的Al层在氧气浓度高于21％的氛围中以300～400℃的温度进行热退火处理制得。
本发明提供的一种液晶显示面板，包括相对间隔设置的第一基板和第二基板，以及填充于第一基板和第二基板之间的液晶，其中，第一基板和第二基板中的一者为阵列基板，该阵列基板包括：衬底基材；栅极，形成于衬底基材上；栅极绝缘层，形成于衬底基材上并覆盖栅极；主动层，形成于栅极绝缘层上且位于栅极的上方，主动层背向栅极的一侧形成有沟道，其中主动层在衬底基材上的正投影覆盖栅极及其两侧的衬底基材，且沟道在衬底基材上的正投影位于栅极所在区域之内；源极和漏极，形成于主动层上且分别位于主动层的两端。
其中，主动层包括依次形成于栅极绝缘层上的多晶硅半导体层、欧姆接触层，多晶硅半导体层背向栅极的一侧形成有沟道，欧姆接触层形成有位于沟道上方且与沟道相通的狭缝。
其中，阵列基板还包括：平坦钝化层，形成于源极、漏极以及主动层上，平坦钝化层形成有暴露漏极的表面的接触孔；像素电极，形成于平坦钝化层上以及接触孔内，像素电极通过接触孔与漏极电连接。
其中，阵列基板还包括：平坦钝化层，形成于源极、漏极以及主动层上，平坦钝化层形成有暴露漏极的表面的接触孔；公共电极，形成于平坦钝化层上；绝缘层，形成于公共电极上；像素电极，形成于绝缘层和平坦钝化层上以及接触孔内，像素电极通过接触孔与漏极电连接。
本发明提供的一种液晶显示装置，包括液晶显示面板以及为液晶显示面板提供光线的背光模组，液晶显示面板的阵列基板包括：衬底基材；栅极，形成于衬底基材上；栅极绝缘层，形成于衬底基材上并覆盖栅极；主动层，形成于栅极绝缘层上且位于栅极的上方，主动层背向栅极的一侧形成有沟道，其中主动层在衬底基材上的正投影覆盖栅极及其两侧的衬底基材，且沟道在衬底基材上的正投影位于栅极所在区域之内；源极和漏极，形成于主动层上且分别位于主动层的两端。
其中，主动层包括依次形成于栅极绝缘层上的多晶硅半导体层、欧姆接触层，多晶硅半导体层背向栅极的一侧形成有沟道，欧姆接触层形成有位于沟道上方且与沟道相通的狭缝。
其中，阵列基板还包括：平坦钝化层，形成于源极、漏极以及主动层上，平坦钝化层形成有暴露漏极的表面的接触孔；像素电极，形成于平坦钝化层上以及接触孔内，像素电极通过接触孔与漏极电连接。
其中，阵列基板还包括：平坦钝化层，形成于源极、漏极以及主动层上，平坦钝化层形成有暴露漏极的表面的接触孔；公共电极，形成于平坦钝化层上；绝缘层，形成于公共电极上；像素电极，形成于绝缘层和平坦钝化层上以及接触孔内，像素电极通过接触孔与漏极电连接。
本发明实施例的阵列基板、液晶显示面板及液晶显示装置，设计薄膜晶体管的主动层在衬底基材上的正投影覆盖栅极及其两侧的衬底基材，且薄膜晶体管的沟道在衬底基材上的正投影位于栅极所在区域之内，即设计栅极的宽度小于主动层的宽度且大于沟道的宽度，通过缩短栅极的宽度，减小源极和漏极与栅极的重叠区域，从而缩小源极和漏极与栅极之间的寄生电容，提升显示品质。
【附图说明】
图1是现有技术一实施例的薄膜晶体管的结构剖视图；
图2是本发明一实施例的阵列基板的结构剖视图；
图3是本发明另一实施例的阵列基板的结构剖视图；
图4是本发明又一实施例的阵列基板的结构剖视图；
图5是本发明一实施例的液晶显示面板的结构剖视图；
图6是本发明一实施例的液晶显示装置的结构剖视图。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明所提供的示例性的实施例的技术方案进行清楚、完整地描述。
图2是本发明一实施例的阵列基板的结构剖视图。如图2所示，所述阵列基板20(Array Substrate，又称Thin Film Transistor Substrate，TFT基板或薄膜晶体管基板)包括衬底基材21以及形成于衬底基材21上的薄膜晶体管22、平坦钝化层(Over coat Layer)23以及像素电极24，薄膜晶体管22包括栅极221、栅极绝缘层222、主动层223以及源极224和漏极225。其中，栅极221形成于衬底基材21上；栅极绝缘层222形成于衬底基材21上并覆盖栅极221；主动层223形成于栅极绝缘层222上且位于栅极221的上方，主动层223背向栅极221的一侧形成有沟道P，该沟道P为薄膜晶体管22的背沟道；源极224和漏极225形成于主动层223上且分别位于主动层223的两端；平坦钝化层23形成于源极224、漏极225、主动层223以及未被薄膜晶体管22覆盖的栅极绝缘层222上，平坦钝化层23形成有暴露漏极225表面的接触孔O1；像素电极24形成于平坦钝化层23上以及接触孔O1内，像素电极24可以通过接触孔O1与薄膜晶体管22的漏极225电连接。
与图1所示现有技术不同的是，在本发明实施例的薄膜晶体管22的结构中，主动层223在衬底基材21上的正投影覆盖栅极221以及位于栅极221两侧的衬底基材21，且沟道P在衬底基材21上的正投影位于栅极221所在区域之内，其中所述正投影指的是沿垂直于衬底基材21的视线方向主动层223以及沟道P在衬底基材21上的投影。
结合图2所示，a表示栅极221所对应区域，b表示主动层223所对应区域，c表示沟道P所对应区域，其中a、b、c也可分别表示栅极221、主 动层223、沟道P沿图中水平方向的宽度。也就是说，本发明实施例设计栅极221的宽度a小于主动层223的宽度b且大于沟道P的宽度c，即c＜a＜b。与现有技术相比，本发明实施例通过缩短栅极221的宽度，减小了源极224与栅极221(在衬底基材21上的正投影)的重叠区域以及漏极225与栅极221(在衬底基材21上的正投影)的重叠区域之和，从而能够缩小源极224和漏极225与栅极221之间的寄生电容，提升具有阵列基板20的液晶显示面板及液晶显示装置的显示品质。
另外，图2所示d和e表示欧姆接触区域，其中d表示背光照射区，e表示栅极遮挡区，当然d、e也可分别表示背光照射区、栅极遮挡区沿图中水平方向的宽度，e＝a-c。在薄膜晶体管22导通时，通过对栅极221施加电压，从而为区域c和区域e的主动层223提供载子；通过背光照射激发，从而为栅极221遮挡之外且位于区域d的主动层223提供载子。在薄膜晶体管22关闭时，由不透光的栅极221遮挡主动层223，从而降低薄膜晶体管22在区域c和区域e之处的漏电流。
在本实施例中，主动层223包括依次形成于栅极绝缘层222上的多晶硅(a-Si)半导体层2231、欧姆接触层2232。其中，欧姆接触层2232包括区域d和区域e，且为多晶硅半导体层2231进行重掺杂之后所形成，多晶硅半导体层2231包括但不限于金属氧化物半导体层，例如包含铟镓氧化物(IGO)、铟锌氧化物(IZO)、铟镓锌氧化物(IGZO)、铟锡氧化物(ITO)，多晶硅半导体层2231背向栅极221的一侧形成有所述沟道P，欧姆接触层2232位于沟道P上方且形成有与沟道P相通的狭缝O2。由于金属氧化物半导体层的载子迁移率高，因此本发明实施例即使在薄膜晶体管22的结构设计上使得源极224和漏极225与栅极221的重叠区域较小，也能够在主动层223中形成导电通道。
本发明实施例的首要目的是通过设计栅极221的宽度a小于主动层223的宽度b以减小源极224和漏极225与栅极221的重叠区域，核心在于栅极221的宽度a小于主动层223的宽度b，而对于源极224和漏极225的宽度无必然限制，当然，为了进一步减小源极224和漏极225与栅极221的重叠区域，本发明实施例在上述基础上还可以进行其他设计，例如：第一种，源极224在衬底基材21上的正投影与栅极221部分重叠，而漏极225 在衬底基材21上的正投影与栅极221无重叠；第二种，漏极225在衬底基材21上的正投影与栅极221部分重叠，而源极224在衬底基材21上的正投影与栅极221无重叠；第三种，源极224和漏极225在衬底基材21上的正投影与栅极221均无重叠。
当然，阵列基板20还具有现有技术的其他结构，例如还包括形成于阵列基板20中的公共电极以及位于公共电极与像素电极24之间的保护层。图3是本发明另一实施例的阵列基板的结构剖视图。为描述各实施例之间的不同，相同结构元件采用相同标号。如图3所示，在图2所示实施例的描述基础上但与之不同的是，本实施例的阵列基板20还包括形成于平坦钝化层23和像素电极24之间的公共电极30和绝缘层31，即：公共电极30形成于平坦钝化层23上；绝缘层31形成于公共电极30上，其中绝缘层31又称PV(Passivation，钝化)层；像素电极24形成于绝缘层31和平坦钝化层23上以及接触孔O1内，像素电极24可以通过接触孔O1与薄膜晶体管22的漏极225电连接。
图4是本发明又一实施例的阵列基板的结构剖视图。为描述各实施例之间的不同，相同结构元件采用相同标号。如图4所示，在图2所示实施例的描述基础上但与之不同的是，本实施例的阵列基板20还包括形成于沟道P上的保护层41。由于形成沟道P的半导体是一种对水和氧极其敏感的材料，水分子和氧分子极易对其电学性能产生影响，因此为了提高沟道P的电学稳定性，需要在沟道P上形成一保护层41，也可称为水氧阻隔层或刻蚀阻挡(Etch Stop Layer，ESL)层。
保护层41的材质包括但不限于为氧化硅SiO2、氮化硅Si3N4，可采用化学气相沉积(Chemical vapor deposition，CVD)、原子层外延(Atom Layer Deposition，ALD)、磁控溅射(Sputter)等方式制得。
当然，保护层41的表面还可以包括Al2O3层，Al2O3层由采用磁控溅射法形成的Al层在氧气浓度高于21％的氛围中以300～400℃的温度进行热退火处理制得。具体地，Al原子在氧气O2浓度高于21％的富氧氛围中发生氧化反应，能够最大程度的生成Al2O3，同时300～400℃的温度能够促使所述氧化反应以使Al层中尽可能多的Al原子被氧化，从而最大程度的保证所形成的Al2O3层的致密性，使其膜质较高，进一步确保沟道P的电学性能。 另外，在富氧氛围中进行热退火处理可同时具有三个作用：一是，降低沟道P的缺陷态密度，获得良好的主动层电学特性；二是，一定程度上修复在主动层223的沉积和图案化过程中，磁控溅射或者刻蚀等制造工艺对沟道P造成的损伤；三是，将Al层氧化为膜质较高的Al2O3层，以形成较好的沟道保护层。
本发明实施例还提供一种如图5所示的液晶显示面板。如图5所示，所述液晶显示面板50包括相对间隔设置的阵列基板51和彩膜基板(Color Filter，CF基板或彩色滤光片基板)52，以及夹持于阵列基板51和彩膜基板52之间的液晶(液晶分子)53，其中，液晶53位于阵列基板51和彩膜基板52叠加组合成的液晶盒内。所述阵列基板51包括上述任一实施例的阵列基板20，因此具有与其相同的有益效果。
本发明实施例还提供一种如图6所示的液晶显示装置60，该液晶显示装置60包括上述液晶显示面板50以及为液晶显示面板50提供光线的背光模组61。由于该液晶显示装置60也具有阵列基板20的上述设计，因此亦具有相同的有益效果。
应理解，以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，例如各实施例之间技术特征的相互结合，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (15)

  1. 一种阵列基板，其中，所述阵列基板包括：
    衬底基材；
    栅极，形成于所述衬底基材上；
    栅极绝缘层，形成于所述衬底基材上并覆盖所述栅极；
    主动层，形成于所述栅极绝缘层上且位于所述栅极的上方，所述主动层包括依次形成于所述栅极绝缘层上的多晶硅半导体层、欧姆接触层，所述多晶硅半导体层背向所述栅极的一侧形成有沟道，所述欧姆接触层形成有位于所述沟道上方且与所述沟道相通的狭缝，其中所述主动层在所述衬底基材上的正投影覆盖所述栅极及其两侧的衬底基材，且所述沟道在所述衬底基材上的正投影位于所述栅极所在区域之内；
    保护层，形成于所述沟道上；
    源极和漏极，形成于所述主动层上且分别位于所述主动层的两端。
  2. 根据权利要求1所述的阵列基板，其中，所述源极在所述衬底基材上的正投影与所述栅极部分重叠，所述漏极在所述衬底基材上的正投影与所述栅极无重叠。
  3. 根据权利要求1所述的阵列基板，其中，所述漏极在所述衬底基材上的正投影与所述栅极部分重叠，所述源极在所述衬底基材上的正投影与所述栅极无重叠。
  4. 根据权利要求1所述的阵列基板，其中，所述源极和所述漏极在所述衬底基材上的正投影与所述栅极无重叠。
  5. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括：
    平坦钝化层，形成于所述源极、所述漏极以及所述主动层上，所述平坦钝化层形成有暴露漏极的表面的接触孔；
    像素电极，形成于所述平坦钝化层上以及所述接触孔内，所述像素电极通过所述接触孔与所述漏极电连接。
  6. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括：
    平坦钝化层，形成于所述源极、所述漏极以及所述主动层上，所述平坦钝化层形成有暴露漏极的表面的接触孔；
    公共电极，形成于所述平坦钝化层上；
    绝缘层，形成于所述公共电极上；
    像素电极，形成于所述绝缘层和所述平坦钝化层上以及所述接触孔内，所述像素电极通过所述接触孔与所述漏极电连接。
  7. 根据权利要求1所述的阵列基板，其中，所述保护层的表面包括Al2O3层，所述Al2O3层由采用磁控溅射法形成的Al层在氧气浓度高于21％的氛围中以300～400℃的温度进行热退火处理制得。
  8. 一种液晶显示面板，其中，所述液晶显示面板包括相对间隔设置的第一基板和第二基板，以及填充于所述第一基板和所述第二基板之间的液晶，其中，所述第一基板和所述第二基板中的一者为的阵列基板，所述阵列基板包括：
    衬底基材；
    栅极，形成于所述衬底基材上；
    栅极绝缘层，形成于所述衬底基材上并覆盖所述栅极；
    主动层，形成于所述栅极绝缘层上且位于所述栅极的上方，所述主动层背向所述栅极的一侧形成有沟道，其中所述主动层在所述衬底基材上的正投影覆盖所述栅极及其两侧的衬底基材，且所述沟道在所述衬底基材上的正投影位于所述栅极所在区域之内；
    源极和漏极，形成于所述主动层上且分别位于所述主动层的两端。
  9. 根据权利要求8所述的液晶显示面板，其中，所述主动层包括依次形成于所述栅极绝缘层上的多晶硅半导体层、欧姆接触层，所述多晶硅半导体层背向所述栅极的一侧形成有所述沟道，所述欧姆接触层形成有位于所述沟道上方且与所述沟道相通的狭缝。
  10. 根据权利要求8所述的液晶显示面板，其中，所述阵列基板还包括：
    平坦钝化层，形成于所述源极、所述漏极以及所述主动层上，所述平坦钝化层形成有暴露漏极的表面的接触孔；
    像素电极，形成于所述平坦钝化层上以及所述接触孔内，所述像素电极通过所述接触孔与所述漏极电连接。
  11. 根据权利要求8所述的液晶显示面板，其中，所述阵列基板还包括：
    平坦钝化层，形成于所述源极、所述漏极以及所述主动层上，所述平 坦钝化层形成有暴露漏极的表面的接触孔；
    公共电极，形成于所述平坦钝化层上；
    绝缘层，形成于所述公共电极上；
    像素电极，形成于所述绝缘层和所述平坦钝化层上以及所述接触孔内，所述像素电极通过所述接触孔与所述漏极电连接。
  12. 一种液晶显示装置，包括液晶显示面板以及为所述液晶显示面板提供光线的背光模组，其中，所述液晶显示面板的阵列基板包括：
    衬底基材；
    栅极，形成于所述衬底基材上；
    栅极绝缘层，形成于所述衬底基材上并覆盖所述栅极；
    主动层，形成于所述栅极绝缘层上且位于所述栅极的上方，所述主动层背向所述栅极的一侧形成有沟道，其中所述主动层在所述衬底基材上的正投影覆盖所述栅极及其两侧的衬底基材，且所述沟道在所述衬底基材上的正投影位于所述栅极所在区域之内；
    源极和漏极，形成于所述主动层上且分别位于所述主动层的两端。
  13. 根据权利要求12所述的液晶显示装置，其中，所述主动层包括依次形成于所述栅极绝缘层上的多晶硅半导体层、欧姆接触层，所述多晶硅半导体层背向所述栅极的一侧形成有所述沟道，所述欧姆接触层形成有位于所述沟道上方且与所述沟道相通的狭缝。
  14. 根据权利要求12所述的液晶显示装置，其中，所述阵列基板还包括：
    平坦钝化层，形成于所述源极、所述漏极以及所述主动层上，所述平坦钝化层形成有暴露漏极的表面的接触孔；
    像素电极，形成于所述平坦钝化层上以及所述接触孔内，所述像素电极通过所述接触孔与所述漏极电连接。
  15. 根据权利要求12所述的液晶显示装置，其中，所述阵列基板还包括：
    平坦钝化层，形成于所述源极、所述漏极以及所述主动层上，所述平坦钝化层形成有暴露漏极的表面的接触孔；
    公共电极，形成于所述平坦钝化层上；
    绝缘层，形成于所述公共电极上；
    像素电极，形成于所述绝缘层和所述平坦钝化层上以及所述接触孔内，所述像素电极通过所述接触孔与所述漏极电连接。
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