WO2017128181A1

WO2017128181A1 - Single board, electronic apparatus and method for channel selection

Info

Publication number: WO2017128181A1
Application number: PCT/CN2016/072526
Authority: WO
Inventors: 刘翔; 师军令
Original assignee: 华为技术有限公司
Priority date: 2016-01-28
Filing date: 2016-01-28
Publication date: 2017-08-03
Also published as: CN108431788A; CN108431788B

Abstract

A single board, an electronic apparatus, and a method for channel selection. The single board comprises: a Joint Test Action Group (JTAG) module (11), a storage module (14), a channel selection module (12) and a storage interface (13). The channel selection module (12) is electrically connected to the JTAG module (11), the storage interface (13), and the storage module (14). The channel selection module (12) connects to the storage interface (13) and to the JTAG module (11) when a JTAG testing device is electrically connected to the storage interface (13), and connects to the storage interface (13) and to the storage module (14) when a storage device is electrically connected to the storage interface (13). The invention can enhance the efficiency of a late-stage JTAG test and an integration density of an electronic device and a visual appearance thereof.

Description

一种单板、电子设备及选通的方法Single board, electronic device and method of gating

技术领域Technical field

本发明涉及电子技术领域，尤其涉及的是一种单板、电子设备及选通的方法。The present invention relates to the field of electronic technologies, and in particular, to a single board, an electronic device, and a method of gating.

背景技术Background technique

目前，电子设备日趋智能化、小型化和高集成度方向发展，电子设备内部的各功能接口也越来越多，为方便后期对电子设备的故障诊断和调试等，一般在电子设备外引出对应内部功能电路的功能接口，如图1-1所示，主控芯片中联合测试工作组(JTAG，Joint Test Action Group)电路和安全数字存储卡(SD，Secure Digital Memory Card)内部电路独立，分别为JTAG电路和SD内部电路引出独立的JTAG接口和SD接口，测试人员通过这两个引出的JTAG接口和SD接口，即可连接外部的JTAG测试设备和SD设备，并进行相应的测试、读/写等操作。由于目前的电子设备的电路板一般较小，且外部接口设计紧凑，故为提高便携度和美观性，一般不会将电子设备内部用于测试、调试等功能接口外引，使得在后期电子设备的故障诊断和调试带来不便，在故障诊断或调试时需要拆开电子设备的壳体，在电子设备内部电路板上飞线，诊断效率或调试效率较低，且容易对壳体和电路板等造成损坏。At present, electronic devices are becoming more and more intelligent, miniaturized, and highly integrated, and various functional interfaces within electronic devices are becoming more and more. In order to facilitate the later diagnosis and debugging of electronic devices, they are generally drawn outside the electronic devices. The function interface of the internal function circuit is as shown in Figure 1-1. The internal test circuit (JTAG, Joint Test Action Group) circuit and the secure digital memory card (SD, Secure Digital Memory Card) are independent of each other. A separate JTAG interface and SD interface are introduced for the JTAG circuit and the SD internal circuit. The tester can connect the external JTAG test device and the SD device through the two JTAG interfaces and the SD interface, and perform corresponding test and read/ Write and other operations. Since the current electronic device has a small circuit board and a compact external interface design, in order to improve portability and aesthetics, the internal functions of the electronic device for testing and debugging are generally not cited, so that the electronic device is in the late stage. The fault diagnosis and debugging are inconvenient. In the fault diagnosis or debugging, the housing of the electronic device needs to be disassembled, and the flying circuit on the internal circuit board of the electronic device has low diagnostic efficiency or debugging efficiency, and is easy for the housing and the circuit board. Cause damage.

现有机制中，一般采用复用电子设备外引的现有接口实现其他功能，实现在不增设额外接口的前提下，也能增加电子设备的功能，以及提高电子设备的集成度。如图1-2所示，在主控芯片内部复用主控芯片的输入/输出(I/O，Input/Output)接口，通过复用SD接口实现JTAG接口的功能，在进行JTAG测试时，需要使用专用转接板连接SD接口和JTAG测试设备，测试人员通过JTAG测试设备中的调试软件，通过专用转接板发送特定指令给主控芯片，使得主控芯片能够识别JTAG测试设备，从而实现JTAG功能与SD功能之间的切换。由于是通过复用主控芯片的I/O接口来实现SD功能与JTAG功能，故只有在主控芯片正常工作时才能完成功能切换，并且还需要专用转接板和专用调试软件，才能实现SD功能和JTAG功能的切换。并且在主控芯片无法正常工作时，无法进行JTAG测试，即无法针对JTAG电路的芯片单体进行JTAG测试。In the existing mechanism, the existing interface of the multiplexed electronic device is generally used to implement other functions, so that the function of the electronic device can be increased and the integration of the electronic device can be improved without adding an additional interface. As shown in Figure 1-2, the input/output (I/O, Input/Output) interface of the main control chip is multiplexed in the main control chip, and the function of the JTAG interface is realized by multiplexing the SD interface. When performing JTAG test, A dedicated adapter board is required to connect the SD interface and the JTAG test equipment. The tester sends a specific instruction to the main control chip through the dedicated adapter board through the debugging software in the JTAG test equipment, so that the main control chip can recognize the JTAG test equipment, thereby realizing Switch between JTAG function and SD function. Since the SD function and the JTAG function are realized by multiplexing the I/O interface of the main control chip, the function switching can be completed only when the main control chip works normally, and a special adapter board and special debugging software are also needed to implement the SD. Switching between functions and JTAG functions. And when the main control chip is not working properly, it cannot enter JTAG test, that is, JTAG test cannot be performed on the chip unit of the JTAG circuit.

发明内容Summary of the invention

本申请提供了一种单板、电子设备及JTAG测试的方法，能够解决现有技术中JTAG测试效率较低的问题。The present application provides a method for a single board, an electronic device, and a JTAG test, which can solve the problem of low efficiency of JTAG testing in the prior art.

本申请第一方面提供了一种单板，所述单板包括：The first aspect of the present application provides a board, where the board includes:

联合测试行动组JTAG模块、存储模块、通道选择模块及存储接口；Joint Test Action Group JTAG module, storage module, channel selection module and storage interface;

所述通道选择模块与所述JTAG模块电连接，所述通道选择模块与所述存储接口电连接，所述通道选择模块与所述存储模块电连接；The channel selection module is electrically connected to the JTAG module, the channel selection module is electrically connected to the storage interface, and the channel selection module is electrically connected to the storage module;

所述通道选择模块，用于在JTAG测试设备与所述存储接口电连接时，连通所述存储接口与所述JTAG模块；The channel selection module is configured to connect the storage interface and the JTAG module when the JTAG test device is electrically connected to the storage interface;

以及在存储设备与所述存储接口电连接时，连通所述存储接口与所述存储模块。通过所述通道选择模块复用存储接口，实现在JTAG模式和存储模式之间切换。所述存储接口为SD接口。And connecting the storage interface and the storage module when the storage device is electrically connected to the storage interface. Switching between the JTAG mode and the storage mode is implemented by the channel selection module multiplexing the storage interface. The storage interface is an SD interface.

在一些可能的设计中，所述通道选择模块，还用于在连通所述存储接口与所述JTAG模块，即所述JTAG测试设备与所述JTAG模块形成通路时，将来自所述JTAG测试设备的JTAG测试信号输入所述JTAG模块；In some possible designs, the channel selection module is further configured to: when the JTAG module is connected to the JTAG module, that is, the JTAG test device forms a path with the JTAG module, from the JTAG test device. a JTAG test signal is input to the JTAG module;

所述JTAG模块，用于根据从所述通道选择模块接收到的JTAG测试信号，执行所述JTAG测试信号对应的测试项，并将测试得到的第一测试数据传输至所述通道选择模块；The JTAG module is configured to execute a test item corresponding to the JTAG test signal according to the JTAG test signal received from the channel selection module, and transmit the first test data obtained by the test to the channel selection module;

所述通道选择模块，还用于将来自所述JTAG模块的所述第一测试数据通过所述存储接口传输至所述JTAG测试设备。通过所述通道选择模块复用存储接口连通到单板上的JTAG模块后，实现JTAG测试功能以及测试数据的输出。The channel selection module is further configured to transmit the first test data from the JTAG module to the JTAG test device through the storage interface. After the channel selection module multiplexes the storage interface and connects to the JTAG module on the board, the JTAG test function and the output of the test data are implemented.

在一些可能的设计中，所述通道选择模块，还用于在连通所述存储接口与所述存储模块，即所述存储设备与所述存储模块形成通路时，将来自所述存储设备的存储测试信号输出至所述存储模块；In some possible designs, the channel selection module is further configured to store the storage device from the storage device when the storage interface is connected to the storage module, that is, the storage device forms a path with the storage module. The test signal is output to the storage module;

所述存储模块，用于根据从所述通道选择模块接收到的存储测试信号，执行所述存储测试信号对应的测试项，并将测试得到的第二测试数据输出至所述通道选择模块； The storage module is configured to execute a test item corresponding to the stored test signal according to the stored test signal received from the channel selection module, and output the tested second test data to the channel selection module;

所述通道选择模块，还用于将来自所述存储模块的所述第二测试数据通过所述存储接口传输至所述存储设备。通过所述通道选择模块选择连通到单板上的存储模块后，实现存储、数据读取、输入输出等功能。The channel selection module is further configured to transmit the second test data from the storage module to the storage device through the storage interface. After the channel selection module selects a storage module connected to the board, functions such as storage, data reading, input and output, and the like are implemented.

在一些可能的设计中，所述通道选择模块包括第一选通端，第二选通端，公共端和选通控制引脚，所述第一选通端与所述JTAG模块的接口端电连接，所述第二选通端与所述存储模块的接口端电连接，所述公共端与所述存储接口电连接。可选的，所述通道选择模块包括多路选择开关，其中，多路选择开关为实现选通功能的模拟开关，可以包括多路复用器、多路选择器、多路模拟开关、数据选择器、多路模拟转换器、多路复用开关、多路切换开关、多路开关等。In some possible designs, the channel selection module includes a first strobe terminal, a second strobe terminal, a common terminal, and a strobe control pin, and the first strobe terminal and the interface end of the JTAG module are electrically The second gating end is electrically connected to the interface end of the storage module, and the common end is electrically connected to the storage interface. Optionally, the channel selection module includes a multi-path selection switch, wherein the multi-channel selection switch is an analog switch that implements a gating function, and may include a multiplexer, a multiplexer, a multi-channel analog switch, and a data selection. , multi-channel analog converter, multiplexer switch, multi-way switch, multiplexer, etc.

在一些可能的设计中，所述通道选择模块还包括选通控制引脚，所述选通控制引脚用于控制所述公共端与所述第一选通端连接，和控制所述公共端与所述第二选通端通信连接。In some possible designs, the channel selection module further includes a gate control pin, the gate control pin is configured to control the common terminal to be connected to the first gate terminal, and control the common terminal Connected to the second strobe.

在一些可能的设计中，所述JTAG模块的接口端包括：测试模式选择引脚、测试时钟引脚、测试数据输入引脚、以及测试数据输出引脚，可选的，还可以包括测试复位引脚；In some possible designs, the interface end of the JTAG module includes: a test mode select pin, a test clock pin, a test data input pin, and a test data output pin, optionally, and may also include a test reset reference. foot;

所述第一选通端包括：与所述测试模式选择引脚对应的第一通道引脚、与所述测试时钟引脚对应的第二通道引脚、与所述测试数据输入引脚对应的第三通道引脚、以及与所述测试数据输出引脚对应的第四通道引脚，相应的，还可以包括与所述测试复位引脚对应的第五通道引脚；The first strobe terminal includes: a first channel pin corresponding to the test mode selection pin, a second channel pin corresponding to the test clock pin, and a corresponding to the test data input pin a third channel pin and a fourth channel pin corresponding to the test data output pin, and correspondingly, a fifth channel pin corresponding to the test reset pin;

输入所述选通控制引脚的信号为第一电平时，所述通道选择模块中的所述第一通道引脚、所述第二通道引脚、所述第三通道引脚以及所述第四通道引脚选通，可选的，在所述选通控制引脚包括第五通道引脚时，所述第五通道引脚也选通。通过在通道选择模块设置选通控制引脚选通与JTAG模块电连接的引脚，实现信号传输。When the signal input to the strobe control pin is at a first level, the first channel pin, the second channel pin, the third channel pin, and the first The four-channel pin is strobed. Optionally, when the strobe control pin includes the fifth channel pin, the fifth channel pin is also strobed. Signal transmission is achieved by setting the strobe control pin to the pin that is electrically connected to the JTAG module in the channel selection module.

在一些可能的设计中，所述存储模块的接口端包括：指令引脚、时钟引脚、第一测试数据引脚、第二测试数据引脚、第三测试数据引脚及第四测试数据引脚；In some possible designs, the interface end of the storage module includes: an instruction pin, a clock pin, a first test data pin, a second test data pin, a third test data pin, and a fourth test data lead. foot;

所述第二选通端包括：与所述指令引脚对应的第六通道引脚、与所述时钟引脚对应的第七通道引脚、与所述第一测试数据引脚对应的第八通道引脚、与所述第二测试数据引脚对应的第九通道引脚、与所述第三测试数据引脚对应的第十通道引脚、及与所述第四测试数据引脚对应的第十一通道引脚；The second strobe terminal includes: a sixth channel pin corresponding to the instruction pin, and the clock a seventh channel pin corresponding to the pin, an eighth channel pin corresponding to the first test data pin, a ninth channel pin corresponding to the second test data pin, and the third test a tenth channel pin corresponding to the data pin and an eleventh channel pin corresponding to the fourth test data pin;

输入所述选通控制引脚的信号为第二电平时，所述通道选择模块中的所述第六通道引脚、所述第七通道引脚、所述第八通道引脚、所述第九通道引脚、所述第十通道引脚、及所述第十一通道引脚选通。When the signal input to the strobe control pin is at a second level, the sixth channel pin, the seventh channel pin, the eighth channel pin, and the A nine-channel pin, the tenth channel pin, and the eleventh channel pin are strobed.

在一些可能的设计中，所述存储接口包括存储设备检测引脚，所述存储设备检测引脚与所述选通控制引脚电连接；In some possible designs, the storage interface includes a storage device detection pin, and the storage device detection pin is electrically connected to the strobe control pin;

所述存储设备检测引脚，用于在JTAG测试设备与所述存储接口电连接时，触发输入所述选通控制引脚的信号为所述第一电平；在存储设备与所述存储接口电连接时，触发输入所述选通控制引脚的信号为所述第二电平。通过在存储模块上的存储设备检测引脚触发相应的电平信号至选通控制引脚，使得选通控制引脚根据信号的电平高低选通对应***存储接口的设备对应的引脚。The storage device detection pin is configured to trigger a signal input to the strobe control pin to be the first level when the JTAG test device is electrically connected to the storage interface; at the storage device and the storage interface When electrically connected, the signal input to the strobe control pin is triggered to the second level. The corresponding level signal is triggered to the strobe control pin by the memory device detection pin on the memory module, so that the strobe control pin strobes the pin corresponding to the device inserted into the memory interface according to the level of the signal.

本发明第二方面提供一种电子设备，所述电子设备包括上述第一方面及第一方面的各可能的设计中的任一所述的单板。A second aspect of the invention provides an electronic device comprising the single board of any of the first aspect and the possible design of the first aspect.

本发明第三方面提供一种选通的方法，所述方法应用于单板，所述方法包括：A third aspect of the present invention provides a method of gating, the method being applied to a single board, the method comprising:

在联合测试行动组JTAG测试设备与所述单板中的存储接口电连接时，所述单板中的通道选择模块连通所述存储接口与所述单板中的JTAG模块；When the joint test action group JTAG test device is electrically connected to the storage interface in the board, the channel selection module in the board connects the storage interface and the JTAG module in the board;

在存储设备与所述单板中的存储接口电连接时，所述通道选择模块连通所述存储接口与所述单板中的存储模块。When the storage device is electrically connected to the storage interface in the board, the channel selection module is connected to the storage interface and the storage module in the board.

在一种可能的设计中，通道选择模块包括第一选通端，第二选通端，公共端和选通控制引脚，所述第一选通端与JTAG模块的接口端电连接，所述第二选通端与所述存储模块的接口端电连接，所述公共端与所述单板中的存储接口电连接；所述存储接口包括存储设备检测引脚，所述存储设备检测引脚与所述选通控制引脚电连接；In a possible design, the channel selection module includes a first strobe terminal, a second strobe terminal, a common terminal and a strobe control pin, and the first strobe terminal is electrically connected to the interface end of the JTAG module. The second strobe is electrically connected to the interface of the storage module, and the common end is electrically connected to the storage interface in the board; the storage interface includes a storage device detection pin, and the storage device detects the reference a pin is electrically connected to the strobe control pin;

所述在联合测试行动组JTAG测试设备与所述单板中的存储接口电连接时，所述单板中的通道选择模块连通所述存储接口与所述单板中的JTAG模块包括：The JTAG test device in the joint test action group is electrically connected to the storage interface in the board The channel selection module in the board is connected to the storage interface and the JTAG module in the board includes:

所述在所述JTAG测试设备与所述单板中的存储接口电连接时，所述存储设备检测引脚输入所述通道选择模块中的选通控制引脚的信号为第一电平，所述选通控制引脚选通所述第一选通端，以使所述JTAG测试设备与所述JTAG模块通信连接；When the JTAG test device is electrically connected to the storage interface in the board, the storage device detects that the signal input to the strobe control pin in the channel selection module is the first level. The strobe control pin strobes the first strobe to enable the JTAG test device to communicate with the JTAG module;

所述在存储设备与所述单板中的存储接口电连接时，所述通道选择模块连通所述存储接口与所述单板中的存储模块，包括：When the storage device is electrically connected to the storage interface in the board, the channel selection module is connected to the storage interface and the storage module in the board, and includes:

所述在所述存储设备与所述单板中的存储接口电连接时，所述存储设备检测引脚输入所述通道选择模块中的选通控制引脚的信号为第二电平，所述选通控制引脚选通所述第二选通端，以使所述存储设备与所述存储模块通信连接；所述第二电平与所述第一电平不同。When the storage device is electrically connected to the storage interface in the board, the storage device detects that the signal input to the strobe control pin of the channel selection module is a second level, A strobe control pin strobes the second strobe to cause the memory device to be in communication with the memory module; the second level being different than the first level.

本发明实施例中，通过使用通道选择模块电连接JTAG模块和存储接口，使得在JTAG测试设备与所述存储接口电连接时，与所述JTAG模块形成通路，从而实现复用该存储接口进行JTAG测试，实现在无需外部转接板、专用调试软件、不拆机和不降低单板的集成度的前提下，复用存储接口进行JTAG测试，有效减少JTAG测试操作和测试用具，也能提高后期JTAG测试的效率、电子设备的集成度和美观性。In the embodiment of the present invention, the JTAG module and the storage interface are electrically connected by using a channel selection module, so that when the JTAG test device is electrically connected to the storage interface, a path is formed with the JTAG module, thereby multiplexing the storage interface for JTAG. Test, realize the JTAG test by multiplexing the storage interface without the need of external adapter board, special debugging software, without disassembling the machine and without reducing the integration degree of the board, effectively reducing JTAG test operation and test equipment, and improving the later stage. The efficiency of JTAG testing, the integration and aesthetics of electronic devices.

附图说明DRAWINGS

图1-1为现有机制中JTAG测试***的一种结构示意图；Figure 1-1 is a schematic structural diagram of a JTAG test system in the existing mechanism;

图1-2为现有机制中JTAG测试***的另一种结构示意图；Figure 1-2 is another schematic diagram of the structure of the JTAG test system in the existing mechanism;

图2为本发明实施例中单板的结构示意图；2 is a schematic structural diagram of a single board according to an embodiment of the present invention;

图2-1为本发明实施例中JTAG测试***的结构示意图；2-1 is a schematic structural diagram of a JTAG test system according to an embodiment of the present invention;

图3为本发明实施例中单板的逻辑电路示意图；3 is a schematic diagram of a logic circuit of a single board in an embodiment of the present invention;

图4为本发明实施例中单板的电路原理示意图；4 is a schematic diagram of a circuit principle of a single board according to an embodiment of the present invention;

图5为本发明实施例中电子设备的结构示意图图；FIG. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present invention; FIG.

图6为本发明实施例中JTAG测试的方法的流程示意图。FIG. 6 is a schematic flowchart diagram of a method for testing a JTAG according to an embodiment of the present invention.

具体实施方式detailed description

下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例，基于本发明中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。The technical solution in the embodiment of the present invention will be clarified in the following with reference to the accompanying drawings in the embodiments of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS It is apparent that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments, based on the embodiments of the present invention, which are obtained by those skilled in the art without creative efforts. All other embodiments are within the scope of the invention.

本发明的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的实施例能够以除了在这里图示或描述的内容以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或模块的过程、方法、***、产品或设备不必限于清楚地列出的那些步骤或模块，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或模块，本文中所出现的模块的划分，仅仅是一种逻辑上的划分，实际应用中实现时可以有另外的划分方式，例如多个模块可以结合成或集成在另一个***中，或一些特征可以忽略，或不执行，另外，所显示的或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，模块之间的间接耦合或通信连接可以是电性或其他类似的形式，本文中均不作限定。并且，作为分离部件说明的模块或子模块可以是也可以不是物理上的分离，可以是也可以不是物理模块，或者可以分不到多个电路模块中，可以根据实际的需要选择其中的部分或全部模块来实现本发明实施例方案的目的。The terms "first", "second" and the like in the specification and claims of the present invention and the above drawings are used to distinguish similar objects, and are not necessarily used to describe a particular order or order. It is to be understood that the data so used may be interchanged where appropriate so that the embodiments described herein can be implemented in a sequence other than what is illustrated or described herein. In addition, the terms "comprises" and "comprises" and "the" and "the" are intended to cover a non-exclusive inclusion, for example, a process, method, system, product, or device that comprises a series of steps or modules is not necessarily limited to Those steps or modules, but may include other steps or modules not explicitly listed or inherent to such processes, methods, products or devices, the division of the modules presented herein is merely a logical division. There may be additional divisions in the implementation of the actual application, for example, multiple modules may be combined or integrated into another system, or some features may be ignored, or not executed, and the displayed or discussed mutual coupling. The direct coupling or the communication connection may be through some interfaces, and the indirect coupling or communication connection between the modules may be electrical or the like, which is not limited herein. Moreover, the module or the sub-module described as the separate component may or may not be physically separated, may not be a physical module, or may not be divided into a plurality of circuit modules, and may select a part thereof according to actual needs or All modules are used to achieve the objectives of the embodiments of the present invention.

本发明实施例提供了一种单板、电子设备及JTAG测试的方法，用于电子技术领域，能够提高JTAG测试效率。以下对本文中的术语进行详细说明。The embodiments of the present invention provide a single board, an electronic device, and a JTAG test method, which are used in the field of electronic technology to improve the efficiency of JTAG testing. The terms in this article are described in detail below.

本文中的JTAG模块可以称为JTAG电路、存储模块可以称为SD模块或SD电路或存储器芯片等。如图3所示，JTAG模块设有与通道选择模块电连接的JTAG接口，一般该JTAG接口包括4个引脚：测试模式选择(TMS，Test Module Select)、测试时钟(TCK，Test Clock)、测试数据输入(TDI，Test Data Input)、测试数据输出(TDO，Test Data Output)，还可以包括测试复位(TRST，Test Reset)。SD模块设有与通道选择模块电连接的SD接口，该SD接口包括6个引脚：指令(CMD，Command)、时钟(CLK，Clock)、数据(DATA0、DATA1、DATA2及DATA3)。相应的，通道选择模块上设有与JTAG接口的5 个引脚相应的5个通道引脚，以及设有与SD接口的6个引脚相应的6个通道引脚。The JTAG module herein may be referred to as a JTAG circuit, and the memory module may be referred to as an SD module or an SD circuit or a memory chip. As shown in FIG. 3, the JTAG module has a JTAG interface electrically connected to the channel selection module. Generally, the JTAG interface includes four pins: TMS (Test Module Select), test clock (TCK, Test Clock), Test Data Input (TDI), Test Data Output (TDO), and test reset (TRST, Test Reset). The SD module is provided with an SD interface electrically connected to the channel selection module. The SD interface includes six pins: an instruction (CMD, Command), a clock (CLK, Clock), and data (DATA0, DATA1, DATA2, and DATA3). Correspondingly, the channel selection module is provided with a JTAG interface 5 The corresponding five channel pins of the pin and the six channel pins corresponding to the six pins of the SD interface.

具有JTAG接口的芯片包括微处理器(MPU，Microprocessor Unit)、微控制器(MCU，Microprogrammed Control Unit)、中央处理器(CPU，Central Processing Unit)、数字信号处理器(DSP，Digital Signal Processor)、复杂可编程逻辑器件(CPLD，Complex Programmable Logic Device)、现场可编程门阵列(FPGA，Field Programmable Gate Array)或其他符合电气和电子工程师协会(IEEE，Institute of Electrical and Electronics Engineers)1149.1标准的芯片。The chip with the JTAG interface includes a microprocessor (MPU), a microprogrammed control unit (MCU), a central processing unit (CPU), a digital signal processor (DSP), and a digital signal processor (DSP). Complex Programmable Logic Device (CPLD), Field Programmable Gate Array (FPGA), or other chip that meets the IEEE9.1 Institute of Electrical and Electronics Engineers (1149.1 standard).

本文中的JTAG测试包括JTAG调试、JTAG边界扫描及JTAG向量仿真测试。JTAG测试主要用于测试芯片的电气特性和调试，例如电子设备在生产过程的故障检测以及返修的电子设备的故障检测，对用户而言，电子设备仅需引出存储接口，以便用户通过该存储接口对电子设备内置的存储模块进行数据读取、数据编辑、数据输入及数据输出等功能。The JTAG tests in this article include JTAG debugging, JTAG boundary scan, and JTAG vector simulation testing. The JTAG test is mainly used to test the electrical characteristics and debugging of the chip, such as the fault detection of the electronic device in the production process and the fault detection of the returned electronic device. For the user, the electronic device only needs to bring out the storage interface, so that the user can pass the storage interface. Data reading, data editing, data input, and data output are performed on the built-in memory module of the electronic device.

其中，JTAG调试是指对固定在电路板上的器件进行在线编程(ISP，In-System Programmable)，例如对摄像头(Camera)、闪存(FLASH)等器件进行编程。Among them, JTAG debugging refers to in-circuit programming (ISP, In-System Programmable) of devices fixed on the circuit board, for example, programming devices such as camera (camera) and flash memory (FLASH).

JTAG边界扫描是指针对电路板上的元器件的贴装工艺、焊接状态等进行硬件故障检测。JTAG boundary scan is a hardware fault detection for the placement process, soldering status, etc. of components on the board.

JTAG向量仿真测试是指针对主控芯片内的各功能模块的测试以及各功能模块的工作状态的观察控制，例如，通过芯片的输入/输出信号对芯片单体进行测试。The JTAG vector simulation test is a pointer to the test of each functional module in the main control chip and the observation and control of the working state of each functional module. For example, the chip unit is tested by the input/output signals of the chip.

本文中的电子设备主要具有至少以下之一的特点：小型、没有单独引出的JTAG接口、不易拆装的电子设备、SD接口和JTAG接口复用等。The electronic device herein mainly has at least one of the following features: a small, no separate JTAG interface, an easy-to-remove electronic device, an SD interface, and a JTAG interface multiplexing.

现有机制中，在追求电子设备小型化的前提下，对电子设备进行JTAG测试时需要专用外部转接板或专用调试软件等复用已有的SD接口，且在主控芯片故障时，无法进行JTAG测试，为解决该技术问题，本发明提供以下方案：In the existing mechanism, in the pursuit of miniaturization of electronic equipment, the JTAG test of electronic equipment requires a dedicated external adapter board or dedicated debugging software to reuse the existing SD interface, and when the main control chip fails, it cannot To solve the technical problem, the present invention provides the following solutions:

1、采用通道选择模块连接单板内部的主控芯片和存储接口。 1. Use the channel selection module to connect the main control chip and storage interface inside the board.

其中，主控芯片包括JTAG模块和存储模块，通道选择模块分别与JTAG模块和存储模块电连接。The main control chip includes a JTAG module and a storage module, and the channel selection module is electrically connected to the JTAG module and the storage module respectively.

2、在JTAG测试设备与存储接口连接时，通道选择模块连通主芯片中的JTAG模块，使得JTAG模块、通道选择模块、存储接口及JTAG测试设备形成通路，实现不需要为JTAG模块设置JTAG接口和不拆机的前提下，复用已有的存储接口，即可实现JTAG测试的功能。另外，也不需要外部转接板或专用调试软件等即可复用已有的存储接口，减少操作步骤和测试用具，提高电子设备的集成度。2. When the JTAG test device is connected to the storage interface, the channel selection module is connected to the JTAG module in the main chip, so that the JTAG module, the channel selection module, the storage interface, and the JTAG test device form a path, so that the JTAG interface is not required to be set for the JTAG module. The JTAG test function can be realized by multiplexing the existing storage interface without disassembling the machine. In addition, external adapter boards or dedicated debugging software are not required to reuse existing storage interfaces, reducing operating steps and test tools, and improving the integration of electronic devices.

请参照图2和图2-1，为本发明提供一种单板1，所述单板1包括：Referring to FIG. 2 and FIG. 2-1, a board 1 is provided, and the board 1 includes:

联合测试行动组JTAG模块11、通道选择模块12及存储接口13；Joint test action group JTAG module 11, channel selection module 12 and storage interface 13;

所述通道选择模块12与所述JTAG模块11电连接，所述通道选择模块12与所述存储接口13电连接；The channel selection module 12 is electrically connected to the JTAG module 11, and the channel selection module 12 is electrically connected to the storage interface 13;

所述通道选择模块12，用于在JTAG测试设备与所述存储接口13电连接时，连通所述存储接口与所述JTAG模块，使JTAG测试设备与所述JTAG模块11形成通路。可选的，由于目前大多电子设备都内置存储电路，然后相对电子设备的壳体外引出一个存储接口13，以便用户通过内置的存储电路对接入存储接口13的存储设备进行读/写等操作，在上述图2实现复用已有的存储接口实现JTAG测试的情况下，在不进行JTAG测试时，用户仍然可以正常使用上述存储接口13通过电子设备内置的存储电路进行与存储器有关的操作。即所述单板1还包括存储模块14，所述通道选择模块12用于使存储设备与所述存储模块14电连接；The channel selection module 12 is configured to connect the storage interface and the JTAG module when the JTAG test device is electrically connected to the storage interface 13, so that the JTAG test device forms a path with the JTAG module 11. Optionally, since most of the electronic devices currently have a built-in storage circuit, a storage interface 13 is externally drawn from the housing of the electronic device, so that the user can read/write the storage device connected to the storage interface 13 through the built-in storage circuit. In the case of implementing the JTAG test by multiplexing the existing storage interface in FIG. 2 above, when the JTAG test is not performed, the user can still use the storage interface 13 to perform the memory-related operations through the storage circuit built in the electronic device. That is, the board 1 further includes a storage module 14 for electrically connecting the storage device to the storage module 14;

所述通道选择模块12，还用于在存储设备与所述存储接口13电连接时，使存储设备与所述存储模块14形成通路。通过所述通道选择模块12复用存储接口13，实现在JTAG测试模式和存储模式之间切换。该存储设备可以是用于测试所述存储模块的设备，也可以是具有单一存储功能的存储器，具体不做作定。The channel selection module 12 is further configured to form a path between the storage device and the storage module 14 when the storage device is electrically connected to the storage interface 13. The storage interface 13 is multiplexed by the channel selection module 12 to switch between the JTAG test mode and the storage mode. The storage device may be a device for testing the storage module, or may be a storage device having a single storage function, which is not specified.

可以理解的是，上述存储接口13用于所述JTAG模块11与接入所述存储接口13的JTAG测试设备进行通信，以及所述存储模块14与接入所述存储接口13的存储设备进行通信。例如，用户通过所述JTAG模块11对接入所述存储接口13的JTAG测试设备进行JTAG测试等功能，以及通过所述存储模块14对接入所述存储接口13的存储设备进行读/写等操作。上述存储接口为现有的用于实现用户通过所述存储模块14对接入所述存储接口13的存储设备进行读/写等功能的存储接口，例如SD接口。It can be understood that the foregoing storage interface 13 is used for the JTAG module 11 to communicate with a JTAG test device accessing the storage interface 13, and the storage module 14 is in communication with a storage device accessing the storage interface 13. . For example, the user accesses the deposit through the JTAG module 11 The JTAG test device of the storage interface 13 performs functions such as JTAG test, and performs operations such as reading/writing on the storage device accessing the storage interface 13 through the storage module 14. The foregoing storage interface is a storage interface, such as an SD interface, for implementing functions such as reading/writing by a user to access a storage device of the storage interface 13 through the storage module 14.

本发明实施例中，通过使用通道选择模块12连接JTAG模块11和存储接口13，使得在JTAG测试设备与所述存储接口13电连接时，与所述JTAG模块11形成通路，从而实现复用该存储接口13进行JTAG测试，实现在无需外部转接板、专用调试软件、不拆机和不降低单板1的集成度的前提下，复用存储接口13进行JTAG测试，有效减少JTAG测试操作和测试用具，也能提高后期JTAG测试的效率、电子设备的集成度和美观性。In the embodiment of the present invention, the JTAG module 11 and the storage interface 13 are connected by using the channel selection module 12, so that when the JTAG test device is electrically connected to the storage interface 13, a path is formed with the JTAG module 11 to implement multiplexing. The storage interface 13 performs the JTAG test, and the multiplexed storage interface 13 performs the JTAG test without the need of the external adapter board, the dedicated debugging software, the disassembly, and the integration of the board 1 to effectively reduce the JTAG test operation and Test equipment can also improve the efficiency of post-JTAG testing, the integration and aesthetics of electronic devices.

可选的，在一些发明实施例中，在后期测试人员需要对电子设备进行JTAG测试时，测试人员只需要将JTAG测试设备***存储接口13，便可实现复用所述存储接口13，通过通道选择模块12使JTAG测试设备与单板内的所述JTAG模块11形成通路，从而启动JTAG测试模式，测试人员便可以通过JTAG测试设备进行JTAG测试。具体启动JTAG测试模式后，电子设备的各模块的信号流向如下：Optionally, in some embodiments of the invention, when the tester needs to perform JTAG test on the electronic device, the tester only needs to insert the JTAG test device into the storage interface 13, so that the storage interface 13 can be multiplexed through the channel. The selection module 12 enables the JTAG test device to form a path with the JTAG module 11 in the board to initiate the JTAG test mode, and the tester can perform JTAG test through the JTAG test device. After the JTAG test mode is specifically activated, the signal flow of each module of the electronic device is as follows:

所述通道选择模块12，还用于在连通所述存储接口13与所述JTAG模块11，即JTAG测试设备与所述JTAG模块11形成通路时，将来自所述JTAG测试设备的JTAG测试信号输入所述JTAG模块11；The channel selection module 12 is further configured to input a JTAG test signal from the JTAG test device when the storage interface 13 and the JTAG module 11 are connected, that is, the JTAG test device forms a path with the JTAG module 11 The JTAG module 11;

所述JTAG模块11，用于根据从所述通道选择模块12接收到的JTAG测试信号，执行所述JTAG测试信号对应的测试项，并将测试得到的第一测试数据传输至所述通道选择模块12；The JTAG module 11 is configured to execute a test item corresponding to the JTAG test signal according to the JTAG test signal received from the channel selection module 12, and transmit the first test data obtained by the test to the channel selection module. 12;

所述通道选择模块12，还用于将来自所述JTAG模块的所述第一测试数据通过所述存储接口13传输至所述JTAG测试设备。通过所述通道选择模块12复用存储接口连通到单板上的JTAG模块11后，实现JTAG测试功能，通过对单板1上的重要电子器件进行JTAG边界扫描测试，可以快速确认与电子器件相关的故障，提高维修分析的效率；或者，通过对单板1上的重要电子器件进行JTAG向量仿真测试，可以根据芯片的工作状态确定故障的芯片，提高故障分析的效率；或者，还可以通过对已组装好的单板1上的多个功能器件同时进行在线编程，写入相应的程序，有效提高单板1的加工进度。The channel selection module 12 is further configured to transmit the first test data from the JTAG module to the JTAG test device through the storage interface 13. After the JTAG module 11 is connected to the JTAG module 11 on the board through the channel selection module 12, the JTAG test function is implemented, and the JTAG boundary scan test is performed on the important electronic devices on the board 1 to quickly confirm the electronic device. The fault improves the efficiency of the maintenance analysis; or, by performing JTAG vector simulation test on the important electronic devices on the single board 1, the faulty chip can be determined according to the working state of the chip, thereby improving The efficiency of the obstacle analysis; or, by simultaneously programming a plurality of functional devices on the assembled single board 1 and writing corresponding programs, the processing progress of the single board 1 is effectively improved.

可选的，在一些发明实施例中，在测试人员对电子设备进行JTAG测试结束后，测试人员还可以将存储设备***存储接口13；或者测试人员直接将存储设备***存储接口13，便可通过通道选择模块12与单板内的所述存储模块13形成通路，从而启动存储模式或存储测试模式，测试人员便可以对连接的存储设备进行读/写、测试等操作。Optionally, in some embodiments of the invention, after the tester performs the JTAG test on the electronic device, the tester can also insert the storage device into the storage interface 13; or the tester directly inserts the storage device into the storage interface 13 to pass the test device. The channel selection module 12 forms a path with the storage module 13 in the board to initiate a storage mode or a storage test mode, and the tester can perform operations such as reading/writing, testing, and the like on the connected storage device.

1、启动存储测试模式后，电子设备的各模块信号流向如下：1. After starting the storage test mode, the signal flow of each module of the electronic device is as follows:

所述通道选择模块12，还用于在连通所述存储接口13与所述存储模块14，即存储设备与所述存储模块14形成通路时，将来自所述存储设备的存储测试信号输出至所述存储模块14；The channel selection module 12 is further configured to output a storage test signal from the storage device to the storage interface 13 and the storage module 14 when the storage device forms a path with the storage module 14 Storage module 14;

所述存储模块14，用于根据从所述通道选择模块12接收到的存储测试信号，执行所述存储测试信号对应的测试项，并将测试得到的第二测试数据输出至所述通道选择模块12；The storage module 14 is configured to execute a test item corresponding to the stored test signal according to the stored test signal received from the channel selection module 12, and output the tested second test data to the channel selection module. 12;

所述通道选择模块12，还用于将来自所述存储模块14的所述第二测试数据通过所述存储接口13传输至所述存储设备。通过所述通道选择模块12选择连通到单板上的存储模块14后，实现存储测试。The channel selection module 12 is further configured to transmit the second test data from the storage module 14 to the storage device through the storage interface 13. After the channel selection module 12 selects the storage module 14 connected to the board, the storage test is implemented.

2、启动存储模式后，电子设备的各模块信号流向如下：2. After the storage mode is started, the signal flow of each module of the electronic device is as follows:

所述通道选择模块12，还用于在连通所述存储接口13与所述存储模块14，即存储设备与所述存储模块14形成通路时，将来自所述存储设备发送的二进制信号输出至所述存储模块14；The channel selection module 12 is further configured to output a binary signal sent from the storage device to the storage interface 13 and the storage module 14 when the storage device forms a path with the storage module 14 Storage module 14;

所述存储模块14，用于根据从所述通道选择模块12接收到的二进制信号，执行输入/输出数据的操作，具体输入/输出数据的过程与现有机制类似，本文不作赘述。在输入数据时，所述存储模块14将来自所述存储设备的数据存储；在输出数据时，所述存储模块14输出数据将输入所述通道选择模块12；The storage module 14 is configured to perform an operation of inputting/outputting data according to the binary signal received from the channel selection module 12. The process of inputting/outputting data is similar to the existing mechanism, and is not described herein. When the data is input, the storage module 14 stores data from the storage device; when outputting data, the storage module 14 output data will be input to the channel selection module 12;

所述通道选择模块12，还用于将来自所述存储模块14的输出数据通过所述存储接口13传输至所述存储设备。通过所述通道选择模块12选择连通到单板上的存储模块14后，实现数据读取、输入、输出等功能。 The channel selection module 12 is further configured to transmit output data from the storage module 14 to the storage device through the storage interface 13. After the channel selection module 12 selects the storage module 14 connected to the board, functions such as data reading, input, and output are implemented.

可选的，如图2-1，本文中的所述通道选择模块12包括第一选通端121，第二选通端122和公共端123，所述第一选通端121与所述JTAG模块11的接口端电连接，所述第二选通端122与所述存储模块14的接口端电连接，所述公共端123与所述存储接口13电连接。所述通道选择模块12可以为多路选择开关，多路选择开关包括选通端、公共端等，如图3&4所示，第一选通端包括NO1-NO6，第二选通端包括NC1-NC6，，公共端包括COM1-COM6，所述多路选择开关的第一选通端与所述JTAG模块11的接口端电连接，所述多路选择开关的第二选通端与所述存储模块14的接口端电连接。可选的，多路选择开关为实现选通功能的模拟开关，可以包括多路复用器、多路选择器、多路模拟开关、数据选择器、多路模拟转换器、多路复用开关、多路切换开关、多路开关等，例如可以使用型号为TS3A27518E的多路模拟开关。Optionally, as shown in FIG. 2-1, the channel selection module 12 includes a first strobe end 121, a second strobe end 122, and a common end 123. The first strobe end 121 and the JTAG are The interface end of the module 11 is electrically connected, the second strobe end 122 is electrically connected to the interface end of the storage module 14, and the common end 123 is electrically connected to the storage interface 13. The channel selection module 12 may be a multiple selection switch, and the multiple selection switch includes a gate terminal, a common terminal, and the like. As shown in FIG. 3 and FIG. 4, the first gate terminal includes NO1-NO6, and the second gate terminal includes NC1- NC6, the common end includes COM1-COM6, the first strobe end of the multiplexer switch is electrically connected to the interface end of the JTAG module 11, the second strobe end of the multiplexer switch and the storage The interface end of module 14 is electrically connected. Optionally, the multiplexer is an analog switch that implements the strobe function, and may include a multiplexer, a multiplexer, a multi-channel analog switch, a data selector, a multi-channel analog converter, and a multiplexing switch. For multi-way switches, multiplex switches, etc., for example, a multi-channel analog switch of the type TS3A27518E can be used.

举例来说，关于通过多路选择开关连接JTAG模块11和存储接口13，或通过多路选择开关连接存储模块14和存储接口13的内部逻辑电路如图3所示，为实现多路选择开关的选通功能，本发明实施例在多路选择开关还包括选通控制引脚，所述选通控制引脚用于控制公共端与所述第一选通端的通信连接，即连通所述存储接口13和所述JTAG模块11，和控制所述公共端与所述第二选通端的通信连接，即连通所述存储接口13和所述存储模块14。实际应用时，例如，可以使用多路选择开关控制通信连接的切换，即在所述多路选择开关中设置选通控制引脚IN，所述选通控制引脚IN用于控制所述公共端与所述第一选通端连通，即存储接口13与所述JTAG模块11的通信连接，以及控制所述公共端与第二选通端连通，即存储接口13与所述存储模块14的通信连接。即通过在多路选择开关设置选通控制引脚IN，即可实现在JTAG测试设备与存储接口13电连接时，选通与JTAG模块11电连接的引脚，从而实现信号传输。For example, the internal logic circuit for connecting the JTAG module 11 and the storage interface 13 through the multiplex selection switch, or connecting the storage module 14 and the storage interface 13 through the multiplex selection switch is as shown in FIG. 3, in order to realize the multiplex selection switch. The gating function, in the embodiment of the present invention, the multiplex control switch further includes a strobe control pin, wherein the strobe control pin is used to control a communication connection between the common end and the first strobe end, that is, the storage interface is connected And the JTAG module 11 and the communication connection between the common terminal and the second strobe, that is, the storage interface 13 and the storage module 14. In practical applications, for example, a multi-way selection switch can be used to control the switching of the communication connection, that is, a strobe control pin IN is provided in the multiplex selection switch, and the strobe control pin IN is used to control the common terminal Communicating with the first gating end, that is, the communication connection between the storage interface 13 and the JTAG module 11, and controlling the communication between the common end and the second gating end, that is, the communication interface 13 communicates with the storage module 14 connection. That is, by setting the strobe control pin IN in the multi-way selection switch, it is possible to strobe the pin electrically connected to the JTAG module 11 when the JTAG test device is electrically connected to the storage interface 13, thereby realizing signal transmission.

可选的，所述选通控制引脚IN用于实现控制所述多路选择开关选通控制引脚的功能，故所述选通控制引脚IN还可以用禁止端、使能端、控制信号端等代替，只要能够实现通过输入所述选通控制引脚IN的高低电平来控制引脚的选通即可，具体类型不作限定。Optionally, the strobe control pin IN is used to implement a function of controlling the multiplex gate strobe control pin, so the strobe control pin IN can also use a disable terminal, an enable terminal, and a control Instead of the signal terminal or the like, the strobe of the pin can be controlled by inputting the high and low levels of the strobe control pin IN, and the specific type is not limited.

可选的，上述选通控制引脚IN的个数可以为1个或多个，具体可以根据芯片的型号和单板的设计选择，例如，可以使用同一个选通控制引脚IN在JTAG测试模式和存储模式之间进行切换，也可以使用一个选通控制引脚IN1控制多路选择开关上对应JTAG模块或存储模块的其中几个引脚，同时使用选通控制引脚IN2控制多路选择开关上对应JTAG模块或存储模块的其他引脚的选通，具体选通控制引脚的数量本文中均不作限定，如图3和图4所示的针对使用IN1和IN2控制选通控制引脚的逻辑电路图，即上述选通控制引脚IN包括第一选通控制引脚IN1和第二选通控制引脚IN2，其中，第一选通控制引脚IN1，用于控制COM1引脚连通所述NC1引脚，或连通NO1引脚，控制COM2引脚连通所述NC2引脚，或连通NO2引脚，COM3引脚连通所述NC3引脚，或连通NO3引脚；第二选通控制引脚IN2，用于控制COM4引脚连通所述NC4引脚，或连通NO4引脚，控制COM5引脚连通所述NC5引脚，或连通NO5引脚，COM6引脚连通所述NC6引脚。Optionally, the number of the strobe control pins IN may be one or more, and may be specifically The chip model and board design options, for example, can be switched between JTAG test mode and memory mode using the same gate control pin IN, or a strobe control pin IN1 can be used to control the multiplexer Corresponding to several pins of the JTAG module or the memory module, and using the strobe control pin IN2 to control the strobe of the corresponding JTAG module or other pins of the memory module on the multiplexer, the number of strobe control pins The middle is not limited, as shown in FIG. 3 and FIG. 4, the logic circuit diagram for controlling the gate control pins using IN1 and IN2, that is, the above gate control pin IN includes the first gate control pin IN1 and the second selection. The control pin IN2, wherein the first strobe control pin IN1 is used to control the COM1 pin to communicate with the NC1 pin, or to connect the NO1 pin, control the COM2 pin to communicate with the NC2 pin, or connect the NO2. Pin, COM3 pin connects to the NC3 pin, or connects to the NO3 pin; the second strobe control pin IN2 is used to control the COM4 pin to connect to the NC4 pin, or to connect the NO4 pin to control the COM5 pin. Connect the pin to the NC5 pin, or connect NO5 pin, COM6 communication with said pin NC6 pin.

图3中各器件之间的连接关系描述如下：The connection relationship between the devices in Figure 3 is described as follows:

一、对于JTAG模块：First, for the JTAG module:

所述JTAG模块11的接口端包括：测试模式选择TMS引脚、测试时钟TCK引脚、测试数据输入TDI引脚、测试数据输出TDO引脚，可选地，还可以包括测试复位TRST引脚；The interface end of the JTAG module 11 includes: a test mode selection TMS pin, a test clock TCK pin, a test data input TDI pin, a test data output TDO pin, and optionally, a test reset TRST pin;

所述多路选择开关的第一选通端包括：与所述测试模式选择TMS引脚对应的第一通道NO1引脚、与所述测试时钟TCK引脚对应的第二通道NO2引脚、与所述测试数据输入TDI引脚对应的第三通道NO3引脚、与所述测试数据输出TDO引脚对应的第四通道NO4引脚，可选的，还可以设置与所述测试复位TRST引脚对应的第五通道NO5引脚。The first strobe terminal of the multiplexer includes: a first channel NO1 pin corresponding to the test mode selection TMS pin, a second channel NO2 pin corresponding to the test clock TCK pin, and The test data is input to a third channel NO3 pin corresponding to the TDI pin, and a fourth channel NO4 pin corresponding to the test data output TDO pin. Optionally, the test reset TRST pin can also be set. Corresponding fifth channel NO5 pin.

其中，TMS引脚与第一通道NO1引脚电连接、TCK引脚与第二通道NO2引脚电连接、TDI引脚与第三通道NO3引脚电连接、TDO引脚与第四通道NO4引脚电连接，及TRST引脚与第五通道NO5引脚电连接。The TMS pin is electrically connected to the first channel NO1 pin, the TCK pin is electrically connected to the second channel NO2 pin, the TDI pin is electrically connected to the third channel NO3 pin, the TDO pin and the fourth channel NO4 lead The pin is electrically connected, and the TRST pin is electrically connected to the fifth channel NO5 pin.

二、对于存储模块：Second, for the storage module:

所述存储模块14的接口端包括：指令CMD引脚、时钟CLK引脚、第一测试数据DATA0引脚、第二测试数据DATA1引脚、第三测试数据DATA2引脚及第四测试数据DATA3引脚； The interface end of the storage module 14 includes: an instruction CMD pin, a clock CLK pin, a first test data DATA0 pin, a second test data DATA1 pin, a third test data DATA2 pin, and a fourth test data DATA3 reference. Feet

所述多路选择开关的第二选通端包括：与所述CMD引脚对应的第六通道NC1引脚、与所述时钟引脚对应的第七通道NC2引脚、与所述第一测试数据DATA0引脚对应的第八通道NC3引脚、与所述第二测试数据DATA1引脚对应的第九通道NC4引脚、与所述第三测试数据DATA2引脚对应的第十通道NC5引脚、及与所述第四测试数据DATA3引脚对应的第十一通道NC6引脚。The second strobe terminal of the multiplexer includes: a sixth channel NC1 pin corresponding to the CMD pin, a seventh channel NC2 pin corresponding to the clock pin, and the first test The eighth channel NC3 pin corresponding to the data DATA0 pin, the ninth channel NC4 pin corresponding to the second test data DATA1 pin, and the tenth channel NC5 pin corresponding to the third test data DATA2 pin And an eleventh channel NC6 pin corresponding to the fourth test data DATA3 pin.

其中，CMD引脚与第六通道NC1引脚电连接、CLK引脚与第七通道NC2引脚电连接、第一测试数据DATA0引脚与第八通道NC3引脚电连接、第二测试数据DATA1引脚与第九通道NC4引脚电连接、第三测试数据DATA2引脚与第十通道NC5引脚电连接，及第四测试数据DATA3引脚与第十通道NC5引脚电连接。The CMD pin is electrically connected to the sixth channel NC1 pin, the CLK pin is electrically connected to the seventh channel NC2 pin, the first test data DATA0 pin is electrically connected to the eighth channel NC3 pin, and the second test data DATA1 The pin is electrically connected to the ninth channel NC4 pin, the third test data DATA2 pin is electrically connected to the tenth channel NC5 pin, and the fourth test data DATA3 pin is electrically connected to the tenth channel NC5 pin.

举例来说，对于实现所述选通控制引脚IN控制所述多路选择开关中引脚的选通，可以对输入所述选通控制引脚IN的信号进行定义从而实现控制，具体为：For example, for implementing the gating control pin IN to control the gating of the pin in the multi-selection switch, the signal input to the gating control pin IN can be defined to implement control, specifically:

所述存储接口13包括存储设备检测引脚(SD-DET，Storage Card-Detector)131，所述存储设备检测引脚131与所述选通控制引脚IN电连接，如图2-1和图4所示；The storage interface 13 includes a storage device detection pin (SD-DET, Storage Card-Detector) 131, and the storage device detection pin 131 is electrically connected to the strobe control pin IN, as shown in FIG. 2-1 and 4;

所述存储设备检测引脚131，用于在JTAG测试设备与所述存储接口13电连接时，触发输入所述选通控制引脚IN的信号为第一电平；在存储设备与所述存储接口13电连接时，触发输入所述选通控制引脚IN的信号为第二电平。通过存储接口13上的存储设备检测引脚131，根据接入存储接口13的设备类型触发相应的高低电平信号至选通控制引脚IN，使得选通控制引脚IN根据信号的电平高低选通对应***存储接口13的设备对应的引脚。其中，所述第二电平与所述第一电平不同，例如可以设置第一电平为高电平(H，High Level)，所述第二电平为低电平(L，Low Level)，具体取值本文不作限定。The storage device detection pin 131 is configured to trigger a signal input to the strobe control pin IN to be a first level when the JTAG test device is electrically connected to the storage interface 13; at the storage device and the storage When the interface 13 is electrically connected, the signal input to the gate control pin IN is triggered to be the second level. Through the storage device detection pin 131 on the storage interface 13, the corresponding high and low level signals are triggered to the strobe control pin IN according to the device type of the access storage interface 13, so that the strobe control pin IN is based on the level of the signal. The pin corresponding to the device inserted into the memory interface 13 is strobed. The second level is different from the first level. For example, the first level may be set to a high level (H, High Level), and the second level is a low level (L, Low Level). ), the specific value is not limited in this article.

举例来说，在所述存储设备检测引脚131触发输入所述选通控制引脚IN的信号为高电平H/低电平L时，如图3和表1所示，所述选通控制引脚IN选通所述多路选择开关的情况主要有以下两种：For example, when the storage device detects that the pin 131 triggers the signal input to the strobe control pin IN to be a high level H/low level L, as shown in FIG. 3 and Table 1, the strobe There are two main cases in which the control pin IN gates the multi-way selection switch:

a、输入所述选通控制引脚IN(包括IN1和IN2)的信号为H时，所述多路选择开关中的所述第一通道引脚NO1、所述第二通道引脚NO2、所述第三通道引脚NO3、所述第四通道引脚NO4及所述第五通道引脚NO5选通；a. When the signal input to the strobe control pin IN (including IN1 and IN2) is H, the first channel pin NO1 and the second channel pin NO2 in the multiplexer switch Third Channel pin NO3, the fourth channel pin NO4, and the fifth channel pin NO5 are strobed;

b、输入所述选通控制引脚IN(包括IN1和IN2)的信号为L时，所述多路选择开关中的所述第六通道引脚NC1、所述第七通道引脚NC2、所述第八通道引脚NC3、所述第九通道引脚NC4、所述第十通道引脚NC5、及所述第十一通道引脚NC6选通。b. When the signal input to the strobe control pin IN (including IN1 and IN2) is L, the sixth channel pin NC1, the seventh channel pin NC2, the multiplex switch The eighth channel pin NC3, the ninth channel pin NC4, the tenth channel pin NC5, and the eleventh channel pin NC6 are strobed.

表1Table 1

参阅图5，本发明还提供一种电子设备2，所述电子设备2包含上述图2-4中任一所述的单板1。Referring to FIG. 5, the present invention further provides an electronic device 2 comprising the single board 1 of any of the above-described FIGS. 2-4.

以上对一种单板1和一种电子设备2的结构进行详细说明，以下以JTAG测试设备对上述单板1或上述电子设备2进行通路的选通进行说明，参阅图6，本发明实施例包括：The following describes the structure of a single board 1 and an electronic device 2. The following describes the gating of the path of the single board 1 or the electronic device 2 by using a JTAG test device. Referring to FIG. 6, the embodiment of the present invention is described. include:

101、在联合测试行动组JTAG测试设备与所述单板中的存储接口电连接时，所述单板中的通道选择模块连通所述存储接口与所述单板中的JTAG模块；The channel selection module in the board is connected to the storage interface and the JTAG module in the board when the joint test action group JTAG test device is electrically connected to the storage interface in the board;

102、在存储设备与所述单板中的存储接口电连接时，所述通道选择模块连通所述存储接口与所述单板中的存储模块。The channel selection module is connected to the storage interface and the storage module in the board when the storage device is electrically connected to the storage interface in the board.

由于所述通道选择模块包括第一选通端，第二选通端，公共端和选通控制引脚，所述第一选通端与JTAG模块的接口端电连接，所述第二选通端与所述存储模块的接口端电连接，所述公共端与所述单板中的存储接口电连接；所述存储接口包括存储设备检测引脚，所述存储设备检测引脚与所述选通控制引脚电连接。则所述通道选通模块选通JTAG模块或存储模块的情况具体如下：Since the channel selection module includes a first gate, a second gate, a common terminal, and a gate control a pin, the first gating end is electrically connected to the interface end of the JTAG module, the second gating end is electrically connected to the interface end of the storage module, and the common end is connected to the storage interface in the board Electrically coupled; the memory interface includes a memory device sense pin, the memory device sense pin being electrically coupled to the gate control pin. The case where the channel gating module strobes the JTAG module or the storage module is as follows:

1、在JTAG测试设备与所述单板中的存储接口电连接时，所述存储设备检测引脚输入所述通道选择模块中的选通控制引脚的信号为第一电平，所述选通控制引脚选通所述第一选通端，以使所述JTAG测试设备与所述JTAG模块通信连接。When the JTAG test device is electrically connected to the storage interface in the board, the storage device detects that the signal input to the strobe control pin in the channel selection module is a first level, and the selection is performed. The first control terminal is gated to control the JTAG test device to be in communication with the JTAG module.

2、在所述存储设备与所述单板中的存储接口电连接时，所述存储设备检测引脚输入所述通道选择模块中的选通控制引脚的信号为第二电平，所述选通控制引脚选通所述第二选通端，以使所述存储设备与所述存储模块通信连接。2. When the storage device is electrically connected to the storage interface in the board, the storage device detects that the signal input to the strobe control pin in the channel selection module is a second level. A strobe control pin strobes the second strobe to cause the memory device to be in communication with the memory module.

其中，所述第二电平与所述第一电平不同，实现输入选通控制引脚的信号为不同的特定电平时，选通相应的选通端，实现复用存储接口。The second level is different from the first level. When the signals of the input strobe control pins are different specific levels, the corresponding strobe ends are strobed to implement the multiplexed storage interface.

本发明实施例中，通过JTAG测试设备与所述存储接口电连接，所述通道选择模块连通所述存储接口与所述JTAG模块，使得JTAG测试设备通过存储接口和通道选择模块两者，与JTAG模块进行通信；在存储设备与所述存储接口电连接时，所述通道选择模块连通所述存储接口与所述存储模块，实现在无需外部转接板、专用调试软件、不拆机和不降低单板的集成度的前提下，复用现有的存储接口进行JTAG测试和功能切换，有效减少JTAG测试操作和测试用具，也能提高后期JTAG测试的效率、电子设备的集成度和美观性。In the embodiment of the present invention, the JTAG test device is electrically connected to the storage interface, and the channel selection module is connected to the storage interface and the JTAG module, so that the JTAG test device passes through both the storage interface and the channel selection module, and the JTAG. The module performs communication; when the storage device is electrically connected to the storage interface, the channel selection module connects the storage interface and the storage module, so that no external adapter board, special debugging software, no teardown, and no reduction are required. Under the premise of the integration degree of the board, the existing storage interface is reused for JTAG test and function switching, which effectively reduces the JTAG test operation and test equipment, and can also improve the efficiency of the late JTAG test, the integration degree and the aesthetics of the electronic device.

本发明还提供一种计算机存储介质，该介质存储有程序，该程序执行时包括上述选通的方法中的部分或者全部步骤。The present invention also provides a computer storage medium storing a program that, when executed, includes some or all of the steps of the gating method described above.

本发明还提供一种计算机存储介质，该介质存储有程序，该程序执行时包括上述单板或电子设备执行一种选通的方法中的部分或者全部步骤。The present invention also provides a computer storage medium storing a program, the program including some or all of the steps of the above-described single board or electronic device performing a gating.

在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。In the above embodiments, the descriptions of the various embodiments are different, and the details that are not detailed in a certain embodiment can be referred to the related descriptions of other embodiments.

所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的***，装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。 A person skilled in the art can clearly understand that for the convenience and brevity of the description, the specific working process of the system, the device and the unit described above can refer to the corresponding process in the foregoing method embodiment, and details are not described herein again.

在本申请所提供的几个实施例中，应该理解到，所揭露的***，装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个***，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。In the several embodiments provided by the present application, it should be understood that the disclosed system, apparatus, and method may be implemented in other manners. For example, the device embodiments described above are merely illustrative. For example, the division of the unit is only a logical function division. In actual implementation, there may be another division manner, for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.

所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.

另外，在本发明各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本发明各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。The integrated unit, if implemented in the form of a software functional unit and sold or used as a standalone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention, which is essential or contributes to the prior art, or all or part of the technical solution, may be embodied in the form of a software product stored in a storage medium. A number of instructions are included to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like. .

以上对本发明所提供的一种单板、电子设备及选通的方法进行了详细介绍，本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的方法及其核心思想；同时，对于本领域的一般技术人员，依据本发明的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本发明的限制。 The foregoing provides a detailed description of a single board, an electronic device, and a gating method provided by the present invention. The principles and embodiments of the present invention are described in the specific examples. The description of the above embodiments is only for helping. Understand the method of the present invention and its core ideas; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in specific embodiments and applications. In the above, the contents of the present specification should not be construed as limiting the present invention.

Claims

一种单板，其特征在于，所述单板包括：A single board, wherein the board includes:

联合测试行动组JTAG模块、存储模块、通道选择模块及存储接口；Joint Test Action Group JTAG module, storage module, channel selection module and storage interface;

所述通道选择模块与所述JTAG模块电连接，所述通道选择模块与所述存储接口电连接，所述通道选择模块与所述存储模块电连接；The channel selection module is electrically connected to the JTAG module, the channel selection module is electrically connected to the storage interface, and the channel selection module is electrically connected to the storage module;

所述通道选择模块，用于在JTAG测试设备与所述存储接口电连接时，连通所述存储接口与所述JTAG模块；The channel selection module is configured to connect the storage interface and the JTAG module when the JTAG test device is electrically connected to the storage interface;

以及在存储设备与所述存储接口电连接时，连通所述存储接口与所述存储模块。And connecting the storage interface and the storage module when the storage device is electrically connected to the storage interface.
根据权利要求1所述的单板，其特征在于，所述通道选择模块包括第一选通端，第二选通端，公共端和选通控制引脚，所述第一选通端与所述JTAG模块的接口端电连接，所述第二选通端与所述存储模块的接口端电连接，所述公共端与所述存储接口电连接。The board according to claim 1, wherein the channel selection module comprises a first strobe terminal, a second strobe terminal, a common terminal and a strobe control pin, and the first strobe terminal The interface end of the JTAG module is electrically connected, the second gating end is electrically connected to the interface end of the storage module, and the common end is electrically connected to the storage interface.

所述选通控制引脚用于控制所述公共端与所述第一选通端连接，和控制所述公共端与所述第二选通端通信连接。The strobe control pin is configured to control the common end to be connected to the first strobe end, and control the common end to communicate with the second strobe end.
根据权利要求2所述的单板，其特征在于，The veneer according to claim 2, wherein

所述JTAG模块的接口端包括：测试模式选择引脚、测试时钟引脚、测试数据输入引脚以及测试数据输出引脚；The interface end of the JTAG module includes: a test mode selection pin, a test clock pin, a test data input pin, and a test data output pin;

所述第一选通端包括：与所述测试模式选择引脚对应的第一通道引脚、与所述测试时钟引脚对应的第二通道引脚、与所述测试数据输入引脚对应的第三通道引脚、以及与所述测试数据输出引脚对应的第四通道引脚；The first strobe terminal includes: a first channel pin corresponding to the test mode selection pin, a second channel pin corresponding to the test clock pin, and a corresponding to the test data input pin a third channel pin and a fourth channel pin corresponding to the test data output pin;

输入所述选通控制引脚的信号为第一电平时，所述通道选择模块中的所述第一通道引脚、所述第二通道引脚、所述第三通道引脚、以及所述第四通道引脚选通。When the signal input to the strobe control pin is at a first level, the first channel pin, the second channel pin, the third channel pin, and the The fourth channel pin is strobed.
根据权利要求2或3所述的单板，其特征在于，A veneer according to claim 2 or 3, wherein

所述存储模块的接口端包括：指令引脚、时钟引脚、第一测试数据引脚、第二测试数据引脚、第三测试数据引脚及第四测试数据引脚；The interface end of the storage module includes: an instruction pin, a clock pin, a first test data pin, a second test data pin, a third test data pin, and a fourth test data pin;

所述第二选通端包括：与所述指令引脚对应的第六通道引脚、与所述时钟引脚对应的第七通道引脚、与所述第一测试数据引脚对应的第八通道引脚、与所述第二测试数据引脚对应的第九通道引脚、与所述第三测试数据引脚对应的第十通道引脚、及与所述第四测试数据引脚对应的第十一通道引脚；The second strobe terminal includes: a sixth channel pin corresponding to the instruction pin, a seventh channel pin corresponding to the clock pin, and an eighth corresponding to the first test data pin Channel pin, and a ninth channel pin corresponding to the second test data pin, a tenth channel pin corresponding to the third test data pin, and an eleventh channel lead corresponding to the fourth test data pin foot;

输入所述选通控制引脚的信号为第二电平时，所述通道选择模块中的所述第六通道引脚、所述第七通道引脚、所述第八通道引脚、所述第九通道引脚、所述第十通道引脚、及所述第十一通道引脚选通；When the signal input to the strobe control pin is at a second level, the sixth channel pin, the seventh channel pin, the eighth channel pin, and the a nine-channel pin, the tenth channel pin, and the eleventh channel pin strobe;

所述第二电平与所述第一电平不同。The second level is different from the first level.
根据权利要求2-4中任一项中所述的单板，其特征在于，所述存储接口包括存储设备检测引脚，所述存储设备检测引脚与所述选通控制引脚电连接；The board according to any one of claims 2 to 4, wherein the storage interface comprises a storage device detection pin, and the storage device detection pin is electrically connected to the strobe control pin;

所述存储设备检测引脚，用于在JTAG测试设备与所述存储接口电连接时，触发输入所述选通控制引脚的信号为所述第一电平；在存储设备与所述存储接口电连接时，触发输入所述选通控制引脚的信号为所述第二电平。The storage device detection pin is configured to trigger a signal input to the strobe control pin to be the first level when the JTAG test device is electrically connected to the storage interface; at the storage device and the storage interface When electrically connected, the signal input to the strobe control pin is triggered to the second level.
根据权利要求1所述的单板，其特征在于，The veneer according to claim 1, wherein

所述通道选择模块，还用于在与所述JTAG模块形成通路时，将来自所述JTAG测试设备的JTAG测试信号输入所述JTAG模块；The channel selection module is further configured to input a JTAG test signal from the JTAG test device into the JTAG module when forming a path with the JTAG module;

所述JTAG模块，用于根据从所述通道选择模块接收到的JTAG测试信号，执行所述JTAG测试信号对应的测试项，并将测试得到的第一测试数据传输至所述通道选择模块；The JTAG module is configured to execute a test item corresponding to the JTAG test signal according to the JTAG test signal received from the channel selection module, and transmit the first test data obtained by the test to the channel selection module;

所述通道选择模块，还用于将来自所述JTAG模块的所述第一测试数据通过所述存储接口传输至所述JTAG测试设备。The channel selection module is further configured to transmit the first test data from the JTAG module to the JTAG test device through the storage interface.
一种电子设备，其特征在于，所述电子设备包括：An electronic device, comprising:

如权利要求1至6任一项中所述的单板。A veneer as claimed in any one of claims 1 to 6.
一种选通的方法，所述方法应用于单板，其特征在于，所述方法包括：A method of strobing, the method being applied to a single board, wherein the method comprises:

在联合测试行动组JTAG测试设备与所述单板中的存储接口电连接时，所述单板中的通道选择模块连通所述存储接口与所述单板中的JTAG模块；When the joint test action group JTAG test device is electrically connected to the storage interface in the board, the channel selection module in the board connects the storage interface and the JTAG module in the board;

在存储设备与所述单板中的存储接口电连接时，所述通道选择模块连通所述存储接口与所述单板中的存储模块。When the storage device is electrically connected to the storage interface in the board, the channel selection module is connected to the storage interface and the storage module in the board.
根据权利要求8所述的方法，其特征在于，所述通道选择模块包括第一选通端，第二选通端，公共端和选通控制引脚，所述第一选通端与JTAG模块的接口端电连接，所述第二选通端与所述存储模块的接口端电连接，所述公共端与所述单板中的存储接口电连接；所述存储接口包括存储设备检测引脚，所述存储设备检测引脚与所述选通控制引脚电连接；The method according to claim 8, wherein the channel selection module comprises a first strobe terminal, a second strobe terminal, a common terminal and a strobe control pin, and the first strobe terminal and the JTAG mode The interface of the block is electrically connected, the second port is electrically connected to the interface of the storage module, and the common end is electrically connected to the storage interface in the board; a memory device detecting pin electrically connected to the strobe control pin;

所述在联合测试行动组JTAG测试设备与所述单板中的存储接口电连接时，所述单板中的通道选择模块连通所述存储接口与所述单板中的JTAG模块，包括：When the joint test action group JTAG test device is electrically connected to the storage interface in the board, the channel selection module in the board is connected to the storage interface and the JTAG module in the board, including:

在所述JTAG测试设备与所述单板中的存储接口电连接时，所述存储设备检测引脚输入所述通道选择模块中的选通控制引脚的信号为第一电平，所述选通控制引脚选通所述第一选通端，以使所述JTAG测试设备与所述JTAG模块通信连接；When the JTAG test device is electrically connected to the storage interface in the board, the storage device detects that the signal input to the strobe control pin in the channel selection module is a first level, and the selection is performed. The first control terminal is gated to control the JTAG test device to communicate with the JTAG module;

所述在存储设备与所述单板中的存储接口电连接时，所述通道选择模块连通所述存储接口与所述单板中的存储模块，包括：When the storage device is electrically connected to the storage interface in the board, the channel selection module is connected to the storage interface and the storage module in the board, and includes:

在所述存储设备与所述单板中的存储接口电连接时，所述存储设备检测引脚输入所述通道选择模块中的选通控制引脚的信号为第二电平，所述选通控制引脚选通所述第二选通端，以使所述存储设备与所述存储模块通信连接；所述第二电平与所述第一电平不同。 When the storage device is electrically connected to the storage interface in the board, the storage device detects that the signal input to the strobe control pin in the channel selection module is a second level, the strobe A control pin strobes the second strobe to cause the memory device to be in communication with the memory module; the second level being different than the first level.