WO2017107931A1 - 一种等效晶体管和三电平逆变器 - Google Patents

一种等效晶体管和三电平逆变器 Download PDF

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Publication number
WO2017107931A1
WO2017107931A1 PCT/CN2016/111373 CN2016111373W WO2017107931A1 WO 2017107931 A1 WO2017107931 A1 WO 2017107931A1 CN 2016111373 W CN2016111373 W CN 2016111373W WO 2017107931 A1 WO2017107931 A1 WO 2017107931A1
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Prior art keywords
transistor
power frequency
frequency rectifier
equivalent
level inverter
Prior art date
Application number
PCT/CN2016/111373
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English (en)
French (fr)
Inventor
崔兆雪
张春涛
Original Assignee
华为技术有限公司
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Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to MYPI2018001037A priority Critical patent/MY195940A/en
Priority to EP16877741.5A priority patent/EP3382881B1/en
Publication of WO2017107931A1 publication Critical patent/WO2017107931A1/zh
Priority to US16/015,217 priority patent/US10333427B2/en

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
    • H02M7/53873—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current with digital control
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H02M7/487—Neutral point clamped inverters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0043—Converters switched with a phase shift, i.e. interleaved
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H02M1/0051—Diode reverse recovery losses
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0095—Hybrid converter topologies, e.g. NPC mixed with flying capacitor, thyristor converter mixed with MMC or charge pump mixed with buck
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present disclosure relates to the field of power electronics, and more particularly to an equivalent transistor and a three-level inverter.
  • Some transistors have their own parasitic diodes. When the voltage applied across the transistor is too high, the diode is usually broken down by the reverse voltage, and then the excessive current flows through the branch of the diode, without flowing through the branch of the transistor. Thus, the transistor can be prevented from being broken by a high voltage.
  • the reverse recovery characteristic of the parasitic diode of the transistor is generally poor, wherein the reverse recovery means that the diode will accumulate a certain amount of charge in the on state, and when the diode is turned off, the diode will release the accumulated charge for a certain period of time. The current until the charge is released. Poor reverse recovery characteristics means that the charge is released for a longer period of time.
  • the transistor switching circuit when the transistor enters the off state from the on state, the parasitic diode takes a long time to release the stored charge, and the forward current on the parasitic diode cannot be quickly disappeared, and the complete off current can be entered after a long time. The state, which causes the switching speed of the transistor to be low.
  • the present disclosure provides an equivalent transistor and a three-level inverter.
  • the technical solution is as follows:
  • an equivalent transistor including a first transistor, Two transistors and diodes, of which:
  • a source of the first transistor is electrically connected to a source of the second transistor
  • a gate of the first transistor is electrically connected to a gate of the second transistor
  • One end of the diode is electrically connected to a drain of the first transistor, and the other end of the diode is electrically connected to a drain of the second transistor.
  • the first transistor and the second transistor are MOSFETs.
  • the high frequency performance of the MOSFET is good, the high frequency performance of the equivalent transistor is good.
  • the diode is a fast recovery diode.
  • a connection between a gate of the first transistor and a gate of the second transistor is an equivalent gate of the equivalent transistor ;
  • a connection end of a source of the first transistor and a source of the second transistor is used to connect a low potential terminal.
  • control of the equivalent transistor can be achieved by changing the voltage applied between the source and the gate.
  • a three-level inverter is provided, the three-level inverter being an I-type three-level inverter, and the outer tube of the three-level inverter is the first aspect Equivalent transistor.
  • the inner tube of the three-level inverter is a MOSFET.
  • the high frequency performance of the three-level inverter is better due to the better high frequency performance of the MOSFET.
  • the three-level inverter includes a first outer tube, a second outer tube, a first inner tube, and a second inner tube, first The outer tube, the first inner tube, the second inner tube and the second outer tube are sequentially connected in series to the circuit;
  • the first outer tube is in complementary conduction with the second inner tube, and the first inner tube is complementary to the second outer tube.
  • a three-level inverter comprising two direct currents The source, the four power frequency rectifier tubes and the equivalent transistor according to any one of claims 1 to 4, wherein the two DC power sources are a first DC power source, a second DC power source, and four power frequency rectifier tubes.
  • the first power frequency rectifier tube, the second power frequency rectifier tube, the third power frequency rectifier tube, and the fourth power frequency rectifier tube are respectively a first equivalent transistor and a second equivalent transistor, wherein :
  • the first end of the first power frequency rectifier tube is electrically connected to the first end of the first DC power source, the second end of the first power frequency rectifier tube and the second power frequency rectifier tube
  • the first end is electrically connected
  • the second end of the second power frequency rectifier is electrically connected to the second end of the first DC power source
  • the first end of the third power frequency rectifier tube is The first end of the second DC power supply is electrically connected
  • the second end of the third power frequency rectifier tube is electrically connected to the first end of the fourth power frequency rectifier tube
  • the fourth power frequency rectifier tube is electrically connected
  • the second end is electrically connected to the second end of the second DC power source
  • a second end of the first equivalent transistor and a first end of the second equivalent transistor are electrically connected, a first end of the first equivalent transistor, and a second end of the first power frequency rectifier The end is electrically connected to the first end of the second power frequency rectifier, the second end of the second equivalent transistor, the second end of the third power frequency rectifier, and the fourth power frequency rectification
  • the first end of the tube is electrically connected;
  • a connection end of the first equivalent transistor and the second equivalent transistor is an output end of the three-level inverter.
  • the four power frequency rectifiers are all IGBTs.
  • the three-level inverter can withstand higher voltages because the IGBT can withstand higher voltages.
  • the first power frequency rectifier, the second power frequency rectifier, the third power frequency rectifier, and the fourth power frequency rectifier are a control signal, in the positive half cycle of the output of the three-level inverter, the first power frequency rectifier tube and the third power frequency rectifier tube are turned on, the second power frequency rectifier tube and the fourth The power frequency rectifier is cut off, the first power frequency rectifier tube and the third power frequency rectifier tube are cut off at the output negative half cycle of the three-level inverter, the second power frequency rectifier tube and the The fourth power frequency rectifier tube is turned on;
  • the first equivalent transistor and the second equivalent transistor are complementary turned on based on the control signals of the first equivalent transistor and the second equivalent transistor, and a switching period of complementary conduction is less than the three The output period of the level inverter.
  • the three-level inverter further includes at least one equivalent transistor group, wherein each of the equivalent transistor groups includes two series An equivalent transistor, a branch formed by connecting two equivalent transistors in series with a branch of the first equivalent transistor and the second equivalent transistor, and two equivalents in each of the equivalent transistor groups The terminals of the transistors are the outputs of the three-level inverter.
  • the equivalent transistor includes a first transistor, a second transistor, and a diode, wherein: a source of the first transistor is electrically connected to a source of the second transistor; a gate of the first transistor and a second transistor The gate is electrically connected; one end of the diode is electrically connected to the drain of the first transistor, and the other end of the diode is electrically connected to the drain of the second transistor.
  • the diodes therein are independent diodes, and a diode with better reverse recovery characteristics can be used. Based on the structure of the equivalent transistor, current cannot flow through the parasitic diodes of the first transistor and the second transistor, but flows through the reverse Recovering a diode with better characteristics can reduce the reverse recovery time and thus increase the switching speed of the equivalent transistor.
  • FIG. 1 is a schematic structural diagram of an equivalent transistor according to an exemplary embodiment
  • FIG. 2 is a circuit diagram of a type I three-level inverter according to an exemplary embodiment
  • FIG. 3 is a circuit diagram of a type I three-level inverter according to an exemplary embodiment
  • FIG. 4 is a schematic diagram of a control signal according to an exemplary embodiment
  • FIG. 5 is a schematic diagram showing current flow in an operating state according to an exemplary embodiment
  • FIG. 6 is a schematic diagram showing current flow in an operating state according to an exemplary embodiment
  • FIG. 7 is a schematic diagram showing current flow in an operating state according to an exemplary embodiment
  • FIG. 8 is a schematic diagram showing current flow in an operating state according to an exemplary embodiment
  • FIG. 9 is a circuit diagram of a three-level inverter according to an exemplary embodiment.
  • FIG. 10 is a schematic diagram of a control signal according to an exemplary embodiment
  • FIG. 11 is a schematic diagram showing current flow in an operating state according to an exemplary embodiment
  • FIG. 12 is a schematic diagram showing current flow in an operating state according to an exemplary embodiment
  • FIG. 13 is a schematic diagram showing current flow in an operating state according to an exemplary embodiment
  • FIG. 14 is a schematic diagram showing current flow in an operating state according to an exemplary embodiment
  • FIG. 15 is a circuit diagram of a three-level inverter according to an exemplary embodiment.
  • the equivalent transistor includes a first transistor T101, a second transistor T102, and a diode D101, wherein:
  • the source of the first transistor T101 is electrically connected to the source of the second transistor T102; the gate of the first transistor T101 is electrically connected to the gate of the second transistor T102; the source of the first transistor T101 and the second transistor T102 The source is electrically connected; one end of the diode D101 is electrically connected to the drain of the first transistor T101, and the other end of the diode D101 is electrically connected to the drain of the second transistor T102.
  • the equivalent transistor includes three solid semiconductor devices of a first transistor T101, a second transistor T102, and a diode D101, and the function thereof can be equivalent to one transistor, wherein the first transistor
  • the gate of T101 is connected to the gate of the second transistor T102
  • the source of the first transistor T101 is connected to the source of the second transistor T102
  • the diode D101 is connected in parallel with the two connected transistors, that is, one end of the diode D101 and the first transistor.
  • the drain of T101 is connected, the other end is connected to the drain of the second transistor T102
  • the equivalent transistor leads out four pins, which are respectively connected to the two drain terminals of the two transistors, a common source terminal and a common gate terminal, which can be seen. Make a separate switching device.
  • the first transistor T101 and the second transistor T102 are MOSFETs (Metal Oxide Semiconductor Field Effect Transistors).
  • the diode D101 is a fast recovery diode.
  • the fast recovery diode is a semiconductor diode with good switching characteristics and short reverse recovery time.
  • a diode with a reverse recovery time of less than 100 ns can be considered as a fast recovery diode.
  • connection end of the gate of the first transistor T101 and the gate of the second transistor T102 is an equivalent gate of the equivalent transistor, and the connection end of the source of the first transistor T101 and the source of the second transistor T102 Used to connect low potential terminals.
  • connection end of the gate of the first transistor T101 and the gate of the second transistor T102 is an equivalent gate of the equivalent transistor, and the source of the first transistor T101 is connected to the source of the second transistor T102.
  • the terminal is the equivalent source of the equivalent transistor and is used to connect the low potential terminal.
  • the embodiment further provides a three-level inverter, as shown in FIG. 2, wherein the three-level inverter is an I-type three-level inverter, the outer tube Q201 of the three-level inverter, Q204 is the equivalent transistor described above.
  • the I-type three-level inverter is a three-level inverter in which four switching elements are connected in an I-shape in a circuit configuration.
  • the three-level inverter is a device that can convert DC power into AC power and can provide three potentials at the output end.
  • the traditional circuit structure of the I-type three-level inverter is shown in Figure 3.
  • capacitors C201 and C202 are DC sources, and provide DC voltages of (-U/2 to +U/2).
  • Transistors Q201', Q202, Q203, and Q204' are high-frequency switching elements such as MOSFETs. Between the negative electrodes, the clamp diodes D201 and D202 are anti-parallel to the middle of the upper and lower arms.
  • External pipe Q201' and inner pipe Q203 during operation The complementary conduction, the inner tube Q202 and the outer tube Q204' are complementarily turned on, and the control signal is as shown in FIG.
  • the positive half cycle Q201' and Q203 of the three-level inverter output alternating current are complementarily turned on, and have dead time, Q202 Continuous conduction, Q204' is continuously turned off; Q202, Q204' are negatively turned on during the negative half cycle, and have dead time, Q203 is continuously turned on, and Q201' is continuously turned off.
  • 5 is a schematic diagram of the current when the positive half cycle Q201' and Q202 are turned on, and the current direction is from C201 to Q201' to Q202;
  • FIG. 6 is a current diagram when the positive half cycle Q203 and Q202 are turned on, and the current direction is grounded.
  • Figure 7 is the current diagram when the negative half cycle Q202, Q203 is on, the current direction is from ground to D201 to Q202, or from Q203 to D202 and then to the ground;
  • Figure 8 is a schematic diagram of the current when the negative half cycle Q203, Q204' is turned on, the current direction is from Q203 to Q204' to C202.
  • the outer tubes Q201' and Q204' are replaced with the above-mentioned equivalent transistors Q201 and Q204, and the rest remain unchanged from the prior art, so that it is effective without changing the control signals of the four switching elements.
  • the problem of poor reverse recovery performance of the parasitic diodes of the original outer tubes Q201' and Q204' is avoided.
  • the inner tubes Q202 and Q203 of the above three-level inverter are MOSFETs.
  • the embodiment further provides a three-level inverter.
  • the three-level inverter includes two DC power sources, four power frequency rectifier tubes and two equivalent transistors, and two The DC power supply is the first DC power source C301 and the second DC power source C302, and the four power frequency rectifier tubes are the first power frequency rectifier tube Q301, the second power frequency rectifier tube Q302, and the third power frequency rectifier tube Q303, respectively.
  • the four power frequency rectifier tube Q304, the two equivalent transistors are a first equivalent transistor Q305 and a second equivalent transistor Q306, wherein:
  • the first end of the first power frequency rectifier Q301 is electrically connected to the first end of the first DC power source C301, and the second end of the first power frequency rectifier tube Q301 and the first end of the second power frequency rectifier tube Q302 are electrically connected.
  • the second end of the second power frequency rectifier tube Q302 is electrically connected to the second end of the first DC power source C301, and the first end of the third power frequency rectifier tube Q303 and the first end of the second DC power source C302 are connected.
  • the second end of the third power frequency rectifier tube Q303 is electrically connected to the first end of the fourth power frequency rectifier tube Q304, and the second end of the fourth power frequency rectifier tube Q304 and the second power source C302 are The two ends are electrically connected; the second end of the second power frequency rectifier Q302, the second end of the first DC power source C301, the first end of the third power frequency rectifier tube Q303, and the first end of the second DC power source C302 Electrically connected and grounded; the second end of the first equivalent transistor Q305 is electrically connected to the first end of the second equivalent transistor Q306, the first end of the first equivalent transistor Q305, and the first power frequency rectifier Q301 The second end is electrically connected to the first end of the second power frequency rectifier tube Q302, The second end of the second equivalent transistor Q306 and the second end of the third power frequency rectifier Q303 are electrically connected to the first end of the fourth power frequency rectifier Q304; the first equivalent transistor Q305 and the second equivalent transistor The connection of the Q306 is the
  • the power frequency rectifier tube is a transistor that can convert alternating current alternating in direction to direct current in a single direction.
  • the capacitors C301 and C302 are DC sources, and provide DC voltages of (-U/2 to +U/2).
  • the transistors Q301, Q302, Q303, and Q304 are power frequency rectifier tubes, and are connected in series to the DC power supply. Between Q302 and Q303, there is a potential of 0, the equivalent transistors Q305 and Q306 are connected in series, and the branches in series are connected in parallel with Q302 and Q303.
  • the terminals of Q305 and Q306 are the outputs of the three-level inverter.
  • the four power frequency rectifiers are IGBTs (Insulated Gate Bipolar Transistors).
  • the output of the three-level inverter is positive In the half cycle, the first power frequency rectifier tube Q301 and the third power frequency rectifier tube Q303 are turned on, the second power frequency rectifier tube Q302 and the fourth power frequency rectifier tube Q304 are turned off, and the output of the three-level inverter is negative for half a week.
  • a power frequency rectifier tube Q301 and a third power frequency rectifier tube Q303 are turned off, the second power frequency rectifier tube Q302 and the fourth power frequency rectifier tube Q304 are turned on; based on the control of the first equivalent transistor Q305 and the second equivalent transistor Q306
  • the signal, the first equivalent transistor Q305 and the second equivalent transistor Q306 are complementarily turned on, and the switching period of the complementary conduction is smaller than the output period of the three-level inverter.
  • the output positive half cycle and the output negative half cycle are the positive half cycle and the negative half cycle of the alternating current output by the three-level inverter.
  • the switching period is the time required for Q305 or Q306 to be turned on, turned off, and turned on again, and the length of the switching period is constantly changing according to the sinusoidal characteristic.
  • the output period is the period of change of the alternating current output by the three-level inverter.
  • FIG. 12 is a schematic diagram of the current when the positive half cycles Q303 and Q306 are turned on, and the current direction is from the ground terminal to Q303 to Q306, or from Q306 to Q303 to ground;
  • Figure 13 is the current diagram when the negative half cycle Q302, Q305 is on, The current direction is from ground to Q302 to Q305, or from Q305 to Q302 to ground.
  • Figure 14 is a schematic diagram of the current when the negative half cycles Q304 and Q306 are turned on. The current direction is from Q306 to Q304 to C302.
  • the three-level inverter further includes at least one equivalent transistor group G, wherein each equivalent transistor group G includes two series-connected equivalent transistors, and two equivalent transistors are connected in series to form a branch and a third
  • the branches of an equivalent transistor Q305 and the second equivalent transistor Q306 are connected in parallel, and the terminals of the two equivalent transistors in each equivalent transistor group are the outputs of the three-level inverter.
  • the circuit structure of the above three-level inverter may further include at least one equivalent transistor group G, as shown in FIG. 15, wherein each equivalent transistor group G includes two series-connected equivalent transistors. A branch formed by connecting two equivalent transistors in series is connected in parallel with a branch of the first equivalent transistor Q305 and the second equivalent transistor Q306, and a connection terminal of two equivalent transistors in each equivalent transistor group is three-level The output of the inverter. It is easy to understand that Q305 and Q306 are an equivalent transistor group G, and the control signals of all equivalent transistor groups can be the same except for the phase difference. In addition, each output can be connected to an LC filter, and the output voltage is filtered and interleaved to form a higher frequency AC.
  • the equivalent transistor includes a first transistor, a second transistor, and a diode, wherein: a source of the first transistor is electrically connected to a source of the second transistor; a gate of the first transistor and a second transistor The gate is electrically connected; one end of the diode is electrically connected to the drain of the first transistor, and the other end of the diode is electrically connected to the drain of the second transistor.
  • the diodes therein are independent diodes, and a diode with better reverse recovery characteristics can be used. Based on the structure of the equivalent transistor, current cannot flow through the parasitic diodes of the first transistor and the second transistor, but flows through the reverse Recovering a diode with better characteristics can reduce the reverse recovery time and thus increase the switching speed of the equivalent transistor.

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  • Power Engineering (AREA)
  • Inverter Devices (AREA)
  • Electronic Switches (AREA)

Abstract

一种等效晶体管和三电平逆变器，等效晶体管包括第一晶体管（T101）、第二晶体管（T102）和二极管（D101），第一晶体管的源极与第二晶体管的源极电性连接，第一晶体管的栅极与第二晶体管的栅极电性连接，二极管的一端与第一晶体管的漏极电性连接，二极管的另一端与第二晶体管的漏极电性连接。等效晶体管的这种结构减少了反向恢复时间并提高了开关速度。

Description

一种等效晶体管和三电平逆变器
本申请要求于2015年12月23日提交中国专利局、申请号为201510981520.X、发明名称为“一种等效晶体管和三电平逆变器”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开是关于电力电子技术领域，尤其是关于一种等效晶体管和三电平逆变器。
背景技术
随着电子技术的飞速发展，晶体管得到了越来越广泛的运用。
有些晶体管本身自带有寄生二极管，当晶体管两端加载的电压过高时，二极管一般先被反向电压击穿，然后过大的电流会流经二极管所在支路，不流经晶体管所在支路，从而可以避免晶体管被高电压击穿。
在实现本公开的过程中，发明人发现至少存在以下问题：
因为晶体管的寄生二极管的反向恢复特性一般较差，其中，反向恢复是指，二极管在导通状态下会蓄积一定量的电荷，当二极管截止时，二极管会释放蓄积的电荷，形成一定时间的电流，直到电荷释放完毕。反向恢复特性较差是指电荷释放的时间较长。在晶体管开关电路中，当晶体管由导通状态进入截止状态时，寄生二极管需要较长时间来释放存储的电荷，寄生二极管上正向电流不能快速消失，在较长时间后才能进入完全截止电流的状态，从而导致晶体管的开关速度较低。
发明内容
为了克服相关技术中存在的问题，本公开提供了一种等效晶体管和三电平逆变器。所述技术方案如下：
第一方面，提供了一种等效晶体管，所述等效晶体管包括第一晶体管、第 二晶体管和二极管，其中：
所述第一晶体管的源极与所述第二晶体管的源极电性连接；
所述第一晶体管的栅极与所述第二晶体管的栅极电性连接；
所述二极管的一端与所述第一晶体管的漏极电性连接，所述二极管的另一端与所述第二晶体管的漏极电性连接。
结合第一方面，在该第一方面的第一种可能实现方式中，所述第一晶体管和所述第二晶体管为MOSFET。
这样，由于MOSFET的高频性能较好，等效晶体管的高频性能较好。
结合第一方面，在该第一方面的第二种可能实现方式中，所述二极管为快恢复二极管。
这样，可以有效减少等效晶体管的反向恢复时间。
结合第一方面，在该第一方面的第三种可能实现方式中，所述第一晶体管的栅极与所述第二晶体管的栅极的连接端为所述等效晶体管的等效栅极；
所述第一晶体管的源极与所述第二晶体管的源极的连接端用于连接低电势端。
这样，可以通过改变加载在源极和栅极之间的电压实现对等效晶体管的控制。
第二方面，提供了一种三电平逆变器，所述三电平逆变器为I型三电平逆变器，所述三电平逆变器的外管为第一方面所述的等效晶体管。
结合第二方面，在该第二方面的第一种可能实现方式中，所述三电平逆变器的内管为MOSFET。
这样，由于MOSFET的高频性能较好，三电平逆变器的高频性能较好。
结合第二方面，在该第二方面的第二种可能实现方式中，所述三电平逆变器包括第一外管、第二外管、第一内管和第二内管，第一外管、第一内管、第二内管、第二外管依次串联接入电路；
所述第一外管与所述第二内管互补导通，所述第一内管与所述第二外管互补导通。
第三方面，提供了一种三电平逆变器，所述三电平逆变器包括两个直流电 源，四个工频整流管和两个如权利要求1-4任一项所述的等效晶体管，两个直流电源分别为第一直流电源、第二直流电源，四个工频整流管分别为第一工频整流管、第二工频整流管、第三工频整流管、第四工频整流管，两个等效晶体管分别为第一等效晶体管、第二等效晶体管，其中：
所述第一工频整流管的第一端与所述第一直流电源的第一端电性连接，所述第一工频整流管的第二端与所述第二工频整流管的第一端电性连接，所述第二工频整流管的第二端与所述第一直流电源的第二端电性连接，所述第三工频整流管的第一端与所述第二直流电源的第一端电性连接，所述第三工频整流管的第二端与所述第四工频整流管的第一端电性连接，所述第四工频整流管的第二端与所述第二直流电源的第二端电性连接；
所述第二工频整流管的第二端、所述第一直流电源的第二端、所述第三工频整流管的第一端以及所述第二直流电源的第一端电性连接并接地；
所述第一等效晶体管的第二端和所述第二等效晶体管的第一端电性连接，所述第一等效晶体管的第一端、所述第一工频整流管的第二端与所述第二工频整流管的第一端电性连接，所述第二等效晶体管的第二端、所述第三工频整流管的第二端与所述第四工频整流管的第一端电性连接；
所述第一等效晶体管和所述第二等效晶体管的连接端为所述三电平逆变器的输出端。
结合第三方面，在该第三方面的第一种可能实现方式中，所述四个工频整流管均为IGBT。
这样，由于IGBT可以承受较高电压，三电平逆变器也可承受较高电压。
结合第三方面，在该第三方面的第二种可能实现方式中，基于所述第一工频整流管、第二工频整流管、第三工频整流管和第四工频整流管的控制信号，在所述三电平逆变器的输出正半周，所述第一工频整流管和所述第三工频整流管导通，所述第二工频整流管和所述第四工频整流管截止，在所述三电平逆变器的输出负半周，所述第一工频整流管和所述第三工频整流管截止，所述第二工频整流管和所述第四工频整流管导通；
基于所述第一等效晶体管和所述第二等效晶体管的控制信号，所述第一等效晶体管和所述第二等效晶体管互补导通，且互补导通的切换周期小于所述三电平逆变器的输出周期。
结合第三方面，在该第三方面的第三种可能实现方式中，所述三电平逆变器还包括至少一个等效晶体管组，其中，每个所述等效晶体管组包括两个串联的等效晶体管，两个等效晶体管串联形成的支路与所述第一等效晶体管、所述第二等效晶体管的支路并联，且每个所述等效晶体管组中两个等效晶体管的连接端均为所述三电平逆变器的输出端。
这样，多个等效晶体管组交错耦合并联，可以提高三电平逆变器的开关频率。
本公开的实施例提供的技术方案可以包括以下有益效果：
本公开实施例中，等效晶体管包括第一晶体管、第二晶体管和二极管，其中：第一晶体管的源极与第二晶体管的源极电性连接；第一晶体管的栅极与第二晶体管的栅极电性连接；二极管的一端与第一晶体管的漏极电性连接，二极管的另一端与第二晶体管的漏极电性连接。这样，其中的二极管为独立的二极管，可以采用反向恢复特性较好的二极管，基于此等效晶体管的结构，电流无法流经第一晶体管和第二晶体管的寄生二极管，而是流经反向恢复特性较好的二极管，可以减少反向恢复时间，从而可以提高等效晶体管的开关速度。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。在附图中：
图1是根据一示例性实施例示出的一种等效晶体管的结构示意图；
图2是根据一示例性实施例示出的一种I型三电平逆变器的电路示意图；
图3是根据一示例性实施例示出的一种I型三电平逆变器的电路示意图；
图4是根据一示例性实施例示出的一种控制信号的示意图；
图5是根据一示例性实施例示出的一种工作状态下电流流向的示意图；
图6是根据一示例性实施例示出的一种工作状态下电流流向的示意图；
图7是根据一示例性实施例示出的一种工作状态下电流流向的示意图；
图8是根据一示例性实施例示出的一种工作状态下电流流向的示意图；
图9是根据一示例性实施例示出的一种三电平逆变器的电路示意图；
图10是根据一示例性实施例示出的一种控制信号的示意图；
图11是根据一示例性实施例示出的一种工作状态下电流流向的示意图；
图12是根据一示例性实施例示出的一种工作状态下电流流向的示意图；
图13是根据一示例性实施例示出的一种工作状态下电流流向的示意图；
图14是根据一示例性实施例示出的一种工作状态下电流流向的示意图；
图15是根据一示例性实施例示出的一种三电平逆变器的电路示意图。
通过上述附图，已示出本公开明确的实施例，后文中将有更详细的描述。这些附图和文字描述并不是为了通过任何方式限制本公开构思的范围，而是通过参考特定实施例为本领域技术人员说明本公开的概念。
图例说明
T101、T102晶体管                     D101二极管
C201、C202直流电源                   D201、D202钳位二极管
Q201’、Q204’、Q202、Q203晶体管     Q201、Q204等效晶体管
C301、C302直流电源                   Q305、Q306等效晶体管
Q301、Q302、Q303、Q304工频整流管     G等效晶体管组
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本公开相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本公开的一些方面相一致的装置和方法的例子。
本公开实施例提供了一种等效晶体管，如图1所示，所述等效晶体管包括第一晶体管T101、第二晶体管T102和二极管D101，其中：
第一晶体管T101的源极与第二晶体管T102的源极电性连接；第一晶体管T101的栅极与第二晶体管T102的栅极电性连接；第一晶体管T101的源极与第二晶体管T102的源极电性连接；二极管D101的一端与第一晶体管T101的漏极电性连接，二极管D101的另一端与第二晶体管T102的漏极电性连接。
在实施中，等效晶体管包括第一晶体管T101、第二晶体管T102和二极管D101三个固体半导体器件，其作用可以等效为一个晶体管，其中，第一晶体管 T101的栅极和第二晶体管T102的栅极相连，第一晶体管T101的源极与第二晶体管T102的源极相连，二极管D101与相连的两个晶体管并联，即二极管D101的一端与第一晶体管T101的漏极相连，另一端与第二晶体管T102的漏极相连，等效晶体管引出4个引脚，分别连接两个晶体管的两个漏极端、一个公共源极端和一个公共栅极端，可以看做一个单独的开关器件。
可选的，第一晶体管T101和第二晶体管T102为MOSFET(Metal Oxide Semiconductor Field Effect Transistor，金属氧化层半导体场效晶体管)。
可选的，二极管D101为快恢复二极管。
其中，快恢复二极管是一种具有开关特性好、反向恢复时间短的特点的半导体二极管，一般反向恢复时间小于100ns的二极管可以认为是快恢复二极管。
可选的，第一晶体管T101的栅极与第二晶体管T102的栅极的连接端为等效晶体管的等效栅极，第一晶体管T101的源极与第二晶体管T102的源极的连接端用于连接低电势端。
在实施中，第一晶体管T101的栅极与第二晶体管T102的栅极的连接端为等效晶体管的等效栅极，第一晶体管T101的源极与所第二晶体管T102的源极的连接端为等效晶体管的等效源极，用于连接低电势端。当等效晶体管的等效源极与等效栅极间电压差大于或等于一定阈值时，第一晶体管T101与第二晶体管T102的漏极与源极间均导通，相当于等效晶体管导通；当晶体管的源极与栅极间电压差小于一定阈值时，第一晶体管T101与第二晶体管T102的漏极与源极间截止，相当于等效晶体管截止。
本实施例还提供了一种三电平逆变器，如图2所示，其中，三电平逆变器为I型三电平逆变器，三电平逆变器的外管Q201、Q204为上述的等效晶体管。
其中，I型三电平逆变器为4个开关元件在电路结构中成I字型排列连接的一种三电平逆变器。
在实施中，三电平逆变器是一种可以将直流电转换为交流电的，并能在输出端提供三种电位的器件，I型三电平逆变器传统的电路结构如图3所示，其中，电容C201、C202为直流源，提供(-U/2～+U/2)的直流电压，晶体管Q201’、Q202、Q203、Q204’为MOSFET等高频开关元件，串联在直流源正负极间，钳位二极管D201、D202反并联于上下桥臂的中间。工作时外管Q201’和内管Q203 互补导通、内管Q202和外管Q204’互补导通，控制信号如图4所示，三电平逆变器输出交流电的正半周Q201’、Q203互补导通，并具有死区时间，Q202持续导通，Q204’持续关断；负半周Q202、Q204’互补导通，并具有死区时间，Q203持续导通，Q201’持续关断。其中，图5为正半周Q201’、Q202导通时的电流示意图，电流方向为由C201至Q201’再至Q202；图6为正半周Q203、Q202导通时的电流示意图，电流方向为由接地端至D201再至Q202，或为由Q203至D202再至接地端；图7为负半周Q202、Q203导通时的电流示意图，电流方向为由接地端至D201再至Q202，或为由Q203至D202再至接地端；图8为负半周Q203、Q204’导通时的电流示意图，电流方向为由Q203至Q204’再至C202。
本方案中将外管Q201’和Q204’替换为上述等效晶体管Q201和Q204，其余部分与现有技术保持不变，这样，在不需要改变4个开关元件的控制信号的前提下，有效的避免了原外管Q201’、Q204’的寄生二极管的反向恢复性能差的问题。
可选的，上述三电平逆变器的内管Q202和Q203为MOSFET。
本实施例还提供了一种三电平逆变器，如图9所示，三电平逆变器包括两个直流电源，四个工频整流管和两个上述的等效晶体管，两个直流电源分别为第一直流电源C301、第二直流电源C302，四个工频整流管分别为第一工频整流管Q301、第二工频整流管Q302、第三工频整流管Q303、第四工频整流管Q304，两个等效晶体管分别为第一等效晶体管Q305、第二等效晶体管Q306，其中：
第一工频整流管Q301的第一端与第一直流电源C301的第一端电性连接，第一工频整流管Q301的第二端与第二工频整流管Q302的第一端电性连接，第二工频整流管Q302的第二端与第一直流电源C301的第二端电性连接，第三工频整流管Q303的第一端与第二直流电源C302的第一端电性连接，第三工频整流管Q303的第二端与第四工频整流管Q304的第一端电性连接，第四工频整流管Q304的第二端与第二直流电源C302的第二端电性连接；第二工频整流管Q302的第二端、第一直流电源C301的第二端、第三工频整流管Q303的第一端以及第二直流电源C302的第一端电性连接并接地；第一等效晶体管Q305的第二端和第二等效晶体管Q306的第一端电性连接，第一等效晶体管Q305的第一端、第一工频整流管Q301的第二端与第二工频整流管Q302的第一端电性连接， 第二等效晶体管Q306的第二端、第三工频整流管Q303的第二端与第四工频整流管Q304的第一端电性连接；第一等效晶体管Q305和第二等效晶体管Q306的连接端为三电平逆变器的输出端。
其中，工频整流管是可以将方向交替变化的交流电变换成单一方向的直流电的晶体管。
在实施中，电容C301、C302为直流源，提供(-U/2～+U/2)的直流电压，晶体管Q301、Q302、Q303、Q304为工频整流管，串联接入直流电源正负级之间，Q302、Q303管之间为0电势位，等效晶体管Q305、Q306串联，且串联的支路与Q302、Q303并联。Q305、Q306的连接端为三电平逆变器的输出端。
可选的，四个工频整流管均为IGBT(Insulated Gate Bipolar Transistor，绝缘栅双极型晶体管)。
可选的，基于第一工频整流管Q301、第二工频整流管Q302、第三工频整流管Q303和第四工频整流管Q304的控制信号，在三电平逆变器的输出正半周，第一工频整流管Q301和第三工频整流管Q303导通，第二工频整流管Q302和第四工频整流管Q304截止，在三电平逆变器的输出负半周，第一工频整流管Q301和第三工频整流管Q303截止，第二工频整流管Q302和第四工频整流管Q304导通；基于第一等效晶体管Q305和第二等效晶体管Q306的控制信号，第一等效晶体管Q305和第二等效晶体管Q306互补导通，且互补导通的切换周期小于三电平逆变器的输出周期。
其中，输出正半周和输出负半周为三电平逆变器输出的交流电的正半周和负半周。切换周期是Q305或Q306经历导通、截止再导通所需的时间，且切换周期长度按正弦特性不断变化。输出周期为三电平逆变器输出的交流电的变化周期。
在实施中，上述三电平逆变器工作时，在输出正半周，Q301与Q303导通，Q302与Q304截止，在输出负半周，Q302与Q304导通，Q301与Q303截止，而对于输出正半周和输出负半周，Q305和Q306均为互补导通，且具有死区时间，具体的控制信号如图10所示。其中，图11为正半周Q301、Q305导通时的电流示意图，电流方向为由C301至Q301再至Q305；图12为正半周Q303、Q306导通时的电流示意图，电流方向为由接地端至Q303再至Q306，或为由Q306至Q303再至接地端；图13为负半周Q302、Q305导通时的电流示意图， 电流方向为由接地端至Q302再至Q305，或为由Q305至Q302再至接地端；图14为负半周Q304、Q306导通时的电流示意图，电流方向为由Q306至Q304再至C 302。
可选的，三电平逆变器还包括至少一个等效晶体管组G，其中，每个等效晶体管组G包括两个串联的等效晶体管，两个等效晶体管串联形成的支路与第一等效晶体管Q305、第二等效晶体管Q306的支路并联，且每个等效晶体管组中两个等效晶体管的连接端均为三电平逆变器的输出端。
在实施中，上述三电平逆变器的电路结构中还可以包括至少一个等效晶体管组G，如图15所示，其中，每个等效晶体管组G包括两个串联的等效晶体管，两个等效晶体管串联形成的支路与第一等效晶体管Q305、第二等效晶体管Q306的支路并联，且每个等效晶体管组中两个等效晶体管的连接端均为三电平逆变器的输出端。容易理解的是，Q305和Q306即为一个等效晶体管组G，且所有的等效晶体管组的控制信号除相位不同外的其它参数均可相同。另外，每个输出端可与LC滤波器相连，输出电压经滤波后交错耦合可形成更高频率的交流电。
本公开实施例中，等效晶体管包括第一晶体管、第二晶体管和二极管，其中：第一晶体管的源极与第二晶体管的源极电性连接；第一晶体管的栅极与第二晶体管的栅极电性连接；二极管的一端与第一晶体管的漏极电性连接，二极管的另一端与第二晶体管的漏极电性连接。这样，其中的二极管为独立的二极管，可以采用反向恢复特性较好的二极管，基于此等效晶体管的结构，电流无法流经第一晶体管和第二晶体管的寄生二极管，而是流经反向恢复特性较好的二极管，可以减少反向恢复时间，从而可以提高等效晶体管的开关速度。
本领域技术人员在考虑说明书及实践这里公开的公开后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由下面的权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结 构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限制。

Claims (11)

  1. 一种等效晶体管，其特征在于，所述等效晶体管包括第一晶体管、第二晶体管和二极管，其中：
    所述第一晶体管的源极与所述第二晶体管的源极电性连接；
    所述第一晶体管的栅极与所述第二晶体管的栅极电性连接；
    所述二极管的一端与所述第一晶体管的漏极电性连接，所述二极管的另一端与所述第二晶体管的漏极电性连接。
  2. 根据权利要求1所述的等效晶体管，其特征在于，所述第一晶体管和所述第二晶体管为MOSFET。
  3. 根据权利要求1所述的等效晶体管，其特征在于，所述二极管为快恢复二极管。
  4. 根据权利要求1所述的等效晶体管，其特征在于，所述第一晶体管的栅极与所述第二晶体管的栅极的连接端为所述等效晶体管的等效栅极；
    所述第一晶体管的源极与所述第二晶体管的源极的连接端用于连接低电势端。
  5. 一种三电平逆变器，其特征在于，所述三电平逆变器为I型三电平逆变器，所述三电平逆变器的外管为权利要求1-4任一项所述的等效晶体管。
  6. 根据权利要求5所述的三电平逆变器，其特征在于，所述三电平逆变器的内管为MOSFET。
  7. 根据权利要求6所述的三电平逆变器，其特征在于，所述三电平逆变器包括第一外管、第二外管、第一内管和第二内管，所述第一外管、所述第一内管、所述第二内管、所述第二外管依次串联接入电路；
    所述第一外管与所述第二内管互补导通，所述第一内管与所述第二外管互补导通。
  8. 一种三电平逆变器，其特征在于，所述三电平逆变器包括两个直流电源，四个工频整流管和两个如权利要求1-4任一项所述的等效晶体管，两个直流电源分别为第一直流电源、第二直流电源，四个工频整流管分别为第一工频整流管、 第二工频整流管、第三工频整流管、第四工频整流管，两个等效晶体管分别为第一等效晶体管、第二等效晶体管，其中：
    所述第一工频整流管的第一端与所述第一直流电源的第一端电性连接，所述第一工频整流管的第二端与所述第二工频整流管的第一端电性连接，所述第二工频整流管的第二端与所述第一直流电源的第二端电性连接，所述第三工频整流管的第一端与所述第二直流电源的第一端电性连接，所述第三工频整流管的第二端与所述第四工频整流管的第一端电性连接，所述第四工频整流管的第二端与所述第二直流电源的第二端电性连接；
    所述第二工频整流管的第二端、所述第一直流电源的第二端、所述第三工频整流管的第一端以及所述第二直流电源的第一端电性连接并接地；
    所述第一等效晶体管的第二端和所述第二等效晶体管的第一端电性连接，所述第一等效晶体管的第一端、所述第一工频整流管的第二端与所述第二工频整流管的第一端电性连接，所述第二等效晶体管的第二端、所述第三工频整流管的第二端与所述第四工频整流管的第一端电性连接；
    所述第一等效晶体管和所述第二等效晶体管的连接端为所述三电平逆变器的输出端。
  9. 根据权利要求8所述的三电平逆变器，其特征在于，所述四个工频整流管均为IGBT。
  10. 根据权利要求8所述的三电平逆变器，其特征在于，基于所述第一工频整流管、第二工频整流管、第三工频整流管和第四工频整流管的控制信号，在所述三电平逆变器的输出正半周，所述第一工频整流管和所述第三工频整流管导通，所述第二工频整流管和所述第四工频整流管截止，在所述三电平逆变器的输出负半周，所述第一工频整流管和所述第三工频整流管截止，所述第二工频整流管和所述第四工频整流管导通；
    基于所述第一等效晶体管和所述第二等效晶体管的控制信号，所述第一等效晶体管和所述第二等效晶体管互补导通，且互补导通的切换周期小于所述三电平逆变器的输出周期。
  11. 根据权利要求8所述的三电平逆变器，其特征在于，所述三电平逆变器还包括至少一个等效晶体管组，其中，每个所述等效晶体管组包括两个串联的等效晶体管，两个等效晶体管串联形成的支路与所述第一等效晶体管、所述 第二等效晶体管的支路并联，且每个所述等效晶体管组中两个等效晶体管的连接端均为所述三电平逆变器的输出端。
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