WO2017107554A1 - 高压发光二极管及其制作方法 - Google Patents

高压发光二极管及其制作方法 Download PDF

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Publication number
WO2017107554A1
WO2017107554A1 PCT/CN2016/097874 CN2016097874W WO2017107554A1 WO 2017107554 A1 WO2017107554 A1 WO 2017107554A1 CN 2016097874 W CN2016097874 W CN 2016097874W WO 2017107554 A1 WO2017107554 A1 WO 2017107554A1
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Prior art keywords
emitting diode
light emitting
light
adjacent
channel
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PCT/CN2016/097874
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English (en)
French (fr)
Inventor
郑高林
洪灵愿
林潇雄
王�锋
林素慧
张家宏
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厦门市三安光电科技有限公司
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Publication of WO2017107554A1 publication Critical patent/WO2017107554A1/zh
Priority to US15/810,076 priority Critical patent/US10242958B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/382—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/385—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending at least partially onto a side surface of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/64—Heat extraction or cooling elements
    • H01L33/648—Heat extraction or cooling elements the elements comprising fluids, e.g. heat-pipes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0016—Processes relating to electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape

Definitions

  • the present invention relates to a high voltage light emitting diode structure and a method of fabricating the same.
  • LED Light Emitting Diode
  • high-power LEDs have become the focus of LED manufacturers in response to lighting needs.
  • Traditional high-power LEDs use high-current and low-voltage single-chip as the light-emitting unit.
  • the junction temperature of the high-current injection chip is increased, which affects the luminous efficiency.
  • international manufacturers have introduced integrated high-voltage LED chips.
  • the high-voltage LED chip refers to a small-current, high-voltage LED chip in which a plurality of microchips are connected in series by metal wires. Compared with conventional low-voltage LEDs, it has the following advantages: low power dissipation, high power conversion efficiency, and low packaging cost.
  • the chip process itself becomes complicated, and the reliability of the same high-voltage LED chip is also reduced.
  • the anti- ESD capability of the high-voltage chip is relatively weak. This is related to the increased probability of ESD failure after serial connection of multiple microchips. The same is also related to the ESD resistance of the materials used in the high-voltage chip manufacturing process.
  • the present invention proposes a chip design scheme for improving the ESD tolerance of high voltage LEDs.
  • a high voltage light emitting diode includes: a substrate and a light emitting epitaxial stack on the substrate; the light emitting epitaxial stack has a plurality of light emitting diode units, and Luminous dipole
  • the tube unit is composed of at least two rows and columns, and each of the LED units is separated from each other by a channel; an electrode interconnection line spans over the channel, and two adjacent LED units are connected by the electrode interconnection line; a disk formed on the outermost light emitting diode unit of the high voltage light emitting diode; an insulating protective layer opening is disposed at a channel of any adjacent two light emitting diodes having a potential difference of ⁇ 3 times the forward voltage of the single light emitting diode The heat generated by the dielectric breakdown of the insulating protective layer is prevented from causing the light-emitting epitaxial stack to be broken down.
  • a high voltage light emitting diode includes: a substrate and a light emitting epitaxial stack on the substrate; the light emitting epitaxial layer has a plurality of light emitting diode units, and The LED units are composed of at least two rows and columns, and the LED units are separated from each other by a channel; an electrode interconnection line spans the channel, and two adjacent LED units are connected by the electrode interconnection line; a pad formed on the outermost light emitting diode unit of the high voltage light emitting diode; the first and second light emitting diode units of the adjacent two adjacent light emitting diode units are adjacent to each other, and an insulating protective layer is provided The heat generated by the dielectric breakdown of the insulating protective layer is prevented from causing the light-emitting epitaxial stack to be broken down.
  • a high voltage light emitting diode includes: a substrate and a light emitting epitaxial layer on the substrate; the light emitting epitaxial layer has a plurality of light emitting diode units, and The LED units are composed of at least two rows and columns, and the LED units are separated from each other by a channel; an electrode interconnection line spans the channel, and two adjacent LED units are connected by the electrode interconnection line; a pad formed on the outermost light emitting diode unit of the high voltage light emitting diode; a wavelength conversion layer as an insulating protective layer formed on a surface of the high voltage light emitting diode except the electrode pad region; the adjacent adjacent The first and last LED units of the two LED unit rows are arranged and provided with an insulating protective layer opening for preventing the insulation layer from being broken by the heat generated by the dielectric breakdown.
  • the light emitting diode unit includes a first type semiconductor layer, a light emitting layer, and a second type semiconductor layer in order from bottom to top.
  • the light emitting unit may be formed in a parallelogram or a rectangle or a square or a circle or an ellipse.
  • Last glow The diode unit and the electrode pad are provided with an insulating protective layer, and the remaining LED units are provided with an insulating protective layer.
  • the LED unit rows are in a C-type or an inverse C-type or an S-type or an inverse-S-type distribution or one of the foregoing combinations.
  • the insulating protective layer is located at a lateral channel and/or a longitudinal channel of the LED unit.
  • the insulating protective layer has a T-shape or an I-shape or a font or any combination of the foregoing.
  • the length of the insulating protective layer of the lateral channel or the longitudinal channel position of the light emitting diode unit is 3 times or more of the channel width.
  • a method of fabricating a high voltage light emitting diode comprising: providing a substrate, and forming a light emitting epitaxial layer on the substrate; patterning the light emitting epitaxial layer and forming a trench The channel is formed until the surface of the substrate is exposed, thereby separating the light-emitting epitaxial stack into a plurality of light-emitting diode units, and the light-emitting diode unit is composed of at least two rows and columns; and an electrode interconnection line is formed across the channel, adjacent to Two LED units are connected through the electrode interconnection line; an electrode pad is formed on the light-emitting diode unit at the outermost periphery of the high-voltage light-emitting diode; and the potential difference between the two adjacent light-emitting diodes is ⁇ a single light-emitting diode An insulating protective layer opening is provided at the channel three times the forward voltage for preventing the heat generated by the
  • a method of fabricating a high voltage light emitting diode comprising: providing a substrate, and forming a light emitting epitaxial layer on the substrate; patterning the light emitting epitaxial layer and forming a trench The channel is formed until the surface of the substrate is exposed, thereby separating the light-emitting epitaxial stack into a plurality of light-emitting diode units, and the light-emitting diode unit is composed of at least two rows and columns; and an electrode interconnection line is formed across the channel, adjacent to Two light emitting diode units are connected through the electrode interconnection line; an electrode pad is formed on the outermost light emitting diode unit of the high voltage light emitting diode; adjacent to the row of any adjacent two light emitting diode units An insulating protective layer opening is formed between the first and last LED units to prevent the insulating protective layer from being broken by the heat generated by the dielectric breakdown.
  • a method of fabricating a high voltage light emitting diode comprising: providing a substrate, and forming a light emitting epitaxial layer on the substrate; patterning the light emitting epitaxial layer and forming a trench Road until Exposing the surface of the substrate, thereby separating the light-emitting epitaxial stack into a plurality of light-emitting diode units, and the light-emitting diode unit is composed of at least two rows and columns; forming an electrode interconnection line across the channel, adjacent two The light emitting diode unit is connected through the electrode interconnection line; the electrode pad is formed on the outermost light emitting diode unit of the high voltage light emitting diode; and the adjacent two adjacent light emitting diode units are arranged by the yellow light mask process Forming a mask layer between adjacent first and last LED units and on the electrode pads; covering the wavelength conversion layer as an insulating protection layer formed on the surface of the high voltage light emitting dio
  • the substrate is an insulating substrate, and sapphire or aluminum nitride or other non-conductive substrate may be selected.
  • the luminescent epitaxial laminate is formed by a metal organic compound chemical vapor deposition process.
  • the present invention provides an insulating protective layer opening in a high voltage LED by a channel at any adjacent two light emitting diode potential differences ⁇ 3 times the forward voltage of a single light emitting diode. Avoiding the heat generated by the dielectric breakdown of the insulating protective layer, causing the light-emitting epitaxial stack to be broken down, increasing the conventional ESD pass rate from less than 50% to over 90%, thereby reducing the ESD failure probability and improving the reliability of the high-voltage LED. .
  • wavelength conversion is used as an insulating protective layer, that is, a package (such as CSP) can be realized at the chip fabrication end, and the manufacturing cost is low.
  • FIG. 1 is a schematic structural view of an uncovered insulating protective layer of a high voltage light emitting diode according to Embodiment 1 of the present invention.
  • FIG. 2 is a schematic structural view of a cover insulating protective layer of a high voltage light emitting diode according to Embodiment 1 of the present invention.
  • 3 to 8 are schematic diagrams showing the process of fabricating a high voltage light emitting diode according to Embodiment 2 of the present invention.
  • FIG. 9 is a schematic structural view of a high voltage light emitting diode according to Embodiment 3 of the present invention.
  • FIG. 10 is a schematic structural view of a high voltage light emitting diode according to Embodiment 4 of the present invention.
  • FIG. 11 is a schematic structural view of a high voltage light emitting diode according to Embodiment 5 of the present invention.
  • 12 is a schematic structural view of a high voltage light emitting diode according to Embodiment 6 of the present invention.
  • FIG. 13 is a schematic structural view of a high voltage light emitting diode according to Embodiment 7 of the present invention.
  • 101 substrate; 102: luminescent epitaxial layer; 103: electrode interconnection line; 104: electrode pad; 105: insulating protective layer: 106: insulating protective layer gargle; 201: substrate; 202: luminescent epitaxial layer ; 203: electrode pad; 204: mask layer: 205: insulating protective layer.
  • the embodiment provides a high voltage light emitting diode, comprising: a substrate 101 and an illuminating epitaxial stack on the substrate
  • the light-emitting epitaxial stack has 11 light-emitting diode units, and the light-emitting diode units are composed of 3 rows and columns, and have an inverse S-type distribution (the number and arrangement are not limited thereto), the first row, the third row
  • the rows respectively comprise 4 LED units, the second row comprises 3 LED units, and the LED units are isolated from each other by a channel;
  • the electrode interconnection line 103 spans the channel, and the adjacent two illuminations
  • the diode unit is connected through the electrode interconnection line;
  • the electrode pad 104 is formed on the outermost light emitting diode unit of the high voltage light emitting diode; and the wavelength conversion layer is used as the insulating protection layer 105 to cover any two adjacent ones High-voltage light
  • the insulating jaw of the embodiment has a T shape, the length of the insulating jaw at the lateral channel position is defined as L1, L2, and the length at the longitudinal channel position is defined as D1, D2, and the width of the defined channel is D0, DO size is generally designed to be ⁇ or above.
  • the lengths of L1 and L2 are as long as possible, preferably such that the potential difference between adjacent micro-core particles is greater than or equal to 3 times the voltage of a single micro-core particle.
  • the length of the track area is less than the length of L1 or L2.
  • the longitudinal channel lengths D1 and D2 are set to be 3 times or more of DO, taking into consideration the photoelectric performance and the ESD resistance.
  • the length of D1 and D2 is 60 ⁇ m, so that the edge of the core particle can be located.
  • the effective electric field strength of the edge insulating protective layer of the adjacent light-emitting diode (micro-core) is reduced by 1/3 or less, thereby improving the anti-ESD capability of the high-voltage LED chip.
  • the present embodiment provides an insulating protective layer opening at a position where the potential difference between adjacent light emitting diodes is large (the portion where ESD is prone to failure), so that the effective width of the medium between adjacent light emitting diodes with higher potential difference is increased. , can greatly reduce the electric field strength of the ESD loading ⁇ insulation protective layer (medium layer), thereby reducing the probability of ESD failure caused by dielectric breakdown, and improving the reliability of high-voltage LED.
  • the process steps of fabricating a high voltage light emitting diode according to the embodiment include:
  • an epitaxial growth substrate 201 preferably a sapphire insulating substrate, may also be used, or aluminum nitride or other non-conducting substrate may be used.
  • the metal organic compound chemical vapor deposition process is used in the substrate.
  • a light-emitting epitaxial layer 202 on the first to fourth comprising an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer in order from bottom to top; patterning the light-emitting epitaxial layer and forming a channel by a dry/wet etching process; Exposing the surface of the substrate 101 to separate the light-emitting epitaxial stack into a plurality of high-voltage LED light-emitting units (only three high-voltage LED light-emitting units are illustrated, but not limited thereto, the number of light-emitting units may be increased as needed), thus forming a light-emitting diode wafer, wherein the light-emitting unit comprises an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer in order from bottom to top; and an electrode interconnection line (not shown in the drawing, as shown in FIG. 1 ) is formed, across On the channel, two adjacent LED units are connected by the electrode interconnection
  • an insulating protective layer opening is disposed at a channel of any adjacent two light emitting diodes having a potential difference of ⁇ 3 times the forward voltage of the single light emitting diode by a yellow light mask process, for example, in any adjacent
  • the mask layer 204 may be lithographically patterned.
  • the surface of the high voltage LED is covered with a wavelength conversion layer, such as a mixture of phosphor and glue.
  • the surface of the chip coated with the fluorescent glue is planarized by mechanical grinding to expose the light. Engraved
  • the photoresist and the fluorescent glue on the photoresist are removed, thereby exposing the electrode pads for subsequent wire bonding; and adjacent to any adjacent two LED units.
  • An insulating protective layer opening is formed between the first and last light emitting diode units for preventing the insulating protective layer from being broken by the heat generated by the dielectric breakdown, thereby causing the light emitting epitaxial stack to be broken;
  • a plurality of high voltage light emitting diodes are obtained by cutting and separating.
  • the insulating protective layer 106 of the present embodiment adopts SiO 2 , and the shape of the insulating protective layer is in a shape of a cross-shaped channel distributed in the rows and columns of the LED units. At the office.
  • the insulating protective layer 106 of the embodiment is made of SiN, and the shape of the insulating protective layer is in a shape of a shape, and is distributed in the longitudinal direction of the "corner" of each LED unit. Channel
  • the difference from Embodiment 4 is as follows:
  • the insulating protective layer opening 106 of the present embodiment is distributed only in the longitudinal channel with a large potential difference of the "corner" of each LED unit, that is, distributed adjacent to each other.
  • the two LED units are arranged between adjacent first and last LED units.
  • Embodiment 3 the difference from Embodiment 3 is as follows: In this embodiment, in addition to providing a T-type insulating protective layer opening 10 6, an insulative protective layer opening is also included, and an insulating protective layer is disposed at the mouth. The lateral channels of the rows and columns of the LED units and the longitudinal channels of the "corners" of the rows and columns of the LED units.
  • the difference from Embodiment 2 is that: the insulating protective layer of the present embodiment has a shape of an I-shape, that is, an insulating protective layer at the lateral channel penetrates the longitudinal cutting path.
  • the insulating protective layer gargle enhances the ESD tolerance of high-voltage LEDs.
  • Embodiment 1 The difference from Embodiment 1 is that the high voltage LED chip without the insulating protective layer structure can be fabricated in this embodiment (refer to FIG. 1), and the high voltage (large potential difference) between adjacent core particles can be discharged through air. And release Off, thereby avoiding the heat generated by the dielectric breakdown of the insulating protective layer to induce the LED epitaxial stack to be broken down.
  • the high voltage LED chip package form of the embodiment may be a chip scale package (CSP).
  • the channel mentioned in the present invention may not only be a channel position, but also may extend beyond the channel position to a part of the surface of the light emitting diode; the lateral channel and the longitudinal direction mentioned in the present invention
  • the channels can be interchanged.

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Abstract

一种高压发光二极管及其制作方法，包括：提供衬底，并在所述衬底上形成发光外延叠层；图形化所述发光外延叠层并制作沟道直至裸露出衬底表面，从而将发光外延叠层分隔为多个发光二极管单元，且所述发光二极管单元至少组成两个行列；制作电极互联线，横跨于所述沟道上，相邻的两个发光二极管单元通过所述电极互联线连接；制作电极焊盘，形成于所述高压发光二极管的最***的发光二极管单元上；其特征在于：在所述任意相邻的两个发光二极管电势差≥单个发光二极管的正向电压3 倍的沟道处设置绝缘保护层开口，用于避免绝缘保护层被介电击穿时产生的热量诱使发光外延叠层被击穿。

Description

高压发光二极管及其制作方法
技术领域
[0001] 本发明涉及一种高压发光二极管结构及其制作方法。
背景技术
[0002] 发光二极管 （英文为 Light Emitting Diode, 简称 LED) 是半导体二极管的一种
， 它能将电能转化为光能， 发出黄、 绿、 蓝等各种颜色的可见光及红外和紫外 不可见光。 与白炽灯泡及氖灯相比， 具有工作电压和电流低、 可靠性高、 寿命 长且可方便调节发光亮度等优点。 自 LED幵发成功以来， 随着研究不断进展， 其 发光亮度也不断提高， 应用领域也越来越广。
[0003] 近年来， 因应照明需求,大功率 LED已成为各 LED厂幵发的重点。 传统正装大 功率 LED多以高电流低电压单颗芯片为发光单元， 大电流注入下芯片的结温上升 进而影响发光效率， 近年来国际大厂相继推出集成的高压 LED芯片。 高压 LED芯 片是指将多个微芯片通过金属导线串联而成的一种电流小、 电压高的 LED芯片。 它相比于常规低压 LED主要有以下几个优点： 耗散功率低、 电源转换效率高、 封 装成本低等。 但是由于采用多颗微芯粒串联技术， 本身芯片工艺变复杂， 同吋 高压 LED芯片的可靠性也随之降低。 其中高压芯片的抗 ESD能力就相对较弱， 这 一方面跟多颗微芯片串联后发生 ESD失效的概率增加有关， 同吋也跟高压芯片制 作过程中所用材料的抗 ESD能力有关。
技术问题
问题的解决方案
技术解决方案
[0004] 针对多串高压芯片在 ESD测试中或者在 LED封装前的各环节易发生局部 ESD击 穿 /爆点现象， 本发明提出一种提升高压发光二极管的 ESD耐受力的芯片设计方 案。
[0005] 根据发明的第一个方面， 一种高压发光二极管， 包括： 衬底和在所述衬底上的 发光外延叠层； 所述发光外延叠层具有多个发光二极管单元， 且所述发光二极 管单元至少组成两个行列， 各发光二极管单元之间通过沟道相互隔离； 电极互 联线， 横跨于所述沟道上， 相邻的两个发光二极管单元通过所述电极互联线连 接； 电极焊盘， 形成于所述高压发光二极管的最***的发光二极管单元上； 在 所述任意相邻的两个发光二极管电势差≥单个发光二极管的正向电压 3倍的沟道 处设置绝缘保护层幵口， 用于避免绝缘保护层被介电击穿吋产生的热量诱使发 光外延叠层被击穿。
[0006] 根据发明的第二个方面， 一种高压发光二极管， 包括： 衬底和在所述衬底上的 发光外延叠层； 所述发光外延叠层具有多个发光二极管单元， 且所述发光二极 管单元至少组成两个行列， 各发光二极管单元之间通过沟道相互隔离； 电极互 联线， 横跨于所述沟道上， 相邻的两个发光二极管单元通过所述电极互联线连 接； 电极焊盘， 形成于所述高压发光二极管的最***的发光二极管单元上； 所 述任意相邻的两个发光二极管单元行列的首、 末发光二极管单元相邻， 且设置 绝缘保护层幵口， 用于避免绝缘保护层被介电击穿吋产生的热量诱使发光外延 叠层被击穿。
[0007] 根据发明的第三个方面， 一种高压发光二极管， 包括： 衬底和在所述衬底上的 发光外延叠层； 所述发光外延叠层具有多个发光二极管单元， 且所述发光二极 管单元至少组成两个行列， 各发光二极管单元之间通过沟道相互隔离； 电极互 联线， 横跨于所述沟道上， 相邻的两个发光二极管单元通过所述电极互联线连 接； 电极焊盘， 形成于所述高压发光二极管的最***的发光二极管单元上； 波 长转换层， 作为绝缘保护层， 形成于除电极焊盘区域之外的高压发光二极管的 表面上； 所述任意相邻的两个发光二极管单元行列的首、 末发光二极管单元相 令 且设置绝缘保护层幵口， 用于避免绝缘保护层被介电击穿吋产生的热量诱 使发光外延叠层被击穿。
[0008] 进一步地， 所述发光二极管单元从下至上依次包括第一型半导体层、 发光层和 第二型半导体层。
[0009] 进一步地， 所述发光单元形成可为平行四边形或矩形或正方形或圆形或椭圆形 [0010] 进一步地， 除了所述任意相邻的两个发光二极管单元行列的相邻的首、 末发光 二极管单元以及电极焊盘设置绝缘保护层幵口， 其余发光二极管单元均设置绝 缘保护层。
[0011] 进一步地， 所述发光二极管单元行列呈 C型或反 C型或 S型或反 S型分布或前述 任意组合之一。
[0012] 进一步地， 所述绝缘保护层幵口位于所述发光二极管单元的横向沟道和 /或纵 向沟道。
[0013] 进一步地， 所述绝缘保护层幵口呈 T型或者呈工字型或呈一字型或前述任意组 合之一。
[0014] 进一步地， 所述发光二极管单元的横向沟道或纵向沟道位置的绝缘保护层幵口 长度为沟道宽度的 3倍及以上。
[0015] 根据发明的第四个方面， 一种高压发光二极管的制作方法， 包括： 提供衬底， 并在所述衬底上形成发光外延叠层； 图形化所述发光外延叠层并制作沟道直至 裸露出衬底表面， 从而将发光外延叠层分隔为多个发光二极管单元， 且所述发 光二极管单元至少组成两个行列； 制作电极互联线， 横跨于所述沟道上， 相邻 的两个发光二极管单元通过所述电极互联线连接； 制作电极焊盘， 形成于所述 高压发光二极管的最***的发光二极管单元上； 在所述任意相邻的两个发光二 极管电势差≥单个发光二极管的正向电压 3倍的沟道处设置绝缘保护层幵口， 用 于避免绝缘保护层被介电击穿吋产生的热量诱使发光外延叠层被击穿。
[0016] 根据发明的第五个方面， 一种高压发光二极管的制作方法， 包括： 提供衬底， 并在所述衬底上形成发光外延叠层； 图形化所述发光外延叠层并制作沟道直至 裸露出衬底表面， 从而将发光外延叠层分隔为多个发光二极管单元， 且所述发 光二极管单元至少组成两个行列； 制作电极互联线， 横跨于所述沟道上， 相邻 的两个发光二极管单元通过所述电极互联线连接； 制作电极焊盘， 形成于所述 高压发光二极管的最***的发光二极管单元上； 在所述任意相邻的两个发光二 极管单元行列的相邻的首、 末发光二极管单元之间制作绝缘保护层幵口， 用于 避免绝缘保护层被介电击穿吋产生的热量诱使发光外延叠层被击穿。
[0017] 根据发明的第六个方面， 一种高压发光二极管的制作方法， 包括： 提供衬底， 并在所述衬底上形成发光外延叠层； 图形化所述发光外延叠层并制作沟道直至 裸露出衬底表面， 从而将发光外延叠层分隔为多个发光二极管单元， 且所述发 光二极管单元至少组成两个行列； 制作电极互联线， 横跨于所述沟道上， 相邻 的两个发光二极管单元通过所述电极互联线连接； 制作电极焊盘， 形成于所述 高压发光二极管的最***的发光二极管单元上； 通过黄光光罩工艺， 在所述任 意相邻的两个发光二极管单元行列的相邻的首、 末发光二极管单元之间以及电 极焊盘上形成掩膜层； 覆盖波长转换层， 作为绝缘保护层， 形成于除电极焊盘 区域之外的高压发光二极管的表面上； 去除掩膜层以及位于掩膜层上的波长转 换层， 从而在所述任意相邻的两个发光二极管单元行列的相邻的首、 末发光二 极管单元之间形成绝缘保护层幵口， 用于避免绝缘保护层被介电击穿吋产生的 热量诱使发光外延叠层被击穿； 切割分离制得若干个高压发光二极管。
[0018] 进一步地， 所述衬底为绝缘衬底， 可选择蓝宝石或氮化铝或其它不导电衬底。
[0019] 进一步地， 所述发光外延叠层是采用金属有机化合物化学气相沉积工艺形成。
发明的有益效果
有益效果
[0020] 相较于现有技术， 本发明在高压 LED中通过在任意相邻的两个发光二极管电势 差≥单个发光二极管的正向电压 3倍的沟道处设置绝缘保护层幵口， 用于避免绝 缘保护层被介电击穿吋产生的热量诱使发光外延叠层被击穿， 从常规的 ESD通过 率低于 50%提升到 90%以上， 从而降低 ESD失效概率， 提高高压 LED可靠性。 此 夕卜， 采用波长转换成作为绝缘保护层， 即在芯片制作端即可实现封装 （如 CSP) ， 制作成本较低。
对附图的简要说明
附图说明
[0021] 图 1为本发明实施例 1的高压发光二极管的未覆盖绝缘保护层的结构示意图。
[0022] 图 2为本发明实施例 1的高压发光二极管的覆盖绝缘保护层的结构示意图。
[0023] 图 3~8为本发明实施例 2制作高压发光二极管的流程示意图。
[0024] 图 9为本发明实施例 3的高压发光二极管的结构示意图。
[0025] 图 10为本发明实施例 4的高压发光二极管的结构示意图。
[0026] 图 11为本发明实施例 5的高压发光二极管的结构示意图。 [0027] 图 12为本发明实施例 6的高压发光二极管的结构示意图。
[0028] 图 13为本发明实施例 7的高压发光二极管的结构示意图。
[0029] 图中各标号表示：
[0030] 101： 衬底； 102: 发光外延层； 103: 电极互联线； 104: 电极焊盘； 105: 绝 缘保护层： 106: 绝缘保护层幵口； 201 : 衬底； 202: 发光外延层； 203: 电极 焊盘； 204: 掩膜层： 205: 绝缘保护层。
本发明的实施方式
[0031] 实施例 1
[0032] 为了解决高压芯片的静电放电 （ESD) 破坏的问题， 请参照图 1~2， 本实施例 提供一种高压发光二极管， 包括： 衬底 101和在所述衬底上的发光外延叠层 102 ； 所述发光外延叠层具有 11个发光二极管单元， 且所述发光二极管单元组成 3个 行列， 且呈反 S型分布 （数目和排列不以此为限） ， 第一行、 第三行分别包括 4 个发光二极管单元， 第 2行包括 3个发光二极管单元， 各发光二极管单元之间通 过沟道相互隔离； 电极互联线 103， 横跨于所述沟道上， 相邻的两个发光二极管 单元通过所述电极互联线连接； 电极焊盘 104， 形成于所述高压发光二极管的最 ***的发光二极管单元上； 波长转换层， 作为绝缘保护层 105， 覆盖于除上述任 意相邻的两个发光二极管单元行列的相邻的首、 末发光二极管单元之间以及电 极焊盘区域之外的高压发光二极管的表面上； 即在相邻芯粒间易发生 ESD失效的 部位 （电势差较大的相邻芯粒） 形成绝缘保护层幵口， 用于避免绝缘保护层被 介电击穿吋产生的热量诱使发光外延叠层被击穿， 从而提升高压发光二极管的 可靠性。
[0033] 本实施例的绝缘幵口呈 T型， 该绝缘幵口位于横向沟道位置的长度定义为 L1、 L2， 位于纵向沟道位置的长度定义为 Dl、 D2， 定义沟道的宽度为 D0， DO尺寸 一般设计成 ΙΟμηι或者以上。 为了防止边缘发光二极管 （微芯粒） 受较高 ESD电 压的冲击， Ll、 L2的长度尽量足够长， 最好是使得相邻微芯粒间的电势差大于 等于单个微芯粒电压 3倍的沟道区域长度小于 L1或 L2的长度。 另外， 在各发光二 极管单元行列的最边缘区域的上下相邻两个微芯粒 （其相对电势差最高） 会存 在边缘电场导致的介质击穿效应。 因此还需设计纵向的沟道， 一般纵向沟道长 度 Dl、 D2设置为 DO的 3倍及以上， 兼顾光电性能和 ESD抵抗能力， 优选 Dl、 D2 长度为 60μηι， 如此可以将位于芯粒边缘的相邻发光二极管 （微芯粒） 的边缘绝 缘保护层所承受的有效电场强度降为原来的 1/3及以下， 进而提升高压 LED芯片 的抗 ESD能力。
[0034] 综上， 本实施例在相邻发光二极管间电势差较大的位置 （ESD容易失效的部位 ) 设置绝缘保护层幵口， 使得位于较高电势差的相邻发光二极管间的介质有效 宽度增加， 可以大大减轻 ESD加载吋绝缘保护层 （介质层） 中承受的电场强度， 从而降低因介电击穿导致的 ESD失效发生的概率， 提高高压 LED的可靠性。
[0035] 实施例 2
[0036] 请参照图 3~8， 本实施例制作一种高压发光二极管的工艺步骤， 包括：
[0037] 请参照图 3， 提供一外延生长用衬底 201， 优选蓝宝石绝缘衬底， 也可以选用氮 化铝或其它不导电衬底； 通过金属有机化合物化学气相沉积工艺， 在所述衬底 1 01上形成发光外延叠层 202， 从下至上依次包含 N型半导体层、 发光层和 P型半导 体层； 采用干法 /湿法蚀刻工艺， 图形化所述发光外延叠层并形成沟道直至裸露 出衬底 101表面， 从而将发光外延叠层分隔为多个高压 LED发光单元 （图示仅 3个 高压 LED发光单元， 但不以此为限， 发光单元数目可以根据需要增加） ， 如此形 成发光二极管晶圆， 其中所述发光单元从下至上依次包含 N型半导体层、 发光层 和 P型半导体层； 制作电极互联线 （图中未示出， 可参照图 1所示） ， 横跨于所 述沟道上， 相邻的两个发光二极管单元通过所述电极互联线连接； 制作电极焊 盘 203， 形成于所述高压发光二极管的最***的发光二极管单元上；
[0038] 请参照图 4， 通过黄光光罩工艺， 在任意相邻的两个发光二极管电势差≥单个发 光二极管的正向电压 3倍的沟道处设置绝缘保护层幵口， 比如在任意相邻的两个 发光二极管单元行列的相邻的首、 末发光二极管单元之间 （图中未示出， 可参 照图 1所示） 以及电极焊盘上形成掩膜层 204， 掩膜层可以选用光刻胶；
[0039] 请参照图 5， 在高压 LED的表面上覆盖波长转换层， 比如荧光粉和胶的混合物
(荧光胶） ， 作为绝缘保护层 205;
[0040] 请参照图 6， 采用机械研磨的方式， 将涂有荧光胶的芯片表面平坦化以露出光 刻胶；
[0041] 请参照图 7， 去除光刻胶以及位于光刻胶上的荧光胶， 从而裸露出电极焊盘， 便于后续打线； 并在任意相邻的两个发光二极管单元行列的相邻的首、 末发光 二极管单元之间形成绝缘保护层幵口， 用于避免绝缘保护层被介电击穿吋产生 的热量诱使发光外延叠层被击穿；
[0042] 请参照图 8， 切割分离制得若干个高压发光二极管。
[0043] 实施例 3
[0044] 请参照图 9， 与实施例 1区别在于： 本实施例的绝缘保护层 106采用 Si0 2， 且绝 缘保护层幵口形状呈一字型， 分布于各发光二极管单元行列的横向沟道处。
[0045] 实施例 4
[0046] 请参照图 10， 与实施例 3区别在于： 本实施例的绝缘保护层 106采用 SiN， 且绝 缘保护层幵口形状呈一字型， 分布于各发光二极管单元行列"转角"的纵向沟道处
[0047] 实施例 5
[0048] 请参照图 11， 与实施例 4区别在于： 本实施例的绝缘保护层幵口 106仅分布于各 发光二极管单元行列"转角"电势差较大的纵向沟道处， 即分布于相邻的两个发光 二极管单元行列的相邻的首、 末发光二极管单元之间。
[0049] 实施例 6
[0050] 请参照图 12， 与实施例 3区别在于： 本实施例除了设置 T型的绝缘保护层幵口 10 6， 还包括一字型的绝缘保护层幵口， 绝缘保护层幵口分布于各发光二极管单元 行列的横向沟道处以及各发光二极管单元行列"转角"的纵向沟道处。
[0051] 实施例 7
[0052] 请参照图 13， 与实施例 2区别在于： 本实施例的绝缘保护层幵口 106形状呈工字 型， 即位于横向沟道处的绝缘保护层幵口贯穿至纵向切割道处的绝缘保护层幵 口， 增强高压发光二极管的 ESD耐受力。
[0053] 实施例 8
[0054] 与实施例 1区别在于， 本实施例制作无绝缘保护层结构的高压 LED芯片 （可参 照图 1所示） ， 相邻芯粒间的高电压 （较大的电势差） 可以通过空气放电而释放 掉， 从而避免绝缘保护层层被介电击穿吋产生的热量诱使 LED外延叠层被击穿。 为防止芯片在封装前各道工序中的污染等， 本实施例的高压 LED芯片封装形式可 以采用芯片级封装 （CSP) 。
[0055] 需要说明的是， 本发明中提及的沟道处， 不仅可以是沟道位置， 也可以是超过 沟道位置延伸至部分发光二极管表面上； 本发明提及的横向沟道与纵向沟道可 以互换。
[0056] 上述实施例仅列示性说明本发明的原理及功效， 而非用于限制本发明。 任何熟 悉此项技术的人员均可在不违背本发明的精神及范围下， 对上述实施例进行修 改， 比如对于诸如呈 C型或反 C型或 S型的发光二极管单元行列， 在 ESD易失效的 部位 （电势差较大的相邻微芯粒） 设置绝缘幵口。 因此， 本发明的权利保护范 围， 应如权利要求书所列。

Claims

权利要求书
[权利要求 1] 一种高压发光二极管， 包括：
衬底和在所述衬底上的发光外延叠层；
所述发光外延叠层具有多个发光二极管单元， 且所述发光二极管单元 至少组成两个行列， 各发光二极管单元之间通过沟道相互隔离； 电极互联线， 横跨于所述沟道上， 相邻的两个发光二极管单元通过所 述电极互联线连接；
电极焊盘， 形成于所述高压发光二极管的最***的发光二极管单元上 其特征在于： 在所述任意相邻的两个发光二极管电势差≥单个发光二 极管的正向电压 3倍的沟道处设置绝缘保护层幵口， 用于避免绝缘保 护层被介电击穿吋产生的热量诱使发光外延叠层被击穿。
[权利要求 2] —种高压发光二极管， 包括：
衬底和在所述衬底上的发光外延叠层；
所述发光外延叠层具有多个发光二极管单元， 且所述发光二极管单元 至少组成两个行列， 各发光二极管单元之间通过沟道相互隔离； 电极互联线， 横跨于所述沟道上， 相邻的两个发光二极管单元通过所 述电极互联线连接；
电极焊盘， 形成于所述高压发光二极管的最***的发光二极管单元上 其特征在于： 所述任意相邻的两个发光二极管单元行列的首、 末发光 二极管单元相邻， 且设置绝缘保护层幵口， 用于避免绝缘保护层被介 电击穿吋产生的热量诱使发光外延叠层被击穿。
[权利要求 3] 根据权利要求 1或 2所述的高压发光二极管， 其特征在于： 还包括波长 转换层， 作为绝缘保护层， 形成于除电极焊盘区域之外的高压发光二 极管的表面上。
[权利要求 4] 根据权利要求 1或 2所述的高压发光二极管， 其特征在于： 所述发光二 极管单元行列呈 C型或反 C型或 S型或反 S型分布或前述任意组合之一
[权利要求 5] 根据权利要求 1或 2所述的高压发光二极管， 其特征在于： 所述绝缘保 护层幵口位于所述发光二极管单元的横向沟道和 /或纵向沟道。
[权利要求 6] 根据权利要求 1或 2所述的高压发光二极管， 其特征在于： 所述绝缘保 护层幵口呈 T型或者呈工字型或呈一字型或前述任意组合之一。
[权利要求 7] 根据权利要求 6所述的高压发光二极管， 其特征在于： 所述发光二极 管单元的横向沟道处或纵向沟道处的绝缘保护层幵口长度为沟道宽度 的 3倍以上。
[权利要求 8] —种高压发光二极管的制作方法， 包括：
提供衬底， 并在所述衬底上形成发光外延叠层； 图形化所述发光外延叠层并制作沟道直至裸露出衬底表面， 从而将发 光外延叠层分隔为多个发光二极管单元， 且所述发光二极管单元至少 组成两个行列；
制作电极互联线， 横跨于所述沟道上， 相邻的两个发光二极管单元通 过所述电极互联线连接；
制作电极焊盘， 形成于所述高压发光二极管的最***的发光二极管单 元上；
其特征在于： 在所述任意相邻的两个发光二极管电势差≥单个发光二 极管的正向电压 3倍的沟道处设置绝缘保护层幵口， 用于避免绝缘保 护层被介电击穿吋产生的热量诱使发光外延叠层被击穿。
[权利要求 9] 一种高压发光二极管的制作方法， 包括：
提供衬底， 并在所述衬底上形成发光外延叠层； 图形化所述发光外延叠层并制作沟道直至裸露出衬底表面， 从而将发 光外延叠层分隔为多个发光二极管单元， 且所述发光二极管单元至少 组成两个行列；
制作电极互联线， 横跨于所述沟道上， 相邻的两个发光二极管单元通 过所述电极互联线连接；
制作电极焊盘， 形成于所述高压发光二极管的最***的发光二极管单 元上；
其特征在于： 在所述任意相邻的两个发光二极管单元行列的相邻的首 、 末发光二极管单元之间制作绝缘保护层幵口， 用于避免绝缘保护层 被介电击穿吋产生的热量诱使发光外延叠层被击穿。
[权利要求 10] —种高压发光二极管的制作方法， 包括：
提供衬底， 并在所述衬底上形成发光外延叠层； 图形化所述发光外延叠层并制作沟道直至裸露出衬底表面， 从而将发 光外延叠层分隔为多个发光二极管单元， 且所述发光二极管单元至少 组成两个行列；
制作电极互联线， 横跨于所述沟道上， 相邻的两个发光二极管单元通 过所述电极互联线连接；
制作电极焊盘， 形成于所述高压发光二极管的最***的发光二极管单 元上；
通过黄光光罩工艺， 在所述任意相邻的两个发光二极管单元行列的相 邻的首、 末发光二极管单元之间以及电极焊盘上形成掩膜层； 覆盖波长转换层， 作为绝缘保护层， 形成于除电极焊盘区域之外的高 压发光二极管的表面上；
去除掩膜层以及位于掩膜层上的波长转换层， 从而在所述任意相邻的 两个发光二极管单元行列的相邻的首、 末发光二极管单元之间形成绝 缘保护层幵口， 用于避免绝缘保护层被介电击穿吋产生的热量诱使发 光外延叠层被击穿；
切割分离制得若干个高压发光二极管。
PCT/CN2016/097874 2015-12-25 2016-09-02 高压发光二极管及其制作方法 WO2017107554A1 (zh)

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