WO2017102834A1

WO2017102834A1 - Process for copper metallization and process for forming a cobalt or a nickel silicide

Info

Publication number: WO2017102834A1
Application number: PCT/EP2016/080985
Authority: WO
Inventors: Vincent Mevellec; Dominique Suhr
Original assignee: Aveni
Priority date: 2015-12-17
Filing date: 2016-12-14
Publication date: 2017-06-22
Also published as: FR3045674B1; TW201727829A; FR3045674A1; TWI633627B

Abstract

A subject-matter of the invention is a process for metallization with copper which uses a specific silicide for increasing the adhesion of the copper deposit on a semiconductor substrate. In a microelectronics application, this process exhibits the advantage of being able to be employed in the manufacture of integrated circuits in three dimensions by the "via-last" technique. This is because this technique is temperature-limited. In a photovoltaic application, the process of the invention makes it possible to produce a silicide/nickel stack in one step with a lower thermal budget. The process of the invention comprises a step consisting in applying a rapid heat treatment to a substrate covered with nickel, so as to form, between the nickel layer and the silicon layer, an interposed layer which constitutes a promoter of adhesion between the substrate and the copper and which comprises a silicide of Si M stoichiometry, M representing nickel, said silicide being formed by diffusion of a portion of the nickel into the silicon so as to leave a layer of residual nickel at the surface, the heat treatment being carried out at a temperature of less than 350°C and for a period of time of less than 30 minutes.

Description

Process for copper metallization and process for forming a cobalt or a nickel silicide The present invention relates generally to the manufacture of semiconductor electronic devices and more particularly to the creation of copper conducting lines and of through silicon vias in a silicon or silicon dioxide substrate, for connecting the components of an integrated circuit or for conducting electricity in a photovoltaic cell.

The metallization process of the invention consists in forming copper in structures hollowed out beforehand in a silicon dioxide substrate or in a silicon substrate covered with a silicon layer dioxide. The step of metallization with copper is preceded by another metallization step which consists in forming a metal or a metal alloy, the function of which is to form a barrier to the diffusion of the copper atoms during the functioning of the device. This intermediate metal layer has to meet three criteria: to exhibit a sufficient conductivity in the case where it is desired to deposit the copper by an electrolytic method, on the one hand, to have an even thickness and to guarantee good adhesion with the silicon dioxide, on the other hand.

In structures of complex shapes which define a nonplanar topography, such as through silicon vias and trenches, attempts are being made to improve the adhesion between the silicon oxide (which acts as electrical insulator) and the copper. In addition, the metallization process has to result in metal layers having a very even thickness (reference is made to high conformity). These two requirements become increasingly more difficult to achieve as the aspect ratio of the structures becomes increasingly high.

The inventors have thus attempted to solve this problem and they have found that dinickel silicide SiNi₂ and dicobalt silicide SiCo₂ are excellent promoters of adhesion between silicon dioxide and copper and between silicon and copper. They have also proved that this is not the case with nickel monosilicide SiNi.

Metal silicides have been used for a long time in the manufacture of integrated circuits in order to reduce the contact resistances between the transistors and the first metal interconnection levels, which are generally made of tungsten. Only the interconnections located in the final levels of the integrated circuit are made of copper.

Nickel monosilicide (SiNi) has replaced cobalt disilicide (Si₂Co), the resistance of which has become too high to connect transistors having gates with smaller sizes (65 nm node).

The silicide SiNi is generally formed in two steps: the deposition of a nickel and platinum alloy, a first heat treatment to form SiNi₂ and a second heat treatment to convert the SiNi₂ into SiNi. For example, in Patent US 6 406 743, nickel silicide SiNi is used as conductor material in a VLSI semiconductor device. The document provides a process for the manufacturing of nickel silicide by deposition of nickel on silicon, followed by heat treatment. This process comprises activation of the polycrystalline silicon surface with a palladium chloride salt in solution in hydrofluoric acid and acetic acid at ambient temperature for approximately ten seconds. After this activation step, a layer of nickel with a thickness of 180 - 220 nm is deposited by the electroless route, for example with a solution of nickel sulphate and of dimethylamine borane in the presence of nickel-complexing agents, such as lactic acid and citric acid. Nickel silicide is formed by bringing the nickel to high temperature (650°C) so as to cause it to migrate into the silicon. The nickel which has not migrated is then removed with a chemical etching solution, before being covered with tungsten.

The document US 6 566 254 describes a process for manufacturing MOS transistors employing a mixture of CoSi and of CoSi₂ which is formed in situ by a two- step heat treatment: a first treatment carried out between 450 and 550°C and then a second between 700 and 800°C.

In the majority of the processes for the manufacture of semiconductors or of photovoltaic cells of the prior art, the stacks of silicon, of silicide and of nickel necessarily have to be manufactured in several steps: deposition of nickel on the silicon, heat treatment to generate the nickel silicide, removal of the nickel remaining at the surface of the silicide which has not migrated into the silicon, cleaning of the surface of the silicide and then deposition of a new layer of nickel. This is because, in the current processes, the interface, obtained on conclusion of the heat treatment step between the silicide formed and the residual nickel which has not migrated - is of very poor quality responsible for mediocre adhesion. The only means of obtaining a good adhesion thus consists in removing the residual nickel in order to redeposit a fresh layer of nickel which is adherent to the silicide.

The inventors have found, surprisingly, a novel means of guaranteeing and even of improving the adhesion of copper to a silicon dioxide substrate by interposing a specific material which had never been used previously in this application.

The inventors have also found a process for the manufacture of stacks of silicon, of silicide and of nickel in a reduced number of steps which does not require the deposition of a fresh layer of nickel after the formation of the nickel silicide.

Recently, nickel monosilicide has been introduced into the manufacture of photovoltaic cells. This is because, on replacing silver with copper, attempts are made to produce electrical contact points of very high conductivity. In these devices, as in transistors, nickel monosilicide is used for the preparation of contacts, due to its good conductivity. Nickel monosilicide is preferred to dinickel silicide as it exhibits a greater conductivity. After deposition of the nickel on silicon by a nonelectrolytic process, a nickel monosilicide interface is formed between the nickel and the silicon by a high temperature heat treatment. During this heat treatment - at a temperature generally of the order of 400 to 750°C - the nickel migrates into the silicon substrate to form a nickel silicide SiNi in which the stoichiometric ratio is 1:1. The residual nickel which has not been converted into nickel silicide is subsequently stripped. A fresh deposition of nickel on the silicide can sometimes be carried out and act as base for the deposition of copper.

However, this process represents several disadvantages: it requires a high thermal budget and requires two steps in order to produce a nickel silicide/nickel stack of good adhesion.

In point of fact, the inventors have found, contrary to the approach followed to date, that the lower conductivity of the dinickel silicide is largely compensated for by that of the copper in the applications targeted by the present invention and that it is possible to produce the nickel/nickel silicide stack in a single step, all this while decreasing the heat treatment temperature while remaining within periods of time compatible with an industrial process.

This is because the inventors have found a means of producing a nickel/silicide stack in a reduced number of steps, whereas numerous steps are required in the prior art. This is because, by activation of the surface of the silicon with metal particles, it is possible to cause the nickel to migrate evenly at low temperature and very rapidly, with the result that the heat treatment can be interrupted before all the nickel is converted into nickel silicide, while obtaining a nickel layer of good quality and a stack of good adhesion.

The invention is particularly advantageous in processes for the manufacture of three-dimensional integrated circuit structures which cannot be exposed to temperatures of greater than 350°C and even greater than 300°C, which would risk weakening the interfaces between the different levels assembled by bonding. In point of fact, due to this limit in temperature, it has not been possible to date to produce copper deposits of good adhesion, in particular when the through silicon vias are manufactured according to the via-last method.

DESCRIPTION OF THE INVENTION

A first subject-matter of the invention is thus a process for forming a silicide on a substrate, which process comprising a step of providing a substrate that is covered with a silicon oxide layer having an exposed silicon dioxide surface, and the steps of: i- forming gold particles or palladium particles on said exposed silicon surface, in order to obtain an activated silicon surface,

ii- forming, on the activated silicon surface, a metal or metal alloy in the form of a layer, said metal being chosen from the group consisting of nickel and cobalt and said metal alloy being chosen from the group consisting of nickel alloys and cobalt alloys, and obtaining an assembly of stacks,

iii- applying a rapid heat treatment to the assembly of stacks obtained in step ii), so as to form, between a) the metal layer or the metal alloy layer and b) the silicon layer, an interposed layer that is in contact with the silicon layer and which predominantly comprises a SiM₂ silicide, M representing nickel or cobalt, said SiM₂ silicide being formed by diffusion of the metal or the metal alloy into the silicon layer, so as to leave, into contact with said silicon layer, a residual part of the metal layer or the residual metal alloy layer having an exposed surface, wherein the rapid heat treatment is carried out at a rapid heat treatment temperature being less than or equal to 350°C.

According to this process, the interposed SiM₂ silicide layer constitutes a promoter for copper adhesion, and advantageously comes into contact with the activated silicon surface.

For example, the process of the invention comprises forming a silicide SiNi₂ or a silicide SiCo₂ material layer that is in contact with the activated silicon surface. Indeed, the here above conditions, such as forming an activated silicon surface and applying a lower rapid heat temperature than expected, advantageously allow formation a SiM₂silicide that comes into direct contact with the silicon material. This is not the case of prior art method of forming silicides.

Known methods of forming a silicide between a silicon substrate and a nickel or cobalt layer use similar heat temperatures, but do not form significant amounts of SiM₂ silicide. More in detail, such prior art methods result in forming significant amounts of SiM silicide between the silicon substrate and the metal M instead. It is true that SiM₂ silicide may formed between the SiM silicon layer and the metal layer, in some of these methods. However, SiM₂ silicide is formed in very low amounts, and is never in contact with the silicon layer.

According to the process of the invention, no significant amount and preferably no SiM silicide is formed at the interface between the silicon layer and the metal M layer. Without being bound by any theory, it is believed that gold or palladium activation of the silicon surface allows for the easier diffusion of the metal into the silicon and entire formation of SiM₂ silicide.

The present invention is about improving low adhesion of SiM silicide on silicon. SiM formation in contact with the silicon substrate is not desirable. According to the process of the invention, the heat treatment step is carried out under conditions which make it possible to obtain a first value of adhesion between the substrate and the copper of greater than or equal to a second adhesion value which is obtained by employing the same process but carried out with a heat treatment temperature of greater than or equal to 350°C in the case of nickel and of greater than or equal to 400°C in the case of cobalt, when the two adhesion values are measured according to the same method and under the same conditions. The methods for the measurement of adhesion are known to a person skilled in the art.

In a specific embodiment, the thickness of the metal layer or metal alloy that is deposited in step ii) is between 10 and 150 nm.

Subsequently, under the action of the heat during step iii), the metal migrates into the silicon. The heat treatment is interrupted before all the amount of the metal deposit has migrated into the silicon and before all the metal is converted into silicide of SiM₂ stoichiometry, M representing nickel or cobalt. Thus, the temperature, the duration, or both the temperature and the duration, applied during the heat treatment are chosen so that the thickness of the residual metal layer preferably ranges from 5 to 100 nm and/or that the thickness of the interposed silicide layer formed under the effect of the heat comprising a silicide of SiM₂ stoichiometry, M representing nickel or cobalt, ranges from 10 to 200 nm, for example from 10 to 50 nm.

For example, the thickness of the residual metal layer preferably lies between two values that are selected in the group consisting of 5 nm, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm and 100 nm and the thickness of the interposed silicide layer a silicide of SiM₂ stoichiometry lies between two values that are selected in the group consisting of 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 100 nm, 120 nm, 140 nm, 160 nm, 180 nm and 200 nm.

Depending on the nature of the metal, according to whether it is composed of nickel, of a nickel alloy, of cobalt or of a cobalt alloy, the temperature will be adjusted so as to form a silicide of SiM₂ stoichiometry, M representing nickel or cobalt, in an amount sufficient to ensure the promotion of the adhesion between the silicon and the copper.

In the context of the invention, the silicide of SiM₂ stoichiometry is used as promoter of adhesion between silicon and copper, and makes it possible in particular to obtain a much greater level of adhesion than that which would be obtained with another silicide, such as a monosilicide of SiM stoichiometry. The inventors have given evidence for the fact that replacing an interposed SiM₂ layer with an interposed SiM layer, in the same structure, makes the adhesion falls from 16/16 to 0/16 according to Standard ASTM 3359.

The temperature and/or the duration of the heat treatment at step iii) can be chosen so that the adhesion of the copper to the substrate, measured by Standard ASTM 3359, is between 5/16 and 16/16, preferably between 10/16 and 16/16, more preferably between 12/16 and 16/16, preferably equal to 16/16.

In a specific embodiment, the metal alloy is a nickel alloy with an element chosen from the group consisting of boron, tungsten and phosphorus. The metal can also be a cobalt alloy with an element chosen from the group consisting of boron, tungsten and phosphorus. In these metal alloys, the element can represent between 0.1 and 10% by weight of the metal alloy.

For example, the metal is a cobalt alloy and of boron (for example approximately 5 atom% of boron), the heat treatment temperature is between 250 and 350°C, preferably equal to 300°C, and the duration of treatment is less than 30 minutes, for example about 10 minutes.

In another example, the metal is a nickel alloy comprising boron (for example approximately 6% by weight or 35 atom% of boron), the heat treatment temperature is between 200 and 300°C, preferably equal to 250°C, and the duration of treatment is less than 30 minutes, for example about 10 minutes.

The atmosphere into which the substrate is immersed is preferably a reducing atmosphere (for example an N₂ + H₂ (4% of H₂) mixture), under standard pressure conditions.

The silicon may be doped or undoped and be chosen from polysilicon, amorphous silicon and crystalline silicon. In a specific example, the metal is deposited on polysilicon.

Step Π

The activation of the surface of the silicon layer with metal particles of gold (Au(0)) or of palladium (Pd(0)) can be carried out in several ways.

One of these ways consists in bringing the surface of the silicon layer into contact with an aqueous solution containing metal ions of gold or of palladium, and fluorine ions.

In the present patent application, the expressions "ranging from ... to ..." and "containing from ... to ..." denote ranges of values comprising the limits. The expression "between ... and ..." excludes the limits of the range of values.

The aqueous solution preferably contains from 0.6 M to 3.0 M of fluorine ions, preferably from 1.0 to 2.0 M and more preferably from 1.4 to 1.6 M of fluorine ions.

The fluorine ions can be contributed by hydrofluoric acid (HF), by NH₄F or by an NH₄F/HF mixture.

The aqueous solution preferably contains from 0.6 M to 3.0 M of hydrofluoric acid (HF) preferably from 1.0 M to 2.0 M and more preferably from 1.4 M to 1.6 M of hydrofluoric acid (HF). The aqueous solution preferably contains from 0.1 mM to 10 mM of metal ions, preferably from 0.1 mM to 5.0 mM and more preferably from 0.5 mM to 1.0 mM of metal ions. The concentration of metal ions is, for example, between 0.65 mM and 0.75 mM.

The gold ions can be contributed by a gold salt chosen from gold(I) and gold(III) salts, such as gold(I) chlorides, gold(III) chlorides or gold(III) bromide.

For example, chloroauric acid (HAuCI₄) is chosen. The solution can contain complexing agents for gold ions, such as aromatic amines, for example a bipyridine, a terpyridine or phenanthroline.

The palladium ions can be contributed in the form of palladium salts or in the form of a palladate complex, for example diammonium tetrachloropalladate(II).

The aqueous solution preferably contains from 0.1 mM to 10 mM of metal ions, preferably from 0.1 to 5.0 mM and more preferably from 0.5 to 1.0 mM of metal ions. The concentration of metal ions is, for example, between 0.65 and 0.75 mM.

According to a preferred embodiment, the aqueous solution contains:

- from 0.1 mM to 10 mM, preferably from 0.5 mM to 1.0 mM, of metal ions, and

- from 0.6 M to 3.0 M, preferably from 1.0 M to 2.0 M, of fluorine ions.

The aqueous solution can contain organic or inorganic acid compounds, whether they are strong or weak, so as to vary the rate of attack on the silicon, in particular to increase it or to decrease it. In one embodiment, the aqueous solution is devoid of acetic acid CH₃COOH.

The solution can additionally contain a surface-active agent. The surface- active agent can be chosen from the compounds comprising at least one anionic or non-ionic polar group and an alkyl chain comprising at least 10 carbon atoms, for example from 10 to 16 carbon atoms, preferably from 10 to 14 carbon atoms. The alkyl chain is preferably linear. It advantageously comprises 12 carbon atoms (also known as dodecyl).

This specific surfactant makes it possible to stabilize the metal particles formed after an oxidation-reduction reaction with the silicon. It also makes it possible to increase their number and to further disperse them at the surface of the silicon. By adding this surfactant to the activation bath, the size of the metal particles can be reduced while increasing their density.

This distribution of the metal particles makes it possible to deposit layers of nickel and then of nickel silicide, which are very thin and continuous at the same time, which the processes of the prior art, for which it is necessary to deposit thicker layers of nickel in order to guarantee an even deposit over the entire surface of the silicon, do not make possible. The thickness of the nickel layer can advantageously be less than 150 nm. An anionic surface-active agent having a molecular weight of between 100 g/mol and 1500 g/mol is preferred.

The polar group can be a non-ionic group, preferably a polyoxyalkylene glycol group, for example a polyoxyethylene glycol or polyoxypropylene glycol group. In this embodiment, the surface-active agent can be chosen from polyoxyalkylene glycol alkyl ethers, preferably the polyoxyalkylene glycol alkyl ethers comprising an alkyl chain having from 10 to 16 carbon atoms, such as, for example, polyoxyethylene glycol dodecyl ethers.

The polar group can be an anionic group, such as a sulphonate (-S0₃ ^"), a sulphate (-OS0₃ ^"), or a carboxylate (-COO^"). A sulphate is preferred in the context of the invention. The surface-active agent is preferably an alkyl sulphate of formula R-OS0₃ ^" in which R is a linear alkyl group having from 10 to 14 carbon atoms, preferably 12 carbon atoms. The surface-active agent can, for example, be sodium dodecyl sulphate.

The surface-active agent preferably represents from 0.1 to 5% by weight, for example from 2.5 to 3.5% by weight, of the solution.

According to a preferred embodiment, the aqueous solution contains from 0.5 mM to 1 mM of chloroauric acid (HAuCI₄), from 1.0 to 2.0 M of hydrofluoric acid (HF) and optionally from 2.5 to 3.5% by weight of sodium dodecyl sulphate, with respect to the weight of the composition.

Preferably, this step of activation of the silicon substrate by deposition of metal grains at its surface is carried out at a temperature of between 15 and 30°C and more preferably at a temperature of between 20 and 25°C.

The duration of contact between the aqueous solution and the silicon substrate is generally of the order of 5 seconds to 5 minutes, preferably of 10 seconds to 2 minutes and more preferably between 20 and 40 seconds. The duration of activation will be chosen as a function of the size and of the number of metal grains which it is desired to form at the surface of the silicon substrate. A size of grains of the order of 5 to 15 nm, preferably of the order of 10 nm, will advantageously be chosen.

The operation in which the surface of the substrate is brought into contact with the activation solution is advantageously carried out by immersion of the substrate in the activation solution, optionally with stirring.

The substrate thus treated is advantageously copiously rinsed with deionized water and dried under a stream of nitrogen, in order to remove any trace of activation solution.

Step ih

The second step of the process of the invention consists in forming, on the substrate covered with gold particles or palladium particles, a layer formed essentially of nickel or of cobalt. Essentially it is understood to mean more than 90% by weight, it being possible for the other elements to be boron, phosphorus or tungsten.

The layer formed essentially of nickel or of cobalt is advantageously uniform when it covers a flat surface and conformable when it covers three-dimensional structures which have been hollowed out in the silicon (example of the TSV vias and interconnections).

The uniformity within the meaning of the invention is equal to the variation in the thickness of the layer formed essentially of nickel or of cobalt on the covered surface. The uniformity of the layer formed essentially of nickel or of cobalt obtained according to the process of the invention is advantageously less than 10%, preferably less than 5% and more preferably less than 1%.

The conformality within the meaning of the invention is equal to the ratio of the thickness of the layer at the top to the thickness of the layer at the bottom of a structure. The conformality within the meaning of the invention can also be equal to the variation in the thickness of the layer over the assembly consisting of the top, the side walls and the bottom of the structure.

The conformality of the layer formed essentially of nickel or of cobalt obtained according to the process of the invention is advantageously between 90 and 110%, preferably greater than 95%, more preferably greater than 99%.

The trenches are generally etched into the silicon and then metallized down to the desired depth before thinning the silicon wafer. The shape and the size of the trenches can vary as a function of the use of the device. The trenches are commonly characterized by their depth, their diameter at the opening and their aspect ratio defining the ratio of the depth to the diameter of the cavity. For example, a trench with an aspect ratio of 10: 1 has a diameter ten times smaller in size than its depth.

The layer formed essentially of nickel or of cobalt is advantageously conformable when it covers the surface of very deep structures: the coverage ratio of the top to the bottom of the structure is advantageously between 90 and 110% when the layer covers trenches exhibiting high aspect ratios, in particular greater than 5: 1, preferably of greater than 10:1.

The aspect ratio - expressed as the ratio of the depth to the opening diameter of the cavities - can vary from 5: 1 to 1000:1, in particular in the case of a NAND memory device, the surface of which consists of an alternation of layers of polycrystalline silicon and of Si0₂. The process according to the invention advantageously makes it possible to deposit a layer of metallic nickel in cavities exhibiting particularly high aspect ratios, for example of greater than 10:1 and above. The aspect ratio of the trenches can advantageously be very high and be between 10: 1 and 1000: 1, for example between 50:1 and 500: 1 or between 100:1 and 200:1. The process of the invention makes it possible to cover the surface cavities having a diameter at their opening ranging from 10 to 100 nm and a depth ranging from 500 nm to 10 microns with a layer formed essentially of nickel or of cobalt having a thickness of between 10 and 150 nm, the conformality of which is greater than 90%, preferably greater than 95%, more preferably greater than 99%.

The metal deposit can be produced by a nonelectrochemical process which does not require the electrical polarization of the substrate.

Use may be made of a dry route (vapour phase) process or a wet route (with an aqueous solution) process.

The metal deposit can be nickel, cobalt, a nickel-boron (NiB) alloy, a cobalt- boron (CoB) alloy, a nickel-phosphorus (NiP) alloy, a cobalt-phosphorus (CoP) alloy or a cobalt-tungsten-phosphorus (CoWP) alloy.

The nickel or cobalt deposit is preferably obtained by the electroless route by exposing the activated substrate to an aqueous solution comprising:

- at least one metal salt of nickel or cobalt ions, preferably in a concentration of between 10^"3 M and 1 M;

- at least one reducing agent for the nickel or cobalt ions, preferably in an amount of between 10^"4 M and 1 M; and

- optionally at least one stabilizing agent for the nickel or cobalt ions, preferably in an amount of between 10^"3 M and 1 M.

The nickel or cobalt salt is preferably a water soluble salt chosen from the group consisting of the chloride, acetate, acetylacetonate, hexafluorophosphate, nitrate, perchlorate, sulphate and tetrafluoroborate.

A metal salt which is preferred in the context of the present invention is chosen from nickel or cobalt sulphate, nickel or cobalt chloride, nickel or cobalt acetate, or nickel or cobalt sulphamate. For example, nickel sulphate hexahydrate is chosen.

Advantageously, the reducing agent can be chosen from the group consisting of phosphorus derivatives, boron derivatives, glucose, formaldehyde and hydrazine.

The phosphorus derivatives can be chosen from hypophosphorous acid

(H₃PO₂) and its salts and the boron derivatives can be chosen from borane complexes.

The reducing agent used is advantageously chosen from borane derivatives and in particular from dimethylamine borane, trimethylamine borane, triethylamine borane, pyridine borane, morpholine borane or tert-butylamine borane. Preferably, dimethylamine borane (DMAB) will be used.

The stabilizing agent can be chosen from the compounds which can complex with nickel ions or with cobalt ions, so as to prevent the reduction of the metal ions in solution by the reducing agent in the absence of catalysts. The stabilizing agent for the metal ions can be chosen from the group consisting of ethylenediamine and the salts of acetic, propionoic, succinic, hydroxyacetic, malonic, aminoacetic, malic or citric acid. Preferably, citric acid or one of its salts is chosen in order to stabilize the Ni²⁺ or Co²⁺ ions.

The pH of the aqueous solution can be acidic or basic and can be adjusted within the desired pH range by means of one or more pH-modifying compounds (or buffers), such as those described in the Handbook of Chemistry and Physics - 84^th Edition, by David R. Lide published by CRC Press.

The aqueous solution can, for example, comprise an agent which makes it possible to adjust the pH to a value of between 3 and 12, for example a nonpolymeric amine in order to adjust the pH between 8 and 12.

Generally, the metal layer can be produced by dipping the substrate in the aqueous solution defined above, at a temperature of between 50 and 90°C, preferably at 65°C, for a period of time of 30 s to 30 min, according to the desired thickness of the layer.

A preliminary step of prewetting the substrate can be carried out before exposing the substrate to the aqueous solution according to the invention. The substrate is, for example, immersed in an aqueous solution or in a solution containing the metal salt with a stabilizing agent thereof with no reducing agent. Preferably, deionized water is used. The combination is subjected to a negative pressure below 500 mbar for 1 to 30 min, preferably for 5 to 15 min.

The step of deposition of the nickel or cobalt layer can be carried out by rotating the substrate to be coated at a speed of between 20 and 600 revolutions per minute, by applying ultrasound or megasound, or by applying a simple recirculation of the aqueous solution in the reactor.

Using the aqueous solution described above, within the abovementioned temperature range, a metal film exhibiting a thickness of between 6 and 200 nanometres was obtained after a contact time period being between 1 min and 20 min.

According to one embodiment, the layer formed essentially of nickel or of cobalt is a layer of nickel-boron and is deposited by exposing the surface of the activated substrate to an aqueous solution containing a nickel salt, a boron-based reducing agent and a stabilizing agent, the pH of the solution being between 9 and 12 and the temperature of the aqueous solution being between 50°C and 90°C.

The aqueous solution containing the nickel salt can advantageously in addition contain a suppressing agent which is adsorbed at the surface of the metal layer as it is being formed.

The suppresser is preferably a polymer comprising "amine" groups or functional groups chosen in particular from polymers and copolymers derived from chitosans, from poly(allylamine)s, from poly(vinylamine)s, from poly(vinylpyridine)s, from poly(aminostyrene)s, from poly(ethyleneimine)s, from poly(L-lysine)s, and the acid (or protonated) forms of these polymers.

According to one embodiment of the invention, it is preferable to use a homopolymer or copolymer of poly(ethyleneimine) in its nonprotonated form.

The choice will be made, for example, of a linear poly(ethyleneimine) with a number-average molar mass M_n of between 500 and 25 000 g/mol.

The concentration of polymer possessing amine functional groups used according to the present invention advantageously ranges from 1 to 250 ppm, more particularly from 1 to 100 ppm, more preferably from 1 to 10 ppm, for example from 1.5 to 3 ppm (1 ppm equivalent to 1 mg/kg of solution).

When the polymer having amine functional groups is a poly(ethyleneimine), the pH of the aqueous solution advantageously ranges from 8 to 12, preferably from 8.5 to 10. It is in particular of the order of 9, for example between 8.9 and 9.1. In this case, it will be possible to use tetramethylammonium hydroxide (TMAH), triethanolamine, Ν,Ν-dimethylethanolamine or N-methylethanolamine as agent which makes it possible to adjust the pH.

The thickness of the nickel or cobalt layer is preferably uniform or conformable. It varies between 10 nm and 150 nm, more preferably between 10 nm and 100 nm, indeed even between 10 nm and 40 nm. The thickness of the nickel or cobalt layer can even be between 10 nm and 20 nm.

Step iii)

The heat treatment can be carried out in a tube furnace or on a heating plate. A tube furnace is a heating electrical furnace in the form of a tube which makes it possible to receive samples of varied shapes and sizes. In the context of the invention, it receives glass tubes, containing the samples, by loading in the longitudinal axis. A stream of a chosen and controlled gas can be combined with the heating of the assembly inside the glass tube.

In the context of the preferred applications of the invention, the process does not comprise a step of removal of the nickel or of the cobalt which has not migrated into the silicon and which has remained at the surface of the silicon substrate, on conclusion of the heat treatment step.

Consequently, the nickel or the cobalt which has not migrated into the silicon on conclusion of the heat treatment step is preferably not removed by chemical cleaning.

This is because the process of the invention makes it possible, very advantageously, to be able to obtain a thin and conformable nickel layer by interrupting the heat treatment. This nickel layer corresponds to the residual metal which has not migrated into the silicon. The inventors have found specific conditions which make it possible to obtain a stack of silicide and of metal in a single step. This stack had to date always been prepared in three steps: heat treatment of long duration in order to cause the maximum amount of nickel to migrate into the silicon, chemical removal of the nickel, cleaning of the surface of the silicide and deposition of a fresh layer of nickel. The process of the invention makes it possible to reduce the amounts of metal (nickel or cobalt) employed, to reduce the number of steps and to reduce the duration of the manufacturing process.

The substrate covered with the metal layer is subjected to a rapid heat treatment at a temperature of less than or equal to 350°C, preferably less than 300°C.

For example, the heat treatment temperature is between 200 and 300°C, preferably between 210 and 290°C, for example between 220 and 270°C, or between 230 and 260°C. The duration of treatment is advantageously less than 30 minutes, for example equal to 10 mins.

In one embodiment, the metal is a nickel alloy or a cobalt alloy comprising boron and is called nickel-boron and cobalt-boron respectively.

The nickel-boron or cobalt-boron alloy has preferably a boron content being from 1 atom% to 10 atom%, for example a boron content that is between two values selected from the group consisting of 1 atom %, 2 atom %, 3 atom %, 4 atom %, 5 atom %, 6 atom %, 7 atom %, 8 atom %, 9 atom % and 10 atom %.

For example, a nickel-boron alloy or a cobalt-boron alloy may have a boron content of 35 atom% (which corresponds to 6% by weight for a nickel-boron alloy).

In the case of a nickel layer or a nickel-boron alloy layer, the rapid heat treatment temperature is preferably between 200°C and 325°C, and preferably between two values that selected in the group consisting of 210°C, 220°C, 225°C, 230°C, 240°C, 250°C; 260°C, 270°C, 275°C, 280°C, 290°C, 300°C, 310°C, 320°C. The rapid heat treatment temperature is still preferably from 240°C to 260°C, for example equal to 250°C. According to one embodiment, the metal alloy is nickel-boron, and the rapid heat treatment temperature is between 200 and 325°C.

In the case of a cobalt layer or a cobalt-boron alloy layer, the rapid heat treatment temperature is preferably between 250°C and 375°C, and preferably between two values that selected in the group consisting of 250°C, 260°C, 270°C, 280°C, 290°C, 300°C, 310°C, 320°C, 330°C, 340°C, 350°C, 360°C, 370°C, and 375°C. The rapid heat treatment temperature is still preferably from 250°C to 350°C, for example equal to 300°C. According to one embodiment, the metal alloy is cobalt- boron, and the rapid heat treatment temperature is from 250 to 375°C, preferably from 250 to 350°C.

The duration of the rapid heat treatment is advantageously less than 30 minutes, for example less than 10 minutes, and may last from 1 to 10 minutes. The rapid heat treatment is preferably performed under a reducing atmosphere with standard pressure conditions (SPC).

The interposed layer predominantly comprises a silicide of SiM₂ stoichiometry, M representing nickel or cobalt, in the sense that it comprises a minimum weight percentage of SiM₂, wherein the minimum weight percentage is selected form the group consisting of 50%, 60%, 70%, 80%, 85%, 90%, 95% and 99%, with respect to the interposed layer weight. The interposed layer preferably consists of SiM₂.

Step iyl

The layer of residual metal is subsequently covered with copper by a conventional electroplating process. These processes, which are well known to a person skilled in the art, comprise the application of a current to the substrate and its immersion in an acidic or basic bath of copper ions. The electroplating composition used can correspond to a product sold under the aveni^®, Sao^®, Rhea^® or Janus^® references.

The copper deposit can take the form of a "germination" layer of a few tens or hundreds of nanometres, or the form of a deposit, the thickness of which is of the order of approximately ten microns.

During this metallization step, the surface to be covered or the structure to be filled is polarized, either in galvanostatic mode (fixed applied current) or in potentiostatic mode (applied potential which is fixed, optionally with respect to a reference electrode) or in pulse mode (pulsed in current or in voltage).

A second subject-matter of the invention is a process for the manufacture of an integrated circuit comprising interconnection lines and through silicon vias, which process comprises the steps of:

A- providing a substrate that is covered with a silicon oxide layer having an exposed silicon dioxide surface,

B - eventually etching structures in said silicon dioxide layer, said structures being intended to form said interconnection lines and said through silicon vias,

C- forming a silicon layer on said exposed silicon oxide surface, and obtaining an exposed silicon surface located at least inside the structures,

D- a step of

i- forming gold particles or palladium particles on said exposed silicon surface, in order to obtain an activated silicon surface,

ii- forming, on the activated silicon surface, a metal or metal alloy in the form of a layer, said metal being chosen from the group consisting of nickel and cobalt and said metal alloy being chosen from the group consisting of nickel alloys and cobalt alloys, and obtaining an assembly of stacks, iii- applying a rapid heat treatment to the assembly of stacks obtained in step ii), so as to form, between a) the metal layer or the metal alloy layer and b) the silicon layer, an interposed layer that is in contact with the silicon layer and which predominantly comprises a SiM2 silicide, M representing nickel or cobalt, said SiM2 silicide being formed by diffusion of the metal or the metal alloy into the silicon layer, so as to leave, into contact with said silicon layer, a residual part of the metal layer or the residual metal alloy layer having an exposed surface, wherein the rapid heat treatment is carried out at a rapid heat treatment temperature being less than or equal to 350°C, and

iv- forming a copper layer on the exposed surface of the residual part of metal layer or the residual part of the metal alloy layer.

This process does not preferably comprise a step of stripping the residual metal after the heat treatment step and does not preferably comprise a step of deposition of an additional nickel or cobalt layer, after the heat treatment step.

All the features that have been disclosed with regard to the first object of the invention apply to the second object of the invention.

The structures can be of various sizes according to whether they fulfil the function of interconnections (or trenches) or of through silicon vias in the case of 3D IC devices. They are, for example, such that their width or their diameter, at the surface of the substrate, is between 100 nm and 100 microns and their depth is between 100 nm and 300 microns.

The through silica vias can be manufactured in BEOL or FEOL (front-end-of- line) fashion.

The invention is more particularly targeted to the manufacture of through silicon vias (TSVs) of via-last type, that is to say vias formed in the integrated circuit after the BEOL (back-end-of-line) steps. In the process for the manufacture of the through silicon vias of via-last type, the installation of the circuit and the possible thinning of the silicon wafer takes place before the creation of the TSVs, the circuit comprising interconnections which will be used to connect the TSVs.

A particularly advantageous embodiment of the invention is a process for the manufacture of an integrated circuit which comprises, in a step subsequent to step C, a step D of heat treatment that is carried out at a temperature lower than the rapid heat treatment temperature of step iii). This is because some configurations of integrated circuits in three dimensions comprise stacks of materials, the cohesion of which can be damaged by excessively high processing temperatures, in particular when the form of integration employs a process which requires a heat treatment in steps subsequent to the assembling of these materials.

The process of the invention thus makes it possible to manufacture stacks of materials in integrated circuits in three dimensions, the cohesion of which is improved not only in the copper conductor network but also in the stacks of the various layers. This is rendered possible by decreasing the temperatures applied in steps subsequent to the steps of assembling the different integration levels. The invention also relates, in a third subject-matter, to a structure intended for the manufacture of electronic components that may be obtained according to a process according to the first or second object of the invention, said structure comprising a stack of layers that are arranged in the following order: a silicon dioxide layer, a nickel silicide SiNi2 or cobalt silicide CoNi2 layer, a cobalt-boron alloy or a nickel-boron alloy layer, and a copper layer, wherein said nickel silicide SiNi2 or said cobalt silicide CoNi2 layer shares a common surface with the silicon dioxide layer.

For an application in the field of microelectronics, the substrate can be composed of a silicon coupon covered with a silicon layer dioxide (Si0₂) having a thickness of between 70 and 110 nm, followed by a silicon layer, for example polycrystalline silicon, having a thickness of between 150 nm and 2 microns.

Polycrystalline silicon, also commonly known as polysilicon or poly-Si, is understood to mean a specific form of silicon which differs from monocrystalline silicon and amorphous silicon. Contrary to the first (composed of just one crystal) and to the second (having no or a very low crystal log raphic coherence), polycrystalline silicon is composed of multiple small crystals of varied sizes and shapes.

A fourth subject-matter of the invention relates to a process for the manufacture of photovoltaic cells which comprises a step of forming copper conducting lines by copper metallization of a silicon according to the process of the second subject-matter of the invention, which process comprises neither a step of stripping the residual metal after the heat treatment step nor a step of deposition of an additional layer of said metal after the heat treatment step.

All the features that have been disclosed with regard to the first object of the invention apply to the fourth object of the invention.

Unless otherwise indicated, these examples were carried out under standard temperature and pressure conditions (approximately 25°C under approximately 1 atom) in ambient air and the reactants used were directly obtained commercially without addition of purification. Example 1: Activation of a substrate covered with a laver of polvcrvstalline silicon starting from a solution containing a gold salt, hydrofluoric acid and an anionic surfactant in order to obtain a nickel silicide (SiNi ) adherent interface a) Cleaning of the surfaces:

Depending on the origin of the substrate and his requirements, a person of the state of the art will know how to adapt a protocol for cleaning the surface. In our case, no cleaning was necessary since the activation solution is also a slow etching solution. In this example, the substrate used is a silicon coupon with side lengths of 1 cm x 2 cm and with a thickness of 750 μιτι covered with a silicon layer dioxide (Si0₂) having a thickness of approximately 260 nm and with a layer of polycrystalline silicon having a thickness of approximately 100 nm. b) Activation of the surface of the substrate:

bl) Preparation of the activation solution:

950 ml of deionized water are mixed with 50 ml of 49% by weight hydrofluoric acid in a clean plastic flask suitable for this type of mixing. 285 mg of gold(III) hydrochloride (HAuCU) and 3 g of SDS (sodium dodecyl sulphate) are subsequently introduced. The solution then assumes a bright yellow colouration. b2) Activation treatment on the surface of the substrate:

The substrate described in step a) is immersed for a given time of 30 seconds to 1 minute in the mixture prepared in step bl). The substrate thus treated is copiously rinsed with deionized water and dried under a stream of nitrogen. c) Deposition of an NiB metal layer by an electroless method:

cl) Preliminary preparation of the electroless solution:

31.11 g of nickel sulphate hexahydrate (0.118 mol), 44.67 g of citric acid

(0.232 mol), 52.26 g of N-methylethanolamine (0.700 mol) and 2.5 ppm of polyethyleneimine (PEI) with Mn = 600 g/mol are introduced, in order, into a 1 litre container and a minimum of deionized water. The final pH was adjusted to 9 with the base and the total volume was adjusted to 1 litre with deionized water.

Immediately before the following step, one volume of a reducing solution is added to 9 volumes of the preceding solution. The reducing solution comprises 28 g/l of dimethylamine borane (DMAB; 0.475 mol) and 60.00 g of N-methylethanolamine (0.798 mol). c2) Formation of the NiB alloy layer on the polycrystalline silicon layer:

A layer of NiB alloy was deposited on the surface of the substrate treated in step b) by immersing it in the electroless solution prepared previously and brought to 65°C, for a period of 30 seconds to 9 minutes, according to the final thickness desired. In this specific case, a time of 5.25 minutes is chosen. d) Formation of the nickel silicide:

The sample obtained in step c), with the NiB alloy on top, is subjected to a rapid thermal annealing (RTA) for 10 minutes under reducing gas (4% H₂ in N₂). Several tests are carried out while varying the temperature from 250°C to 350°C. The operation can be carried out with a tube furnace or a heating plate.

e) Formation of a copper layer:

A copper layer was deposited on the coated substrate on conclusion of step d) by using a commercial solution (Aveni^® AF600 or Janus^®). The electroplating process employed in this example comprised a step of growth of the copper during which the treated substrate obtained on conclusion of step d) was polarized cathodically in galvanic mode and simultaneously rotated at a speed of 60 revolutions per minute. The galvanic protocol (DC; Direct Current) which was used is 16.25 mA/cm². The duration of this step depends, as is understood, on the desired thickness of the copper layer. This duration can be easily determined by a person skilled in the art, the growth of the film being a function of the charge passed through the circuit. Under the abovementioned conditions, a duration of the electroplating step of the order of 10 minutes made it possible to obtain a coating having a thickness of approximately 2.4 microns. The substrate thus coated with copper was removed from the electroplating solution at a zero speed of rotation in approximately 2 seconds and then rinsed with deionized water (18.2 Mohm/cm) and dried under flushing with nitrogen.

The metal stack thus obtained was annealed at 250°C for 10 minutes under a reducing atmosphere (N₂ + H₂ mixture (4% of H₂)). f) Results:

Figure 1 shows the ion polishing of the profile of the sample obtained according to steps a) to e), in the case where the thermal annealing temperature is equal to 250°C.

The profile of the sample, observed by SEM, makes it possible to confirm the quality of the stack of materials and their thickness: silicon (750 microns), silicon oxide (260 nm), polysilicon (35 nm), SiNi₂ (30 nm), NiB (35 nm), and copper (2.4 microns). The adhesion of the stacks was measured under the conditions of Standard ASTM 3359 for each of the samples prepared. The results are summarized in the following table. Table 1 - Adhesion of the Si/Si0₂/polySi/SiNi₂/NiB/Cu stacks

Example 2: Activation of a substrate covered with a layer of polvcrvstalline silicon starting from a solution containing a gold salt, hydrofluoric acid and an anionic surfactant in order to obtain a cobalt silicide (SiCo₂) adherent interface a) Cleaning of the surfaces:

This step is completely identical to step a) of Example 1. b) Activation of the surface of the substrate:

This step, with the substeps bl) and b2), is identical to that of Example 1. c) Deposition of a layer of CoB metal by an electroless method:

cl) Preliminary preparation of the electroless solution:

5.8 g of cobalt chloride hexahydrate (0.025 mol), 8.9 g of citric acid (0.046 mol), 12 g of N-methylethanolamine (0.328 mol) and 2.5 ppm of polyethyleneimine (PEI) with Mn = 600 g/mol are introduced, in order, into a 200 ml container and a minimum amount of deionized water. The final pH was adjusted to 9 with the base and the total volume was adjusted to 200 ml with deionized water.

Immediately before the following step, one volume of a reducing solution is added to 9 volumes of the preceding solution. The reducing solution comprises 28 g/l of dimethylamine borane (DMAB; 0.475 mol) and 60.00 g of N-methylethanolamine (0.798 mol).

c2) Formation of the CoB alloy layer on the polycrystalline silicon layer:

A layer of CoB metal alloy was prepared on the surface of the substrate treated in step b) by immersing it in the electroless solution prepared previously and brought to 74°C, for a period of 30 seconds to 5 minutes, according to the final thickness desired. The duration of immersion in the electroless solution is determined so as to obtain a minimum thickness of cobalt with a good uniformity and conductivity. In this example, the dipping period is 4 minutes and the CoB thickness is approximately 45 nm. d) Formation of the cobalt silicide (SiCo₂):

As in step d), Example 1, the sample obtained in step c), with the CoB alloy on top, is subjected to a rapid thermal annealing at 250°C, 300°C or 350°C for 10 minutes. ) Formation of a copper layer:

This step is completely identical to e) in Example 1. ft Results:

Figure 2 is an SEM photograph which shows the ion polishing of the profile of the sample obtained according to steps a) to e), in the case where the thermal annealing temperature is equal to 300°C.

The ion polishing of the profile of the sample obtained according to steps a) to e) makes it possible to confirm the quality of the stack of the materials and their thickness: silicon (750 microns), silicon oxide (260 nm), polysilicon (35 nm), SiCo₂ (30 nm), CoB (35 nm), and copper (2.4 microns).

The measurement of the adhesion carried out on this stack according to Standard ASTM 3359 provides a result of 16/16, reinforcing the concept described previously. The Rs (resistivity) measurement is in the order of 10 to 15 ohm/square at the end of the same step d).

Table 2 - Adhesion of the Si/Si0₂/polySi/SiCo₂/CoB/Cu stacks

Annealing

250°C 300°C 350°C

temperature

Adhesion

Standard ASTM 16/16 16/16 16/16

3359 Example 3: Activation of a substrate covered with a laver of polvcrvstalline silicon starting from a solution containing a aoldflll) complex and hydrofluoric acid in order to obtain a nickel silicide fSiNU) adherent interface a) Cleaning of the surfaces:

This step is completely identical to step a) according to Example 1. b) Activation of the surface of the substrate:

bl) Preparation of the activation solution:

40 mg of gold (III) hydrochloride (HAuCI₄), 20 mg of bipyridine and 10 ml of EDI are successively introduced into a 25 ml round-bottomed flask. The mixture is brought to reflux for 5 to 10 minutes. A yellow precipitate, which is formed first, dissolves after a few minutes when the solution has reached boiling point. This solution is subsequently mixed with 40 ml of 2.5% HF.

b2) Activation treatment on the surface of the substrate:

The substrate described in step a) is immersed for a given time of 30 seconds to 1 minute in the mixture prepared in step bl). The substrate thus treated is copiously rinsed with deionized water and dried under a stream of nitrogen. c) Deposition of a layer of metal NiB by an electroless method:

This step is identical to step c) of Example 1. d) Formation of the nickel silicide (SiNi₂):

The sample obtained in step c), with the NiB alloy on top, is subjected to a rapid thermal annealing (RTA) under the reducing gas at 250°C for ten minutes. e) Formation of a copper laver:

This step is strictly identical to e) in Example 1. ft Results:

The measurement of the adhesion carried out on this stack according to Standard ASTM 3359 provides a result of 16/16.

Claims

1. A process for the manufacture of an integrated circuit comprising interconnection lines and through silicon vias, which process comprises the steps of:

D- a step of

iii- applying a rapid heat treatment to the assembly of stacks obtained in step ii), so as to form, between a) the metal layer or the metal alloy layer and b) the silicon layer, an interposed layer that is in contact with the silicon layer and which predominantly comprises a SiM₂ silicide, M representing nickel or cobalt, said SiM₂ silicide being formed by diffusion of the metal or the metal alloy into the silicon layer, so as to leave, into contact with said silicon layer, a residual part of the metal layer or the residual metal alloy layer having an exposed surface, wherein the rapid heat treatment is carried out at a rapid heat treatment temperature being less than or equal to 350°C, and

2. The process according to Claim 1, wherein the thickness of metal layer or the metal alloy layer is deposited in step ii) is between 10 and 150 nm, and wherein the layer of residual metal or the layer of residual metal alloy is conformal and has a thickness being from 5 to 100 nm.

3. The process according to claim 1 or 2, wherein step i) comprises forming gold particles.

4. The process according to any one of the preceding claims, wherein the interposed layer consists in SiM₂ and has a thickness being from 10 to 200 nm.

5. The process according to any one of the preceding claims, wherein the metal alloy is nickel-boron, and wherein the rapid heat treatment temperature is from

200 to 325°C, preferably from 225°C to 275°C.

6. The process according to any one of the preceding claims, wherein the metal alloy is cobalt-boron, and wherein the rapid heat treatment temperature is from 250 to 375°C, preferably from 250 to 350°C.

7. The process according to any one of the preceding claims, wherein the rapid heat treatment is performed under a reducing atmosphere for a time period between 1 minute to 30 minutes, preferably for a time period between 1 and 10 minutes.

8. The process according to any one of the preceding claims, wherein silicon of the silicon layer is doped or undoped silicon, and is chosen from the group consisting of polysilicon, amorphous silicon and crystalline silicon.

9. The process according to any one of the preceding claims, wherein the structures have a width or a mean diameter, at the surface of the substrate, that is between 100 nm and 100 microns and a depth that is between 100 nm and 300 microns.

10. The process according to any one of the preceding claims, wherein step D is followed by a step E comprising a heat treatment that is carried out at a temperature being lower than the rapid heat treatment temperature of step iii).

11. The process according to any one of the preceding claims, which process does not comprise a step of forming an additional metal layer on the residual metal layer between step iii) and step iv), and which process does not comprise a step of forming an additional metal alloy layer on the residual metal alloy layer between step iii) and step iv).

12. A Process for forming a silicide on a substrate, which process comprising a step of providing a substrate that is covered with a silicon oxide layer having an exposed silicon dioxide surface, and the steps of: i- forming gold particles or palladium particles on said exposed silicon surface, in order to obtain an activated silicon surface,

13. Structure intended for the manufacture of electronic components that may be obtained from a process according to any one of claims 1-11 or from a process according to claim 12, said structure comprising a stack of layers that are arranged in the following order: a silicon dioxide layer, a nickel silicide SiNi2 or cobalt silicide CoNi2 layer, a cobalt-boron alloy or a nickel-boron alloy layer, and a copper layer, wherein said nickel silicide SiNi2 or said cobalt silicide CoNi2 layer shares a common surface with the silicon dioxide layer.

14. A process for the manufacture of photovoltaic cells which comprises a step of forming copper conducting lines by copper metallization of a silicon according to the process of Claim 12, wherein said process for the manufacture of photovoltaic cells comprises neither a step of stripping the residual metal after the heat treatment step nor a step of deposition of an additional layer of said metal after the heat treatment step.