WO2017101061A1 - 一种自举驱动电路及其驱动方法 - Google Patents

一种自举驱动电路及其驱动方法 Download PDF

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Publication number
WO2017101061A1
WO2017101061A1 PCT/CN2015/097682 CN2015097682W WO2017101061A1 WO 2017101061 A1 WO2017101061 A1 WO 2017101061A1 CN 2015097682 W CN2015097682 W CN 2015097682W WO 2017101061 A1 WO2017101061 A1 WO 2017101061A1
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Prior art keywords
switch
unit
pull
driving
circuit
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PCT/CN2015/097682
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English (en)
French (fr)
Inventor
唐样洋
张臣雄
Original Assignee
华为技术有限公司
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Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN201580085227.3A priority Critical patent/CN108432104B/zh
Priority to PCT/CN2015/097682 priority patent/WO2017101061A1/zh
Publication of WO2017101061A1 publication Critical patent/WO2017101061A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters

Definitions

  • the present invention relates to the field of circuits, and in particular, to a bootstrap driving circuit and a driving method thereof.
  • Switched inductor power supplies are the most widely used off-chip or on-chip power supplies.
  • a positive-electrode metal oxide semiconductor (PMOS) transistor is used as its pull-up switch, and a circuit design of a negative-electrode metal oxide semiconductor (NMOS) transistor as its pull-down switch is gradually being eliminated.
  • the pull-up switch and the pull-down switch both use NMOS tube design to improve the conversion efficiency of the switching power supply and reduce the area of the switching power supply.
  • the drive circuit design of the pull-up NMOS transistor becomes a problem.
  • a common solution in the prior art is to use a pull-up bootstrap drive circuit to drive the pull-up switch M H .
  • the main bootstrap driver circuit with an additional capacitor C boot gate voltage to achieve M H can reach higher than the voltage VDD.
  • the voltage at the Vx terminal that is, the voltage at the source of M H
  • the voltage value of VDD can reach the NMOS conduction characteristics of the source voltage of M H tube to reach the VDD.
  • require higher than a gate-source voltage of M H M H tube pipe in this switching power supply applications, usually require The gate voltage of the M H tube reaches 2*VDD.
  • the defect of the bootstrap driving circuit in the prior art is that a high withstand voltage MOS is required in the driving circuit, so that the cost realized by the circuit is improved.
  • Embodiments of the present invention provide a bootstrap driving circuit and a driving method thereof for providing a bootstrap driving circuit using a low withstand voltage component.
  • a first aspect of the present invention provides a bootstrap driving circuit, including:
  • a charge and discharge unit a stacked circuit unit, and a pull-up switch unit
  • the stack circuit unit sends a first driving signal to the charging and discharging unit, so that the power supply voltage VDD is turned on to the charging circuit of the charging and discharging unit, and the power supply voltage VDD charges the charging and discharging unit;
  • the charge and discharge unit discharges the stacked circuit unit, and the stack circuit unit sends the second drive signal to the pull-up switch unit, and the voltage value of the second drive signal is at least twice the voltage value of the power supply voltage VDD.
  • the pull-up switch unit is a driving object of the bootstrap driving circuit. If the pull-up switch unit is to be driven, the driving signal of at least twice the voltage value of the power supply voltage VDD is to be pulled up by the switching unit, and the bootstrap driving circuit is driven.
  • the stack circuit unit When the pull-up switch unit is not turned on, the stack circuit unit sends a first driving signal to the charging and discharging unit, and the charging and discharging unit is charged by the power supply voltage VDD according to the first driving signal; when the pull-up switching unit is turned on, charging and discharging The unit discharges the stacked circuit unit, and the stacked circuit unit sends the second driving signal to the pull-up switching unit, the voltage value of the second driving signal is at least twice the voltage value of the power supply voltage VDD; and the second driving is due to the existence of the stacked circuit unit
  • the voltage value of the signal is adjusted to be at least twice the voltage value of the power supply voltage VDD, and the voltage serving as the discharge of the electric unit is the power supply voltage VDD, and the voltage across the other circuit components of the bootstrap driving circuit can be controlled below the power supply voltage VDD. This eliminates the need for high-voltage MOS during the implementation of the bootstrap driver circuit, thereby reducing the cost of circuit implementation.
  • the pull-up switching unit comprises: a pull-up switch M H;
  • the charging and discharging unit comprises: a capacitor state control switch M12 and a bootstrap capacitor C boot ;
  • the drain terminals of the capacitor state control switch M12 and the pull-up switch M H are connected to the power supply voltage VDD; the source terminals of the capacitor state control switch M12 and the pull-up switch M H are respectively connected to the two ends of the bootstrap capacitor C boot ;
  • the stacked circuit unit is connected to the bootstrap capacitor C boot from opposite ends of the connection, the stack state control circuit unit and the capacitance of the gate terminal of the switch M12, a stack switch circuit unit is pulled up to the gate terminal of M H outputs a second driving signal, the capacitor circuit unit stacked the gate terminal of M12 is controlled switches outputs a first driving signal, the first driving signal is represented by a voltage value of 0V drive voltage V Shift, the second driving signal is not less than 2 * VDD driving voltage represented by the voltage V Shift value.
  • the stack circuit unit When the pull-up switch M H is not turned on, the stack circuit unit outputs a first driving signal to the gate terminal of the capacitance control switch M12, the first driving signal is represented by a driving voltage V Shift having a voltage value of 0V, and the first driving signal makes the capacitor control switch M12 is turned on, capacitor after controlling the switch M12 is turned on by the power supply voltage VDD to the bootstrap capacitor C boot charging, pull switch M H is turned on when the upper capacitor control switch M12 is not turned on, bootstrap capacitor C boot of The stacked circuit unit discharges, so that the stacked circuit unit outputs a second driving signal to the gate terminal of the pull-up switch M H , and the second driving signal is represented by a driving voltage V Shift whose voltage value is not less than 2*VDD, by changing the capacitance in the charging and discharging unit
  • the conduction state of the switch M12 is controlled to realize charging and discharging of the charging and discharging unit, so that the specific implementation of the present solution can be
  • the stacking circuit unit transmits a first driving signal to the charging and discharging unit to turn on the power supply voltage VDD to the charging circuit of the charging and discharging unit.
  • the power supply voltage VDD charges the charge and discharge unit, including:
  • the stack circuit unit adjusts the driving voltage V Shift to 0V and sends it to the gate terminal of the capacitor state control switch M12, so that the capacitor state control switch M12 is turned on, and the power supply voltage VDD is turned on to the charging circuit of the bootstrap capacitor C boot , and the power supply voltage is turned on.
  • VDD charges the bootstrap capacitor C boot .
  • the circuit unit stacked on the source terminal of M H is pull-up switch connected to the pull-up switch M H of the source terminal voltage to 0V, the The stack circuit unit adjusts the driving voltage V Shift to 0V, sends it to the gate terminal of the capacitor state control switch M12, the capacitor state control switch M12 is turned on, and the power supply voltage VDD is turned on to the charging circuit of the bootstrap capacitor C boot , so that the power supply voltage VDD is turned on. It is applied to both ends of the bootstrap capacitor C boot , and the bootstrap capacitor C boot is charged to realize the charging function of the charging and discharging unit, so that the scheme is more specific.
  • the charging and discharging unit discharges the stacked circuit unit, and the stacked circuit unit sends the second driving signal to the pull-up switching unit, including:
  • the capacitor state control switch M12 is not turned on, the bootstrap capacitor Cboot discharges the stacked circuit unit, and the stack circuit unit adjusts the driving voltage V Shift to at least twice the power supply voltage VDD, and sends it to the gate terminal of the pull-up switch M H .
  • M H due to the pull switch is NMOS transistor, a source terminal connected to the circuit unit stacked on the pull-up switch M H, a source terminal of the pull-up switch M H voltage value VDD, the capacitance state control switch M12 is not turned on, bootstrap capacitor C boot of stacked circuit cell discharge, the stacked circuit unit driving voltage V Shift was adjusted to at least 2 * VDD, the transmission-oriented gate terminal of the pull-up switch M H, the charge-discharge unit implements a discharge
  • the function and the stacking circuit unit form a second driving signal for specific description, so that the scheme is clearer.
  • the stacking circuit unit includes: a first submodule, and a second submodule;
  • the first sub-module outputs a control voltage V G2 to the second sub-module, and the second sub-module outputs a driving voltage V Shift to the gate terminals of the capacitive state control switch M12 and the pull-up switch M H , when the pull-up switch M H is not turned on
  • the control voltage V G2 is equal to 0V; when the pull-up switch M H is turned on, the control voltage V G2 is equal to the power supply voltage VDD.
  • the pull-up switch M H When the pull-up switch M H is not turned on, the source terminal voltage value of the pull-up switch M H becomes 0V, and the first sub-module is connected to the source terminal of the pull-up switch M H , so that the first sub-module is to the second sub-module
  • the output control voltage V G2 becomes 0V
  • the second sub-module receives the control voltage V G2 of the first sub-module, and outputs a driving voltage V Shift having a voltage value of 0V to the capacitive state control switch M12, that is, the first driving signal;
  • the pull switch M H When the pull switch M H is turned on, the source terminal voltage of the pull-up switch M H becomes VDD, the control voltage V G2 outputted by the first sub-module to the second sub-module becomes VDD, and the charge and discharge unit discharges the second sub-module So that the second sub-module pulls up the switch M H to output a driving voltage V Shift having a
  • the first sub-module includes: a first switch tube M1, a fourth switch tube M4, and a fifth switch tube M5;
  • the second sub-module includes: a second switch tube M2, a third switch tube M3, a sixth switch tube M6, a seventh switch tube M7, an eighth switch tube M8, and a ninth switch tube M9; the fourth switch tube M4
  • the source terminal is connected to the drain terminal of the fifth switching transistor M5, and the drain terminal of the first switching transistor M1 and the fourth switching transistor The drain terminals of M4 are connected;
  • the drain terminal of the second switch transistor M2 is connected to the source terminal of the third switch transistor M3, the drain terminal of the sixth switch transistor M6 is connected to the source terminal of the seventh switch transistor M7, and the source terminal of the eighth switch transistor M8 is connected to the ninth The drain terminal of the switch tube M9 is connected;
  • the first switch tube M1, the second switch tube M2, the third switch tube M3, the eighth switch tube M8, and the ninth switch tube M9 are PMOS tubes, and the fourth switch tube M4, the fifth switch tube M5, and the sixth switch tube M6 and a seventh switching transistor of the NMOS transistor M7, M H is pull-up switch NMOS transistor.
  • a second aspect of the present invention provides a driving method of a bootstrap driving circuit, which is applied to a bootstrap driving circuit.
  • the bootstrap driving circuit includes a charging and discharging unit, a stacked circuit unit, and a pull-up switching unit.
  • the driving method includes:
  • the stack circuit unit sends a first driving signal to the charging and discharging unit, so that the power supply voltage VDD is turned on to the charging circuit of the charging and discharging unit, and the power supply voltage VDD charges the charging and discharging unit;
  • the charge and discharge unit discharges the stacked circuit unit, and the stack circuit unit sends the second drive signal to the pull-up switch unit, and the voltage value of the second drive signal is at least twice the voltage value of the power supply voltage VDD.
  • the stacking circuit unit When the pull-up switch unit is in a non-conducting state, the stacking circuit unit sends a first driving signal to the charging and discharging unit, the power supply voltage VDD is turned on to the charging circuit of the charging and discharging unit, and the power supply voltage VDD charges the charging and discharging unit; When the switching unit is turned on, the charging and discharging unit discharges the stacked circuit unit, and the stacked circuit unit sends the second driving signal to the pull-up switching unit. Due to the existence of the stacked circuit unit, the voltage value of the second driving signal can be adjusted to the voltage of the power supply voltage VDD.
  • the voltage serving as the discharge of the electric unit is the power supply voltage VDD, and the voltage across the other circuit elements of the bootstrap driving circuit can be controlled below the power supply voltage VDD, so that the driving method is implemented in the bootstrap driving circuit.
  • the driving method is implemented in the bootstrap driving circuit.
  • MOS high withstand voltage MOS, which reduces the cost of circuit implementation.
  • the pull-up switch unit includes: a pull-up switch M H ;
  • the charging and discharging unit comprises: a capacitor state control switch M12 and a bootstrap capacitor C boot ;
  • the stacking circuit unit sends a first driving signal to the charging and discharging unit, so that the power supply voltage VDD is turned on to the charging circuit of the charging and discharging unit, and the power supply voltage VDD charges the charging and discharging unit, including:
  • the stack circuit unit adjusts the driving voltage V Shift to 0V and sends it to the gate terminal of the capacitor state control switch M12, so that the capacitor state control switch M12 is turned on, and the power supply voltage VDD is turned on to the charging circuit of the bootstrap capacitor C boot , and the power supply voltage is turned on.
  • VDD charges the bootstrap capacitor C boot .
  • the circuit unit stacked on the source terminal of M H is pull-up switch connected to the pull-up switch M H of the source terminal voltage to 0V
  • the The stack circuit unit sends a driving voltage V Shift having a voltage value of 0V to the gate terminal of the capacitor state control switch M12, so that the capacitor state control switch M12 is turned on, and the power supply voltage VDD is turned on to the charging circuit of the bootstrap capacitor C boot , and the power supply voltage VDD is turned on.
  • the bootstrap capacitor C boot is charged, and the charging step of the charging and discharging unit is specifically described, so that the scheme is more specific.
  • the pull-up switch unit includes: a pull-up switch M H ;
  • the charging and discharging unit comprises: a capacitor state control switch M12 and a bootstrap capacitor C boot ;
  • the charging and discharging unit discharges the stacked circuit unit, and the stacked circuit unit sends the second driving signal to the pull-up switching unit, including:
  • the capacitor state control switch M12 is not turned on, the bootstrap capacitor Cboot discharges the stacked circuit unit, and the stack circuit unit adjusts the driving voltage V Shift to at least twice the power supply voltage VDD, and sends it to the gate terminal of the pull-up switch M H .
  • M H due to the pull switch is NMOS transistor, a source terminal connected to the circuit unit stacked on the pull-up switch M H, a source terminal of the pull-up switch M H voltage value VDD, the capacitance
  • the state control switch M12 is not turned on, the bootstrap capacitor Cboot discharges the stacked circuit unit, and the stacked circuit unit adjusts the driving voltage V Shift to at least 2*VDD, and sends it to the gate terminal of the pull-up switch M H to discharge the charging and discharging unit.
  • the stacking circuit unit forms a second driving signal for specific description, so that the solution is more clear.
  • the stacking circuit unit includes: a first submodule, and a second submodule;
  • the first sub-module When the pull-up switch M H is not turned on, the first sub-module outputs a control voltage V G2 to the second sub-module, the control voltage V G2 is equal to 0V, and the second sub-module outputs a driving voltage with a voltage value of 0V according to the control voltage V G2 .
  • V Shift When the pull-up switch M H is not turned on, the first sub-module outputs a control voltage V G2 to the second sub-module, the control voltage V G2 is equal to 0V, and the second sub-module outputs a driving voltage with a voltage value of 0V according to the control voltage V G2 .
  • the control voltage V G2 is equal to the power supply voltage VDD, and the second sub-module outputs a driving voltage V Shift having a voltage value of at least 2*VDD according to the control voltage V G2 .
  • the first sub-module outputs a control voltage V G2 of different voltage values to the second sub-module according to the conduction or non-conduction state of the pull-up switch M H , and the second sub-module adjusts the driving voltage according to the control voltage V G2 of different voltage values.
  • the voltage value of V Shift that is, the output of the first driving signal or the second driving signal, describes a method of outputting the first driving signal and the second driving signal by the stacked circuit unit, and clarifies the process of obtaining the driving signal by the stacked circuit unit.
  • FIG. 1 is a schematic diagram of a prior art bootstrap driving circuit
  • FIG. 2 is a schematic diagram of a bootstrap driving circuit of an embodiment of the present invention.
  • FIG. 3 is another schematic diagram of a bootstrap driving circuit in accordance with an embodiment of the present invention.
  • FIG. 4 is another schematic diagram of a bootstrap driving circuit in accordance with an embodiment of the present invention.
  • FIG. 5 is another schematic diagram of a bootstrap driving circuit according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of a driving method of a bootstrap driving circuit according to an embodiment of the present invention.
  • an embodiment of a bootstrap driving circuit in an embodiment of the present invention includes:
  • a charge and discharge unit a stacked circuit unit, and a pull-up switch unit
  • the stack circuit unit sends a first driving signal to the charging and discharging unit, so that the power supply voltage VDD is turned on to the charging circuit of the charging and discharging unit, and the power supply voltage VDD charges the charging and discharging unit;
  • the charge and discharge unit discharges the stacked circuit unit, and the stack circuit unit sends the second drive signal to the pull-up switch unit, and the voltage value of the second drive signal is at least twice the voltage value of the power supply voltage VDD.
  • the stack circuit unit when the pull-up switch unit is not turned on, the stack circuit unit sends a first driving signal to the charging and discharging unit, so that the power supply voltage VDD is turned on to the charging circuit of the charging and discharging unit, and the power supply voltage VDD is charged and discharged.
  • the unit performs charging; when the pull-up switch unit is turned on, the charging and discharging unit discharges the stacked circuit unit, and the stacked circuit unit sends the second driving signal to the pull-up switching unit, and the voltage value of the second driving signal is the voltage value of the power supply voltage VDD.
  • the voltage value of the second driving signal is adjusted to at least twice the voltage value of the power supply voltage VDD, and the voltage discharged by the charging and discharging unit is the power supply voltage VDD, and the bootstrap driving circuit can be The voltage across the other circuit components is controlled below the power supply voltage VDD, so that high voltage MOS is not required in the implementation of the bootstrap driving circuit, thereby reducing the cost of circuit implementation.
  • the pull-up switch unit includes: a pull-up switch M H , and the pull-up switch M H is an NMOS transistor;
  • the charging and discharging unit comprises: a capacitor state control switch M12, a bootstrap capacitor C boot ;
  • the drain terminals of the capacitor state control switch M12 and the pull-up switch M H are connected to the power supply voltage VDD; the source terminals of the capacitor state control switch M12 and the pull-up switch M H are respectively connected to the two ends of the bootstrap capacitor C boot ;
  • the stacked circuit unit is connected to the bootstrap capacitor C boot from opposite ends of the connection, the stack state control circuit unit and the capacitance of the gate terminal of the switch M12, a stack switch circuit unit is pulled up to the gate terminal of M H outputs a second driving signal, the capacitor circuit unit stacked the gate terminal of M12 is controlled switches outputs a first driving signal, the first driving voltage signal is 0V drive voltage V Shift said second driving signal is not less than 2 * VDD driving voltage represented by the voltage value V Shift;
  • the charging and discharging unit is configured to: when the pull-up switch M H is not turned on, the first driving signal causes the capacitive state control switch M12 to be turned on, and the power supply voltage VDD to the charging circuit of the bootstrap capacitor Cboot turns on the power supply voltage VDD to the bootstrap capacitor C
  • the boot performs charging; when the pull-up switch M H is turned on, the capacitor state control switch M12 is not turned on, so that the bootstrap capacitor C boot is discharged, so that the potential of other circuit components in the bootstrap driving circuit rises.
  • the stacking circuit unit is configured to adjust the driving voltage V Shift to 0V when the pull-up switch M H is not turned on, and send it to the gate terminal of the capacitor state control switch M12; when the pull-up switch M H is turned on, the driving voltage is V Shift adjusted to at least twice the power supply voltage VDD.
  • the capacitor state control switch M12 When the pull-up switch M H is not turned on, the capacitor state control switch M12 is turned on, and the power supply voltage VDD charges the bootstrap capacitor C boot . At this time, the voltage of the voltage V Cboot of the bootstrap capacitor C boot is equal to the power source.
  • the stacked circuit unit may include two sub-modules, which are a first sub-module and a second sub-module, respectively.
  • the first sub-module includes five connection points in the bootstrap driving circuit
  • the second sub-module includes seven connection points in the bootstrap driving circuit, and the connection relationship is as follows:
  • the first connection point of the first sub-module inputs a power supply voltage VDD, and the second connection point and the third connection point of the first sub-module are respectively connected to two ends of the bootstrap capacitor Cboot , and the fourth connection point input of the first sub-module First control signal
  • the fifth connection point of the first submodule is connected to the first connection point of the second submodule;
  • the second connection point of the second sub-module is input with the power supply voltage VDD, the third connection point of the second sub-module is connected to one end of the bootstrap capacitor Cboot , and the fourth connection point of the second sub-module is input to the source of the pull-up switch M H
  • the extreme source voltage V X the fifth connection point of the second sub-module is connected to the gate terminal of the pull-up switch M H , the sixth connection point of the second sub-module is grounded, and the seventh connection point of the second sub-module is input
  • Second control signal V H_Ctrl first control signal
  • the first sub-module may further include: a first switch tube M1, a fourth switch tube M4, and a fifth switch tube M5; and the second sub-module may further include: a second switch The tube M2, the third switch tube M3, the sixth switch tube M6, the seventh switch tube M7, the eighth switch tube M8, and the ninth switch tube M9.
  • the first switch tube M1, the second switch tube M2, the third switch tube M3, the eighth switch tube M8, and the ninth switch tube M9 are PMOS tubes; the fourth switch tube M4, the fifth switch tube M5, and the sixth switch
  • the tube M6 and the seventh switch tube M7 are NMOS tubes.
  • connection relationship of each switch component is as follows:
  • the source terminal of the fourth switch transistor M4 is connected to the drain terminal of the fifth switch transistor M5; the connection point between the drain terminal of the first switch transistor M1 and the drain terminal of the fourth switch transistor M4 serves as a fifth connection point of the first submodule;
  • the drain terminal of the second switch transistor M2 is connected to the source terminal of the third switch transistor M3, the drain terminal of the sixth switch transistor M6 is connected to the source terminal of the seventh switch transistor M7, and the source terminal and the ninth switch of the eighth switch transistor M8 are connected.
  • the drain terminals of the tube M9 are connected;
  • the gate ends of the first switching transistor M1 and the fourth switching transistor M4 serve as the first connection of the first submodule Point
  • the source terminal of the first switch M1 serves as a second connection point of the first submodule
  • the source terminal of the fifth switch M5 serves as a third connection point of the first submodule
  • the gate end of the fifth switch M5 As a fourth connection point of the first submodule
  • the gate end of the second switch M2 serves as a first connection point of the second submodule
  • the gate ends of the sixth switch M6 and the eighth switch M8 serve as a second connection point of the second submodule
  • the second switch M2 and The source terminals of the sixth switch tube M6 are collectively used as the third connection point of the second sub-module
  • the gate ends of the third switch tube M3 and the seventh switch tube M7 serve as the fourth connection point of the second sub-module
  • the third switch tube M3 The drain terminal, the drain terminal of the seventh switch transistor M7, and the drain terminal of the eighth switch transistor M8 together serve as a fifth connection point of the second submodule
  • the source terminal of the ninth switch transistor M9 serves as a sixth connection point.
  • the gate end of the ninth switching transistor M9 serves as a seventh connection point.
  • V H_Ctrl VDD
  • V X 0V
  • V GH 0V
  • V Shift 0V
  • V Cboot+ VDD
  • V H_Ctrl 0V
  • the inter-electrode voltage (such as the voltage between the source and the drain) of any two of the switching transistors in the stacked circuit unit may exceed the power supply voltage VDD.
  • the transistor connection design of the stacked circuit unit such as the setting and connection mode of M 8 and M 9 , can make the voltage between the poles of any two poles of each switch of M1 to M9 not exceed the power supply voltage VDD, thereby protecting the switch tube. .
  • the bootstrap driving circuit further includes: a voltage limiter and a cache chain unit, specifically:
  • the voltage limiter is a diode series group, and the two ends of the voltage limiter are respectively connected with the source terminal of the capacitor state control switch M12 and the fifth connection point of the second submodule, and the fifth connection point of the second submodule is M3, The connection point of the drain terminals of M7 and M8.
  • the voltage limiter can limit the voltage difference between V Cboot+ and V Shift below the power supply voltage VDD, that is, the glitch that removes the voltage difference between V Cboot+ and V Shift beyond the power supply voltage VDD portion.
  • connection point connection point of a first cache unit and a second sub-chain connection module the connection point between the gate terminal of the second buffer chain units and M H is pull-up switch, the third connection point and the second buffer chain units
  • the four connection points are respectively connected to the two ends of the bootstrap capacitor C boot .
  • the buffer chain unit is configured to increase the driving current of the pull-up switch M H , thereby improving the conduction speed of the pull-up switch M H , wherein the buffer chain unit includes at least one group of switching tubes, and one switching tube group includes two switches in series a tube, such as M10 and M11 in FIG.
  • a fifth connection point of the second sub-module is commonly connected to the gate terminal of the switch transistor M10 and the gate terminal of the switch transistor M11, the drain terminal of the switch transistor M10, and the drain terminal of the switch transistor M11 Connected, the source terminal of the switch M10 and the source terminal of the switch M11 are respectively connected to the two ends of the bootstrap capacitor Cboot , wherein the switch M10 is a PMOS transistor, and the switch M11 is an NMOS transistor.
  • an embodiment of the present invention provides a driving method of a bootstrap driving circuit, which is applied to a bootstrap driving circuit.
  • the bootstrap driving circuit includes a charging and discharging unit, a stacked circuit unit, and a pull-up switching unit.
  • the driving method includes:
  • the stack circuit unit sends a first driving signal to the charging and discharging unit, so that the power supply voltage VDD is turned on to the charging circuit of the charging and discharging unit, and the power supply voltage VDD charges the charging and discharging unit.
  • the stack circuit unit When the pull-up switch unit is not turned on, the stack circuit unit sends a first driving signal to the charging and discharging unit, and the first driving signal enables the charging circuit between the power supply voltage VDD and the charging and discharging unit to be turned on, and the charging circuit is turned on. Thereafter, the power supply voltage VDD is applied to both ends of the charge and discharge unit to charge the charge and discharge unit.
  • the charge and discharge unit discharges the stacked circuit unit, and the stacked circuit unit sends the second drive signal to the pull-up switch unit.
  • the charging and discharging unit Since the charging and discharging unit has been charged while the pull-up switch unit is not conducting, when it is pulled up When the off unit is turned on, the charging and discharging unit discharges the stacked circuit unit, and after receiving the electric energy released by the charging and discharging unit, the stacked circuit unit sends the second driving signal to the pull-up switching unit, and the voltage value of the second driving signal is the power supply voltage. At least twice the voltage of VDD.
  • the charging and discharging unit when the pull-up switch unit is not turned on, the charging and discharging unit is charged, when the pull-up switch unit is not turned on, the charging and discharging unit discharges to the stacking circuit unit, and the pull-up switching unit sends the second driving signal. Due to the presence of the stacked circuit unit, the voltage value of the second driving signal is adjusted to at least twice the voltage value of the power supply voltage VDD, and the voltage discharged by the charging and discharging unit is the power supply voltage VDD, which can be used for other circuit components of the bootstrap driving circuit The voltage at both ends is controlled below the power supply voltage VDD, so that high-voltage MOS is not required in the process of implementing the bootstrap driving circuit, thereby reducing the cost of circuit implementation.
  • the pull-up switch unit includes: a pull-up switch M H ;
  • the charging and discharging unit comprises: a capacitor state control switch M12 and a bootstrap capacitor C boot ;
  • the stacking circuit unit sends a first driving signal to the charging and discharging unit, so that the power supply voltage VDD is turned on to the charging circuit of the charging and discharging unit, and the power supply voltage VDD charges the charging and discharging unit, including:
  • the stack circuit unit adjusts the driving voltage V Shift to 0V and sends it to the gate terminal of the capacitor state control switch M12, so that the capacitor state control switch M12 is turned on, and the power supply voltage VDD is turned on to the charging circuit of the bootstrap capacitor C boot , and the power supply voltage is turned on.
  • VDD charges the bootstrap capacitor Cboot.
  • the pull-up switch M H when the pull-up switch M H nonconductive, due to the pull switch M H is the NMOS transistor, stacked circuit unit pullup switch M H connected terminal, the pull-up switch M H source terminal of the embodiment of the present invention
  • the stack circuit unit sends a driving voltage V Shift with a voltage value of 0V to the gate terminal of the capacitor state control switch M12, so that the capacitor state control switch M12 is turned on, and the power supply voltage VDD reaches the charging circuit of the bootstrap capacitor C boot .
  • the power supply voltage VDD charges the bootstrap capacitor C boot , and the charging step of the charging and discharging unit is specifically described, so that the scheme is more specific.
  • the pull-up switch unit includes: a pull-up switch M H ;
  • the charging and discharging unit comprises: a capacitor state control switch M12 and a bootstrap capacitor C boot ;
  • the charging and discharging unit discharges the stacked circuit unit, and the stacked circuit unit sends the second driving signal to the pull-up switching unit, including:
  • the capacitor state control switch M12 is not turned on, the bootstrap capacitor Cboot discharges the stacked circuit unit, and the stack circuit unit adjusts the driving voltage V Shift to at least twice the power supply voltage VDD, and sends it to the gate terminal of the pull-up switch M H .
  • Embodiments of the present invention when the pull-up switch M H is turned on, since the pull-up switch M H is the NMOS transistor, is connected to a source terminal of stacked circuit unit and the pull switch M H, a source pull-up switch M H extreme voltage
  • the capacitor state control switch M12 is not turned on, the bootstrap capacitor Cboot discharges the stacked circuit unit, and the stack circuit unit adjusts the driving voltage V Shift to at least 2*VDD, and sends it to the gate terminal of the pull-up switch M H
  • the charging step of the charging and discharging unit and the forming of the second driving signal by the stacked circuit unit are specifically described to make the scheme clearer.
  • the stacking circuit unit includes: a first submodule, and a second submodule;
  • the first sub-module When the pull-up switch M H is not turned on, the first sub-module outputs a control voltage V G2 to the second sub-module, the control voltage V G2 is equal to 0V, and the second sub-module outputs a driving voltage with a voltage value of 0V according to the control voltage V G2 .
  • V Shift When the pull-up switch M H is not turned on, the first sub-module outputs a control voltage V G2 to the second sub-module, the control voltage V G2 is equal to 0V, and the second sub-module outputs a driving voltage with a voltage value of 0V according to the control voltage V G2 .
  • the control voltage V G2 is equal to the power supply voltage VDD, and the second sub-module outputs a driving voltage V Shift having a voltage value of at least 2*VDD according to the control voltage V G2 .
  • the first sub-module outputs a control voltage V G2 of different voltage values to the second sub-module according to the conduction or non-conduction state of the pull-up switch M H , and the second sub-module is controlled according to different voltage values.
  • V G2 voltage adjustment voltage V Shift value of the driving voltage i.e. the output of the first drive signal or the second driving signal
  • a method of stacking the circuit unit outputs a first driving signal and the second drive signal will be described, to give a clear driving circuit unit stacked The process of the signal.
  • CMOS complementary metal oxide semiconductor
  • VDD power supply voltage
  • the disclosed apparatus can be implemented in other ways.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

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Abstract

一种自举驱动电路及其驱动方法，用于提供一种使用低耐压元器件的自举驱动电路。自举驱动电路包括：充放电单元，堆叠电路单元以及上拉开关单元；当上拉开关单元不导通时，以使得电源电压VDD到充放电单元的充电电路导通，电源电压VDD对充放电单元进行充电；当上拉开关单元导通时，充放电单元对堆叠电路单元放电，堆叠电路单元向上拉开关单元发送第二驱动信号，第二驱动信号的电压值为电源电压VDD的电压值的至少两倍。

Description

一种自举驱动电路及其驱动方法 技术领域
本发明涉及电路领域，尤其涉及一种自举驱动电路及其驱动方法。
背景技术
开关电感电源为使用最为广泛的片外或片内电源。然而，正极金属氧化半导体(PMOS，positive channel Metal Oxide Semiconductor)管作为其上拉开关，负极金属氧化半导体(NMOS，Negative channel Metal Oxide Semiconductor)管作为其下拉开关的电路设计逐渐被淘汰。取而代之的则是上拉开关和下拉开关都采用NMOS管设计，从而提高开关电源的转化效率，且降低开关电源的面积。然而上拉NMOS管的驱动电路设计则成为难题。
在现有技术中，存在一种高耐压晶体管组成的上拉驱动电路，驱动上拉NMOS管的现行驱动电路基本采用自举驱动电路。然而，这类自举驱动电路都要求其自身的驱动电路的晶体管具备高耐压的特性。相比通用的晶体管库，高耐压的晶体管的需求使得驱动电路的实现难度及成本上升。
如图1所示，现有技术中通用的解决办法则是采用上拉自举驱动电路来驱动上拉开关管MH。具体的，自举驱动电路主要采用额外的电容Cboot来实现MH的栅极电压能够达到比VDD还要高的电压。这样的话，Vx端的电压，也即是MH的源极的电压，则能达到VDD的电压值。由于NMOS的导通特性，MH管的源极电压要达到VDD，要求MH管的栅极要比MH管的源极的电压更高，在这种开关电源的应用情况下，通常需要MH管的栅极电压达到2*VDD。
因此，现有技术中自举驱动电路的缺陷为：驱动电路中需采用高耐压MOS，从而使得电路实现的成本提高。
发明内容
本发明实施例提供了一种自举驱动电路及其驱动方法，用于提供一种使用低耐压元器件的自举驱动电路。
本发明第一方面提供一种自举驱动电路，包括：
充放电单元，堆叠电路单元以及上拉开关单元；
当上拉开关单元不导通时，堆叠电路单元向充放电单元发送第一驱动信号，以使得电源电压VDD到充放电单元的充电电路导通，电源电压VDD对充放电单元进行充电；
当上拉开关单元导通时，充放电单元对堆叠电路单元放电，堆叠电路单元向上拉开关单元发送第二驱动信号，第二驱动信号的电压值为电源电压VDD的电压值的至少两倍。
上拉开关单元为自举驱动电路的驱动对象，若要驱动上拉开关单元，则要向上拉开关单元发送至少两倍于电源电压VDD的电压值的驱动信号，自举驱动电路驱动的过程中，当上拉开关单元不导通时，堆叠电路单元向充放电单元发送第一驱动信号，充放电单元根据第一驱动信号通过电源电压VDD进行充电；当上拉开关单元导通时，充放电单元对堆叠电路单元放电，堆叠电路单元向上拉开关单元发送第二驱动信号，第二驱动信号的电压值为电源电压VDD的电压值的至少两倍；由于堆叠电路单元的存在，将第二驱动信号的电压值调节为电源电压VDD的电压值的至少两倍，并且充当电单元放电的电压为电源电压VDD，可以将自举驱动电路的其它电路元件的两端电压控制在电源电压VDD以下，使得在自举驱动电路实现的过程中无需使用高耐压MOS，从而降低电路实现的成本。
结合本发明第一方面，本发明第一方面第一实施方式中，
上拉开关单元包括：上拉开关MH；
充放电单元包括：电容状态控制开关M12和自举电容Cboot；
电容状态控制开关M12和上拉开关MH的漏极端接入电源电压VDD；电容状态控制开关M12和上拉开关MH的源极端分别与自举电容Cboot的两端相连；
堆叠电路单元与自举电容Cboot的两端连接，堆叠电路单元与电容状态控制开关M12的栅极端连接，堆叠电路单元向上拉开关MH的栅极端输出第二驱动信号，堆叠电路单元向电容控制开关M12的栅极端输出第一驱动信号，第一驱动信号用电压值为0V的驱动电压VShift表示，第二驱动信号用电压值不 小于2*VDD的驱动电压VShift表示。
当上拉开关MH不导通时，堆叠电路单元向电容控制开关M12的栅极端输出第一驱动信号，第一驱动信号用电压值为0V的驱动电压VShift表示，第一驱动信号使得电容控制开关M12导通，电容控制开关M12导通之后通过电源电压VDD对自举电容Cboot进行充电，当上拉开关MH导通时，电容控制开关M12不导通，自举电容Cboot对堆叠电路单元进行放电，使得堆叠电路单元向上拉开关MH的栅极端输出第二驱动信号，第二驱动信号用电压值不小于2*VDD的驱动电压VShift表示，通过改变充放电单元中电容控制开关M12的导通状态来实现充放电单元的充电及放电，使得本方案的具体实施能落到实处。
结合本发明第一方面第一实施方式，本发明第一方面第二实施方式中，堆叠电路单元向充放电单元发送第一驱动信号，以使得电源电压VDD到充放电单元的充电电路导通，电源电压VDD对充放电单元进行充电，包括：
堆叠电路单元将驱动电压VShift调节至0V，并发送至电容状态控制开关M12的栅极端，使得电容状态控制开关M12导通，电源电压VDD到自举电容Cboot的充电电路导通，电源电压VDD对自举电容Cboot进行充电。
当上拉开关MH不导通时，由于上拉开关MH为NMOS管，堆叠电路单元与上拉开关MH的源极端相连，上拉开关MH的源极端的电压值为0V时，堆叠电路单元将驱动电压VShift调节至0V，发送至电容状态控制开关M12的栅极端，电容状态控制开关M12导通，电源电压VDD到自举电容Cboot的充电电路导通，使得电源电压VDD施加在自举电容Cboot的两端，自举电容Cboot进行充电，对充放电单元实现充电功能的具体说明，使得方案更加具体。
结合本发明第一方面第一实施方式，本发明第一方面第三实施方式中，充放电单元对堆叠电路单元放电，堆叠电路单元向上拉开关单元发送第二驱动信号，包括：
电容状态控制开关M12不导通，自举电容Cboot对堆叠电路单元放电，堆叠电路单元将驱动电压VShift调节至电源电压VDD的至少两倍，发送至上拉开关MH的栅极端。
当上拉开关MH导通时，由于上拉开关MH为NMOS管，堆叠电路单元与上 拉开关MH的源极端相连，上拉开关MH的源极端的电压值为VDD时，电容状态控制开关M12不导通，自举电容Cboot对堆叠电路单元放电，堆叠电路单元将驱动电压VShift调节至至少2*VDD，发送至上拉开关MH的栅极端，对充放电单元实现放电功能以及堆叠电路单元形成第二驱动信号进行具体说明，使得方案更加清晰。
结合本发明第一方面第二实施方式或第一方面第三实施方式，本发明第一方面第四实施方式中，
堆叠电路单元包括：第一子模块，第二子模块；
第一子模块向第二子模块输出控制电压VG2，第二子模块向电容状态控制开关M12和上拉开关MH的栅极端输出驱动电压VShift，当上拉开关MH不导通时，控制电压VG2等于0V；当上拉开关MH导通时，控制电压VG2等于电源电压VDD。
当上拉开关MH不导通时，上拉开关MH的源极端电压值变为0V，第一子模块与上拉开关MH的源极端相连，使得第一子模块向第二子模块输出的控制电压VG2变为0V，第二子模块接收第一子模块的控制电压VG2，向电容状态控制开关M12输出电压值为0V的驱动电压VShift，即第一驱动信号；当上拉开关MH导通时，上拉开关MH的源极端电压变为VDD，第一子模块向第二子模块输出的控制电压VG2变为VDD，并且充放电单元对第二子模块放电，使得第二子模块向上拉开关MH输出电压值为至少2*VDD的驱动电压VShift，即第二驱动信号，第一子模块根据上拉开关MH的导通或不导通状态，输出不同的控制电压VG2，第二子模块根据不同的控制电压VG2调节驱动电压VShift的电压值，即输出第一驱动信号或第二驱动信号，通过堆叠电路单元中第一子模块和第二子模块之间的控制电压VG2的改变来实现堆叠电路单元输出第一驱动信号和第二驱动信号，明确了堆叠电路单元得到驱动信号的过程。
结合本发明第一方面第四实施方式，本发明第一方面第五实施方式中，
第一子模块包括：第一开关管M1、第四开关管M4和第五开关管M5；
第二子模块包括：第二开关管M2、第三开关管M3、第六开关管M6、第七开关管M7、第八开关管M8和第九开关管M9；所述第四开关管M4的源极端与第五开关管M5的漏极端相连，第一开关管M1的漏极端与第四开关管 M4的漏极端相连；
第二开关管M2的漏极端与第三开关管M3的源级端相连，第六开关管M6的漏极端与第七开关管M7的源极端相连，第八开关管M8的源极端与第九开关管M9的漏极端相连；
第一开关管M1、第二开关管M2、第三开关管M3、第八开关管M8和第九开关管M9为PMOS管，第四开关管M4、第五开关管M5、第六开关管M6和第七开关管M7为NMOS管，上拉开关MH为NMOS管。
本发明第二方面提供一种自举驱动电路的驱动方法，应用于自举驱动电路，自举驱动电路包括充放电单元、堆叠电路单元及上拉开关单元，驱动方法包括：
当上拉开关单元不导通时，堆叠电路单元向充放电单元发送第一驱动信号，以使得电源电压VDD到充放电单元的充电电路导通，电源电压VDD对充放电单元进行充电；
当上拉开关单元导通时，充放电单元对堆叠电路单元放电，堆叠电路单元向上拉开关单元发送第二驱动信号，第二驱动信号的电压值为电源电压VDD的电压值的至少两倍。
上拉开关单元处于不导通状态时，堆叠电路单元向充放电单元发送第一驱动信号，电源电压VDD到充放电单元的充电电路导通，电源电压VDD对充放电单元进行充电；当上拉开关单元导通时，充放电单元对堆叠电路单元放电，堆叠电路单元向上拉开关单元发送第二驱动信号，由于堆叠电路单元的存在，第二驱动信号的电压值可以调节为电源电压VDD的电压值的至少两倍，并且充当电单元放电的电压为电源电压VDD，可以将自举驱动电路的其它电路元件的两端电压控制在电源电压VDD以下，使得在自举驱动电路实现驱动方法的过程中无需使用高耐压MOS，从而降低电路实现的成本。
结合本发明第二方面，本发明第二方面第一实施方式中，
上拉开关单元包括：上拉开关MH；
充放电单元包括：电容状态控制开关M12和自举电容Cboot；
堆叠电路单元向充放电单元发送第一驱动信号，以使得电源电压VDD到充放电单元的充电电路导通，电源电压VDD对充放电单元进行充电，包括：
堆叠电路单元将驱动电压VShift调节至0V，并发送至电容状态控制开关M12的栅极端，使得电容状态控制开关M12导通，电源电压VDD到自举电容Cboot的充电电路导通，电源电压VDD对自举电容Cboot进行充电。
当上拉开关MH不导通时，由于上拉开关MH为NMOS管，堆叠电路单元与上拉开关MH的源极端相连，上拉开关MH的源极端的电压值为0V时，堆叠电路单元向电容状态控制开关M12的栅极端发送电压值为0V的驱动电压VShift，使得电容状态控制开关M12导通，电源电压VDD到自举电容Cboot的充电电路导通，电源电压VDD对自举电容Cboot进行充电，对充放电单元的充电步骤进行具体说明，使得方案更加具体。
结合本发明第二方面，本发明第二方面第二实施方式中，
上拉开关单元包括：上拉开关MH；
充放电单元包括：电容状态控制开关M12和自举电容Cboot；
充放电单元对堆叠电路单元放电，堆叠电路单元向上拉开关单元发送第二驱动信号，包括：
电容状态控制开关M12不导通，自举电容Cboot对堆叠电路单元放电，堆叠电路单元将驱动电压VShift调节至电源电压VDD的至少两倍，发送至上拉开关MH的栅极端。
当上拉开关MH导通时，由于上拉开关MH为NMOS管，堆叠电路单元与上拉开关MH的源极端相连，上拉开关MH的源极端的电压值为VDD时，电容状态控制开关M12不导通，自举电容Cboot对堆叠电路单元放电，堆叠电路单元将驱动电压VShift调节至至少2*VDD，发送至上拉开关MH的栅极端，对充放电单元放电步骤以及堆叠电路单元形成第二驱动信号进行具体说明，使得方案更加清晰。
结合本发明第一方面第二实施方式或第一方面第三实施方式，本发明第一方面第四实施方式中，
堆叠电路单元包括：第一子模块，第二子模块；
当上拉开关MH不导通时，第一子模块向第二子模块输出控制电压VG2，控制电压VG2等于0V，第二子模块根据控制电压VG2输出电压值为0V的驱动电压VShift；
当上拉开关MH导通时，控制电压VG2等于电源电压VDD，第二子模块根据控制电压VG2输出电压值为至少2*VDD的驱动电压VShift。
第一子模块根据上拉开关MH的导通或不导通状态，向第二子模块输出不同电压值的控制电压VG2，第二子模块根据不同电压值的控制电压VG2调节驱动电压VShift的电压值，即输出第一驱动信号或第二驱动信号，对堆叠电路单元输出第一驱动信号和第二驱动信号的方法进行说明，明确了堆叠电路单元得到驱动信号的过程。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是现有技术自举驱动电路的一个示意图；
图2是本发明实施例自举驱动电路的一个示意图；
图3是本发明实施例自举驱动电路的另一个示意图；
图4是本发明实施例自举驱动电路的另一个示意图；
图5是本发明实施例自举驱动电路的另一个示意图；
图6是本发明实施例自举驱动电路的驱动方法的一个示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明的说明书和权利要求书及上述附图中的术语“第一”、“第二”、“第三”、“第四”等(如果存在)是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本发明的实施例如能够以除了在这里图示或描述的那些以外的顺序实 施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、***、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
请参阅图2，本发明实施例中自举驱动电路的一个实施例包括：
充放电单元，堆叠电路单元以及上拉开关单元；
当上拉开关单元不导通时，堆叠电路单元向充放电单元发送第一驱动信号，以使得电源电压VDD到充放电单元的充电电路导通，电源电压VDD对充放电单元进行充电；
当上拉开关单元导通时，充放电单元对堆叠电路单元放电，堆叠电路单元向上拉开关单元发送第二驱动信号，第二驱动信号的电压值为电源电压VDD的电压值的至少两倍。
本发明实施例中，当上拉开关单元不导通时，堆叠电路单元向充放电单元发送第一驱动信号，以使得电源电压VDD到充放电单元的充电电路导通，电源电压VDD对充放电单元进行充电；当上拉开关单元导通时，充放电单元对堆叠电路单元放电，堆叠电路单元向上拉开关单元发送第二驱动信号，第二驱动信号的电压值为电源电压VDD的电压值的至少两倍；由于堆叠电路单元的存在，将第二驱动信号的电压值调节为电源电压VDD的电压值的至少两倍，并且充放电单元放电的电压为电源电压VDD，可以将自举驱动电路的其它电路元件的两端电压控制在电源电压VDD以下，使得在自举驱动电路实现的过程中无需使用高耐压MOS，从而降低电路实现的成本。
请参阅图3，本发明的一些实施例中，
上拉开关单元包括：上拉开关MH，上拉开关MH为NMOS管；
充放电单元包括：电容状态控制开关M12，自举电容Cboot；
电容状态控制开关M12和上拉开关MH的漏极端接入电源电压VDD；电容状态控制开关M12和上拉开关MH的源极端分别与自举电容Cboot的两端相连；
堆叠电路单元与自举电容Cboot的两端连接，堆叠电路单元与电容状态控制开关M12的栅极端连接，堆叠电路单元向上拉开关MH的栅极端输出第二 驱动信号，堆叠电路单元向电容控制开关M12的栅极端输出第一驱动信号，第一驱动信号用电压值为0V的驱动电压VShift表示，第二驱动信号用电压值不小于2*VDD的驱动电压VShift表示；
充放电单元用于当上拉开关MH不导通时，第一驱动信号使得电容状态控制开关M12导通，电源电压VDD到自举电容Cboot的充电电路导通电源电压VDD对自举电容Cboot进行充电；当上拉开关MH导通时，电容状态控制开关M12不导通，使得自举电容Cboot放电，使得自举驱动电路中的其它电路元件的电势升高。
堆叠电路单元用于当上拉开关MH不导通时，将驱动电压VShift调节至0V，并发送至电容状态控制开关M12的栅极端；当上拉开关MH导通时，将驱动电压VShift调节至电源电压VDD的至少两倍。
堆叠电路单元对电路中的电信号进行调节时，堆叠电路单元需要输入额外的控制信号，控制信号包括：第一控制信号
Figure PCTCN2015097682-appb-000001
和第二控制信号VH_Ctrl，第一控制信号
Figure PCTCN2015097682-appb-000002
与第二控制信号VH_Ctrl是一对相反的位脉冲电压信号，当上拉开关MH导通的时候，第二控制信号VH_Ctrl＝0V，第一控制信号
Figure PCTCN2015097682-appb-000003
当上拉开关MH不导通的时候，第二控制信号VH_Ctrl＝VDD，第一控制信号
Figure PCTCN2015097682-appb-000004
Figure PCTCN2015097682-appb-000005
当上拉开关MH不导通时，电容状态控制开关M12导通，电源电压VDD对自举电容Cboot进行充电，此时，自举电容Cboot的两端电压VCboot的电压值等于电源电压VDD，第二控制信号VH_Ctrl＝VDD，上拉开关MH的源极电压VX＝0V，驱动电压VShift＝0V。
当上拉开关MH导通时，电容状态控制开关M12不导通，自举电容Cboot向堆叠电路单元放电，此时，自举电容Cboot的两端电压VCboot＝VDD，第一控制信号上拉开关MH的源极电压VX＝VDD，驱动电压VShift＝2*VDD。
请参阅图4，本发明的一些实施例中，堆叠电路单元可以包括两个子模块，分别为第一子模块和第二子模块。
第一子模块在自举驱动电路中包括有5个连接点，第二子模块在自举驱动电路中包括有7个连接点，连接关系如下：
第一子模块的第一连接点输入电源电压VDD，第一子模块的第二连接点和第三连接点分别与自举电容Cboot的两端相连，第一子模块的第四连接点输入第一控制信号
Figure PCTCN2015097682-appb-000007
第一子模块的第五连接点与第二子模块的第一连接点相连；
第二子模块的第二连接点输入电源电压VDD，第二子模块的第三连接点与自举电容Cboot的一端相连，第二子模块的第四连接点输入上拉开关MH的源极端的源极电压VX，第二子模块的第五连接点与上拉开关MH的栅极端相连，第二子模块的第六连接点接地，第二子模块的第七连接点输入第二控制信号VH_Ctrl，第一控制信号
Figure PCTCN2015097682-appb-000008
与第二控制信号VH_Ctrl是一对相反的位脉冲电压信号，当上拉开关MH导通的时候，第二控制信号VH_Ctrl＝0V，第一控制信号
Figure PCTCN2015097682-appb-000009
当上拉开关MH不导通的时候，第二控制信号VH_Ctrl＝VDD，第一控制信号
Figure PCTCN2015097682-appb-000010
第一子模块向第二子模块输出控制电压VG2；第二子模块向上拉开关MH的栅极端输出驱动电压VShift，当上拉开关MH不导通时，控制电压VG2＝0V；当上拉开关MH导通时，控制电压VG2＝VDD。
请参阅图5，本发明的一些实施例中，第一子模块还可以包括：第一开关管M1、第四开关管M4和第五开关管M5；第二子模块还可以包括：第二开关管M2、第三开关管M3、第六开关管M6、第七开关管M7、第八开关管M8和第九开关管M9。其中，第一开关管M1、第二开关管M2、第三开关管M3、第八开关管M8和第九开关管M9为PMOS管；第四开关管M4、第五开关管M5、第六开关管M6和第七开关管M7为NMOS管。
在实际应用中，各个开关管元件的连接关系如下：
第四开关管M4的源极端与第五开关管M5的漏极端相连；第一开关管M1的漏极端与第四开关管M4的漏极端的相连点作为第一子模块的第五连接点；
第二开关管M2的漏极端与第三开关管M3的源极端相连，第六开关管M6的漏极端与第七开关管M7的源极端相连，第八开关管M8的源极端与第九开关管M9的漏极端相连；
第一开关管M1和第四开关管M4的栅极端作为第一子模块的第一连接 点，第一开关管M1的源极端作为第一子模块的第二连接点，第五开关管M5的源极端作为所述第一子模块的第三连接点，第五开关管M5的栅极端作为所述第一子模块的第四连接点；
第二开关管M2的栅极端作为第二子模块的第一连接点，第六开关管M6和第八开关管M8的栅极端作为第二子模块的第二连接点，第二开关管M2及第六开关管M6的源极端共同作为第二子模块的第三连接点，第三开关管M3及第七开关管M7的栅极端作为第二子模块的第四连接点，第三开关管M3的漏极端、第七开关管M7的漏极端以及第八开关管M8的漏极端的连接点共同作为第二子模块的第五连接点，第九开关管M9的源极端作为第六连接点，第九开关管M9的栅极端作为第七连接点。
当MH不导通时，则经过M12对Cboot进行充电，此时，VH_Ctrl＝VDD，
Figure PCTCN2015097682-appb-000011
Figure PCTCN2015097682-appb-000012
VX＝0V，VGH＝0V，VShift＝0V，VCboot+＝VDD；
当MH导通时，VH_Ctrl＝0V，
Figure PCTCN2015097682-appb-000013
此时，M4和M5导通，VG2＝VX，M2导通，使得VD2的电压值上拉至与VCboot+相等，VD2＝VCboot+；M3导通，将VShift的电压值上拉至与VD2相等，VShift＝VD2＝VCboot+；由于M12的栅极电压为VGH＝VShift＝VCboot+，因此使得M12不导通，M12不导通使得自举电容Cboot向自举驱动电路放电，此时VX＝VDD，VCboot+＝2*VDD，使得M1导通，然后M2、M3、M4、M5都不导通，但由于VCboot+此时已经等于2*VDD,M6和M7是导通的，VShift会被上拉至VCboot+，最终VX＝VDD,VShift＝VCboot+＝2*VDD。
在本发明实施例中，在非理想状态下，堆叠电路单元中有些开关管的任意两极的极间电压(如源极和漏极之间的电压)可能会超过电源电压VDD。这时候堆叠电路单元的晶体管连接设计时，如M8与M9的设置和连接方式可以使得M1至M9各个开关管的任意两极的极间电压不超过电源电压VDD，起到保护开关管的作用。
同参阅图5，本发明的一些实施例中，自举驱动电路还包括：限压器和缓存链单元，具体的：
限压器为二极管串联组，限压器的两端分别与电容状态控制开关M12的源极端以及第二子模块的第五连接点相连，第二子模块的第五连接点即M3、 M7及M8的漏极端的连接点。
限压器可以将将VCboot+与VShift的电压差限制在电源电压VDD以下，即能够去除VCboot+与VShift的电压差超过电源电压VDD部分的毛刺。
缓存链单元的第一连接点与第二子模块的第五连接点连接，缓存链单元的第二连接点与上拉开关MH的栅极端之间，缓存链单元的第三连接点和第四连接点分别与自举电容Cboot的两端连接。
缓存链单元用于提高上拉开关MH的驱动电流，从而提高上拉开关MH导通速度，其中，缓存链单元至少包括一组的开关管组，一个开关管组包括串联的两个开关管，如图5中的M10和M11；第二子模块的第五连接点与开关管M10的栅极端以及开关管M11的栅极端共同连接，开关管M10的漏极端以及开关管M11的漏极端相连接，开关管M10的源极端以及开关管M11的源极端分别连接自举电容Cboot的两端，其中，开关管M10为PMOS管，开关管M11为NMOS管。
上述实施例对自举驱动电路进行了说明，下面通过实施例对自举驱动电路的驱动方法进行详细说明。
请参阅图6，本发明实施例提供一种自举驱动电路的驱动方法，应用于自举驱动电路，自举驱动电路包括充放电单元、堆叠电路单元及上拉开关单元，驱动方法包括：
601、当上拉开关单元不导通时，堆叠电路单元向充放电单元发送第一驱动信号，以使得电源电压VDD到充放电单元的充电电路导通，电源电压VDD对充放电单元进行充电；
当上拉开关单元不导通时，堆叠电路单元向充放电单元发送第一驱动信号，第一驱动信号能够使得电源电压VDD到充放电单元之间的充电电路变为导通，充电电路导通之后，电源电压VDD施加在充放电单元的两端，对充放电单元进行充电。
602、当上拉开关单元导通时，充放电单元对堆叠电路单元放电，堆叠电路单元向上拉开关单元发送第二驱动信号。
由于充放电单元在上拉开关单元不导通状态下已经进行了充电，当上拉开 关单元导通时，充放电单元对堆叠电路单元进行放电，堆叠电路单元接收到充放电单元所释放的电能后，向上拉开关单元发送第二驱动信号，第二驱动信号的电压值为电源电压VDD的电压值的至少两倍。
本发明实施例中，当上拉开关单元不导通时，充放电单元的充电，当上拉开关单元不导通，充放电单元向堆叠电路单元放电，向上拉开关单元发送第二驱动信号，由于堆叠电路单元的存在，第二驱动信号的电压值调节为电源电压VDD的电压值的至少两倍，并且充放电单元放电的电压为电源电压VDD，可以将自举驱动电路的其它电路元件的两端电压控制在电源电压VDD以下，使得在自举驱动电路实现的过程中无需使用高耐压MOS，从而降低电路实现的成本。
可选的，本发明的一些实施例中，
上拉开关单元包括：上拉开关MH；
充放电单元包括：电容状态控制开关M12和自举电容Cboot；
堆叠电路单元向充放电单元发送第一驱动信号，以使得电源电压VDD到充放电单元的充电电路导通，电源电压VDD对充放电单元进行充电，包括：
堆叠电路单元将驱动电压VShift调节至0V，并发送至电容状态控制开关M12的栅极端，使得电容状态控制开关M12导通，电源电压VDD到自举电容Cboot的充电电路导通，电源电压VDD对自举电容Cboot进行充电。
本发明实施例中，当上拉开关MH不导通时，由于上拉开关MH为NMOS管，堆叠电路单元与上拉开关MH的源极端相连，上拉开关MH的源极端的电压值为0V时，堆叠电路单元向电容状态控制开关M12的栅极端发送电压值为0V的驱动电压VShift，使得电容状态控制开关M12导通，电源电压VDD到自举电容Cboot的充电电路导通，电源电压VDD对自举电容Cboot进行充电，对充放电单元的充电步骤进行具体说明，使得方案更加具体。
可选的，本发明的一些实施例中，
上拉开关单元包括：上拉开关MH；
充放电单元包括：电容状态控制开关M12和自举电容Cboot；
充放电单元对堆叠电路单元放电，堆叠电路单元向上拉开关单元发送第二驱动信号，包括：
电容状态控制开关M12不导通，自举电容Cboot对堆叠电路单元放电，堆叠电路单元将驱动电压VShift调节至电源电压VDD的至少两倍，发送至上拉开关MH的栅极端。
本发明实施例中，当上拉开关MH导通时，由于上拉开关MH为NMOS管，堆叠电路单元与上拉开关MH的源极端相连，上拉开关MH的源极端的电压值为VDD时，电容状态控制开关M12不导通，自举电容Cboot对堆叠电路单元放电，堆叠电路单元将驱动电压VShift调节至至少2*VDD，发送至上拉开关MH的栅极端，对充放电单元放电步骤以及堆叠电路单元形成第二驱动信号进行具体说明，使得方案更加清晰。
可选的，本发明的一些实施例中，
堆叠电路单元包括：第一子模块，第二子模块；
当上拉开关MH不导通时，第一子模块向第二子模块输出控制电压VG2，控制电压VG2等于0V，第二子模块根据控制电压VG2输出电压值为0V的驱动电压VShift；
当上拉开关MH导通时，控制电压VG2等于电源电压VDD，第二子模块根据控制电压VG2输出电压值为至少2*VDD的驱动电压VShift。
本发明实施例中，第一子模块根据上拉开关MH的导通或不导通状态，向第二子模块输出不同电压值的控制电压VG2，第二子模块根据不同电压值的控制电压VG2调节驱动电压VShift的电压值，即输出第一驱动信号或第二驱动信号，对堆叠电路单元输出第一驱动信号和第二驱动信号的方法进行说明，明确了堆叠电路单元得到驱动信号的过程。
在实际的应用场景中，如现今电子芯片中经常所需的片内或片外开关式电感电源的开关管，很多时候要求开关管的驱动电路尽可能采用通用的标准互补金属氧化半导体(CMOS，Complementary Metal Oxide Semiconductor)工艺。这样一来，就能使得驱动电路尽可能的片内集成，减少额外的物料清单，以节省成本。然而，驱动电路的晶体管耐压要求较高时，则达到这一点。而本发明实施例则解决了这一棘手问题，使得驱动电路的耐压控制在电源电压VDD以下，满足了电子芯片的主流需求。
在本申请所提供的几个实施例中，应该理解到，所揭露的装置可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个***，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本发明各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应所述以权利要求的保护范围为准。

Claims (10)

  1. 一种自举驱动电路，其特征在于，包括：
    充放电单元，堆叠电路单元以及上拉开关单元；
    当所述上拉开关单元不导通时，所述堆叠电路单元向所述充放电单元发送第一驱动信号，以使得电源电压VDD到所述充放电单元的充电电路导通，所述电源电压VDD对所述充放电单元进行充电；
    当所述上拉开关单元导通时，所述充放电单元对所述堆叠电路单元放电，所述堆叠电路单元向所述上拉开关单元发送第二驱动信号，所述第二驱动信号的电压值为所述电源电压VDD的电压值的至少两倍。
  2. 根据权利要求1所述的自举驱动电路，其特征在于，
    所述上拉开关单元包括：上拉开关MH；
    所述充放电单元包括：电容状态控制开关M12和自举电容Cboot；
    所述电容状态控制开关M12和所述上拉开关MH的漏极端接入电源电压VDD，所述电容状态控制开关M12和所述上拉开关MH的源极端分别与所述自举电容Cboot的两端相连；
    所述堆叠电路单元与所述自举电容Cboot的两端连接，所述堆叠电路单元与所述电容状态控制开关M12的栅极端连接，所述堆叠电路单元向所述上拉开关MH的栅极端输出所述第二驱动信号，所述堆叠电路单元向所述电容控制开关M12的栅极端输出所述第一驱动信号，所述第一驱动信号用电压值为0V的驱动电压VShift表示，所述第二驱动信号用电压值不小于2*VDD的驱动电压VShift表示。
  3. 根据权利要求2所述的自举驱动电路，其特征在于，所述堆叠电路单元向所述充放电单元发送第一驱动信号，以使得电源电压VDD到所述充放电单元的充电电路导通，所述电源电压VDD对所述充放电单元进行充电，包括：
    所述堆叠电路单元将所述驱动电压VShift调节至0V，并发送至所述电容状态控制开关M12的栅极端，使得所述电容状态控制开关M12导通，电源电压VDD到所述自举电容Cboot的充电电路导通，所述电源电压VDD对所述自举电容Cboot进行充电。
  4. 根据权利要求2所述的自举驱动电路，其特征在于，所述充放电单元对 所述堆叠电路单元放电，所述堆叠电路单元向所述上拉开关单元发送第二驱动信号，包括：
    所述电容状态控制开关M12不导通，所述自举电容Cboot对所述堆叠电路单元放电，所述堆叠电路单元将所述驱动电压VShift调节至所述电源电压VDD的至少两倍，发送至所述上拉开关MH的栅极端。
  5. 根据权利要求3或4所述的自举驱动电路，其特征在于，
    所述堆叠电路单元包括：第一子模块，第二子模块；
    所述第一子模块向所述第二子模块输出控制电压VG2，所述第二子模块向所述电容状态控制开关M12和所述上拉开关MH的栅极端输出驱动电压VShift，当所述上拉开关MH不导通时，所述控制电压VG2等于0V；当所述上拉开关MH导通时，所述控制电压VG2等于所述电源电压VDD。
  6. 根据权利要求5所述的自举驱动电路，其特征在于，所述自举驱动电路还包括：限压器及缓存链单元；
    所述限压器为二极管串联组，所述限压器的两端分别与所述电容状态控制开关M12的源极端以及所述第二子模块相连。
    所述缓存链单元与所述第二子模块连接，所述缓存链单元与所述上拉开关MH的栅极端连接，所述缓存链单元与所述自举电容Cboot的两端连接。
  7. 一种自举驱动电路的驱动方法，其特征在于，应用于自举驱动电路，所述自举驱动电路包括充放电单元、堆叠电路单元及上拉开关单元，所述驱动方法包括：
    当上拉开关单元不导通时，所述堆叠电路单元向所述充放电单元发送第一驱动信号，以使得电源电压VDD到所述充放电单元的充电电路导通，所述电源电压VDD对充放电单元进行充电；
    当所述上拉开关单元导通时，所述充放电单元对所述堆叠电路单元放电，所述堆叠电路单元向所述上拉开关单元发送第二驱动信号，所述第二驱动信号的电压值为所述电源电压VDD的电压值的至少两倍。
  8. 根据权利要求7所述的驱动方法，其特征在于，
    所述上拉开关单元包括：上拉开关MH；
    所述充放电单元包括：电容状态控制开关M12和自举电容Cboot；
    所述堆叠电路单元向充放电单元发送第一驱动信号，以使得电源电压VDD到所述充放电单元的充电电路导通，所述电源电压VDD对充放电单元进行充电，包括：
    所述堆叠电路单元将驱动电压VShift调节至0V，并发送至所述电容状态控制开关M12的栅极端，使得所述电容状态控制开关M12导通，电源电压VDD到所述自举电容Cboot的充电电路导通，所述电源电压VDD对所述自举电容Cboot进行充电。
  9. 根据权利要求7所述的驱动方法，其特征在于，
    所述上拉开关单元包括：上拉开关MH；
    所述充放电单元包括：电容状态控制开关M12和自举电容Cboot；
    所述充放电单元对所述堆叠电路单元放电，所述堆叠电路单元向所述上拉开关单元发送第二驱动信号，包括：
    所述电容状态控制开关M12不导通，所述自举电容Cboot对所述堆叠电路单元放电，所述堆叠电路单元将所述驱动电压VShift调节至所述电源电压VDD的至少两倍，发送至所述上拉开关MH的栅极端。
  10. 根据权利要求8或9所述的方法，其特征在于，
    所述堆叠电路单元包括：第一子模块，第二子模块；
    当所述上拉开关MH不导通时，所述第一子模块向所述第二子模块输出控制电压VG2，所述控制电压VG2等于0V，所述第二子模块根据所述控制电压VG2输出电压值为0V的驱动电压VShift；
    当所述上拉开关MH导通时，所述控制电压VG2等于所述电源电压VDD，所述第二子模块根据所述控制电压VG2输出电压值为至少2*VDD的驱动电压VShift。
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