WO2017092451A1 - 发光二极管芯片及其制作方法 - Google Patents

发光二极管芯片及其制作方法 Download PDF

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Publication number
WO2017092451A1
WO2017092451A1 PCT/CN2016/097808 CN2016097808W WO2017092451A1 WO 2017092451 A1 WO2017092451 A1 WO 2017092451A1 CN 2016097808 W CN2016097808 W CN 2016097808W WO 2017092451 A1 WO2017092451 A1 WO 2017092451A1
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Prior art keywords
layer
electrical connection
light
connection layer
geometric pattern
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PCT/CN2016/097808
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English (en)
French (fr)
Inventor
杨恕帆
吴俊毅
吴超瑜
王笃祥
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天津三安光电有限公司
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Publication of WO2017092451A1 publication Critical patent/WO2017092451A1/zh
Priority to US15/853,890 priority Critical patent/US10340469B2/en
Priority to US16/409,740 priority patent/US10673003B2/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K30/00—Organic devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation
    • H10K30/80—Constructional details
    • H10K30/81—Electrodes
    • H10K30/82—Transparent electrodes, e.g. indium tin oxide [ITO] electrodes
    • H10K30/83—Transparent electrodes, e.g. indium tin oxide [ITO] electrodes comprising arrangements for extracting the current from the cell, e.g. metal finger grid systems to reduce the serial resistance of transparent electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/042—PV modules or arrays of single PV cells
    • H01L31/0445—PV modules or arrays of single PV cells including thin film solar cells, e.g. single thin film a-Si, CIS or CdTe solar cells
    • H01L31/046—PV modules composed of a plurality of thin film solar cells deposited on the same substrate
    • H01L31/0468—PV modules composed of a plurality of thin film solar cells deposited on the same substrate comprising specific means for obtaining partial light transmission through the module, e.g. partially transparent thin film solar modules for windows
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/382—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0016—Processes relating to electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H01L33/42—Transparent materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to the field of semiconductor illumination, and more particularly to a light emitting diode chip having a light-emitting surface without a metal extension electrode and a method of fabricating the same.
  • LEDs light emitting diodes
  • FIG. 1 shows a prior art AlGalnP-based LED chip structure that uses a bonding technique to convert a light-absorbing gallium arsenide substrate into a silicon substrate having a mirror system to achieve increased brightness.
  • the electrode needs to form an ohmic contact with the epitaxial semiconductor and conduct current diffusion through the extension strip, but the electrode extension strip has the effect of shielding the light to reduce the photoelectric efficiency.
  • ITO conduction is used instead of the metal extension strip, but can form with ITO.
  • the limited semiconductor materials for ohmic contacts have led to many limitations in structural design.
  • FIG. 2 shows another prior art LED chip seed structure in which an inner-side metal-matched trench structure is substituted for a surface extension strip, and a current flows from the top electrode 7 to the n-type semiconductor layer 3, by means of an electron of a semiconductor material.
  • the active layer 1 and the p-type semiconductor layer 2 are connected to each other, and then the circuit is completed by conducting the metal material 5 and the bottom electrode 6, wherein the dielectric layer 4 is used to insulate the active layer 1 from the metal material 5.
  • the shortest path of the current selection is the shortest path, the lateral expansion effect of the current is not ideal.
  • the current path R1 indicates the farthest range of the lateral conduction of the outer ring current, and the conduction effect of the current path R2 has disappeared, and the actual size of the illumination area is less than the entire surface.
  • the light-emitting area therefore, the characteristic conversion of the photovoltaic element is worse than the conventional structure.
  • the present invention provides an LED chip and a manufacturing method thereof, which are provided with an electrical connection layer on a light-emitting surface of a light-emitting epitaxial laminate, which can be separated by a dielectric material and not connected, and the surface is subjected to chemical mechanical polishing (CMP). After the treatment, a transparent current spreading layer is plated on the extremely flat surface, thereby reducing the lateral conduction resistance of the transparent current spreading layer and performing lateral conduction instead of the metal extension strip.
  • CMP chemical mechanical polishing
  • an LED chip comprising: a light emitting epitaxial stack, comprising a first type of semiconductor, a second type of semiconductor, and an active layer sandwiched therebetween, having two opposite a surface, wherein the second surface is a light-emitting surface; a first electrical connection layer, located on the first surface of the light-emitting epitaxial layer, and arranged by a first geometric pattern array; a second electrical connection layer, located in the light-emitting epitaxial stack
  • the second surface of the layer is composed of a second array of geometric patterns; a transparent current spreading layer is located on the surface of the two electrical connection layers; when the external power supply is turned on, a current flows through the horizontal of the transparent current spreading layer
  • the sheet resistance value is less than the resistance value of the second electrical connection layer.
  • the LED chip further includes a top electrode disposed on the second electrical connection layer, and when a current is injected into the top electrode, conducting to the transparent current spreading layer, preferentially performing lateral conduction and then implanting a second electrical connection layer.
  • the transparent current spreading layer is mainly responsible for lateral conduction and is connected to the second electrical connection layer.
  • the roughness average Ra of the surface of the second electrical connection layer is less than or equal to 1 nm.
  • the first geometric pattern array and the second geometric pattern array are staggered.
  • the first geometric pattern array is spaced apart by the first dielectric material so as not to be connected
  • the second geometric pattern array is spaced apart by the second dielectric material so as not to be connected.
  • the first and second geometric pattern arrays have a size of 5 to 10 micrometers.
  • the area of the second geometric pattern array is less than or equal to 1/10 of the light-emitting area of the light-emitting epitaxial stack.
  • the first dielectric material is composed of a single layer or a plurality of layers of materials, has a light source that reflects the radiation of the active layer and reduces optical loss.
  • the second dielectric material is composed of a single layer or a plurality of layers of materials, has an anti-reflection effect, increases the amount of light source penetration of the source layer radiation, and reduces optical loss.
  • the second electrical connection layer is an AuGe, AuGeNi or TiAu alloy.
  • the luminescent epitaxial laminate is made of an AlGalnP-based material.
  • the transparent current spreading layer comprises a transparent conductive oxide such as indium tin oxide or zinc oxide.
  • the present invention also provides a method for fabricating an LED chip, comprising the steps of: 1) epitaxial growth An optical epitaxial stack comprising a first type of semiconductor, a second type of semiconductor, and an active layer sandwiched therebetween, having opposite surfaces, wherein the first surface is a light exiting surface; 2) the light emitting epitaxy Forming a first electrical connection layer on the first surface of the laminate, which is composed of a first geometric pattern array; 3) fabricating a second electrical connection layer on the second surface of the light-emitting epitaxial laminate, the second geometric pattern Forming an array; 4) forming a transparent current spreading layer on the second electrical connection layer, and when the external power source is turned on, a lateral current resistance of the current flowing through the transparent current spreading layer is smaller than the first electric current flowing through the first current The resistance value of the connection layer.
  • the method further includes a step 6): forming an electrode on the transparent current spreading layer, and injecting a current ⁇ into the first electrode, conducting to the transparent current spreading layer, preferentially performing lateral conduction, and then injecting into the first Electrical connection layer.
  • the step 3) is: depositing a second electrical connection layer on the second surface of the light-emitting epitaxial layer; continuing to vapor-deposit a second dielectric material layer on the surface, etching
  • the second electrical connection layer region exposes the second electrical connection layer, and the surface of the second connection layer is planarized by a CMP process.
  • the surface after CMP planarization is scanned by an atomic force microscope, and the roughness average Ra can be reduced to less than 1 nm.
  • the transparent current spreading layer is evaporated on the extremely flat interface to effectively increase the conductivity and realize lateral conduction. The effect of conduction.
  • 1 is a side cross-sectional view of a conventional LED chip.
  • FIG. 2 is a side cross-sectional view of another conventional LED chip.
  • FIG. 3 is a side cross-sectional view of an LED chip in accordance with an embodiment of the present invention.
  • FIG. 4 is a schematic view showing the distribution of a first electrical connection layer and a second electrical connection layer of the LED chip shown in FIG. 3.
  • FIG. 5 is a side cross-sectional view of another LED chip in accordance with an embodiment of the present invention.
  • FIG. 6 is a side cross-sectional view of another LED core chip in accordance with an embodiment of the present invention.
  • the following embodiments disclose an LED chip, respectively forming a first electrical connection layer and a second electrical connection layer on both sides of the light-emitting epitaxial laminate, the first and second electrical connection layers being extremely small in size
  • the array is arranged in an array, and the two arrays do not overlap in front view, and the layout is staggered, and the metal-free extended electrode connection is formed on the light-emitting surface.
  • the light-emitting surface of the light-emitting epitaxial layer is covered with a dielectric material optical film, and the surface is planarized by a CMP process to achieve an extremely low roughness value, and a transparent current is formed after the planarization process.
  • the extended layer, the lateral resistance of the current conduction to the transparent current spreading layer is smaller than the resistance value of the transparent current spreading layer, so that conduction through the transparent current spreading layer can be performed to turn on the respective regions of the second electrical connection layer;
  • the underside of the laminate is covered with a dielectric layer optical film structure having a high reflectivity. Therefore, the surface shielding rate of the LED chip is extremely small, and the current guiding flow range is increased to increase the chip size light emitting area, thereby achieving the effect of improving the photoelectric conversion efficiency of the component.
  • an LED chip includes, in order from top to bottom, a top electrode 10, a transparent current spreading layer 11, a second electrical connection layer 12, and a second type semiconductor layer 14.
  • the active layer 15, the first type semiconductor layer 16, the first electrical connection layer 18, the metal material layer 19, and the conductive substrate 20
  • the first semiconductor layer 16, the active layer 15 and the second semiconductor layer 14 constitute a light-emitting epitaxial layer, wherein one side surface of the second type semiconductor layer 14 is a light-emitting surface.
  • an AlGalnP-based material is used, in which the first type semiconductor layer 16 is a p-type material and the second type semiconductor layer 14 is an n-type material.
  • the light-emitting surface of the light-emitting epitaxial laminate can be roughened as shown in FIG.
  • the first electrical connection layer 18 is a metal material that forms an ohmic contact with the first type semiconductor layer 16, and may be an alloy such as AuBe, AuZn, CrAu, etc.; the second electrical connection layer 12 is formed with the second type semiconductor layer 14.
  • the metal material of the ohmic contact may specifically be an alloy such as AuGe, AuGeNi or TiAu.
  • the first electrical connection layer 18 and the second electrical connection layer 12 are circular or other geometric shapes each of which is arranged in an array arrangement, and does not overlap in front view.
  • the first and second electrical connection layers are each a circular array of 5-10 micrometer diameter, and the staggered arrangement presents the closest packing, wherein the area of the second geometric pattern array is less than or equal to the light emitting area of the light emitting epitaxial layer. 1/10, that is, the overall light-emitting area electrode shielding rate is ⁇ 10%, which is lower than that of the metal electrode extension strip.
  • the first electrical connection layer 18 is in communication with the metal material layer 19 (the bottom electrode), and the region in the array may be deposited with a dielectric material 17 such as SiO 2 , and the dielectric material may be a single layer or multiple layers.
  • the same or different dielectric materials function as a source of specular reflection active layer 15 radiation and reduce optical loss, increasing forward light output.
  • Layer 12 and is electrically connected to a second power 14 is turned on, the second area array type semiconductor layer may be deposited as a dielectric material such as SiN x 13, the dielectric material 13 may be a single layer or a multilayer, the same or different dielectric materials It acts as an anti-reflection effect, increases the amount of light source penetration of the active layer 15 radiation and reduces optical loss.
  • the surface of the dielectric material 13 is subjected to CMP planarization treatment, and the surface after the treatment is subjected to atomic force microscopy (AFM) scanning, and the roughness average Ra can be reduced to below 1 nm.
  • AFM atomic force microscopy
  • the transparent current spreading layer 11 comprises a transparent conductive oxide such as indium tin oxide or zinc oxide.
  • the main function in the structure of the chip is to conduct lateral conduction conduction, and the roughness can be reduced by CMP to reduce the cross-sectional resistance. The purpose of lateral conduction. After the current is conducted from the top electrode 10 to the transparent current spreading layer 11, the lateral conduction resistance of the transparent current spreading layer 11 is extremely low. If the resistance is directly lower than the resistance of the light-emitting epitaxial stack, the current is selected.
  • the lateral conduction is prioritized, so that it can be smoothly conducted to the electrical connection layer of the outer ring of the light-emitting area of the chip, and is uniformly and uniformly diffused to the entire surface of the light-emitting area and coupled to the active layer to emit light.
  • FIG. 5 shows a schematic diagram of a current path using the above structure.
  • the top electrode 10 When the top electrode 10 is energized, part of the current is conducted to the first electrical connection layer through the R1 path.
  • the current density of the R1 path increases and the conduction resistance begins to rise above the R2 conduction path, the current selects the low resistance R2 path.
  • the lateral conduction extending to the second electrical connection layer 12 of the entire illumination area, overcomes the difficulty of the lateral expansion of the prior art. Since the second electrical connection layer 12 and the first electrical connection layer 18 are alternately distributed, current flows into the second connection layer 14 to continue lateral conduction, and flows through the active layer 15 and the first electrical connection layer 18 to be electrically connected to the bottom electrode 19.
  • the light emitting region of the active layer 15 emits light upward to avoid electrode shielding, and the current distribution is uniformly diffused, so that a better light-emitting effect and photoelectric characteristics can be achieved.
  • FIG. 6 shows another LED chip according to an embodiment of the present invention, which differs from the LED chip shown in FIG. 3 in that: the first electrical connection layer 18 is an in-cell electrode that partially penetrates the first type of semiconductor layer. 16.
  • the active layer 15 to the second type semiconductor layer 14 are insulated from the active layer 15 to the second type semiconductor layer 14 by a dielectric material 17.
  • the regions of the first electrical connection layer 18 that are in contact with the first type of semiconductor layer 16 are also arranged in a geometric pattern array, staggered with the second electrical connection layer 12.
  • FIGS. 7 to 14 show a method for fabricating the LED chip shown in FIG. 5, which will be briefly described below with reference to the accompanying drawings.
  • a second type of semiconductor layer 14, an active layer 15, and a first type semiconductor layer 16 are epitaxially grown on a gallium arsenide or a substrate substrate 22 suitable for growing a quaternary material, as shown in FIG.
  • Next step forming a first electrical connection layer 18 on the surface of the first type semiconductor layer 16, and defining a pattern thereof
  • Next step The dielectric material 17 is deposited and the dielectric material on the surface of the first electrical connection layer 18 is removed to have a structure as shown in FIG.
  • a bonding metal 19 is formed on the surface of the first electrical connection layer 18, and bonded to the conductive substrate 20, and after the bonding is completed, the substrate 22 is removed, and the structure is as shown in FIG.
  • the second electrical connection layer 12 is evaporated on the surface of the second type semiconductor layer 14, and the light-emitting region of the second type semiconductor layer 14 is roughened, and the structure is as shown in FIG.
  • a dielectric material 12 is formed on the surface of the second electrical connection layer 12, and the second electrical connection layer 12 region is etched to expose the second electrical connection layer 12, and the rough surface is planarized by CMP. Process shown in Figure 1
  • a transparent current spreading layer 11 is formed on the surface of the second electrical connection layer 12, and a top electrode 10 is formed as shown in FIG.

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Abstract

提供一种发光二极管芯片及其制作方法，其在发光外延叠层的出光面上设置电连接层（12），可由介电材料（13）间隔从而不相连，表面经CMP处理后在极平坦的面上镀上透明电流扩展层（11），从而降低透明电流扩展层的横向传导阻值并代替金属扩展条进行横向传导。

Description

说明书 发明名称：发光二极管芯片及其制作方法 技术领域
[0001] 本发明涉及半导体照明领域， 具体的说是一种出光面无金属扩展电极的发光二 极管芯片及其制作方法。
背景技术
[0002] 近几年， 发光二极管 （light emitting diode,简称 LED) 得到了广泛的应用， 在 各种显示***、 照明***、 汽车尾灯等领域起着越来越重要的作用。
[0003] 图 1显示了现有的一种 AlGalnP系 LED芯片结构， 其采用键合技术将吸光的砷化 镓基板转换成具有镜面***的硅基板以达到增加亮度的方法。 但是， 电极需与 外延半导体形成欧姆接触， 并通过扩展条进行电流扩散， 但电极拓展条有遮蔽 出光减少光电效率之影响， 后续有提出采用 ITO传导取代金属扩展条之结构， 但 是能和 ITO形成欧姆接触之半导体材料有限， 导致结构设计面临诸多限制。
[0004] 图 2显示了现有的另一种 LED芯片种结构， 其以内親式金属搭配沟槽结构取代 表面扩展条， 电流从顶部电极 7流向 n型半导体层 3， 借由半导体材料之电子飘移 横向传导， 连通有源层 1与 p型半导体层 2， 接着通过金属材料 5与底部电极 6导通 完成回路， 其中介电层 4用于隔绝有源层 1与金属材料 5。 但因电流选择最低阻值 最短路径导通， 导致电流横向拓展效果不理想， 电流路径 R1示意外圈电流横向 传导最远范围， 电流路径 R2之导通效果已消失， 实际尺寸发光面积不及整面发 光区， 因此光电原件之特性转换相较于传统结构更差。
技术问题
问题的解决方案
技术解决方案
[0005] 针对上述问题， 本发明提出一种 LED芯片及制作方法， 其在发光外延叠层的出 光面上设置电连接层， 可由介电材料间隔从而不相连， 表面经化学机械研磨抛 光 (CMP)处理后在极平坦的面上镀上透明电流扩展层， 从而降低透明电流扩展层 的横向传导阻值并代替金属扩展条进行横向传导。 [0006] 本发明解决问题的具体方案为： 发光二极管芯片， 包括： 发光外延叠层， 包含 第一类型半导体、 第二类型半导体及夹在两者之间的有源层， 具有相对的两个 表面， 其中第二表面为出光面； 第一电连接层， 位于所述发光外延叠层的第一 表面上， 由第一几何图形阵列排列构成； 第二电连接层， 位于所述发光外延叠 层的第二表面上， 由第二几何图形阵列排列构成； 透明电流扩展层， 位于所述 二电连接层的表面上； 当接通外部电源吋， 电流流经所述透明电流扩展层之横 面电阻值小于其流经所述第二电连接层的电阻值。
[0007] 进一步地， 所述 LED芯片还包括设于所述第二电连接层上的顶部电极， 当向该 顶部电极注入电流吋， 传导至所述透明电流扩展层吋优先进行横向传导后注入 第二电连接层。
[0008] 在上述 LED芯片中， 透明电流扩展层主要负责横向传导， 与第二电连接层相接
， 不直接与外延层结构导通， 克服大部分外延四元材料无法直接与透明电流扩 展层欧姆接触导通的问题。
[0009] 优选地， 所述第二电连接层表面的粗糙度均值 Ra小于或等于 lnm。
[0010] 优选地， 所述第一几何图形阵列和所述第二几何图形阵列交错排列。
[0011] 优选地， 所述第一几何图形阵列由第一介电材料间隔从而不相连， 所述第二几 何图形阵列由第二介电材料间隔从而不相连。
[0012] 优选地， 所述第一、 第二几何图形阵列的尺寸为 5~10微米。
[0013] 优选地， 所述第二几何图形阵列的面积小于或等于所述发光外延叠层的出光面 积的 1/10。
[0014] 优选地， 所述第一介电材料由单层或多层材料构成， 具有反射有源层辐射之光 源并且减少光学损耗。
[0015] 优选地， 所述第二介电材料由单层或多层材料构成， 具有抗反射作用， 增加有 源层辐射之光源穿透量并且减少光学损耗。
[0016] 优选地， 所述第二电连接层为 AuGe、 AuGeNi或 TiAu合金。
[0017] 优选地， 所述发光外延叠层选用 AlGalnP系材料。
[0018] 优选地， 所述透明电流扩展层包含氧化铟锡、 氧化锌等透明导电氧化物。
[0019] 本发明还提供了一种发光二极管芯片的制作方法， 包括步骤： 1) 外延生长发 光外延叠层， 其包含第一类型半导体、 第二类型半导体及夹在两者之间的有源 层， 具有相对的两个表面， 其中第一表面为出光面； 2) 在所述发光外延叠层的 第一表面上制作第一电连接层， 其由第一几何图形阵列构成； 3) 在所述发光外 延叠层的第二表面上制作第二电连接层， 其由第二几何图形阵列构成； 4) 在所 述第二电连接层上制作透明电流扩展层， 当接通外部电源吋， 电流流经所述透 明电流扩展层之横面电阻值小于其流经所述第一电连接层的电阻值。
[0020] 进一步地， 还包括步骤 6) ： 在所述透明电流扩展层上制作电极， 当向该第一 电极注入电流吋， 传导至所述透明电流扩展层吋优先进行横向传导后注入第一 电连接层。
[0021] 优选地， 所述步骤 3) 为： 在所述发光外延叠层的第二表面上蒸镀第二电连接 层； 继续在所述表面上蒸镀第二介电材料层， 蚀刻第二电连接层区域使其裸露 出第二电连接层， 采用 CMP工艺对所述第二连接层的表面进行平坦化处理。 优 选地， 经过 CMP平坦化处理后的表面采用原子力显微镜扫测， 其粗糙度均值 Ra 可降低至 lnm以下， 在极平坦的接口上蒸镀透明电流扩展层可有效增加导电率， 实现进行横向传导导通的功效。
发明的有益效果
对附图的简要说明
附图说明
[0022] 附图用来提供对本发明的进一步理解， 并且构成说明书的一部分， 与本发明的 实施例一起用于解释本发明， 并不构成对本发明的限制。 此外， 附图数据是描 述概要， 不是按比例绘制。
[0023] 图 1为现有一种 LED芯片的侧面剖视图。
[0024] 图 2为现有的另一种 LED芯片的侧面剖视图。
[0025] 图 3为根据本发明实施的一种 LED芯片的侧面剖视图。
[0026] 图 4为图 3所示 LED芯片之第一电连接层和第二电连接层的分布示意图。
[0027] 图 5为根据本发明实施的另一种 LED芯片的侧面剖视图。
[0028] 图 6为根据本发明实施的另一种 LED芯芯片的侧面剖视图。
[0029] 图 7~14为制作图 5所示 LED芯片过程中的部分侧面剖视图。 本发明的实施方式
[0030] 下面各实施例公幵了一种 LED芯片， 分别在发光外延叠层的两侧表面形成第一 电连接层与第二电连接层， 该第一、 第二电连接层尺寸极小并以阵列排列布满 整面， 两阵列以正面俯视皆不重迭， 呈现交错堆积之布局， 出光面上无金属扩 展电极连接。 进一步地， 发光外延叠层的发光面除第二电连接层外， 采用介电 材料光学膜布满其间， 表面经过 CMP工艺平坦化处理达到极低的粗糙度值， 平 坦化处理后制作透明电流扩展层， 电流传导至该透明电流扩展层的横面电阻值 小于其传导至发光外延叠层的阻值， 因此通过透明电流扩展层传导， 可以实现 导通第二电连接层各个区域； 发光外延叠层的下方采用具高反射率之介电层光 学膜结构布满其间。 因此， 该 LED芯片表面电极遮蔽率极小， 电流导引流通范围 增大从而增加芯片尺寸发光面积， 达到提升组件光电转换效率之效果。
[0031] 请参看附图 3， 根据本发明实施的一种发光二极管芯片， 从上到下依次包括： 顶部电极 10、 透明电流扩展层 11、 第二电连接层 12、 第二类型半导体层 14、 有 源层 15、 第一类型半导体层 16、 第一电连接层 18、 金属材料层 19， 导电基板 20
[0032] 具体的， 第一半导体层 16、 有源层 15和第二半导体层 14构成发光外延叠层， 其 中第二类型半导体层 14的一侧表面为出光面。 在本实施例中， 采用 AlGalnP系材 料， 其中第一类型半导体层 16为 p型材料， 第二类型半导体层 14为 n型材料。 较 佳的， 发光外延叠层的出光面可以作粗化处理， 如图 5所示。
[0033] 第一电连接层 18为与第一类型半导体层 16形成欧姆接触的金属材料， 具体可以 为 AuBe、 AuZn、 CrAu等合金； 第二电连接层 12为和第二类型半导体层 14形成欧 姆接触的金属材料， 具体可为 AuGe、 AuGeNi、 TiAu等合金由。
[0034] 参看图 4， 第一电连接层 18和第二电连接层 12的形状为圆形或其他几何图形各 自以阵列排列方式布满整面， 以正面俯视皆不重迭。 较佳的， 第一、 第二电连 接层各自为 5~10微米直径之圆形阵列， 交错排列呈现最密堆积， 其中第二几何 图形阵列的面积小于或等于发光外延叠层的出光面积的 1/10， 即整体发光区域电 极遮蔽率<10%， 较金属电极拓展条之遮蔽率更低。 [0035] 在本实施例中， 第一电连接层 18与金属材料层 19 (底层电极） 相通， 阵列中区 域可沉积如 Si0 2等介电材料 17， 介电材料可以是单层或者多层、 相同或不同之 介电材料， 其作用为镜面反射有源层 15辐射之光源并且减少光学损耗， 增加正 向出光。 第二电连接层 12与第二类型半导体层 14通电导通， 阵列中区域可沉积 如 SiN x等介电材料 13， 介电材料 13可以是单层或者多层、 相同或不同之介电材 料， 其作用为抗反射效果， 增加有源层 15辐射之光源穿透量并且减少光学损耗 。 较佳的， 在第二电连接层中， 针对表面之介电材料 13进行 CMP平坦化处理， 处理后表面经原子力显微镜 (AFM)扫测， 其粗糙度均值 Ra可降低至 lnm以下， 在极平坦的接口上制作透明电流扩展层可有效增加导电率。
[0036] 透明电流扩展层 11包含氧化铟锡、 氧化锌等透明导电氧化物， 在本芯片结构中 的主要功用是进行横向传导导通， 经由 CMP后降低粗糙度可以降低横截面阻值 ， 达成横向导通的目的。 电流由顶部电极 10传导至所述透明电流扩展层 11后， 因透明电流扩展层 11之电流横向传导阻值极低， 若小于直接传导至发光外延叠 层的阻值， 此吋电流会选择以横向传导为优先， 如此可顺利传导至芯片发光区 外圈之电连接层， 充分均匀扩散至整面发光区与有源层耦合发光。
[0037] 图 5显示了采用上述结构的电流路径示意图。 当顶部电极 10通电后， 部分电流 经过 R1路径导通至第一电连接层， 当 R1路径电流密度增加， 传导阻值幵始高于 R2传导路径后， 电流便会选择低阻值之 R2路径进行横向传导， 扩展至整面发光 区之第二电连接层 12， 克服了原有技术横向扩展不佳之困难。 由于第二电连接 层 12与第一电连接层 18交错分布， 电流进入第二连接层 14后继续进行横向传导 ， 流经有源层 15和第一电连接层 18， 与底部电极 19导通， 如此有源层 15发光区 域向上出光可避免电极遮蔽， 并且电流分布扩散均匀， 可达到较佳之出光效果 与光电特性。
[0038] 图 6显示了根据本发明实施的另一种 LED芯片， 其与图 3所示 LED芯片的区别在 于： 第一电连接层 18采用内嵌式电极， 其部分贯穿第一类型半导体层 16、 有源 层 15至第二类型半导体层 14， 并通过介电材料 17与有源层 15至第二类型半导体 层 14绝缘。 在该结构中， 第一电连接层 18与第一类型半导体层 16接触的区域同 样呈几何图形阵列排列， 与第二电连接层 12交错分布。 [0039] 图 7~14显示了一种用于制作图 5所示 LED芯片的， 下面结合附图进行简单描述
[0040] 首先， 在砷化镓或者适合生长四元材料之基板衬底 22上外延生长第二类型半导 体层 14、 有源层 15和第一类型半导体层 16， 如图 7所示。
[0041] 下一步： 在第一类型半导体层 16表面上形成第一电连接层 18， 并且定义其图形
， 如图 8所示。
[0042] 下一步： 沉积介电材料 17， 并去除第一电连接层 18表面的介电材料， 使其结构 如 9所示。
[0043] 下一步： 在第一电连接层 18表面上形成键合金属 19， 并与导电基板 20键合， 键 合完成后去除衬底 22， 结构如图 10所示。
[0044] 下一步： 在第二类型半导体层 14表面上蒸镀第二电连接层 12， 并对第二类型半 导体层 14的发光区域作粗化处理， 结构如图 11所示。
[0045] 下一步： 在第二电连接层 12表面制作介电材料 12， 并蚀刻第二电连接层 12区域 使其裸露出第二电连接层 12， 采用 CMP对粗糙表面进行平坦化处理， 过程如图 1
2和 13所示。
[0046] 下一步： 经 CMP处理后， 在第二电连接层 12表面形成透明电流扩展层 11， 并制 作顶部电极 10， 如图 14所示。
[0047] 很明显地， 本发明的说明不应理解为仅仅限制在上述实施例， 而是包括利用本 发明构思的所有可能的实施方式。

Claims

权利要求书
发光二极管芯片， 包括：
发光外延叠层， 包含第一类型半导体层、 第二类型半导体层及夹在两 者之间的有源层， 具有相对的两个表面， 其中第二表面为出光面； 第一电连接层， 位于所述发光外延叠层的第一表面上， 由第一几何图 形阵列排列构成； 第二电连接层， 位于所述发光外延叠层的第二表面上， 由第二几何图 形阵列排列构成； 透明电流扩展层， 位于所述第二电连接层的表面上；
当接通外部电源吋， 电流流经所述透明电流扩展层之横面电阻值小于 其流经所述第二电连接层的电阻值。
根据权利要求 1所述的发光二极管芯片， 其特征在于： 还包括设于所 述第二电连接层上的电极， 当向该电极注入电流吋， 传导至所述透明 电流扩展层吋优先进行横向传导后注入第二电连接层。
根据权利要求 2所述的发光二极管芯片， 其特征在于： 所述第二电连 接层表面的粗糙度均值 Ra小于或等于 lnm。
根根据权利要求 2所述的发光二极管芯片， 其特征在于： 所述第一几 何图形阵列和所述第二几何图形阵列交错排列。
据权利要求 2所述的发光二极管芯片， 其特征在于： 所述第一几何图 形阵列由第一介电材料间隔从而不相连， 所述第二几何图形阵列由第 二介电材料间隔从而不相连。
根据权利要求 5所述的发光二极管芯片， 其特征在于： 所述第二几何 图形阵列的面积小于或等于所述发光外延叠层的出光面积的 1/10。 根据权利要求 5所述的发光二极管芯片， 其特征在于： 所述第一介电 材料由单层或多层材料构成， 具有反射有源层辐射之光源并且减少光 学损耗。
根据权利要求 5所述的发光二极管芯片， 其特征在于： 所述第二介电 材料由单层或多层材料构成， 具有抗反射作用， 增加有源层辐射之光 源穿透量并且减少光学损耗。
根据权利要求 2所述的发光二极管芯片， 其特征在于： 所述第二电连 接层为 AuGe、 AuGeNi或 TiAu合金。
根据权利要求 1所述的发光二极管芯片， 其特征在于： 所述发光外延 叠层选用 AlGalnP系材料。
一种发光二极管芯片的制作方法， 包括步骤：
1) 外延生长发光外延叠层， 其包含第一类型半导体层、 第二类型半 导体层及夹在两者之间的有源层， 具有相对的两个表面， 其中第一表 面为出光面；
2) 在所述发光外延叠层的第一表面上制作第一电连接层， 其由第一 几何图形阵列构成；
3) 在所述发光外延叠层的第二表面上制作第二电连接层， 其由第二 几何图形阵列构成；
4) 在所述第二电连接层上制作透明电流扩展层， 当接通外部电源吋
， 电流流经所述透明电流扩展层之横面电阻值小于其流经所述第一电 连接层的电阻值。
根据权利要求 11所述的发光二极管芯片的制作方法， 其特征在于： 还 包括步骤 6) ： 在所述透明电流扩展层上制作电极， 当向该第一电极 注入电流吋， 传导至所述透明电流扩展层吋优先进行横向传导后注入 第一电连接层。
根据权利要求 11所述的发光二极管芯片的制作方法， 其特征在于： 所 述步骤 3) 为： 在所述发光外延叠层的第二表面上蒸镀第二电连接层 ； 继续在所述表面上蒸镀第二介电材料层， 蚀刻第二电连接层区域使 其裸露出第二电连接层， 采用化学机械研磨抛光工艺对所述第二连接 层的表面进行平坦化处理。
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