WO2017080093A1 - 栅极驱动电路以及移位寄存电路 - Google Patents

栅极驱动电路以及移位寄存电路 Download PDF

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Publication number
WO2017080093A1
WO2017080093A1 PCT/CN2015/100355 CN2015100355W WO2017080093A1 WO 2017080093 A1 WO2017080093 A1 WO 2017080093A1 CN 2015100355 W CN2015100355 W CN 2015100355W WO 2017080093 A1 WO2017080093 A1 WO 2017080093A1
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WIPO (PCT)
Prior art keywords
gate
nmos transistor
circuit
pmos transistor
transistor
Prior art date
Application number
PCT/CN2015/100355
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English (en)
French (fr)
Inventor
郝思坤
Original Assignee
深圳市华星光电技术有限公司
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Publication date
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Priority to US15/032,309 priority Critical patent/US9905313B2/en
Publication of WO2017080093A1 publication Critical patent/WO2017080093A1/zh

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H03K17/6872—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor using complementary field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular to a gate driving circuit and a shift register circuit.
  • GOA Gate Driver On The Array circuit
  • the GOA circuit has two basic functions: the first is to input the gate drive pulse, drive the gate line in the panel, and open the TFT in the display area (Thin Film Transistor, thin film field effect transistor), the pixel is charged by the gate line; the second is shift register, when the output of the nth gate drive pulse is completed, n+1 gate drive pulses can be performed by clock control Output, and pass it on.
  • the GOA circuit includes a pull-up circuit and a pull-up control (Pull-up control) Circuit),Pull-down circuit, Pull-down control Circuit) and the rising circuit responsible for the potential rise (Boost) Circuit).
  • the pull-up circuit is mainly responsible for outputting an input clock signal (Clock) to the gate of the thin film transistor as a driving signal of the liquid crystal display.
  • the pull-up control circuit is responsible for controlling the opening of the pull-up circuit, which is generally a signal transmitted by the upper-level GOA circuit.
  • the pull-down circuit is responsible for quickly pulling the scan signal low to low after the output of the scan signal, that is, the potential of the gate of the thin film transistor is pulled low to a low potential;
  • the pull-down hold circuit is responsible for the signal of the scan signal and the pull-up circuit (commonly called For Q point) Staying in the off state (ie, the set negative potential), there are usually two pull-down holding circuits that alternate.
  • the rising circuit is responsible for the secondary rise of the Q point potential, thus ensuring the normal output of the G(N) of the pull-up circuit.
  • LTPS Low Temperature Poly-silicon, low-temperature polysilicon process
  • CMOS Complementary Metal Oxide Semiconductor, Complementary Metal Oxide Semiconductor
  • the LTPS process has the advantages of low power consumption, high electron mobility, and wide noise margin. Therefore, it is gradually used by panel manufacturers, so it is necessary to develop a GOA circuit corresponding to the CMOS LTPS process.
  • the embodiment of the invention provides a gate driving circuit and a shift register circuit, which can be applied to a CMOS process, and has low power consumption and wide noise tolerance.
  • the present invention provides a gate driving circuit including a plurality of cascaded shift register circuits, each shift register circuit including a signal transmission circuit and a NOR gate latch circuit, wherein the signal transmission circuit includes a first signal transmission circuit And a second signal transmission circuit, the first signal transmission circuit transmits a high level portion of the transmission signal of the previous stage to the NOR gate latch circuit according to the first clock signal, and the second signal transmission circuit outputs the front according to the first clock signal The low level portion of the one-stage transmission signal is transmitted to the NAND gate latch circuit for latching, and is triggered by the second clock signal to output the gate drive pulse of the current stage.
  • the signal transmission circuit and the NAND gate latch circuit are respectively triggered by rising edges.
  • the first signal transmission circuit includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first PMOS transistor, and a second PMOS transistor, and the gate of the first NMOS transistor is connected to the previous stage.
  • a gate of the second NMOS transistor is connected to the first clock signal, a source is connected to a drain of the first NMOS transistor, a drain is connected to a source of the first PMOS transistor, a gate of the second PMOS transistor, and a third NMOS a drain of the tube, a gate of the fourth NMOS transistor, and a NAND gate latch circuit, a gate of the third NMOS transistor and a gate of the first PMOS transistor, a source of the second PMOS transistor, and a fourth NMOS transistor a drain connection, a source of the first NMOS transistor, a source of the third NMOS transistor, and a source of the fourth NMOS transistor are connected to a first reference level, and a drain of the first PMOS transistor is connected to a drain of the second PMOS transistor Second reference level.
  • the second signal transmission circuit includes a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and a third PMOS transistor.
  • the gate of the fifth NMOS transistor and the gate of the third PMOS transistor are connected to the transmission signal of the previous stage.
  • a drain of the fifth NMOS transistor is connected to a source of the third PMOS transistor and a gate of the sixth NMOS transistor, and a source of the fifth NMOS transistor and a source of the sixth NMOS transistor are connected to a first reference level, and a third The drain of the PMOS transistor is connected to the second reference level, the drain of the sixth NMOS transistor is connected to the source of the seventh NMOS transistor, the gate of the seventh NMOS transistor is connected to the first clock signal, and the drain of the seventh NMOS transistor is The NAND gate latch circuit is connected.
  • the NOR gate latch circuit includes a NOR gate circuit, and the NOR gate circuit includes an eighth NMOS transistor, a ninth NMOS transistor, a fourth PMOS transistor, and a fifth PMOS transistor, and the gate and the fourth NMOS transistor have a gate and a fourth NMOS transistor.
  • the gate of the PMOS transistor is connected to the signal transmission circuit, the drain is connected to the source of the ninth NMOS transistor, the source is connected to the drain of the fourth PMOS transistor and the drain of the fifth PMOS transistor, and the gate of the ninth NMOS transistor
  • a second clock signal is connected to the gate of the fifth PMOS transistor, and the source of the fourth PMOS transistor and the source of the fifth PMOS transistor are connected to the first reference level.
  • the NOR gate latch circuit further includes a multi-stage inverter circuit connected to the NOR gate circuit.
  • the multi-stage inverter circuit comprises a plurality of inverters arranged in series, the inverter comprises a tenth NMOS transistor and a sixth PMOS transistor, the drain of the tenth NMOS transistor is connected to the second reference level, and the sixth PMOS transistor
  • the source is connected to the first reference level
  • the gate of the tenth NMOS transistor is connected to the gate of the sixth PMOS transistor, and is an input terminal of the inverter, and is connected to the NOR gate circuit or the inverter of the previous stage
  • the source of the ten NMOS transistor is connected to the drain of the sixth PMOS transistor and is the output terminal of the inverter.
  • the number of inverters is three.
  • the first clock signal is offset by one-half of a clock cycle to obtain a second clock signal.
  • the present invention also provides a shift register circuit comprising a signal transmission circuit and a NOR gate latch circuit, the signal transmission circuit comprising a first signal transmission circuit and a second signal transmission circuit, the first signal transmission circuit according to the first clock signal
  • the high level portion of the transmission signal of the previous stage is transmitted to the NOR gate latch circuit, and the second signal transmission circuit transmits the low level portion of the transmission signal of the previous stage to the NOR gate latch circuit according to the first clock signal.
  • the gate drive pulse of the current stage is output.
  • the signal transmission circuit and the NAND gate latch circuit are respectively triggered by rising edges.
  • the first signal transmission circuit includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first PMOS transistor, and a second PMOS transistor, and the gate of the first NMOS transistor is connected to the previous stage.
  • a gate of the second NMOS transistor is connected to the first clock signal, a source is connected to a drain of the first NMOS transistor, a drain is connected to a source of the first PMOS transistor, a gate of the second PMOS transistor, and a third NMOS a drain of the tube, a gate of the fourth NMOS transistor, and a NAND gate latch circuit, a gate of the third NMOS transistor and a gate of the first PMOS transistor, a source of the second PMOS transistor, and a fourth NMOS transistor a drain connection, a source of the first NMOS transistor, a source of the third NMOS transistor, and a source of the fourth NMOS transistor are connected to a first reference level, and a drain of the first PMOS transistor is connected to a drain of the second PMOS transistor Second reference level.
  • the second signal transmission circuit includes a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and a third PMOS transistor.
  • the gate of the fifth NMOS transistor and the gate of the third PMOS transistor are connected to the transmission signal of the previous stage.
  • a drain of the fifth NMOS transistor is connected to a source of the third PMOS transistor and a gate of the sixth NMOS transistor, and a source of the fifth NMOS transistor and a source of the sixth NMOS transistor are connected to a first reference level, and a third The drain of the PMOS transistor is connected to the second reference level, the drain of the sixth NMOS transistor is connected to the source of the seventh NMOS transistor, the gate of the seventh NMOS transistor is connected to the first clock signal, and the drain of the seventh NMOS transistor is The NAND gate latch circuit is connected.
  • the NOR gate latch circuit includes a NOR gate circuit, and the NOR gate circuit includes an eighth NMOS transistor, a ninth NMOS transistor, a fourth PMOS transistor, and a fifth PMOS transistor, and the gate and the fourth NMOS transistor have a gate and a fourth NMOS transistor.
  • the gate of the PMOS transistor is connected to the signal transmission circuit, the drain is connected to the source of the ninth NMOS transistor, the source is connected to the drain of the fourth PMOS transistor and the drain of the fifth PMOS transistor, and the gate of the ninth NMOS transistor
  • a second clock signal is connected to the gate of the fifth PMOS transistor, and the source of the fourth PMOS transistor and the source of the fifth PMOS transistor are connected to the first reference level.
  • the NOR gate latch circuit further includes a multi-stage inverter circuit connected to the NOR gate circuit.
  • the multi-stage inverter circuit comprises a plurality of inverters arranged in series, the inverter comprises a tenth NMOS transistor and a sixth PMOS transistor, the drain of the tenth NMOS transistor is connected to the second reference level, and the sixth PMOS transistor
  • the source is connected to the first reference level
  • the gate of the tenth NMOS transistor is connected to the gate of the sixth PMOS transistor, and is an input terminal of the inverter, and is connected to the NOR gate circuit or the inverter of the previous stage
  • the source of the ten NMOS transistor is connected to the drain of the sixth PMOS transistor and is the output terminal of the inverter.
  • the number of inverters is three.
  • the first clock signal is offset by one-half of a clock cycle to obtain a second clock signal.
  • the gate driving circuit of the present invention comprises a plurality of cascaded shift register circuits, each of the shift register circuits includes a signal transmission circuit and a NAND gate latch circuit, and the signal transmission
  • the circuit includes a first signal transmission circuit and a second signal transmission circuit, and the first signal transmission circuit transmits the high level portion of the transmission signal of the previous stage to the NOR gate latch circuit according to the first clock signal, and the second signal transmission
  • the circuit transmits the low-level portion of the transmission signal of the previous stage to the NOR gate latch circuit according to the first clock signal, or the non-gate latch circuit is configured to latch the transmission signal and trigger by the second clock signal It outputs the gate drive pulse of the current stage and can be applied to CMOS process with low power consumption and wide noise margin.
  • FIG. 1 is a schematic structural view of a driving circuit according to an embodiment of the present invention.
  • Figure 2 is a circuit diagram of the shift register circuit of the nth stage of Figure 1;
  • Figure 3 is a circuit diagram of the shift register circuit of the n+1th stage of Figure 1;
  • FIG. 4 is a circuit diagram of a shift register circuit of the n+2th stage of FIG. 1;
  • Figure 5 is a circuit diagram of the shift register circuit of the n+3th stage of Figure 1;
  • Fig. 6 is a timing chart showing the simulation of the gate driving circuit of the embodiment of the present invention.
  • FIG. 1 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present invention.
  • the gate driving circuit 1 includes a plurality of cascaded shift register circuits 10, each of which includes a signal transmission circuit 11 and a NOR gate latch circuit 12, wherein the signal transmission circuit 11
  • the first signal transmission circuit 110 and the second signal transmission circuit 111 are included, and the first signal transmission circuit 110 transmits the high-level portion of the transmission signal Qn-1 of the previous stage to the NOR gate latch circuit 12 according to the first clock signal.
  • the second signal transmission circuit 111 transmits the low-level portion of the previous-stage transmission signal Qn-1 to the NOR gate latch circuit 12 according to the first clock signal, or the NOT gate latch circuit 12 is used to transmit the signal Qn.
  • -1 is latched and triggered by the second clock signal CK2 to output the gate drive pulse Gn of the current stage.
  • the signal transmission circuit 11 and the NOR gate latch circuit 12 are respectively triggered by rising edges.
  • the transmission signal Qn-1 of the previous stage is transmitted through the signal transmission circuit 11 to output the transmission signal Qn of the current stage, and the gate drive pulse Gn of the current stage is output via the NOR gate latch circuit 12.
  • the transmission signal Qn of the current stage is transmitted through the signal transmission circuit 11 in the shift register circuit 10 of the next stage, and then the transmission signal Qn+1 of the next pole is output, and the NAND gate lock is applied to the shift register circuit 10 of the next stage.
  • the memory circuit 12 outputs the gate drive pulse Gn+1 of the next stage, thereby continuously transmitting, and is capable of outputting the gate drive pulses of the respective stages.
  • the signal transmission circuit 11 controls the signal transmission of the upper and lower stages, and the signal is latched by the NOR gate latch circuit 12, which can be applied to the CMOS process, and has low power consumption and wide noise tolerance.
  • n is a positive integer
  • the first signal transmission circuit 110 includes a first NMOS transistor T1 and a second NMOS transistor T2.
  • the source is connected to the drain of the first NMOS transistor T1, the drain and the source of the first PMOS transistor P1, the gate of the second PMOS transistor P2, the drain of the third NMOS transistor T3,
  • the gate of the fourth NMOS transistor T4 and the NAND gate latch circuit 12 are connected, the gate of the third NMOS transistor T3 and the gate of the first PMOS transistor P1, the source of the second PMOS transistor P2, and the fourth NMOS transistor T4.
  • the drain is connected, the source of the first NMOS transistor T1, the source of the third NMOS transistor T3, and the source of the fourth NMOS transistor T4 are connected to the first reference level Vgl, and the drain and the second of the first PMOS transistor P1.
  • the drain of the PMOS transistor P2 is connected to the second reference level Vgh.
  • the value of the first reference level Vgl is smaller than the value of the second reference level Vgh.
  • the second signal transmission circuit 111 includes a fifth NMOS transistor T5, a sixth NMOS transistor T6, a seventh NMOS transistor T7, and a third PMOS transistor P3.
  • the gate of the fifth NMOS transistor T5 is connected to the gate of the third PMOS transistor P3.
  • a drain of the fifth NMOS transistor T5 is connected to a source of the third PMOS transistor P3 and a gate of the sixth NMOS transistor T6, a source of the fifth NMOS transistor T5, and a sixth NMOS transistor
  • the source of T6 is connected to the first reference level Vgl
  • the drain of the third PMOS transistor P3 is connected to the second reference level Vgh
  • the drain of the sixth NMOS transistor T6 is connected to the source of the seventh NMOS transistor T7
  • the gate of the transistor T7 is connected to the first clock signal CK1
  • the drain of the seventh NMOS transistor T7 is connected to the NOR gate latch circuit 12.
  • the specific working principle of the signal transmission circuit 11 is as follows:
  • the transmission signal Qn-1 of the previous stage is at a low level
  • the first NMOS transistor T1 is turned off, and the first signal transmission circuit 110 does not work, that is, the transmission signal of the previous stage cannot be transmitted.
  • Qn-1 is transmitted to the NOR gate latch circuit 12 through the first signal transmission circuit 110; the fifth NMOS transistor T5 is turned off, and the third PMOS transistor P3 is turned on, so that the sixth NMOS transistor T6 is turned on, and the seventh NMOS transistor T7 is turned on.
  • the transmission signal Qn of the current stage outputted by the second signal transmission circuit 111 is at a low level.
  • the transmission signal Qn-1 of the previous stage is at a high level
  • the fifth NMOS transistor T5 is turned on
  • the third PMOS transistor P3 is turned off, so that the sixth NMOS transistor T6 is turned off
  • the second The signal transmission circuit 111 does not work, that is, the transmission signal Qn-1 of the previous stage cannot be transmitted to the NOR gate circuit 12 through the second signal transmission circuit 111;
  • the first NMOS transistor T1 is turned on, and the second NMOS transistor T2 is turned on.
  • the second PMOS transistor P2 is turned on, and the current signal transmission signal Qn outputted by the first signal transmission circuit 110 is at a high level.
  • the third NMOS transistor T3 is also turned on, and the first PMOS transistor P1 and the fourth NMOS transistor are turned on. T4 deadline.
  • the first signal transmission circuit 110 transmits the high-level portion of the transmission signal Qn-1 of the previous stage to the NOR gate latch circuit 12 at the rising edge of the first clock signal CK1, and the second signal transmission circuit 111
  • the rising edge of the first clock signal CK1 transfers the low level portion of the previous stage of the transmission signal Qn-1 to the NOR gate latch circuit 12, which in combination outputs the complete current stage transmission signal Qn to the NAND gate lock.
  • the circuit 12 is stored.
  • the NOR gate circuit 12 includes a NOR circuit 120, and the NOR circuit 120 includes an eighth NMOS transistor T8, a ninth NMOS transistor T9, a fourth PMOS transistor P4, and a fifth PMOS transistor P5, and an eighth
  • the gate of the NMOS transistor T8 is connected to the gate of the fourth PMOS transistor P4 and the signal transmission circuit 11, the drain is connected to the source of the ninth NMOS transistor T9, the source and the drain of the fourth PMOS transistor P4, and the fifth PMOS.
  • the drain of the tube P5 is connected, the gate of the ninth NMOS transistor T9 and the gate of the fifth PMOS transistor P5 are connected to the second clock signal CK2, the source of the fourth PMOS transistor P4 and the source of the fifth PMOS transistor P5 are connected.
  • a reference level Vgl is connected to the drain of the tube P5 .
  • the NOR gate latch circuit 12 further includes a multi-stage inverter circuit coupled to the NOR gate circuit 120.
  • the multi-stage inverter circuit includes a plurality of inverters 121 arranged in series, the inverter 121 includes a tenth NMOS transistor T10 and a sixth PMOS transistor P6, and the drain of the tenth NMOS transistor T10 is connected to the second reference level Vgh.
  • the source of the sixth PMOS transistor P6 is connected to the first reference level Vgl, and the gate of the tenth NMOS transistor T10 is connected to the gate of the sixth PMOS transistor P6, which is an input terminal of the inverter 121, and a NOR gate circuit.
  • the number of inverters is preferably three.
  • the first clock signal CK1 is shifted by one-half clock cycle to obtain the second clock signal CK2.
  • the specific working principle of the NAND latch circuit 12 is as follows: As can be seen from FIG. 1 together with FIG. 2, only when the rising edge of the second clock signal CK2 and the current stage transmission signal Qn output by the signal transmission circuit 11 are at a high level, The NOR circuit 120 outputs a low level, and outputs a high level after passing through the three-stage inverter 121, that is, the gate drive pulse Gn of the current stage outputted at this time is at a high level.
  • the first clock signal is the clock CK3
  • the second clock signal is the clock CK4
  • the gate of the first NMOS transistor T1 and the third PMOS transistor P3.
  • the gate and the gate of the first NMOS transistor T5 input the transmission signal Qn of the current stage.
  • the transmission signal Qn of the current stage is generated by the shift register circuit 10 of the nth stage.
  • the first signal transmission circuit 110 When the clock CK3 is a rising edge and the transmission signal Qn of the current stage (ie, the nth stage) is at a high level, the first signal transmission circuit 110 outputs a high level portion of the transmission signal Qn+1 of the (n+1)th stage, and the clock CK3 When the rising edge and the nth stage of the transmission signal Qn are at a low level, the second signal transmission circuit 111 outputs the low level portion of the n+1th stage of the transmission signal Qn+1, the first signal transmission circuit 110 and the second The signal transmission circuit 111 combines and outputs the complete n+1th transmission signal Qn+1.
  • the gate drive pulse Gn+1 of the n+1th stage is output through the NOR gate latch circuit composed of the NOR gate circuit 120 and the plurality of inverters 121 arranged in series.
  • the first clock signal is the clock CK2
  • the second clock signal is the clock CK1
  • the gate of the first NMOS transistor T1
  • the third PMOS transistor P3 The gate and the gate of the first NMOS transistor T5 are input to the n+1th order transmission signal Qn+1.
  • the n+1th transmission signal Qn+1 is generated by the n+1th stage shift register circuit 10.
  • the first signal transmission circuit 110 When the clock CK2 is a rising edge and the n+1th transmission signal Qn+1 is at a high level, the first signal transmission circuit 110 outputs a high level portion of the n+2th transmission signal Qn+2, and the clock CK2 is When the rising edge and the transmission signal Qn+1 of the n+1th stage are low level, the second signal transmission circuit 111 outputs the low level portion of the transmission signal Qn+2 of the n+2th stage, and the combination of the two outputs complete The transmission signal Qn+2 of the n+2th stage.
  • the gate drive pulse Gn+2 of the n+2th stage is output through the NOR gate latch circuit composed of the NOR gate circuit 120 and the plurality of inverters 121 arranged in series.
  • the first clock signal is the clock CK4
  • the second clock signal is the clock CK3
  • the gate of the first NMOS transistor T1 and the third PMOS transistor P3.
  • the gate and the gate of the first NMOS transistor T5 are input to the n+2th transmission signal Qn+2.
  • the transmission signal Qn+2 of the n+2th stage is generated by the shift register circuit 10 of the n+2th stage.
  • the first signal transmission circuit 110 When the clock CK4 is a rising edge and the n+2th transmission signal Qn+2 is at a high level, the first signal transmission circuit 110 outputs a high level portion of the n+3th transmission signal Qn+3, and the clock CK4 is When the rising edge and the transmission signal Qn+2 of the n+2th stage are low level, the second signal transmission circuit 111 outputs the low level part of the transmission signal Qn+3 of the n+3th stage, and the combination of the two outputs complete The transmission signal Qn+3 of the n+3th stage.
  • the gate drive pulse Gn+3 of the n+3th stage is output through the NOR gate latch circuit composed of the NOR gate circuit 120 and the plurality of inverters 121 arranged in series.
  • the first clock signal CK1 is offset by a quarter of a clock cycle to obtain a third clock signal CK3, and the first clock signal CK3 continues to be shifted by a quarter of a clock cycle to obtain a second clock signal CK2.
  • the first clock signal CK2 continues to shift by a quarter of a clock cycle to obtain the second clock signal CK4, that is, the clock CK4 is different from the clock CK3 by one-half clock cycle.
  • the clock CK2 and the clock CK1 are also separated by one-half clock cycle.
  • the gate register circuit 1 of the embodiment of the present invention is obtained by sequentially multiplexing the shift register circuit 10 of FIGS. 2 to 5 and sequentially cycling.
  • FIG. 6 is a timing chart showing the simulation of the gate driving circuit of the embodiment of the present invention.
  • the ordinate is the voltage Voltage and the abscissa is the time Time.
  • FIG. 6 simulates the clocks CK1, CK2, CK3, and CK4 of the shift register circuit 10 of the nth stage to the shift register circuit 10 of the n+3th stage, and the gate drive pulses Gn, Gn+1, Timing diagram of Gn+2 and Gn+3.
  • This timing chart corresponds to the gate drive circuit diagrams of FIGS. 2-5.
  • the gate drive pulse Gn of the nth stage in the gate drive circuit, the gate drive pulse Gn+1 of the n+1th stage, and the gate of the n+2th stage are sequentially output from the left to the right.
  • the present invention also provides a shift register circuit including a signal transfer circuit 11 and a NOR gate latch circuit 12.
  • the signal transmission circuit 11 includes a first signal transmission circuit 110 and a second signal transmission circuit 111.
  • the first signal transmission circuit 110 transmits the high-level portion of the transmission signal Qn-1 of the previous stage to the NOR gate latch circuit 12 in accordance with the first clock signal CK1.
  • the second signal transmission circuit 111 transmits the low-level portion of the transmission signal Qn-1 of the previous stage to the NOR gate latch circuit 12 for latching according to the first clock signal CK1, and is triggered by the second clock signal CK2. , the gate drive pulse Gn of the current stage is output.
  • the first signal transmission circuit 110 includes a first NMOS transistor T1, a second NMOS transistor T2, a third NMOS transistor T3, a fourth NMOS transistor T4, a first PMOS transistor P1, and a second PMOS transistor P2.
  • the gate of the first NMOS transistor T1 The gate of the second NMOS transistor T2 is connected to the first clock signal CK1, the source is connected to the drain of the first NMOS transistor T1, and the drain is connected to the source of the first PMOS transistor P1.
  • the gate of the tube P1, the source of the second PMOS transistor P2, and the drain of the fourth NMOS transistor T4 are connected, the source of the first NMOS transistor T1, the source of the third NMOS transistor T3, and the source of the fourth NMOS transistor T4.
  • the first reference level Vgl is connected to the first reference level Vgl, and the drain of the first PMOS transistor P1 and the drain of the second PMOS transistor P2 are connected to the second reference level Vgh.
  • the value of the first reference level Vgl is smaller than the value of the second reference level Vgh.
  • the second signal transmission circuit 111 includes a fifth NMOS transistor T5, a sixth NMOS transistor T6, a seventh NMOS transistor T7, and a third PMOS transistor P3.
  • the gate of the fifth NMOS transistor T5 is connected to the gate of the third PMOS transistor P3.
  • a drain of the fifth NMOS transistor T5 is connected to a source of the third PMOS transistor P3 and a gate of the sixth NMOS transistor T6, a source of the fifth NMOS transistor T5, and a sixth NMOS transistor
  • the source of T6 is connected to the first reference level Vgl
  • the drain of the third PMOS transistor P3 is connected to the second reference level Vgh
  • the drain of the sixth NMOS transistor T6 is connected to the source of the seventh NMOS transistor T7
  • the gate of the transistor T7 is connected to the first clock signal CK1
  • the drain of the seventh NMOS transistor T7 is connected to the NOR gate latch circuit 12.
  • the specific working principle of the signal transmission circuit 11 is as follows:
  • the transmission signal Qn-1 of the previous stage is at a low level
  • the first NMOS transistor T1 is turned off, and the first signal transmission circuit 110 does not work, that is, the transmission signal of the previous stage cannot be transmitted.
  • Qn-1 is transmitted to the NOR gate latch circuit 12 through the first signal transmission circuit 110; the fifth NMOS transistor T5 is turned off, and the third PMOS transistor P3 is turned on, so that the sixth NMOS transistor T6 is turned on, and the seventh NMOS transistor T7 is turned on.
  • the transmission signal Qn of the current stage outputted by the second signal transmission circuit 111 is at a low level.
  • the transmission signal Qn-1 of the previous stage is at a high level
  • the fifth NMOS transistor T5 is turned on
  • the third PMOS transistor P3 is turned off, so that the sixth NMOS transistor T6 is turned off
  • the second The signal transmission circuit 111 does not work, that is, the transmission signal Qn-1 of the previous stage cannot be transmitted to the NOR gate circuit 12 through the second signal transmission circuit 111;
  • the first NMOS transistor T1 is turned on, and the second NMOS transistor T2 is turned on.
  • the second PMOS transistor P2 is turned on, and the current signal transmission signal Qn outputted by the first signal transmission circuit 110 is at a high level.
  • the third NMOS transistor T3 is also turned on, and the first PMOS transistor P1 and the fourth NMOS transistor are turned on. T4 deadline.
  • the first signal transmission circuit 110 transmits the high-level portion of the transmission signal Qn-1 of the previous stage to the NOR gate latch circuit 12 at the rising edge of the first clock signal CK1, and the second signal transmission circuit 111
  • the rising edge of the first clock signal CK1 transfers the low level portion of the previous stage of the transmission signal Qn-1 to the NOR gate latch circuit 12, which in combination outputs the complete current stage transmission signal Qn to the NAND gate lock.
  • the circuit 12 is stored.
  • the NOR gate circuit 12 includes a NOR circuit 120, and the NOR circuit 120 includes an eighth NMOS transistor T8, a ninth NMOS transistor T9, a fourth PMOS transistor P4, and a fifth PMOS transistor P5, and an eighth
  • the gate of the NMOS transistor T8 is connected to the gate of the fourth PMOS transistor P4 and the signal transmission circuit 11, the drain is connected to the source of the ninth NMOS transistor T9, the source and the drain of the fourth PMOS transistor P4, and the fifth PMOS.
  • the drain of the tube P5 is connected, the gate of the ninth NMOS transistor T9 and the gate of the fifth PMOS transistor P5 are connected to the second clock signal CK2, the source of the fourth PMOS transistor P4 and the source of the fifth PMOS transistor P5 are connected.
  • a reference level Vgl is connected to the drain of the tube P5 .
  • the NOR gate latch circuit 12 further includes a multi-stage inverter circuit coupled to the NOR gate circuit 120.
  • the multi-stage inverter circuit includes a plurality of inverters 121 arranged in series, the inverter 121 includes a tenth NMOS transistor T10 and a sixth PMOS transistor P6, and the drain of the tenth NMOS transistor T10 is connected to the second reference level Vgh.
  • the source of the sixth PMOS transistor P6 is connected to the first reference level Vgl, and the gate of the tenth NMOS transistor T10 is connected to the gate of the sixth PMOS transistor P6, which is an input terminal of the inverter 121, and a NOR gate circuit.
  • the number of inverters is preferably three.
  • the first clock signal CK1 is shifted by one-half clock cycle to obtain the second clock signal CK2.
  • the specific working principle of the NAND latch circuit 12 is as follows: As can be seen from FIG. 1 together with FIG. 2, only when the rising edge of the second clock signal CK2 and the current stage transmission signal Qn output by the signal transmission circuit 11 are at a high level, The NOR circuit 120 outputs a low level, and outputs a high level after passing through the three-stage inverter 121, that is, the gate drive pulse Gn of the current stage outputted at this time is at a high level.
  • the gate driving circuit 1 of the present invention includes a plurality of cascaded shift register circuits 10, each shift register circuit 10 includes a signal transmission circuit 11 and a NOR gate latch circuit 12, and a signal transmission circuit 11 includes a first signal transmission circuit 110 and a second signal transmission circuit 111, and the first signal transmission circuit 110 transmits a high level portion of the transmission signal of the previous stage to the NOR gate latch circuit 12 according to the first clock signal,
  • the second signal transmission circuit 111 transmits the low-level portion of the transmission signal of the previous stage to the NOR gate latch circuit 12 according to the first clock signal, or the NOT gate latch circuit 12 is used to latch the transmission signal, and Triggered by the second clock signal to output the gate drive pulse of the current stage, which can be applied to a CMOS process, with low power consumption and wide noise margin.

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Abstract

一种栅极驱动电路（1）以及移位寄存电路（10），栅极驱动电路（1）包括多个级联设置的移位寄存电路（10），每一移位寄存电路（10）包括信号传输电路（11）以及或非门锁存电路（12），其中信号传输电路（11）包括第一信号传输电路（110）和第二信号传输电路（111），第一信号传输电路（110）根据第一时钟信号（CK1）将前一级的传输信号（Qn-1）的高电平部分传输至或非门锁存电路（12），第二信号传输电路（111）根据第一时钟信号（CK1）将前一级的传输信号（Qn-1）的低电平部分传输至或非门锁存电路（12）以进行锁存，并由第二时钟信号（CK2）进行触发，输出当前级的栅极驱动脉冲（Gn）。通过以上方式，栅极驱动电路（1）能够适用于CMOS制程，功耗低、噪声容限宽。

Description

栅极驱动电路以及移位寄存电路
【技术领域】
本发明涉及液晶显示技术领域，特别是涉及一种栅极驱动电路以及移位寄存电路。
【背景技术】
GOA（Gate Driver On Array）电路是利用现有的液晶显示器的Array制程将栅极扫描驱动电路制作在Array基板上，以实现逐行扫描的驱动方式。其具有降低生产成本和窄边框设计的优点，为多种显示器所使用。GOA电路要具有两项基本功能：第一是输入栅极驱动脉冲，驱动面板内的栅极线，打开显示区内的TFT（Thin Film Transistor，薄膜场效应晶体管），由栅极线对像素进行充电；第二是移位寄存，当第n个栅极驱动脉冲输出完成后，可以通过时钟控制进行n+1个栅极驱动脉冲的输出，并依此传递下去。
GOA电路包括上拉电路（Pull-up circuit）、上拉控制电路（Pull-up control circuit）、下传电路（Pull-down circuit）、下拉电路（Pull-down control circuit）以及负责电位抬升的上升电路（Boost circuit）。具体地，上拉电路主要负责将输入的时钟讯号（Clock）输出至薄膜晶体管的栅极，作为液晶显示器的驱动信号。上拉控制电路负责控制上拉电路的打开，一般是由上级GOA电路传递来的信号作用。下拉电路负责在输出扫描信号后，快速将扫描信号拉低为低电位，即薄膜晶体管的栅极的电位拉低为低电位；下拉保持电路则负责将扫描信号和上拉电路的信号（通常称为Q点） 保持在关闭状态（即设定的负电位），通常有两个下拉保持电路交替作用。上升电路则负责Q点电位的二次抬升，这样确保上拉电路的G(N)正常输出。
不同的GOA电路可以使用不同的制程。LTPS（Low Temperature Poly-silicon，低温多晶硅）制程具有高电子迁移率和技术成熟的优点，目前被中小尺寸显示器广泛使用。CMOS（Complementary Metal Oxide Semiconductor，互补金属氧化物半导体） LTPS制程具有低功耗、电子迁移率高、噪声容限宽等优点, 因此逐渐为面板厂商使用，如此需要开发与CMOS LTPS制程对应的GOA电路。
【发明内容】
本发明实施例提供了一种栅极驱动电路以及移位寄存电路，能够适用于CMOS制程，功耗低、噪声容限宽。
本发明提供一种栅极驱动电路，包括多个级联设置的移位寄存电路，每一移位寄存电路包括信号传输电路以及或非门锁存电路，其中信号传输电路包括第一信号传输电路和第二信号传输电路，第一信号传输电路根据第一时钟信号将前一级的传输信号的高电平部分传输至或非门锁存电路，第二信号传输电路根据第一时钟信号将前一级的传输信号的低电平部分传输至或非门锁存电路以进行锁存，并由第二时钟信号进行触发，输出当前级的栅极驱动脉冲。
其中，信号传输电路和或非门锁存电路分别为上升沿触发。
其中，第一信号传输电路包括第一NMOS管、第二NMOS管、第三NMOS管、第四NMOS管、第一PMOS管以及第二PMOS管，第一NMOS管的栅极接前一级的传输信号，第二NMOS管的栅极接第一时钟信号，源极与第一NMOS管的漏极连接，漏极与第一PMOS管的源极、第二PMOS管的栅极、第三NMOS管的漏极、第四NMOS管的栅极以及或非门锁存电路连接，第三NMOS管的栅极与第一PMOS管的栅极、第二PMOS管的源极以及第四NMOS管的漏极连接，第一NMOS管的源极、第三NMOS管的源极以及第四NMOS管的源极接第一参考电平，第一PMOS管的漏极与第二PMOS管的漏极接第二参考电平。
其中，第二信号传输电路包括第五NMOS管、第六NMOS管、第七NMOS管以及第三PMOS管，第五NMOS管的栅极与第三PMOS管的栅极接前一级的传输信号，第五NMOS管的漏极与第三PMOS管的源极以及第六NMOS管的栅极连接，第五NMOS管的源极以及第六NMOS管的源极接第一参考电平，第三PMOS管的漏极接第二参考电平，第六NMOS管的漏极与第七NMOS管的源极连接，第七NMOS管的栅极接第一时钟信号，第七NMOS管的漏极与或非门锁存电路连接。
其中，或非门锁存电路包括一或非门电路，或非门电路包括第八NMOS管、第九NMOS管、第四PMOS管以及第五PMOS管，第八NMOS管的栅极与第四PMOS管的栅极以及信号传输电路连接，漏极与第九NMOS管的源极连接，源极与第四PMOS管的漏极以及第五PMOS管的漏极连接，第九NMOS管的栅极和第五PMOS管的栅极接第二时钟信号，第四PMOS管的源极以及第五PMOS管的源极接第一参考电平。
其中，或非门锁存电路进一步包括与或非门电路连接的多级反相电路。
其中，多级反相电路包括串联设置的多个反相器，反相器包括第十NMOS管和第六PMOS管，第十NMOS管的漏极接第二参考电平，第六PMOS管的源极接第一参考电平，第十NMOS管的栅极与第六PMOS管的栅极连接，为反相器的输入端，与或非门电路或者前一级的反相器连接，第十NMOS管的源极与第六PMOS管的漏极连接，为反相器的输出端。
其中，反相器的数量为三个。
其中，第一时钟信号偏移二分之一个时钟周期得到第二时钟信号。
本发明还提供一种移位寄存电路，包括信号传输电路以及或非门锁存电路，信号传输电路包括第一信号传输电路和第二信号传输电路，第一信号传输电路根据第一时钟信号将前一级的传输信号的高电平部分传输至或非门锁存电路，第二信号传输电路根据第一时钟信号将前一级的传输信号的低电平部分传输至或非门锁存电路以进行锁存，并由第二时钟信号进行触发，输出当前级的栅极驱动脉冲。
其中，信号传输电路和或非门锁存电路分别为上升沿触发。
其中，第一信号传输电路包括第一NMOS管、第二NMOS管、第三NMOS管、第四NMOS管、第一PMOS管以及第二PMOS管，第一NMOS管的栅极接前一级的传输信号，第二NMOS管的栅极接第一时钟信号，源极与第一NMOS管的漏极连接，漏极与第一PMOS管的源极、第二PMOS管的栅极、第三NMOS管的漏极、第四NMOS管的栅极以及或非门锁存电路连接，第三NMOS管的栅极与第一PMOS管的栅极、第二PMOS管的源极以及第四NMOS管的漏极连接，第一NMOS管的源极、第三NMOS管的源极以及第四NMOS管的源极接第一参考电平，第一PMOS管的漏极与第二PMOS管的漏极接第二参考电平。
其中，第二信号传输电路包括第五NMOS管、第六NMOS管、第七NMOS管以及第三PMOS管，第五NMOS管的栅极与第三PMOS管的栅极接前一级的传输信号，第五NMOS管的漏极与第三PMOS管的源极以及第六NMOS管的栅极连接，第五NMOS管的源极以及第六NMOS管的源极接第一参考电平，第三PMOS管的漏极接第二参考电平，第六NMOS管的漏极与第七NMOS管的源极连接，第七NMOS管的栅极接第一时钟信号，第七NMOS管的漏极与或非门锁存电路连接。
其中，或非门锁存电路包括一或非门电路，或非门电路包括第八NMOS管、第九NMOS管、第四PMOS管以及第五PMOS管，第八NMOS管的栅极与第四PMOS管的栅极以及信号传输电路连接，漏极与第九NMOS管的源极连接，源极与第四PMOS管的漏极以及第五PMOS管的漏极连接，第九NMOS管的栅极和第五PMOS管的栅极接第二时钟信号，第四PMOS管的源极以及第五PMOS管的源极接第一参考电平。
其中，或非门锁存电路进一步包括与或非门电路连接的多级反相电路。
其中，多级反相电路包括串联设置的多个反相器，反相器包括第十NMOS管和第六PMOS管，第十NMOS管的漏极接第二参考电平，第六PMOS管的源极接第一参考电平，第十NMOS管的栅极与第六PMOS管的栅极连接，为反相器的输入端，与或非门电路或者前一级的反相器连接，第十NMOS管的源极与第六PMOS管的漏极连接，为反相器的输出端。
其中，反相器的数量为三个。
其中，第一时钟信号偏移二分之一个时钟周期得到第二时钟信号。
通过上述方案，本发明的有益效果是：本发明的栅极驱动电路包括多个级联设置的移位寄存电路，每一移位寄存电路包括信号传输电路以及或非门锁存电路，信号传输电路包括第一信号传输电路和第二信号传输电路，通过第一信号传输电路根据第一时钟信号将前一级的传输信号的高电平部分传输至或非门锁存电路，第二信号传输电路根据第一时钟信号将前一级的传输信号的低电平部分传输至或非门锁存电路，或非门锁存电路用于对传输信号进行锁存，并由第二时钟信号进行触发，输出当前级的栅极驱动脉冲，能够适用于CMOS制程，功耗低、噪声容限宽。
【附图说明】
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。其中：
图1是本发明实施例的驱动电路的结构示意图；
图2是图1中的第n级的移位寄存电路的电路图；
图3是图1中的第n+1级的移位寄存电路的电路图；
图4是图1中的第n+2级的移位寄存电路的电路图；
图5是图1中的第n+3级的移位寄存电路的电路图;
图6是本发明实施例的栅极驱动电路的模拟时序图。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性的劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参见图1所示，图1是本发明实施例的栅极驱动电路的结构示意图。如图1所示，栅极驱动电路1包括多个级联设置的移位寄存电路10，每一移位寄存电路10包括信号传输电路11以及或非门锁存电路12，其中信号传输电路11包括第一信号传输电路110和第二信号传输电路111，第一信号传输电路110根据第一时钟信号将前一级的传输信号Qn-1的高电平部分传输至或非门锁存电路12，第二信号传输电路111根据第一时钟信号将前一级的传输信号Qn-1的低电平部分传输至或非门锁存电路12，或非门锁存电路12用于对传输信号Qn-1进行锁存，并由第二时钟信号CK2进行触发，输出当前级的栅极驱动脉冲Gn。其中，信号传输电路11和或非门锁存电路12分别为上升沿触发。前一级的传输信号Qn-1经过信号传输电路11传输后输出当前级的传输信号Qn，经或非门锁存电路12输出当前级的栅极驱动脉冲Gn。当前级的传输信号Qn在下一级的移位寄存电路10中通过信号传输电路11传输后输出下一极的传输信号Qn+1，经下一级的移位寄存电路10中的或非门锁存电路12输出下一级的栅极驱动脉冲Gn+1，以此连续传递，能够输出各级栅极驱动脉冲。本发明实施例通过信号传输电路11控制上下级信号传递，通过或非门锁存电路12锁存信号，能够适用于CMOS制程，功耗低、噪声容限宽。
在更具体的实施例中，如图2所示，以第n级的移位寄存器为例，n为正整数，第一信号传输电路110包括第一NMOS管T1、第二NMOS管T2、第三NMOS管T3、第四NMOS管T4、第一PMOS管P1以及第二PMOS管P2，第一NMOS管T1的栅极接前一级的传输信号Qn-1，第二NMOS管T2的栅极接第一时钟信号CK1，源极与第一NMOS管T1的漏极连接，漏极与第一PMOS管P1的源极、第二PMOS管P2的栅极、第三NMOS管T3的漏极、第四NMOS管T4的栅极以及或非门锁存电路12连接，第三NMOS管T3的栅极与第一PMOS管P1的栅极、第二PMOS管P2的源极以及第四NMOS管T4的漏极连接，第一NMOS管T1的源极、第三NMOS管T3的源极以及第四NMOS管T4的源极接第一参考电平Vgl，第一PMOS管P1的漏极与第二PMOS管P2的漏极接第二参考电平Vgh。其中，第一参考电平Vgl的值小于第二参考电平Vgh的值。
第二信号传输电路111包括第五NMOS管T5、第六NMOS管T6、第七NMOS管T7以及第三PMOS管P3，第五NMOS管T5的栅极与第三PMOS管P3的栅极接前一级的传输信号Qn-1，第五NMOS管T5的漏极与第三PMOS管P3的源极以及第六NMOS管T6的栅极连接，第五NMOS管T5的源极以及第六NMOS管T6的源极接第一参考电平Vgl，第三PMOS管P3的漏极接第二参考电平Vgh，第六NMOS管T6的漏极与第七NMOS管T7的源极连接，第七NMOS管T7的栅极接第一时钟信号CK1，第七NMOS管T7的漏极与或非门锁存电路12连接。
信号传输电路11具体的工作原理如下：
如果第一时钟信号为上升沿时，前一级的传输信号Qn-1为低电平，则第一NMOS管T1截止，第一信号传输电路110不工作，即不能将前一级的传输信号Qn-1通过第一信号传输电路110传输至或非门锁存电路12；第五NMOS管T5截止，第三PMOS管P3导通，使得第六NMOS管T6导通，同时第七NMOS管T7导通，第二信号传输电路111输出的当前级的传输信号Qn为低电平。
如果第一时钟信号为上升沿时，前一级的传输信号Qn-1为高电平，则第五NMOS管T5导通，第三PMOS管P3截止，使得第六NMOS管T6截止，第二信号传输电路111不工作，即不能将前一级的传输信号Qn-1通过第二信号传输电路111传输至或非门锁存电路12；第一NMOS管T1导通，第二NMOS管T2导通，第二PMOS管P2导通，第一信号传输电路110输出的当前级的传输信号Qn为高电平，此时第三NMOS管T3也导通，第一PMOS管P1和第四NMOS管T4截止。
因此，第一信号传输电路110在第一时钟信号CK1的上升沿将前一级的传输信号Qn-1的高电平部分传输至或非门锁存电路12，而第二信号传输电路111在第一时钟信号CK1的上升沿将前一级的传输信号Qn-1的低电平部分传输至或非门锁存电路12，两者结合输出完整的当前级的传输信号Qn至或非门锁存电路12。
优选地，或非门锁存电路12包括一或非门电路120，或非门电路120包括第八NMOS管T8、第九NMOS管T9、第四PMOS管P4以及第五PMOS管P5，第八NMOS管T8的栅极与第四PMOS管P4的栅极以及信号传输电路11连接，漏极与第九NMOS管T9的源极连接，源极与第四PMOS管P4的漏极以及第五PMOS管P5的漏极连接，第九NMOS管T9的栅极和第五PMOS管P5的栅极接第二时钟信号CK2，第四PMOS管P4的源极以及第五PMOS管P5的源极接第一参考电平Vgl。
优选地，或非门锁存电路12进一步包括与或非门电路120连接的多级反相电路。其中，多级反相电路包括串联设置的多个反相器121，反相器121包括第十NMOS管T10和第六PMOS管P6，第十NMOS管T10的漏极接第二参考电平Vgh，第六PMOS管P6的源极接第一参考电平Vgl，第十NMOS管T10的栅极与第六PMOS管P6的栅极连接，为反相器121的输入端，与或非门电路120或者前一级的反相器121连接，第十NMOS管T10的源极与第六PMOS管P6的漏极连接，为反相器121的输出端，与下一级的反相器121连接，或者作为末级输出。在本发明实施例中，反相器的数量优选为三个。第一时钟信号CK1偏移二分之一个时钟周期得到第二时钟信号CK2。
或非门锁存电路12具体的工作原理如下：由图1结合图2可知，只有在第二时钟信号CK2的上升沿，且信号传输电路11输出的当前级的传输信号Qn为高电平时，或非门电路120才输出低电平，经过三级反相器121后输出高电平，即此时输出的当前级的栅极驱动脉冲Gn为高电平。
如图3所示，在第n+1级的移位寄存电路10中，第一时钟信号为时钟CK3，第二时钟信号为时钟CK4，第一NMOS管T1的栅极、第三PMOS管P3的栅极以及第一NMOS管T5的栅极输入当前级的传输信号Qn。其中当前级的传输信号Qn由第n级的移位寄存电路10产生。时钟CK3为上升沿，且当前级(即第n级)的传输信号Qn为高电平时，第一信号传输电路110输出第n+1级的传输信号Qn+1的高电平部分，时钟CK3为上升沿，且第n级的传输信号Qn为低电平时，第二信号传输电路111输出第n+1级的传输信号Qn+1的低电平部分，第一信号传输电路110和第二信号传输电路111组合输出完整的第n+1级的传输信号Qn+1。再经过由或非门电路120和串联设置的多个反相器121组成的或非门锁存电路输出第n+1级的栅极驱动脉冲Gn+1。
如图4所示，在第n+2级的移位寄存电路10中，第一时钟信号为时钟CK2，第二时钟信号为时钟CK1，第一NMOS管T1的栅极、第三PMOS管P3的栅极以及第一NMOS管T5的栅极输入第n+1级的传输信号Qn+1。其中第n+1级的传输信号Qn+1由第n+1级的移位寄存电路10产生。时钟CK2为上升沿，且第n+1级的传输信号Qn+1为高电平时，第一信号传输电路110输出第n+2级的传输信号Qn+2的高电平部分，时钟CK2为上升沿，且第n+1级的传输信号Qn+1为低电平时，第二信号传输电路111输出第n+2级的传输信号Qn+2的低电平部分，两者组合输出完整的第n+2级的传输信号Qn+2。再经过由或非门电路120和串联设置的多个反相器121组成的或非门锁存电路输出第n+2级的栅极驱动脉冲Gn+2。
如图5所示，在第n+3级的移位寄存电路10中，第一时钟信号为时钟CK4，第二时钟信号为时钟CK3，第一NMOS管T1的栅极、第三PMOS管P3的栅极以及第一NMOS管T5的栅极输入第n+2级的传输信号Qn+2。其中第n+2级的传输信号Qn+2由第n+2级的移位寄存电路10产生。时钟CK4为上升沿，且第n+2级的传输信号Qn+2为高电平时，第一信号传输电路110输出第n+3级的传输信号Qn+3的高电平部分，时钟CK4为上升沿，且第n+2级的传输信号Qn+2为低电平时，第二信号传输电路111输出第n+3级的传输信号Qn+3的低电平部分，两者组合输出完整的第n+3级的传输信号Qn+3。再经过由或非门电路120和串联设置的多个反相器121组成的或非门锁存电路输出第n+3级的栅极驱动脉冲Gn+3。
以上图2至图5中，第一时钟信号CK1偏移四分之一个时钟周期得到第三时钟信号CK3，第一时钟信号CK3继续偏移四分之一个时钟周期得到第二时钟信号CK2，第一时钟信号CK2继续偏移四分之一个时钟周期得到第二时钟信号CK4，即时钟CK4与时钟CK3相差二分之一个时钟周期。而时钟CK2与时钟CK1也相差二分之一个时钟周期。
将以上图2至图5中的移位寄存电路10顺次级联，并依次循环即得到本发明实施例的栅极驱动电路1。
图6是本发明实施例的栅极驱动电路的模拟时序图。纵坐标为电压Voltage，横坐标为时间Time。其中，图6模拟出第n级的移位寄存电路10至第n+3级的移位寄存电路10的时钟CK1、CK2、CK3以及CK4，和栅极驱动脉冲Gn、Gn+1、 Gn+2以及Gn+3的时序图。该时序图与图2-图5中的栅极驱动电路图相对应。从图中可以看出，从左边至右边依次输出栅极驱动电路中的第n级的栅极驱动脉冲Gn、第n+1级的栅极驱动脉冲Gn+1、第n+2级的栅极驱动脉冲Gn+2以及第n+3级的栅极驱动脉冲Gn+3。可见，栅极驱动电路的模拟时序与期望的理论时序相同，能够适用于CMOS制程，功耗低、噪声容限宽。
本发明还提供一种移位寄存电路，移位寄存电路10包括信号传输电路11以及或非门锁存电路12。参见图2，信号传输电路11包括第一信号传输电路110和第二信号传输电路111。第一信号传输电路110根据第一时钟信号CK1将前一级的传输信号Qn-1的高电平部分传输至或非门锁存电路12。第二信号传输电路111根据第一时钟信号CK1将前一级的传输信号Qn-1的低电平部分传输至或非门锁存电路12以进行锁存，并由第二时钟信号CK2进行触发，输出当前级的栅极驱动脉冲Gn。
第一信号传输电路110包括第一NMOS管T1、第二NMOS管T2、第三NMOS管T3、第四NMOS管T4、第一PMOS管P1以及第二PMOS管P2，第一NMOS管T1的栅极接前一级的传输信号Qn-1，第二NMOS管T2的栅极接第一时钟信号CK1，源极与第一NMOS管T1的漏极连接，漏极与第一PMOS管P1的源极、第二PMOS管P2的栅极、第三NMOS管T3的漏极、第四NMOS管T4的栅极以及或非门锁存电路12连接，第三NMOS管T3的栅极与第一PMOS管P1的栅极、第二PMOS管P2的源极以及第四NMOS管T4的漏极连接，第一NMOS管T1的源极、第三NMOS管T3的源极以及第四NMOS管T4的源极接第一参考电平Vgl，第一PMOS管P1的漏极与第二PMOS管P2的漏极接第二参考电平Vgh。其中，第一参考电平Vgl的值小于第二参考电平Vgh的值。
第二信号传输电路111包括第五NMOS管T5、第六NMOS管T6、第七NMOS管T7以及第三PMOS管P3，第五NMOS管T5的栅极与第三PMOS管P3的栅极接前一级的传输信号Qn-1，第五NMOS管T5的漏极与第三PMOS管P3的源极以及第六NMOS管T6的栅极连接，第五NMOS管T5的源极以及第六NMOS管T6的源极接第一参考电平Vgl，第三PMOS管P3的漏极接第二参考电平Vgh，第六NMOS管T6的漏极与第七NMOS管T7的源极连接，第七NMOS管T7的栅极接第一时钟信号CK1，第七NMOS管T7的漏极与或非门锁存电路12连接。
信号传输电路11具体的工作原理如下：
如果第一时钟信号为上升沿时，前一级的传输信号Qn-1为低电平，则第一NMOS管T1截止，第一信号传输电路110不工作，即不能将前一级的传输信号Qn-1通过第一信号传输电路110传输至或非门锁存电路12；第五NMOS管T5截止，第三PMOS管P3导通，使得第六NMOS管T6导通，同时第七NMOS管T7导通，第二信号传输电路111输出的当前级的传输信号Qn为低电平。
如果第一时钟信号为上升沿时，前一级的传输信号Qn-1为高电平，则第五NMOS管T5导通，第三PMOS管P3截止，使得第六NMOS管T6截止，第二信号传输电路111不工作，即不能将前一级的传输信号Qn-1通过第二信号传输电路111传输至或非门锁存电路12；第一NMOS管T1导通，第二NMOS管T2导通，第二PMOS管P2导通，第一信号传输电路110输出的当前级的传输信号Qn为高电平，此时第三NMOS管T3也导通，第一PMOS管P1和第四NMOS管T4截止。
因此，第一信号传输电路110在第一时钟信号CK1的上升沿将前一级的传输信号Qn-1的高电平部分传输至或非门锁存电路12，而第二信号传输电路111在第一时钟信号CK1的上升沿将前一级的传输信号Qn-1的低电平部分传输至或非门锁存电路12，两者结合输出完整的当前级的传输信号Qn至或非门锁存电路12。
优选地，或非门锁存电路12包括一或非门电路120，或非门电路120包括第八NMOS管T8、第九NMOS管T9、第四PMOS管P4以及第五PMOS管P5，第八NMOS管T8的栅极与第四PMOS管P4的栅极以及信号传输电路11连接，漏极与第九NMOS管T9的源极连接，源极与第四PMOS管P4的漏极以及第五PMOS管P5的漏极连接，第九NMOS管T9的栅极和第五PMOS管P5的栅极接第二时钟信号CK2，第四PMOS管P4的源极以及第五PMOS管P5的源极接第一参考电平Vgl。
优选地，或非门锁存电路12进一步包括与或非门电路120连接的多级反相电路。其中，多级反相电路包括串联设置的多个反相器121，反相器121包括第十NMOS管T10和第六PMOS管P6，第十NMOS管T10的漏极接第二参考电平Vgh，第六PMOS管P6的源极接第一参考电平Vgl，第十NMOS管T10的栅极与第六PMOS管P6的栅极连接，为反相器121的输入端，与或非门电路120或者前一级的反相器121连接，第十NMOS管T10的源极与第六PMOS管P6的漏极连接，为反相器121的输出端，与下一级的反相器121连接，或者作为末级输出。在本发明实施例中，反相器的数量优选为三个。第一时钟信号CK1偏移二分之一个时钟周期得到第二时钟信号CK2。
或非门锁存电路12具体的工作原理如下：由图1结合图2可知，只有在第二时钟信号CK2的上升沿，且信号传输电路11输出的当前级的传输信号Qn为高电平时，或非门电路120才输出低电平，经过三级反相器121后输出高电平，即此时输出的当前级的栅极驱动脉冲Gn为高电平。
综上所述，本发明的栅极驱动电路1包括多个级联设置的移位寄存电路10，每一移位寄存电路10包括信号传输电路11以及或非门锁存电路12，信号传输电路11包括第一信号传输电路110和第二信号传输电路111，通过第一信号传输电路110根据第一时钟信号将前一级的传输信号的高电平部分传输至或非门锁存电路12，第二信号传输电路111根据第一时钟信号将前一级的传输信号的低电平部分传输至或非门锁存电路12，或非门锁存电路12用于对传输信号进行锁存，并由第二时钟信号进行触发，输出当前级的栅极驱动脉冲，能够适用于CMOS制程，功耗低、噪声容限宽。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (18)

  1. 一种栅极驱动电路，其中，所述栅极驱动电路包括多个级联设置的移位寄存电路，每一所述移位寄存电路包括信号传输电路以及或非门锁存电路，其中所述信号传输电路包括第一信号传输电路和第二信号传输电路，所述第一信号传输电路根据第一时钟信号将前一级的传输信号的高电平部分传输至所述或非门锁存电路，所述第二信号传输电路根据第一时钟信号将所述前一级的传输信号的低电平部分传输至所述或非门锁存电路以进行锁存，并由第二时钟信号进行触发，输出当前级的栅极驱动脉冲。
  2. 根据权利要求1所述的栅极驱动电路，其中，所述信号传输电路和所述或非门锁存电路分别为上升沿触发。
  3. 根据权利要求1所述的栅极驱动电路，其中，所述第一信号传输电路包括第一NMOS管、第二NMOS管、第三NMOS管、第四NMOS管、第一PMOS管以及第二PMOS管，所述第一NMOS管的栅极接所述前一级的传输信号，所述第二NMOS管的栅极接所述第一时钟信号，源极与所述第一NMOS管的漏极连接，漏极与所述第一PMOS管的源极、所述第二PMOS管的栅极、所述第三NMOS管的漏极、所述第四NMOS管的栅极以及所述或非门锁存电路连接，所述第三NMOS管的栅极与所述第一PMOS管的栅极、所述第二PMOS管的源极以及所述第四NMOS管的漏极连接，所述第一NMOS管的源极、所述第三NMOS管的源极以及所述第四NMOS管的源极接第一参考电平，所述第一PMOS管的漏极与所述第二PMOS管的漏极接第二参考电平。
  4. 根据权利要求1所述的栅极驱动电路，其中，所述第二信号传输电路包括第五NMOS管、第六NMOS管、第七NMOS管以及第三PMOS管，所述第五NMOS管的栅极与所述第三PMOS管的栅极接所述前一级的传输信号，所述第五NMOS管的漏极与所述第三PMOS管的源极以及所述第六NMOS管的栅极连接，所述第五NMOS管的源极以及所述第六NMOS管的源极接第一参考电平，所述第三PMOS管的漏极接第二参考电平，所述第六NMOS管的漏极与所述第七NMOS管的源极连接，所述第七NMOS管的栅极接所述第一时钟信号，所述第七NMOS管的漏极与所述或非门锁存电路连接。
  5. 根据权利要求1所述的栅极驱动电路，其中，所述或非门锁存电路包括一或非门电路，所述或非门电路包括第八NMOS管、第九NMOS管、第四PMOS管以及第五PMOS管，所述第八NMOS管的栅极与所述第四PMOS管的栅极以及所述信号传输电路连接，漏极与所述第九NMOS管的源极连接，源极与所述第四PMOS管的漏极以及所述第五PMOS管的漏极连接，所述第九NMOS管的栅极和所述第五PMOS管的栅极接所述第二时钟信号，所述第四PMOS管的源极以及所述第五PMOS管的源极接第一参考电平。
  6. 根据权利要求5所述的栅极驱动电路，其中，所述或非门锁存电路进一步包括与所述或非门电路连接的多级反相电路。
  7. 根据权利要求6所述的栅极驱动电路，其中，所述多级反相电路包括串联设置的多个反相器，所述反相器包括第十NMOS管和第六PMOS管，所述第十NMOS管的漏极接所述第二参考电平，所述第六PMOS管的源极接所述第一参考电平，所述第十NMOS管的栅极与所述第六PMOS管的栅极连接，为所述反相器的输入端，与所述或非门电路或者前一级的所述反相器连接，所述第十NMOS管的源极与所述第六PMOS管的漏极连接，为所述反相器的输出端。
  8. 根据权利要求7所述的栅极驱动电路，其中，所述反相器的数量为三个。
  9. 根据权利要求1所述的栅极驱动电路，其中，所述第一时钟信号偏移二分之一个时钟周期得到所述第二时钟信号。
  10. 一种移位寄存电路，其中，所述移位寄存电路包括信号传输电路以及或非门锁存电路，所述信号传输电路包括第一信号传输电路和第二信号传输电路，所述第一信号传输电路根据第一时钟信号将前一级的传输信号的高电平部分传输至所述或非门锁存电路，所述第二信号传输电路根据第一时钟信号将所述前一级的传输信号的低电平部分传输至所述或非门锁存电路以进行锁存，并由第二时钟信号进行触发，输出当前级的栅极驱动脉冲。
  11. 根据权利要求10所述的移位寄存电路，其中，所述信号传输电路和所述或非门锁存电路分别为上升沿触发。
  12. 根据权利要求10所述的移位寄存电路，其中，所述第一信号传输电路包括第一NMOS管、第二NMOS管、第三NMOS管、第四NMOS管、第一PMOS管以及第二PMOS管，所述第一NMOS管的栅极接所述前一级的传输信号，所述第二NMOS管的栅极接所述第一时钟信号，源极与所述第一NMOS管的漏极连接，漏极与所述第一PMOS管的源极、所述第二PMOS管的栅极、所述第三NMOS管的漏极、所述第四NMOS管的栅极以及所述或非门锁存电路连接，所述第三NMOS管的栅极与所述第一PMOS管的栅极、所述第二PMOS管的源极以及所述第四NMOS管的漏极连接，所述第一NMOS管的源极、所述第三NMOS管的源极以及所述第四NMOS管的源极接第一参考电平，所述第一PMOS管的漏极与所述第二PMOS管的漏极接第二参考电平。
  13. 根据权利要求10所述的移位寄存电路，其中，所述第二信号传输电路包括第五NMOS管、第六NMOS管、第七NMOS管以及第三PMOS管，所述第五NMOS管的栅极与所述第三PMOS管的栅极接所述前一级的传输信号，所述第五NMOS管的漏极与所述第三PMOS管的源极以及所述第六NMOS管的栅极连接，所述第五NMOS管的源极以及所述第六NMOS管的源极接第一参考电平，所述第三PMOS管的漏极接第二参考电平，所述第六NMOS管的漏极与所述第七NMOS管的源极连接，所述第七NMOS管的栅极接所述第一时钟信号，所述第七NMOS管的漏极与所述或非门锁存电路连接。
  14. 根据权利要求10所述的移位寄存电路，其中，所述或非门锁存电路包括一或非门电路，所述或非门电路包括第八NMOS管、第九NMOS管、第四PMOS管以及第五PMOS管，所述第八NMOS管的栅极与所述第四PMOS管的栅极以及所述信号传输电路连接，漏极与所述第九NMOS管的源极连接，源极与所述第四PMOS管的漏极以及所述第五PMOS管的漏极连接，所述第九NMOS管的栅极和所述第五PMOS管的栅极接所述第二时钟信号，所述第四PMOS管的源极以及所述第五PMOS管的源极接第一参考电平。
  15. 根据权利要求14所述的移位寄存电路，其中，所述或非门锁存电路进一步包括与所述或非门电路连接的多级反相电路。
  16. 根据权利要求15所述的移位寄存电路，其中，所述多级反相电路包括串联设置的多个反相器，所述反相器包括第十NMOS管和第六PMOS管，所述第十NMOS管的漏极接所述第二参考电平，所述第六PMOS管的源极接所述第一参考电平，所述第十NMOS管的栅极与所述第六PMOS管的栅极连接，为所述反相器的输入端，与所述或非门电路或者前一级的所述反相器连接，所述第十NMOS管的源极与所述第六PMOS管的漏极连接，为所述反相器的输出端。
  17. 根据权利要求16所述的移位寄存电路，其中，所述反相器的数量为三个。
  18. 根据权利要求10所述的移位寄存电路，其中，所述第一时钟信号偏移二分之一个时钟周期得到所述第二时钟信号。
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