WO2017067336A1 - 阵列基板及其制作方法、显示面板、显示装置 - Google Patents

阵列基板及其制作方法、显示面板、显示装置 Download PDF

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WO2017067336A1
WO2017067336A1 PCT/CN2016/097961 CN2016097961W WO2017067336A1 WO 2017067336 A1 WO2017067336 A1 WO 2017067336A1 CN 2016097961 W CN2016097961 W CN 2016097961W WO 2017067336 A1 WO2017067336 A1 WO 2017067336A1
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amorphous silicon
silicon layer
region
photoresist
layer
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PCT/CN2016/097961
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English (en)
French (fr)
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田雪雁
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京东方科技集团股份有限公司
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Priority to US15/537,748 priority Critical patent/US10084000B2/en
Publication of WO2017067336A1 publication Critical patent/WO2017067336A1/zh

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    • H01L27/1229—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with different crystal properties within a device or between different devices
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    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
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    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1233—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with different thicknesses of the active layer in different devices
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H01L27/1281—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor by using structural features to control crystal growth, e.g. placement of grain filters
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H01L27/1285—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/10—Materials and properties semiconductor
    • G02F2202/104—Materials and properties semiconductor poly-Si
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • Embodiments of the present disclosure relate to an array substrate, a method of fabricating the same, a display panel, and a display device.
  • AMOLED Active Matrix Organic Light Emitting Diode
  • the polysilicon layer of a thin film transistor is fabricated in the backplane technology of AMOLED, including Excimer Laser Annealing (ELA), Solid Phase Crystallization (SPC), and Metal Induced Crystallization (Metal Induced Crystallization). MIC) and other production methods.
  • ELA Excimer Laser Annealing
  • SPC Solid Phase Crystallization
  • Metal Induced Crystallization Metal Induced Crystallization
  • MIC Metal Induced Crystallization
  • the low temperature polysilicon thin film transistor in the peripheral circuit region needs to have a high electron mobility, and the low temperature polysilicon thin film transistor in the display region needs to have a low leakage current.
  • the polysilicon layer in the low temperature polysilicon thin film transistor has the same grain size in the display region and the peripheral circuit region, and cannot meet the requirements of the display region and the peripheral circuit region for the low temperature polysilicon thin film transistor.
  • the polysilicon layer produced by the conventional technology cannot simultaneously satisfy the requirements of the low temperature polysilicon thin film transistor in the display region and the peripheral circuit region.
  • At least one embodiment of the present disclosure provides a method of fabricating an array substrate, including fabricating a polysilicon layer, including:
  • Forming an amorphous silicon film on the base substrate forming a first amorphous silicon layer in the display region and a second amorphous silicon layer in the peripheral circuit region by a patterning process, such that the first amorphous silicon layer The thickness is less than the thickness of the second amorphous silicon layer;
  • the first amorphous silicon layer and the second amorphous silicon layer are subjected to excimer laser annealing to form a display a first polysilicon layer of the display region and a second polysilicon layer at the peripheral circuit region, the first polysilicon layer having a grain size smaller than a grain size of the second polysilicon layer.
  • the peripheral circuit region is formed when the thickness of the amorphous silicon layer in the display region is smaller than the thickness of the amorphous silicon layer in the peripheral circuit region, and then the subsequent excimer laser annealing is performed to form the polysilicon layer.
  • the thin film transistor in the peripheral circuit region can satisfy the requirement of high electron mobility; and the thin film transistor in the display region can meet the requirement of low leakage current.
  • the patterning process is used to form a first amorphous silicon layer in the display region and a second amorphous silicon layer in the peripheral circuit region, including:
  • the photoresist completely reserved area corresponds to a region where the peripheral circuit region needs to form an amorphous silicon layer
  • the photoresist partially reserved area corresponds to a region where the display region needs to form an amorphous silicon layer
  • the glue complete removal area corresponds to an area other than the display area and the peripheral circuit area;
  • the photoresist in the completely remaining region of the photoresist is removed to form the second amorphous silicon layer.
  • the first amorphous silicon layer has a thickness value of 40 nm to 50 nm; and the second amorphous silicon layer has a thickness value of 60 nm to 80 nm.
  • the method before performing the excimer laser annealing on the first amorphous silicon layer and the second amorphous silicon layer, the method further includes:
  • the first amorphous silicon layer and the second amorphous silicon layer are subjected to heat treatment at a temperature of 400 ° C to 450 ° C for 0.5 to 3 hours.
  • a cesium chloride laser, or a cesium fluoride laser, or an argon fluoride laser is used for excimer laser annealing.
  • the laser when performing excimer laser annealing, has a pulse frequency of 450 Hz to 550 Hz, an overlap ratio of 92% to 98%, a scan rate of 4 mm/s to 16 mm/s, and an energy density of 300 mJ/ Cm 2 to 500 mJ/cm 2 .
  • At least one embodiment of the present disclosure also provides an array substrate, which is an array substrate fabricated by the above method.
  • the display region includes a thin film transistor having a polysilicon layer having a thickness of 40 nm to 50 nm; and the peripheral circuit region includes a thin film transistor having a polysilicon layer having a thickness of 60 nm to 80 nm. Nano.
  • At least one embodiment of the present disclosure also provides a display panel including the above array substrate.
  • At least one embodiment of the present disclosure also provides a display device including the above display panel.
  • FIG. 1 is a schematic structural view of an array substrate according to an embodiment of the present disclosure
  • FIG. 2 is a flow chart of a method of fabricating a polysilicon layer in an array substrate in accordance with an embodiment of the present disclosure
  • FIG. 3 is a schematic cross-sectional view of a method of fabricating an array substrate after forming a polysilicon film according to an embodiment of the present disclosure
  • FIG. 4 is a schematic cross-sectional view of a method of fabricating an array substrate after forming a photoresist according to an embodiment of the present disclosure
  • FIG. 5 is a schematic cross-sectional view of a method of fabricating an array substrate after exposure and development of a photoresist according to an embodiment of the present disclosure
  • FIG. 6 is a schematic cross-sectional view of a method of fabricating an array substrate after forming a first amorphous silicon layer and a second amorphous silicon layer, in accordance with an embodiment of the present disclosure
  • FIG. 7 is a schematic plan view showing a planar structure of a polysilicon layer formed using an excimer laser beam according to an embodiment of the present disclosure
  • Figure 8 is a schematic diagram showing the overlap ratio of laser light in one embodiment of the present disclosure.
  • FIG. 9 is a cross-sectional structural diagram of an array substrate including a polysilicon layer according to an embodiment of the present disclosure. intention.
  • the array substrate includes a display area 31 and a peripheral circuit area 32.
  • a driving pixel electrode is formed in the display area 31, a driving pixel electrode is formed.
  • a thin film transistor (not shown) is shown in the peripheral circuit region 32 to form an active drive circuit region 121, a gate (not shown) and other drive circuit regions 122.
  • the fabrication method includes fabricating a polysilicon layer on a substrate, comprising:
  • Forming an amorphous silicon film on the base substrate forming a first amorphous silicon layer in the display region and a second amorphous silicon layer in the peripheral circuit region by a patterning process, such that the first amorphous silicon layer The thickness is less than the thickness of the second amorphous silicon layer;
  • the first plurality The grain size of the crystalline silicon layer is smaller than the grain size of the second polysilicon layer.
  • the substrate is a glass substrate as an example.
  • the base substrate 20 is pre-cleaned.
  • a buffer layer is formed on the base substrate 20.
  • the buffer layer is formed in a two-layer structure.
  • PECVD plasma enhanced chemical vapor deposition
  • SiN silicon nitride
  • the SiO 2 ) layer 22 the SiN layer 21 and the SiO 2 layer 22 are used as the buffer layer in this embodiment.
  • the buffer layer may be fabricated in a single layer structure or a buffer layer may not be formed.
  • an amorphous silicon film 23 is deposited on the substrate on which the buffer layer is formed. The resulting structure is shown in Figure 3.
  • a first amorphous silicon layer located in the display region 31 and a peripheral circuit are formed by a patterning process.
  • the second amorphous silicon layer of the region 32 is such that the thickness of the first amorphous silicon layer is less than the thickness of the second amorphous silicon layer.
  • the thickness of the first amorphous silicon layer of the display region is 40 nm to 50 nm
  • the thickness of the second amorphous silicon layer of the peripheral circuit region is 60 nm to 80 nm.
  • the patterning process referred to in the present disclosure includes coating, exposure, development, etching, and some or all of the process of removing the photoresist.
  • a photoresist 24 is coated on the deposited amorphous silicon film 23, and the photoresist is exposed and developed using a halftone or gray tone mask to form a photoresist completely reserved area 240,
  • the photoresist partial retention area 241 and the photoresist complete removal area 242; the photoresist complete retention area 240 corresponds to the area where the peripheral circuit area 32 needs to form an amorphous silicon layer, and the photoresist partial retention area 241 needs to be formed corresponding to the display area 31.
  • the region of the amorphous silicon layer, the photoresist complete removal region 242 corresponds to the region of the substrate substrate except the display region 31 and the peripheral circuit region 32, and a cross-sectional view of the formed structure is shown in FIG.
  • the amorphous silicon film in the photoresist completely removed region 242 is not removed by the first dry etching; then the photoresist in the photoresist partial retention region 241 is removed by an ashing process.
  • a portion of the thickness of the amorphous silicon layer in the display region is removed by a second dry etching, for example, 20 nm to 30 nm, and a first thickness value of about 40 nm to 50 nm is formed in the display region 31.
  • the resulting structure is shown in Figure 6. It should be noted that the thickness of the first amorphous silicon layer 231 and the second amorphous silicon layer 232 may be selected by a technician according to design requirements, as long as the thickness of the first amorphous silicon layer 231 is less than the thickness of the second amorphous silicon layer 232. .
  • the first amorphous silicon layer 231 of the display region 31 and the second amorphous silicon layer 232 of the peripheral circuit region 32 are simultaneously subjected to excimer laser annealing to make the first amorphous silicon of the display region 31.
  • the layer 231 and the second amorphous silicon layer 232 of the peripheral circuit region 32 form a first polysilicon layer and a second polysilicon layer, respectively.
  • the peripheral circuit region 32 includes a source driving circuit region 121, a gate (not shown), and other driving circuit regions 122.
  • the thickness of the first polysilicon layer of the thin film transistor included in the display region 31 is smaller than that of the peripheral circuit region 32.
  • the first amorphous silicon layer and the second amorphous silicon layer are annealed by using an excimer laser, the first amorphous silicon layer and the second amorphous silicon layer are melted by laser and then recrystallized, as being formed in the display region 31
  • the thickness of the first amorphous silicon layer 231 is smaller than the thickness of the second amorphous silicon layer 232 formed in the peripheral circuit region 32.
  • the grain size formed when the second amorphous silicon layer after melting is recrystallized is larger than the grain size formed when the first amorphous silicon layer after melting is recrystallized.
  • a ruthenium chloride laser or a krypton fluoride laser or a argon fluoride laser is used, and the direction of the arrow in FIG. 7 indicates the moving direction of the laser beam 30 of the laser. .
  • the laser For excimer laser annealing, for example, the laser has a pulse frequency of 450 Hz to 550 Hz, an overlap ratio of 92% to 98%, a scan rate of 4 mm/s to 16 mm/s, and an energy density of 300 mJ/cm 2 to 500 mJ/cm 2 .
  • the calculation formula of the overlap ratio of the laser is as follows:
  • Laser overlap ratio [(width of laser beam - scan pitch) / width of laser beam] * 100%
  • the scanning pitch a is the distance between the right boundary line of the laser beam region 41 of the Nth laser scanning and the right boundary line of the laser beam region 42 of the N-1th laser scanning; or, the Nth time The distance between the left boundary line of the laser scanned laser beam region 41 and the left boundary line of the laser beam region 42 of the N-1th laser scanning.
  • the display is performed before the amorphous silicon layer of the display region and the amorphous silicon layer of the peripheral circuit region are subjected to excimer laser annealing.
  • the amorphous silicon layer of the region and the amorphous silicon layer of the peripheral circuit region are subjected to heat treatment at a temperature of 400 ° C to 450 ° C for 0.5 to 3 hours.
  • the thickness of the polysilicon layer formed in the display region is small, and the average grain size of the polycrystalline silicon crystal grains is between about 300 nm and 400 nm, and the uniformity is good, and the crystal grain size is small.
  • the thin film transistor formed by the polysilicon layer has good uniformity and can meet the requirements of low leakage current and threshold voltage uniformity.
  • the thickness of the polysilicon layer formed in the peripheral circuit region is thick, and the average grain size of the polycrystalline silicon crystal grains is between 500 nm and 700 nm, and the thin film formed by the polycrystalline silicon layer having a large crystal grain size is formed.
  • Transistors have higher mobility and mobility can easily exceed 200cm2/Vs, which can meet the requirements of high electron mobility.
  • the polysilicon layer and the thin film transistor formed by the above method are suitable for low temperature poly-Silicon Active Matrix Organic Light Emitting Diode (LTPS-AMOLED) and low temperature polysilicon thin film transistor liquid crystal display (Low) Temperature Poly-Silicon Thin Film Transistor Liquid Crystal Display, LTPS TFT-LCD).
  • LTPS-AMOLED low temperature poly-Silicon Active Matrix Organic Light Emitting Diode
  • Low temperature polysilicon thin film transistor liquid crystal display Low Temperature Poly-Silicon Thin Film Transistor Liquid Crystal Display, LTPS TFT-LCD
  • each film layer in the drawings do not reflect the true proportion of each film layer, and the purpose is only to illustrate the contents of the present disclosure.
  • At least one embodiment of the present disclosure further provides an array substrate including a display area 31 and a peripheral circuit area 32, which is an array substrate formed by the above method.
  • the thickness of the first polysilicon layer 111 of the thin film transistor included in the display region 31 of the array substrate is set to a first thickness
  • the thickness of the second polysilicon layer 112 of the thin film transistor included in the peripheral circuit region 32 is set to be the first The second thickness, the value of the first thickness is less than the value of the second thickness.
  • the first polysilicon layer 111 of the thin film transistor included in the display region 31 has a thickness value of 40 nanometers (nm) to 50 nm; the peripheral circuit region 32 includes a second polysilicon of the thin film transistor.
  • the layer 112 has a thickness value of 60 nm to 80 nm.
  • the thickness of the polysilicon layer of the display region is small, and the average grain size of the polycrystalline silicon crystal is about 300 nm to 400 nm, and the uniformity is good, and the polysilicon layer having a small crystal grain size is formed.
  • the thin film transistor has good uniformity and low leakage current. At this time, although the mobility of the formed thin film transistor is low, the requirement for the thin film transistor in the display region can be satisfied.
  • the thickness of the polysilicon layer in the peripheral circuit region is relatively thick, and the average grain size of the polycrystalline silicon crystal is about 500 nm to 700 nm, and the thin film transistor formed by using the polycrystalline silicon layer having a larger crystal grain size has a larger thickness.
  • the high mobility can well meet the switching requirements of the thin film transistors of the driver circuit.
  • At least one embodiment of the present disclosure also provides a display panel including the above array substrate.
  • At least one embodiment of the present disclosure further provides a display device, which includes the above display panel, which may be a liquid crystal panel, a liquid crystal display, a liquid crystal television, an Organic Light Emitting Diode (OLED) panel, A display device such as an OLED display, an OLED television, or an electronic paper.
  • a display panel which may be a liquid crystal panel, a liquid crystal display, a liquid crystal television, an Organic Light Emitting Diode (OLED) panel, A display device such as an OLED display, an OLED television, or an electronic paper.
  • embodiments of the present disclosure provide a method for fabricating an array substrate, comprising: forming a polysilicon layer on a substrate, the method comprising: forming an amorphous silicon film on the substrate, using a patterning process Forming a first amorphous silicon layer in the display region and forming a second amorphous silicon layer in the peripheral circuit region such that the thickness of the first amorphous silicon layer is less than the thickness of the second amorphous silicon layer;
  • the layer and the second amorphous silicon layer are subjected to excimer laser annealing to form a first polysilicon layer in the display region and a second polysilicon layer in the peripheral circuit region, wherein the grain size of the first polysilicon layer Less than the grain size of the second polysilicon layer.
  • the crystal grains of the second polysilicon layer formed in the peripheral circuit region are formed when the polysilicon layer is formed by excimer laser annealing
  • the size is larger than the grain size of the first polysilicon layer formed in the display region, and therefore, the polycrystalline silicon layer of the thin film transistor formed in the peripheral circuit region has a larger crystal grain size, which meets the requirement of high electron mobility;
  • the polysilicon layer of the thin film transistor in the display region has a small and uniform crystal grain, which can meet the requirements of low leakage current and threshold voltage uniformity.

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Abstract

一种阵列基板的制作方法，该阵列基板包括显示区(31)和周边电路区(32)，所述方法包括在衬底基板上制作多晶硅层，其中：在衬底基板上形成一层非晶硅薄膜(23)，采用构图工艺在显示区(31)中形成第一非晶硅层(231)和在周边电路区(32)中形成第二非晶硅层(232)，其中，第一非晶硅层(231)的厚度小于第二非晶硅层(232)的厚度；同时对第一非晶硅层(231)和第二非晶硅层(232)进行准分子激光退火，形成位于显示区(31)的第一多晶硅层(111)和位于周边电路区的第二多晶硅层(112)，其中，第一多晶硅层(111)的晶粒尺寸小于第二多晶硅层(112)的晶粒尺寸。还公开了一种阵列基板以及包括该阵列基板的显示面板和包括该显示面板的显示装置。

Description

阵列基板及其制作方法、显示面板、显示装置 技术领域
本公开的实施例涉及一种阵列基板及其制作方法、显示面板、显示装置。
背景技术
有源矩阵有机发光二极管(Active Matrix Organic Light Emitting Diode，AMOLED)凭借高画质、移动图像响应时间短、低功耗、宽视角及超轻、超薄等优点，成为了未来显示技术的最好选择。
目前AMOLED的背板技术中制作薄膜晶体管的多晶硅层时，采用包括准分子激光退火(Excimer Laser Annealing，ELA)、固相晶化(Solid Phase Crystallization，SPC)、金属诱导晶化(Metal Induced Crystallization，MIC)等多种制作方法。而采用ELA工艺得到背板中薄膜晶体管的多晶硅层是唯一实现量产的方法。
但是，在惯常技术的AMOLED显示装置中，其周边电路区中的低温多晶硅薄膜晶体管需要具有较高的电子迁移率，显示区中的低温多晶硅薄膜晶体管则需具备较低的漏电流。而目前低温多晶硅薄膜晶体管中的多晶硅层在显示区和周边电路区的晶粒尺寸相同，不能同时满足显示区和周边电路区对低温多晶硅薄膜晶体管的要求。
综上所述，惯常技术制作的多晶硅层，无法同时满足显示区和周边电路区对低温多晶硅薄膜晶体管的要求。
发明内容
本公开的至少一个实施例提供了一种阵列基板的制作方法，包括制作多晶硅层，包括：
在衬底基板上形成一层非晶硅薄膜，采用构图工艺形成位于显示区的第一非晶硅层和位于周边电路区的第二非晶硅层，使得所述第一非晶硅层的厚度小于第二非晶硅层的厚度；
同时对第一非晶硅层和第二非晶硅层进行准分子激光退火，形成位于显 示区的第一多晶硅层和位于周边电路区的第二多晶硅层，所述第一多晶硅层的晶粒尺寸小于第二多晶硅层的晶粒尺寸。
在根据本公开的阵列基板的制作方法中，由于显示区的非晶硅层的厚度小于周边电路区的非晶硅层的厚度，再经过后续的准分子激光退火形成多晶硅层时，周边电路区形成的第二多晶硅层的晶粒尺寸大于显示区形成的第一多晶硅层的晶粒尺寸，因此，在采用形成在显示区的第一多晶硅层和形成在周边电路区的第二多晶硅层分别形成薄膜晶体管之后，周边电路区的薄膜晶体管可以满足高电子迁移率的需求；而显示区的薄膜晶体管可以满足低漏电流的需求。
在本公开的一个实施例中，采用构图工艺形成位于显示区的第一非晶硅层和位于周边电路区的第二非晶硅层，包括：
在所述非晶硅薄膜上涂覆光刻胶，使用半色调或灰色调掩膜板对所述光刻胶曝光、显影，形成光刻胶完全保留区、光刻胶部分保留区和光刻胶完全去除区；所述光刻胶完全保留区对应周边电路区需要形成非晶硅层的区域，所述光刻胶部分保留区对应显示区需要形成非晶硅层的区域，所述光刻胶完全去除区对应除显示区和周边电路区外的区域；
通过第一次刻蚀，去除光刻胶完全去除区的非晶硅薄膜；
去除光刻胶部分保留区的光刻胶，通过第二次刻蚀，去除光刻胶部分保留区的非晶硅薄膜的一部分厚度，形成所述第一非晶硅层；
去除光刻胶完全保留区的光刻胶，形成所述第二非晶硅层。
在本公开的一个实施例中，所述第一非晶硅层的厚度值为40纳米到50纳米；所述第二非晶硅层的厚度值为60纳米到80纳米。
在本公开的一个实施例中，所述对第一非晶硅层和第二非晶硅层进行准分子激光退火之前，所述方法还包括：
对所述第一非晶硅层和所述第二非晶硅层在400℃到450℃的温度下，进行0.5到3个小时的加热处理。
在本公开的一个实施例中，进行准分子激光退火时，采用氯化氙激光器，或氟化氪激光器，或氟化氩激光器。
在本公开的一个实施例中，进行准分子激光退火时，激光的脉冲频率为450Hz到550Hz，重叠率为92％到98％，扫描速率为4mm/s到16mm/s，能 量密度为300mJ/cm2到500mJ/cm2。
本公开的至少一个实施例还提供了一种阵列基板，所述阵列基板为采用上述方法制作得到的阵列基板。
在本公开的一个实施例中，所述显示区包括的薄膜晶体管的多晶硅层的厚度值为40纳米到50纳米；所述周边电路区包括的薄膜晶体管的多晶硅层的厚度值为60纳米到80纳米。
本公开的至少一个实施例还提供了一种显示面板，该显示面板包括上述的阵列基板。
本公开的至少一个实施例还提供了一种显示装置，该显示装置包括上述的显示面板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为根据本公开的一个实施例的阵列基板的结构示意图；
图2为根据本公开的一个实施例的在阵列基板中的制作多晶硅层的方法流程图；
图3为根据本公开的一个实施例的阵列基板的制作方法在形成多晶硅薄膜后的截面结构示意图；
图4为根据本公开的一个实施例的阵列基板的制作方法在形成光刻胶之后的截面结构示意图；
图5为根据本公开的一个实施例的阵列基板的制作方法在对光刻胶进行曝光显影之后所形成的截面结构示意图；
图6为根据本公开的一个实施例的阵列基板的制作方法在形成第一非晶硅层和第二非晶硅层之后所形成的截面结构示意图；
图7为根据本公开的一个实施例的采用准分子激光束形成多晶硅层的平面结构示意图；
图8为本公开的一个实施例中激光的重叠率示意图；以及
图9为本公开的一个实施例的一种阵列基板包括多晶硅层的截面结构示 意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开的至少一个实施例提供了一种阵列基板的制作方法，如图1所示，该阵列基板包括显示区31和周边电路区32，在显示区31中形成有驱动像素电极(图中未示出)的薄膜晶体管(图中未示出)，在周边电路区32中形成有源驱动电路区域121，栅极(图中未示出)及其它驱动电路区域122。
如图2所示，该制作方法包括在在衬底基板上制作多晶硅层，其包括：
在衬底基板上形成一层非晶硅薄膜，采用构图工艺形成位于显示区的第一非晶硅层和位于周边电路区的第二非晶硅层，使得所述第一非晶硅层的厚度小于第二非晶硅层的厚度；
同时对第一非晶硅层和第二非晶硅层进行准分子激光退火，形成位于显示区的第一多晶硅层和位于周边电路区的第二多晶硅层，所述第一多晶硅层的晶粒尺寸小于第二多晶硅层的晶粒尺寸。
下文将对根据本公开的一个实施例制作薄膜晶体管的多晶硅层的方法进行详细描述。在该实施例中，以衬底基板为玻璃基板为例。
首先，对衬底基板20进行预清洗。接着，在衬底基板20上制作缓冲层。在该实施例中，制作的缓冲层以双层结构。例如，采用等离子体增强化学气相沉积(Plasma Enhanced Chemical Vapor Deposition，PECVD)的方法首先沉积一层50nm到150nm的氮化硅(SiN)层21，接着再沉积一层100nm到350nm的二氧化硅(SiO2)层22，SiN层21和SiO2层22作为本实施例中的缓冲层。需要说明的是，在本公开的实施例中，可以将缓冲层制作为单层结构，或者不制作缓冲层。接着，在制作有缓冲层的衬底基板上沉积一层非晶硅薄膜23。所形成的结构如图3所示。
之后，采用构图工艺形成位于显示区31的第一非晶硅层和位于周边电路 区32的第二非晶硅层，使得第一非晶硅层的厚度小于第二非晶硅层的厚度。在该实施例中，例如，显示区的第一非晶硅层的厚度值为40nm到50nm，周边电路区的第二非晶硅层的厚度值为60nm到80nm。
在本公开中提及的构图工艺包括光刻胶的涂覆、曝光、显影、刻蚀以及去除光刻胶的部分或全部过程。例如，如图4所示，在沉积的非晶硅薄膜23上涂覆光刻胶24，使用半色调或灰色调掩膜板对光刻胶曝光、显影，形成光刻胶完全保留区240、光刻胶部分保留区241和光刻胶完全去除区242；光刻胶完全保留区240对应周边电路区32需要形成非晶硅层的区域，光刻胶部分保留区241对应显示区31需要形成非晶硅层的区域，光刻胶完全去除区242对应衬底基板除显示区31和周边电路区32外的其它区域，所形成的结构的截面图如图5所示。
之后通过第一次干法刻蚀，去除光刻胶完全去除区242中未被光刻胶覆盖区域的非晶硅薄膜；接着通过灰化工艺去除光刻胶部分保留区241的光刻胶，露出显示区31的非晶硅薄膜，通过第二次干法刻蚀去除显示区中非晶硅层的一部分厚度，例如20nm到30nm，在显示区31形成厚度值约为40nm到50nm的第一非晶硅层231；最后，去除剩余的光刻胶，在周边电路区32形成60nm到80nm的第二非晶硅层232。所形成的结构如图6所示。需要说明的是技术人员可以根据设计需要选择第一非晶硅层231和第二非晶硅层232的厚度，只要满足第一非晶硅层231的厚度小于第二非晶硅层232的厚度。
接着，如图7所示，同时对显示区31的第一非晶硅层231和周边电路区32的第二非晶硅层232进行准分子激光退火，使得显示区31的第一非晶硅层231和周边电路区32的第二非晶硅层232分别形成第一多晶硅层和第二多晶硅层。
周边电路区32包括源驱动电路区域121，栅极(图中未示出)及其它驱动电路区域122，显示区31包括的薄膜晶体管的第一多晶硅层的厚度小于周边电路区32包括的薄膜晶体管的第二多晶硅层的厚度。
在采用准分子激光对第一非晶硅层和第二非晶硅层进行退火时，第一非晶硅层和第二非晶硅层被激光熔化然后再结晶，由于形成在显示区31中的第一非晶硅层231的厚度小于形成在周边电路区32中的第二非晶硅层232的厚 度，熔化后的第二非晶硅层再结晶时形成的晶粒尺寸比溶化后的第一非晶硅层再结晶时形成的晶粒尺寸大。
在本公开的实施例中，进行准分子激光退火时，采用氯化氙激光器，或采用氟化氪激光器，或采用氟化氩激光器，图7中的箭头方向表示激光器的激光束30的移动方向。
进行准分子激光退火时，例如，激光的脉冲频率为450Hz到550Hz，重叠率为92％到98％，扫描速率为4mm/s到16mm/s，能量密度为300mJ/cm2到500mJ/cm2。在本公开的实施例中，激光的重叠率的计算公式如下：
激光的重叠率＝[(激光束的宽度-扫描间距)/激光束的宽度]*100％
如图8所示，扫描间距a为第N次激光扫描的激光束区域41的右边界线与第N-1次激光扫描的激光束区域42的右边界线之间的距离；或者，为第N次激光扫描的激光束区域41的左边界线与第N-1次激光扫描的激光束区域42的左边界线之间的距离。
为了使得非晶硅层更好地转换为多晶硅层，在本公开的实施例中，在对显示区的非晶硅层和周边电路区的非晶硅层进行准分子激光退火之前，先对显示区的非晶硅层和周边电路区的非晶硅层在400℃到450℃的温度下，进行0.5到3个小时的加热处理。
在本公开的实施例中，在显示区形成的多晶硅层的厚度较小，其多晶硅晶粒的平均晶粒尺寸约为300nm到400nm之间，并且均匀性较好，采用晶粒尺寸较小的多晶硅层形成的薄膜晶体管的均匀性较好，可以符合低漏电流及阈值电压均匀性的需求。
在本公开的实施例中，在周边电路区形成的多晶硅层的厚度较厚，其多晶硅晶粒的平均晶粒尺寸约为500nm到700nm之间，采用晶粒尺寸较大的多晶硅层形成的薄膜晶体管具有较高的迁移率，迁移率可以轻松大于200cm2/V.s，可以符合高电子迁移率的需求。
通过上述方法制作形成的多晶硅层及其薄膜晶体管，适用于低温多晶硅有源矩阵有机发光二极管显示器(Low Temperature Poly-Silicon Active Matrix Organic Light Emitting Diode，LTPS-AMOLED)及低温多晶硅薄膜晶体管液晶显示器(Low Temperature Poly-Silicon Thin Film Transistor Liquid Crystal Display，LTPS TFT-LCD)等领域。
下面介绍根据本公开实施例的阵列基板。
附图中各膜层厚度和区域大小、形状不反应各膜层的真实比例，目的只是示意说明本公开的内容。
如图7和图9所示，本公开的至少一个实施例还提供了一种阵列基板，包括显示区31和周边电路区32，该阵列基板为采用上述方法制作形成的阵列基板。其中，该阵列基板的显示区31包括的薄膜晶体管的第一多晶硅层111的厚度设置为第一厚度，周边电路区32包括的薄膜晶体管的第二多晶硅层112的厚度设置为第二厚度，第一厚度的值小于第二厚度的值。
在本公开的一个实施例中，显示区31包括的薄膜晶体管的第一多晶硅层111的厚度值为40纳米(nm)到50nm；周边电路区32包括的薄膜晶体管的第二多晶硅层112的厚度值为60nm到80nm。
在本公开的实施例中，显示区的多晶硅层的厚度较小，多晶硅晶粒的平均晶粒尺寸约为300nm到400nm之间，并且均匀性较好，采用晶粒尺寸较小的多晶硅层形成的薄膜晶体管的均匀性较好，并且漏电流较低，这时虽然形成的薄膜晶体管的迁移率较低，但是对于显示区对薄膜晶体管的要求是可以满足的。
在本公开的实施例中，周边电路区的多晶硅层的厚度较厚，多晶硅晶粒的平均晶粒尺寸约为500nm到700nm之间，采用晶粒尺寸较大的多晶硅层形成的薄膜晶体管具有较高的迁移率，能够很好的满足驱动电路的薄膜晶体管的开关要求。
本公开的至少一个实施例还提供了一种显示面板，该显示面板包括上述阵列基板。
本公开的至少一个实施例还提供了一种显示装置，该显示装置包括上述显示面板，该显示装置可以为液晶面板、液晶显示器、液晶电视、有机发光二极管(Organic Light Emitting Diode，OLED)面板、OLED显示器、OLED电视或电子纸等显示装置。
综上所述，本公开的实施例提供一种阵列基板的制作方法，包括在衬底基板上制作多晶硅层，该方法包括：在衬底基板上形成一层非晶硅薄膜，采用构图工艺在显示区中形成第一非晶硅层和在周边电路区中形成第二非晶硅层，使得第一非晶硅层的厚度小于第二非晶硅层的厚度；同时对第一非晶硅 层和第二非晶硅层进行准分子激光退火，形成位于显示区的第一多晶硅层和位于周边电路区的第二多晶硅层，其中，第一多晶硅层的晶粒尺寸小于第二多晶硅层的晶粒尺寸。由于显示区中的非晶硅层的厚度小于周边电路区中的非晶硅层的厚度，通过准分子激光退火形成多晶硅层时，形成在周边电路区中的第二多晶硅层的晶粒尺寸大于形成在显示区中的第一多晶硅层的晶粒尺寸，因此，形成在周边电路区中的薄膜晶体管的多晶硅层的晶粒较大，符合高电子迁移率的需求；而形成在显示区中的薄膜晶体管的多晶硅层的晶粒较小且均匀，可以符合低漏电流及阈值电压均匀性的需求。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。
本申请要求于2015年10月23日递交的中国专利申请第201510697688.8号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (10)

  1. 一种阵列基板的制作方法，该阵列基板包括显示区和周边电路区，所述方法包括在衬底基板上制作多晶硅层，其中：
    在衬底基板上形成一层非晶硅薄膜，采用构图工艺在显示区形成第一非晶硅层和在周边电路区形成第二非晶硅层，使得所述第一非晶硅层的厚度小于第二非晶硅层的厚度；
    同时对第一非晶硅层和第二非晶硅层进行准分子激光退火，在显示区中形成第一多晶硅层和在周边电路区的第二多晶硅层，所述第一多晶硅层的晶粒尺寸小于第二多晶硅层的晶粒尺寸。
  2. 根据权利要求1所述的方法，其中，采用构图工艺在显示区形成第一非晶硅层和在周边电路区形成第二非晶硅层，包括：
    在所述非晶硅层上涂覆光刻胶，使用半色调或灰色调掩膜板对所述光刻胶曝光、显影，形成光刻胶完全保留区、光刻胶部分保留区和光刻胶完全去除区；所述光刻胶完全保留区对应周边电路区需要形成非晶硅层的区域，所述光刻胶部分保留区对应显示区需要形成非晶硅层的区域，所述光刻胶完全去除区对应除显示区和周边电路区外的区域；
    通过第一次刻蚀，去除光刻胶完全去除区的非晶硅薄膜；
    去除光刻胶部分保留区的光刻胶，通过第二次刻蚀，去除光刻胶部分保留区的非晶硅薄膜的一部分厚度，形成所述第一非晶硅层；以及
    去除光刻胶完全保留区的光刻胶，形成所述第二非晶硅层。
  3. 根据权利要求1或2所述的方法，其中，所述第一非晶硅层的厚度值为40纳米到50纳米；以及所述第二非晶硅层的厚度值为60纳米到80纳米。
  4. 根据权利要求1至3中任何一项所述的方法，其中，对第一非晶硅层和第二非晶硅层进行准分子激光退火之前，所述方法还包括：
    在400℃到450℃的温度下对所述第一非晶硅层和所述第二非晶硅层加热0.5到3个小时。
  5. 根据权利要求1至4中任何一项所述的方法，其中，进行准分子激光退火时，采用氯化氙激光器或氟化氪激光器或氟化氩激光器。
  6. 根据权利要求1至5中任何一项所述的方法，其中，进行准分子激光 退火时，激光的脉冲频率为450Hz到550Hz，重叠率为92％到98％，扫描速率为4mm/s到16mm/s，能量密度为300mJ/cm2到500mJ/cm2。
  7. 一种阵列基板，包括显示区和周边电路区，其中，所述阵列基板为采用权利要求1-6任一项所述的方法制作得到。
  8. 根据权利要求7所述的阵列基板，其中，所述显示区中的第一多晶硅层的厚度值为40纳米到50纳米；所述周边电路区中的第二多晶硅层的厚度值为60纳米到80纳米。
  9. 一种显示面板，其包括权利要求7或8所述的阵列基板。
  10. 一种显示装置，其包括权利要求9所述的显示面板。
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