WO2017045255A1 - 驱动装置以及液晶显示器 - Google Patents

驱动装置以及液晶显示器 Download PDF

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WO2017045255A1
WO2017045255A1 PCT/CN2015/093495 CN2015093495W WO2017045255A1 WO 2017045255 A1 WO2017045255 A1 WO 2017045255A1 CN 2015093495 W CN2015093495 W CN 2015093495W WO 2017045255 A1 WO2017045255 A1 WO 2017045255A1
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pixel
gray value
value
adjacent
sub
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PCT/CN2015/093495
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English (en)
French (fr)
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朱江
陈宥烨
郭东胜
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深圳市华星光电技术有限公司
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Priority to US14/909,955 priority Critical patent/US9886919B2/en
Publication of WO2017045255A1 publication Critical patent/WO2017045255A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2074—Display of intermediate tones using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0235—Field-sequential colour display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit

Definitions

  • the present invention relates to the field of liquid crystal display, and more particularly to a driving device and a liquid crystal display.
  • one pixel of a conventional red, green and blue (RGB) liquid crystal display panel includes three sub-pixels of red, green and blue, and each sub-pixel has a total of 256 gray levels from 0 to 255, through different red and green colors.
  • the gray combination of blue sub-pixels can form different colors.
  • the pixel of the red, green, blue and white (RGBW) liquid crystal display panel includes four sub-pixels of red, green, blue and white, and each sub-pixel has a total of 256 gray levels from 0 to 255, through different red, green, blue and white sub-pixels.
  • the grayscale combination of pixels can form different colors.
  • the resolution is the total number of pixels in a unit area.
  • the resolution of the liquid crystal display is a. *b.
  • the requirements for timing control chips are also increasing. When the resolution is doubled, the complexity of the timing control chip will increase several times, resulting in a corresponding increase in the cost of the timing control chip.
  • the technical problem to be solved by the embodiments of the present invention is to provide a driving device and a liquid crystal display, which realizes reducing the complexity of the timing control chip.
  • the present invention provides a driving apparatus including: a timing control chip and a data driving chip, wherein the timing control chip is connected to the data driving chip, and the timing control chip is used for grayscale from a pixel of a first value Selectively receive the gray value of the pixel with the second value and send it to The data driving chip, wherein the first value and the second value are both positive integers, and the first value is greater than the second value; the data driving chip is configured to receive the timing control chip to send
  • the number of pixels is the gray value of the pixel of the second value, and the gray value of the pixel of the first value is obtained according to the gray value of the pixel of the second value, and the number obtained is the first
  • the gray value of the pixel of the value drives the liquid crystal display.
  • the first value is 2a*b
  • the second value is a*b
  • the first value is a*2b
  • the second value is a*b
  • a is The number of pixel points of the first dimensional coordinate of the liquid crystal display
  • b is the number of pixel points of the second dimensional coordinate of the liquid crystal display.
  • the timing control chip is specifically configured to interleave the gray value of the pixel point from the gray value of the pixel of the number of 2a*b, thereby obtaining the gray value of the pixel of the quantity a*b,
  • the gradation value of the pixel is received from the gradation value of the pixel of the number 2a*b, thereby obtaining the gradation value of the pixel of the number a*b.
  • the data driving chip is specifically configured to interpolate the gray value of the intermediate pixel according to the gray value of the adjacent pixel, thereby interpolating the gray value of the pixel of the quantity a*b into a quantity
  • the gradation value of the pixel of 2a*b, or the gradation value of the pixel of the number a*b is interpolated into the gradation value of the pixel of the number a*2b.
  • the adjacent pixel points are any one of left and right adjacent pixel points, upper and lower adjacent pixel points, and four neighboring adjacent pixel points.
  • the data driving chip is specifically configured to interpolate the gray value of the red sub-pixel of the intermediate pixel according to the gray value of the adjacent red sub-pixel, and interpolate according to the gray value of the adjacent green sub-pixel.
  • the gradation value of the green sub-pixel of the intermediate pixel is interpolated based on the gradation value of the adjacent blue sub-pixel by the gradation value of the blue sub-pixel of the intermediate pixel.
  • the data driving chip is further configured to interpolate the gray value of the white sub-pixel of the intermediate pixel according to the gray value of the adjacent white sub-pixel.
  • the data driving chip includes: a shift register, a data register, a row data latch, an extended adder, a voltage shifter, a digital-to-analog converter, and an output buffer, wherein the shift register and the a serial connection between the data register, the row data latch, the extended adder, the voltage shifter, the digital to analog converter, and the output buffer, the data register being used in With the cooperation of the shift register, the serial pixel transmitted by the timing control chip will be received.
  • the row data latch is used to latch the a gray value of a parallel pixel sent by the data register, and sent to the extended adder;
  • the extended adder is configured to output grayscale of parallel pixel points sent by the data register to the voltage transfer And adding the gradations of adjacent pixels, and outputting the result of the upper eight bits to the voltage shifter as the gray value of the intermediate pixel;
  • the voltage shifter is used for And shifting a voltage of a gray value of a pixel point output by the extended adder to the analog-to-digital converter;
  • the analog-to-digital converter is configured to transfer a voltage of the voltage output by the voltage shifter
  • the gray value is converted into an analog signal and sent to the output buffer;
  • the output buffer is used to output the gray value of the simulated pixel to drive the pixel.
  • a first input end of the extended adder is used to input a gray value of a sub-pixel of a first adjacent pixel
  • a second input end of the extended adder is used to input a second adjacent pixel a gray value of a sub-pixel of the same color
  • a first output of the extended adder for directly outputting a gray value of a sub-pixel of the first adjacent pixel
  • a second output of the extended adder a gray value for outputting a sub-pixel of the second adjacent pixel
  • a third output of the extended adder for outputting a gray value of the sub-pixel of the first adjacent pixel and the The upper eight bits of the sum of the gray values of the sub-pixels of the same color of two adjacent pixels.
  • the present invention provides a liquid crystal display including a back panel and a liquid crystal panel, the liquid crystal panel including a driving device, the driving device including: a timing control chip and a data driving chip, wherein the timing control chip is connected to the data driving chip ,
  • the timing control chip is configured to selectively receive a gray value of the pixel of the second value from the gray value of the pixel of the first value, and send the gray value to the data driving chip, where
  • the first value and the second value are both positive integers, and the first value is greater than the second value;
  • the data driving chip is configured to receive a gray value of a pixel of the second value sent by the timing control chip, and obtain a pixel with a first value according to a gray value of the pixel of the second value
  • the gray value of the point is output, and the output is obtained by driving the liquid crystal display with the gray value of the pixel of the first value.
  • the first value is 2a*b
  • the second value is a*b
  • the first value is a*2b
  • the second value is a*b
  • a is The number of pixels in the first dimension of the liquid crystal display
  • b The number of pixel points of the second dimensional coordinate of the liquid crystal display.
  • the timing control chip is specifically configured to interleave the gray value of the pixel point from the gray value of the pixel of the number of 2a*b, thereby obtaining the gray value of the pixel of the quantity a*b,
  • the gradation value of the pixel is received from the gradation value of the pixel of the number 2a*b, thereby obtaining the gradation value of the pixel of the number a*b.
  • the data driving chip is specifically configured to interpolate the gray value of the intermediate pixel according to the gray value of the adjacent pixel, thereby interpolating the gray value of the pixel of the quantity a*b into a quantity
  • the gradation value of the pixel of 2a*b, or the gradation value of the pixel of the number a*b is interpolated into the gradation value of the pixel of the number a*2b.
  • the adjacent pixel points are any one of left and right adjacent pixel points, upper and lower adjacent pixel points, and four neighboring adjacent pixel points.
  • the data driving chip is specifically configured to interpolate the gray value of the red sub-pixel of the intermediate pixel according to the gray value of the adjacent red sub-pixel, and interpolate according to the gray value of the adjacent green sub-pixel.
  • the gradation value of the green sub-pixel of the intermediate pixel is interpolated based on the gradation value of the adjacent blue sub-pixel by the gradation value of the blue sub-pixel of the intermediate pixel.
  • the data driving chip is further configured to interpolate the gray value of the white sub-pixel of the intermediate pixel according to the gray value of the adjacent white sub-pixel.
  • the data driving chip includes: a shift register, a data register, a row data latch, an extended adder, a voltage shifter, a digital-to-analog converter, and an output buffer, wherein the shift register and the Serial connection between the data register, the row data latch, the extended adder, the voltage shifter, the digital to analog converter, and the output buffer,
  • the data register is configured to receive, by the shift register, a gray value of a serial pixel point sent by the timing control chip, and convert the gray value of the serial pixel point into a parallel pixel a gray value of the point and sent to the row data latch;
  • the row data latch is configured to latch a gray value of parallel pixel points sent by the data register, and send the gray value to the extended adder;
  • the extended adder is configured to output the gray scale of the parallel pixel points sent by the data register to the voltage shifter, and add the gray levels of the adjacent pixel points, and take the added result
  • the upper eight bits are output to the voltage diverter as a gray value of the intermediate pixel point;
  • the voltage diverter is configured to transfer a voltage of a gray value of a pixel point output by the extended adder, and output the voltage to the analog to digital converter;
  • the analog-to-digital converter is configured to convert a gray value of a pixel point after voltage transfer output by the voltage transfer device into an analog signal, and send the signal to the output buffer;
  • the output buffer is configured to output a gray value of the simulated pixel point to drive the pixel point.
  • a first input end of the extended adder is used to input a gray value of a sub-pixel of a first adjacent pixel
  • a second input end of the extended adder is used to input a second adjacent pixel a gray value of a sub-pixel of the same color
  • a first output of the extended adder for directly outputting a gray value of a sub-pixel of the first adjacent pixel
  • a second output of the extended adder a gray value for outputting a sub-pixel of the second adjacent pixel
  • a third output of the extended adder for outputting a gray value of the sub-pixel of the first adjacent pixel and the The upper eight bits of the sum of the gray values of the sub-pixels of the same color of two adjacent pixels.
  • the timing control chip when the timing control chip receives the gradation value of the pixel of the first value, it can selectively receive only the gradation value of the pixel of the second value, and when outputting to the data driving chip Then, the interpolation method is used to restore the gray value of the pixel with the first value. Therefore, the number of pixels to be processed by the timing control chip is greatly reduced, thereby reducing the complexity of the timing control chip, thereby reducing the cost of the timing control chip.
  • FIG. 1 is a schematic diagram of a pixel point of an RGB liquid crystal display and an RGBW liquid crystal display
  • FIG. 2 is a schematic structural view of a driving device according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a pixel dot matrix of an RGB liquid crystal display
  • FIG. 4 is a schematic diagram showing changes in data amount of a driving device of the present invention when passing through a timing control chip and a data driving chip;
  • FIG. 5 is a schematic structural diagram of a data driving chip according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of an extended adder according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of a driving apparatus according to an embodiment of the present invention.
  • the driving device 100 of the present invention includes a timing control chip 110 and a data driving chip 120, and a timing control chip (TCON) 110 is connected to a data driving chip (Driver IC) 120.
  • TCON timing control chip
  • Driver IC data driving chip
  • the liquid crystal display generally includes a plurality of pixel points 210.
  • the gradation value of the pixel of the first value is transmitted to the timing control chip 110.
  • the first value is a positive integer, and the first value is usually the total number of all pixel points 210 of the liquid crystal display.
  • the value of the first value is 2a*b, or if the liquid crystal display includes a*2b pixels, the value of the first value is a*2b,
  • a is the number of pixel points 210 on the abscissa of the liquid crystal display
  • b is the number of pixel points 210 on the ordinate of the liquid crystal display.
  • each pixel 210 includes three sub-pixels of red, green, and blue. Therefore, for an RGB type liquid crystal display, the gray value of each pixel 210 includes three sub-pixels of red, green, and blue. grayscale value.
  • each pixel 210 includes four sub-pixels of red, green, blue, and white. Therefore, for an RGBW type liquid crystal display, the gray value of each pixel 210 includes red, green, and blue. Gray value of four sub-pixels.
  • the timing control chip 110 selectively receives the gradation value of the pixel point 210 of the second value from the gradation value of the pixel 210 of the first value, and transmits it to the data driving chip 120.
  • the first value is a positive integer, and the first value is greater than the second value.
  • the timing control chip 110 can selectively receive the gray value of the pixel point 210 by interlacing, and can selectively receive the gray value of the pixel point 210 by means of interlacing, which can be selected by two lines.
  • the gray value of the pixel 210 can be selectively received by two columns, or the gray value of the pixel 210 can be selectively received in an irregular manner. No specific limitation. Referring to FIG.
  • timing control chip 110 selectively receives the gray value of the pixel point 210 in an interlaced manner, only the number of pixels of the number of the pixel points 210 of the number 2a*b is a*b.
  • the gray value of point 210 is received by timing control chip 110.
  • the timing control chip 110 transmits the gradation value of the pixel point 210 of the second value to the data driving chip 120
  • the data driving chip 120 receives the gradation value of the pixel point 210 of the second value transmitted by the timing control chip 110. And obtaining the gradation value of the pixel point 210 of the first value according to the gradation value of the pixel 210 of the second value, and outputting the gradation value of the obtained pixel point 210 to drive the liquid crystal display.
  • the gray value of the pixel point 210 of the first value can be obtained by interpolation.
  • the gray value of the intermediate pixel point 210 can be obtained by interpolation of the gray value of the adjacent pixel point 210, thereby interpolating the gray value of the pixel point 210 of the second value into the pixel point 210 of the first value.
  • the gradation value of the intermediate pixel point 210 is obtained by interpolating the gradation values of the upper and lower adjacent pixel points 210, and the gradation of the intermediate pixel point 210 can be obtained by interpolating the gradation values of the two adjacent pixels 210.
  • the value may be obtained by interpolating the gray value of the adjacent pixel point 210 of the four neighborhoods to obtain the gray value of the intermediate pixel 210, etc., and interpolating the gray value of the pixel 210 of the second value into the first value.
  • the manner in which the data driving chip 120 is interpolated corresponds to the manner in which the timing control chip 110 selects the pixel point 210 to be received.
  • the data driving chip 120 uses the gray value of the upper and lower adjacent pixel points 210 to interpolate to obtain the gray value of the intermediate pixel point 210 or Interpolation is performed in such a manner that the gradation values of the two adjacent pixel points 210 are interpolated to obtain the gradation value of the intermediate pixel point 210.
  • the gray value of the red sub-pixel of the intermediate pixel point 210 can be obtained according to the gray value of the red sub-pixel of the adjacent pixel point, according to the adjacent image.
  • the gray value of the green sub-pixel of the prime point is interpolated to obtain the gray value of the green sub-pixel of the intermediate pixel 210
  • the blue sub-pixel of the intermediate pixel 210 is obtained according to the gray value of the blue sub-pixel of the adjacent pixel.
  • Gray value For the RGBW type liquid crystal display, it is also necessary to interpolate the gray value of the white sub-pixel of the adjacent pixel to obtain the gray value of the white sub-pixel of the intermediate pixel 210.
  • the data driving chip 120 includes a shift register 121, a data register 122, a line latch 123, an adder 124, and a voltage shifter. Shift) 125, a digital to analog converter (DAC) 126, and an output buffer 127.
  • the shift register 121, the data register 122, the row data latch 123, the extended adder 124, the voltage shifter 125, the digital-to-analog converter 126, and the output buffer 127 are connected in series.
  • the data register 122 receives the gray value of the serial pixel point sent by the timing control chip 110 in cooperation with the shift register 121, and converts the gray value of the serial pixel point into the gray value of the parallel pixel point. And sent to the row data latch 123.
  • the row data latch 123 latches the gray value of the parallel pixel points transmitted by the data register 122 and sends it to the extended adder 124.
  • the extended adder 124 outputs the gradation of the parallel pixel points transmitted by the data register 123 to the voltage shifter 125, and adds the gradations of the adjacent pixel points, and takes the added result as a high eight-bit output.
  • the voltage shifter 125 is taken to be the gray value of the intermediate pixel point. Specifically, the gradation value of the sub-pixel of the intermediate pixel is calculated by using the gradation value of the sub-pixel of the left and right adjacent pixel points, and the structure of the extended adder 124 is as shown in FIG.
  • the 8-bit first input terminal A of the extended adder 124 is used to input the gray value of the red sub-pixel of the left adjacent pixel
  • the 8-bit second input of the extended adder 124 is used.
  • the 8-bit first output C of the extended adder 124 is used to directly output the gray value of the red sub-pixel of the left adjacent pixel
  • the extended adder The 8-bit second output terminal D of 124 is used to output the gray value of the green sub-pixel of the right adjacent pixel
  • the third output of the extended adder 124 is used to output the gray of the red sub-pixel of the left adjacent pixel.
  • the third output end of the extended adder 124 outputs only the upper eight bits of the sum of the gray value of the red sub-pixel of the left adjacent pixel and the gray value of the red sub-pixel of the right adjacent pixel.
  • the gray value of the red sub-pixel of the adjacent pixel and the gray value of the red sub-pixel of the right adjacent pixel are averaged.
  • the extended adder 124 can calculate the intermediate pixel points in the same manner. Gray value of green sub-pixel, blue sub-pixel, and white sub-pixel.
  • the voltage shifter 125 shifts the voltage of the gradation value of the pixel point output from the adder 124, and outputs it to the analog-to-digital converter 126, which converts the voltage output from the voltage shifter 125 to the pixel point.
  • the gray value is converted to an analog signal and sent to the output buffer 127.
  • the output buffer 127 outputs the gray value of the simulated pixel point to drive the pixel point.
  • the timing control chip when the timing control chip receives the gradation value of the pixel of the first value, it can selectively receive only the gradation value of the pixel of the second value, and when outputting to the data driving chip Then, the interpolation method is used to restore the gray value of the pixel with the first value. Therefore, the number of pixels to be processed by the timing control chip is greatly reduced, thereby reducing the complexity of the timing control chip, thereby reducing the cost of the timing control chip.
  • the present invention also provides a liquid crystal display comprising a back plate and a liquid crystal panel.
  • the liquid crystal panel includes the driving devices shown in FIG. 2, FIG. 4, FIG. 5 and FIG. 6.
  • the storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

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  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

公开了一种驱动装置和液晶显示器。驱动装置（100）包括：时序控制芯片（110）以及数据驱动芯片（120），时序控制芯片（110）连接数据驱动芯片（120），时序控制芯片（110）用于从数量为第一值的像素点的灰度值中选择性接收数量为第二值的像素点的灰度值，并发送给数据驱动芯片（120），其中，第一值和第二值均为正整数，第一值大于第二值；数据驱动芯片（120）用于接收时序控制芯片（110）发送的数量为第二值的像素点灰度值，并输出插值后的数量为第一值像素点的灰度值对液晶显示器进行驱动。该驱动装置可减少时序控制芯片（110）的复杂度。

Description

驱动装置以及液晶显示器
本发明要求2015年09月15日递交的发明名称为“驱动装置以及液晶显示器”的申请号201510587211.4的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及液晶显示领域，尤其涉及一种驱动装置以及液晶显示器。
背景技术
如图1所示，传统红绿蓝(RGB)液晶显示面板的一个像素点包括红、绿、蓝三个子像素，每个子像素有0～255共256个灰度等级，通过不同红、绿、蓝子像素的灰度组合，可以形成不同的颜色。而红绿蓝白(RGBW)液晶显示面板的一个像素点包括红、绿、蓝、白四个子像素，每个子像素有0～255共256个灰度等级，通过不同红、绿、蓝、白子像素的灰度组合，可以形成不同的颜色。
解析度为单位面积中像素点的总数量，在液晶显示器领域，如果单位面积中，行坐标的像素点的数量为a，列坐标的像素点的数量为b，则液晶显示器的解析度为a*b。解析度越高，显示的画面越逼真。所以，对于液晶显示器来说，提高解析度是液晶显示器发展的一个重要方向。但是，随着解析度的升高，对时序控制芯片要求亦越来越高。当解析度每增加一倍，时序控制芯片的复杂度将会增加几倍，从而导致时序控制芯片的成本也会相应地增加几倍。
发明内容
本发明实施例所要解决的技术问题在于，提供一种驱动装置以及液晶显示器，实现了减少时序控制芯片的复杂度。
本发明提供了一种驱动装置，包括：时序控制芯片以及数据驱动芯片，所述时序控制芯片连接所述数据驱动芯片，所述时序控制芯片用于从数量为第一值的像素点的灰度值中选择性接收数量为第二值的像素点的灰度值，并发送给 所述数据驱动芯片，其中，所述第一值和所述第二值均为正整数，所述第一值大于所述第二值；所述数据驱动芯片用于接收所述时序控制芯片发送的数量为第二值的像素点的灰度值，并根据数量为第二值的像素点的灰度值得到数量为第一值的像素点的灰度值，并输出得到的数量为第一值的像素点的灰度值对液晶显示器进行驱动。
可选地，所述第一值为2a*b，所述第二值为a*b，或，所述第一值为a*2b，所述第二值为a*b，其中，a为液晶显示器的第一维坐标的像素点的数量，b为所述液晶显示器的第二维坐标的像素点的数量。
可选地，所述时序控制芯片具体用于从数量为2a*b的像素点的灰度值中隔行接收像素点的灰度值，从而获得数量为a*b的像素点的灰度值，或者，从数量为2a*b的像素点的灰度值中隔列接收像素点的灰度值，从而获得数量为a*b的像素点的灰度值。
可选地，所述数据驱动芯片具体用于根据相邻的像素点的灰度值插值出中间像素点的灰度值，从而将数量为a*b的像素点的灰度值插值成数量为2a*b的像素点的灰度值，或者，将数量为a*b的像素点的灰度值插值成数量为a*2b的像素点的灰度值。
可选地，所述相邻的像素点为左右相邻的像素点、上下相邻的像素点、四邻域相邻的像素点中的任意一种。
可选地，所述数据驱动芯片具体用于根据相邻的红色子像素的灰度值插值出中间像素点的红色子像素的灰度值，根据相邻的绿色子像素的灰度值插值出中间像素点的绿色子像素的灰度值，根据相邻的蓝色子像素的灰度值插值出中间像素点的蓝色子像素的灰度值。
可选地，所述数据驱动芯片还具体用于根据相邻的白色子像素的灰度值插值出中间像素点的白色子像素的灰度值。
可选地，所述数据驱动芯片包括：移位寄存器、数据寄存器、行数据锁存器、扩展加法器、电压转移器、数模转换器以及输出缓存器，其中，所述移位寄存器、所述数据寄存器、所述行数据锁存器、所述扩展加法器、所述电压转移器、所述数模转换器以及所述输出缓存器之间串行连接，所述数据寄存器用于在所述移位寄存器的配合下，将接收所述时序控制芯片所发送的串行的像素 点的灰度值，并将串行的像素点的灰度值转变为并行的像素点的灰度值，并发送给所述行数据锁存器；所述行数据锁存器用于锁存所述数据寄存器所发送的并行的像素点的灰度值，并发送给所述扩展加法器；所述扩展加法器用于将所述数据寄存器发送的并行的像素点的灰度输出到所述电压转移器，并将相邻的像素点的灰度进行相加，并将相加后的结果取高八位输出到所述电压转移器以作为中间像素点的灰度值；所述电压转移器用于将所述扩展加法器输出的像素点的灰度值的电压进行转移，并输出到所述模数转换器；所述模数转换器用于将所述电压转移器输出的电压转移后的像素点的灰度值转变为模拟信号，并发送给所述输出缓存器；所述输出缓存器用于将模拟的像素点的灰度值进行输出以驱动像素点。
可选地，所述扩展加法器的第一输入端用于输入第一相邻像素点的子像素的灰度值，所述扩展加法器的第二输入端用于输入第二相邻像素点的同一颜色的子像素的灰度值，所述扩展加法器的第一输出端用于直接输出所述第一相邻像素点的子像素的灰度值，所述扩展加法器的第二输出端用于输出第二相邻像素点的子像素的灰度值，所述扩展加法器的第三输出端用于输出所述第一相邻像素点的子像素的灰度值和所述第二相邻像素点的同一颜色的子像素的灰度值之和的高八位。
本发明提供了一种液晶显示器，包括背板以及液晶面板，所述液晶面板包括驱动装置，所述驱动装置包括包括：时序控制芯片以及数据驱动芯片，所述时序控制芯片连接所述数据驱动芯片，
所述时序控制芯片用于从数量为第一值的像素点的灰度值中选择性接收数量为第二值的像素点的灰度值，并发送给所述数据驱动芯片，其中，所述第一值和所述第二值均为正整数，所述第一值大于所述第二值；
所述数据驱动芯片用于接收所述时序控制芯片发送的数量为第二值的像素点的灰度值，并根据数量为第二值的像素点的灰度值得到数量为第一值的像素点的灰度值，并输出得到的数量为第一值像素点的灰度值对所述液晶显示器进行驱动。
可选地，所述第一值为2a*b，所述第二值为a*b，或，所述第一值为a*2b，所述第二值为a*b，其中，a为液晶显示器的第一维坐标的像素点的数量，b 为所述液晶显示器的第二维坐标的像素点的数量。
可选地，所述时序控制芯片具体用于从数量为2a*b的像素点的灰度值中隔行接收像素点的灰度值，从而获得数量为a*b的像素点的灰度值，或者，从数量为2a*b的像素点的灰度值中隔列接收像素点的灰度值，从而获得数量为a*b的像素点的灰度值。
可选地，所述数据驱动芯片具体用于根据相邻的像素点的灰度值插值出中间像素点的灰度值，从而将数量为a*b的像素点的灰度值插值成数量为2a*b的像素点的灰度值，或者，将数量为a*b的像素点的灰度值插值成数量为a*2b的像素点的灰度值。
可选地，所述相邻的像素点为左右相邻的像素点、上下相邻的像素点、四邻域相邻的像素点中的任意一种。
可选地，所述数据驱动芯片具体用于根据相邻的红色子像素的灰度值插值出中间像素点的红色子像素的灰度值，根据相邻的绿色子像素的灰度值插值出中间像素点的绿色子像素的灰度值，根据相邻的蓝色子像素的灰度值插值出中间像素点的蓝色子像素的灰度值。
可选地，所述数据驱动芯片还具体用于根据相邻的白色子像素的灰度值插值出中间像素点的白色子像素的灰度值。
可选地，所述数据驱动芯片包括：移位寄存器、数据寄存器、行数据锁存器、扩展加法器、电压转移器、数模转换器以及输出缓存器，其中，所述移位寄存器、所述数据寄存器、所述行数据锁存器、所述扩展加法器、所述电压转移器、所述数模转换器以及所述输出缓存器之间串行连接，
所述数据寄存器用于在所述移位寄存器的配合下，接收所述时序控制芯片所发送的串行的像素点的灰度值，将串行的像素点的灰度值转变为并行的像素点的灰度值，并发送给所述行数据锁存器；
所述行数据锁存器用于锁存所述数据寄存器所发送的并行的像素点的灰度值，并发送给所述扩展加法器；
所述扩展加法器用于将所述数据寄存器发送的并行的像素点的灰度输出到所述电压转移器，并将相邻的像素点的灰度进行相加，并将相加后的结果取高八位输出到所述电压转移器以作为中间像素点的灰度值；
所述电压转移器用于将所述扩展加法器输出的像素点的灰度值的电压进行转移，并输出到所述模数转换器；
所述模数转换器用于将所述电压转移器输出的电压转移后的像素点的灰度值转变为模拟信号，并发送给所述输出缓存器；
所述输出缓存器用于将模拟的像素点的灰度值进行输出以驱动像素点。
可选地，所述扩展加法器的第一输入端用于输入第一相邻像素点的子像素的灰度值，所述扩展加法器的第二输入端用于输入第二相邻像素点的同一颜色的子像素的灰度值，所述扩展加法器的第一输出端用于直接输出所述第一相邻像素点的子像素的灰度值，所述扩展加法器的第二输出端用于输出第二相邻像素点的子像素的灰度值，所述扩展加法器的第三输出端用于输出所述第一相邻像素点的子像素的灰度值和所述第二相邻像素点的同一颜色的子像素的灰度值之和的高八位。
通过实施本发明实施例，能够在时序控制芯片接收数量为第一值的像素点的灰度值时，选择性只接收第二值的像素点的灰度值，并在输出到数据驱动芯片时，再通过插值的方法还原为数量为第一值的像素点的灰度值。所以，时序控制芯片所需要处理的像素点的数量大大减少，从而减少了时序控制芯片的复杂度，进而减少了时序控制芯片的成本。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是RGB液晶显示器和RGBW液晶显示器一像素点的示意图；
图2是本发明实施例的一种驱动装置的结构示意图；
图3是RGB液晶显示器的像素点矩阵示意图；
图4是本发明驱动装置经过时序控制芯片和数据驱动芯片时的数据量变化的示意图；
图5是本发明实施例的一种数据驱动芯片的结构示意图；
图6是本发明实施例的一种扩展加法器的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
需要说明的是，在本发明实施例中使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本发明。在本发明实施例和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。还应当理解，本文中使用的术语“和/或”是指并包含一个或多个相关联的列出项目的任何或所有可能组合。
请参阅图2，图2是本发明实施例的一种驱动装置的结构示意图。本发明的驱动装置100包括：时序控制芯片110以及数据驱动芯片120，时序控制芯片(TCON)110连接数据驱动芯片(Driver IC)120。
请一并参阅图3，液晶显示器通常包括多个像素点210。当需要对液晶显示器的像素点210进行驱动时，将数量为第一值的像素点的灰度值向时序控制芯片110发送。其中，第一值为正整数，第一值通常为液晶显示器所有像素点210的总数量。例如，如果液晶显示器的包括2a*b个像素点，则第一值的数值为2a*b，或者，如果液晶显示器的包括a*2b个像素点，则第一值的数值为a*2b，其中，a为液晶显示器的横坐标的像素点210的数量，b为液晶显示器的纵坐标的像素点210的数量。对于RGB型的液晶显示器，每个像素点210包括红、绿、蓝三个子像素，所以，对于RGB型的液晶显示器，每个像素点210的灰度值包括红、绿、蓝三个子像素的灰度值。而对于RGBW型的液晶显示器，每个像素点210包括红、绿、蓝、白四个子像素，所以，对于RGBW型的液晶显示器，每个像素点210的灰度值包括红、绿、蓝、白四个子像素的灰度值。
时序控制芯片110从数量为第一值的像素点210的灰度值中选择性接收数量为第二值的像素点210的灰度值，并发送给数据驱动芯片120。其中，第一值为正整数，第一值大于第二值。具体地，时序控制芯片110可以通过隔行的方式选择性地接收像素点210的灰度值，可以通过隔列的方式选择性地接收像素点210的灰度值，可以通过隔两行的方式选择性接收像素点210的灰度值，可以通过隔两列的方式选择性接收像素点210的灰度值，也可以以不规则的方式选择性接收像素点210的灰度值等等，本发明不作具体限定。请一并参阅图4，当时序控制芯片110以隔行的方式选择性接收像素点210的灰度值时，数量为2a*b的像素点210的灰度值中只有数量为a*b的像素点210的灰度值被时序控制芯片110接收。
在时序控制芯片110向数据驱动芯片120发送数量为第二值的像素点210的灰度值之后，数据驱动芯片120接收时序控制芯片110发送的数量为第二值的像素点210的灰度值，并根据数量为第二值的像素点210的灰度值得到数量为第一值的像素点210的灰度值，并输出得到的像素点210的灰度值对液晶显示器进行驱动。
具体地，可以通过插值法得到数量为第一值的像素点210的灰度值。例如，可以通过相邻像素点210的灰度值插值得到中间像素点210的灰度值，从而将数量为第二值的像素点210的灰度值插值成数量为第一值的像素点210的灰度值。具体地，通过上下两个相邻像素点210的灰度值插值得到中间像素点210的灰度值，可以通过左右两个相邻像素点210的灰度值插值得到中间像素点210的灰度值，可以通过四邻域的相邻像素点210的灰度值插值得到中间像素点210的灰度值等等方式将数量为第二值的像素点210的灰度值插值成数量为第一值的像素点210的灰度值。其中，数据驱动芯片120插值的方式与时序控制芯片110选择接收像素点210的方式是对应的。例如，当时序控制芯片110采用的是以隔行的方式接收像素点时，则数据驱动芯片120采用通过上下两个相邻像素点210的灰度值插值得到中间像素点210的灰度值或者通过左右两个相邻像素点210的灰度值插值得到中间像素点210的灰度值的方式进行插值。
可以理解的是，对于RGB型的液晶显示器，可以根据相邻像素点的红色子像素的灰度值插值得到中间像素点210的红色子像素的灰度值，根据相邻像 素点的绿色子像素的灰度值插值得到中间像素点210的绿色子像素的灰度值，根据相邻像素点的蓝色子像素的灰度值插值得到中间像素点210的蓝色子像素的灰度值。而对于RGBW型的液晶显示器，还需要根据相邻像素点的白色子像素的灰度值插值得到中间像素点210的白色子像素的灰度值。
下面将结合数据驱动芯片的具体结构说明如何实现插值。参阅图5，数据驱动芯片120包括移位寄存器(Shift register)121、数据寄存器(Data register)122、行数据锁存器(Line latch)123、扩展加法器(Adder)124、电压转移器(Level shift)125、数模转换器(DAC)126以及输出缓存器(Output buffer)127。其中，移位寄存器121、数据寄存器122、行数据锁存器123、扩展加法器124、电压转移器125、数模转换器126以及输出缓存器127之间串行连接。
数据寄存器122在移位寄存器121的配合下，接收时序控制芯片110所发送的串行的像素点的灰度值，将串行的像素点的灰度值转变为并行的像素点的灰度值，并发送给行数据锁存器123。行数据锁存器123锁存数据寄存器122所发送的并行的像素点的灰度值，并发送给扩展加法器124。
扩展加法器124将数据寄存器123发送的并行的像素点的灰度输出到电压转移器125，并将相邻的像素点的灰度进行相加，并将相加后的结果取高八位输出到电压转移器125以作为中间像素点的灰度值。具体地，以左右相邻的像素点的子像素的灰度值计算得到中间像素点的子像素的灰度值为例，扩展加法器124的结构如图6所示，由于灰度值通常是通过0～255来表示，所以扩展加法器124的8位的第一输入端A用于输入左相邻像素点的红色子像素的灰度值，扩展加法器124的8位第二输入端用于输入右相邻像素点的红色子像素的灰度值，扩展加法器124的8位的第一输出端C用于直接输出左相邻像素点的红色子像素的灰度值，扩展加法器124的8位的第二输出端D用于输出右相邻像素点的绿色子像素的灰度值，扩展加法器124的第三输出端用于输出左相邻像素点的红色子像素的灰度值和右相邻像素点的红色子像素的灰度值之和的高八位。其中，扩展加法器124的第三输出端只输出左相邻像素点的红色子像素的灰度值和右相邻像素点的红色子像素的灰度值之和的高八位相当于对左相邻像素点的红色子像素的灰度值和右相邻像素点的红色子像素的灰度值求平均值。类似地，扩展加法器124可以用同样的方式计算得到中间像素点 的绿色子像素、蓝色子像素和白色子像素的灰度值。
电压转移器125将扩展加法器124输出的像素点的灰度值的电压进行转移，并输出到模数转换器126，模数转换器126将电压转移器125输出的电压转移后的像素点的灰度值转变为模拟信号，并发送给输出缓存器127。输出缓存器127将模拟的像素点的灰度值进行输出以驱动像素点。
通过实施本发明实施例，能够在时序控制芯片接收数量为第一值的像素点的灰度值时，选择性只接收第二值的像素点的灰度值，并在输出到数据驱动芯片时，再通过插值的方法还原为数量为第一值的像素点的灰度值。所以，时序控制芯片所需要处理的像素点的数量大大减少，从而减少了时序控制芯片的复杂度，进而减少了时序控制芯片的成本。
本发明还提供了一种液晶显示器，包括背板以及液晶面板，液晶面板包括图2、图4、图5以及图6所示的驱动装置，具体请参阅图2、图4、图5、图6以及相关描述，此处不在一一赘述。
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程，是可以通过计算机程序来指令相关的硬件来完成，所述的程序可存储于一计算机可读取存储介质中，该程序在执行时，可包括如上述各方法的实施例的流程。其中，所述的存储介质可为磁碟、光盘、只读存储记忆体(Read-Only Memory，ROM)或随机存储记忆体(Random Access Memory，RAM)等。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (18)

  1. 一种驱动装置，其特征在于，包括：时序控制芯片以及数据驱动芯片，所述时序控制芯片连接所述数据驱动芯片，
    所述时序控制芯片用于从数量为第一值的像素点的灰度值中选择性接收数量为第二值的像素点的灰度值，并发送给所述数据驱动芯片，其中，所述第一值和所述第二值均为正整数，所述第一值大于所述第二值；
    所述数据驱动芯片用于接收所述时序控制芯片发送的数量为第二值的像素点的灰度值，并根据数量为第二值的像素点的灰度值得到数量为第一值的像素点的灰度值，并输出得到的数量为第一值像素点的灰度值对所述液晶显示器进行驱动。
  2. 根据权利要求1所述的驱动装置，其特征在于，所述第一值为2a*b，所述第二值为a*b，或，所述第一值为a*2b，所述第二值为a*b，其中，a为液晶显示器的第一维坐标的像素点的数量，b为所述液晶显示器的第二维坐标的像素点的数量。
  3. 根据权利要求2所述的驱动装置，其特征在于，所述时序控制芯片具体用于从数量为2a*b的像素点的灰度值中隔行接收像素点的灰度值，从而获得数量为a*b的像素点的灰度值，或者，从数量为2a*b的像素点的灰度值中隔列接收像素点的灰度值，从而获得数量为a*b的像素点的灰度值。
  4. 根据权利要求2所述的驱动装置，其特征在于，所述数据驱动芯片具体用于根据相邻的像素点的灰度值插值出中间像素点的灰度值，从而将数量为a*b的像素点的灰度值插值成数量为2a*b的像素点的灰度值，或者，将数量为a*b的像素点的灰度值插值成数量为a*2b的像素点的灰度值。
  5. 根据权利要求4所述的驱动装置，其特征在于，所述相邻的像素点为左右相邻的像素点、上下相邻的像素点、四邻域相邻的像素点中的任意一种。
  6. 根据权利要求4所述的驱动装置，其特征在于，所述数据驱动芯片具体用于根据相邻的红色子像素的灰度值插值出中间像素点的红色子像素的灰度值，根据相邻的绿色子像素的灰度值插值出中间像素点的绿色子像素的灰度值，根据相邻的蓝色子像素的灰度值插值出中间像素点的蓝色子像素的灰度值。
  7. 根据权利要求6所述的驱动装置，其特征在于，所述数据驱动芯片还具体用于根据相邻的白色子像素的灰度值插值出中间像素点的白色子像素的灰度值。
  8. 根据权利要求4所述的驱动装置，其特征在于，所述数据驱动芯片包括：移位寄存器、数据寄存器、行数据锁存器、扩展加法器、电压转移器、数模转换器以及输出缓存器，其中，所述移位寄存器、所述数据寄存器、所述行数据锁存器、所述扩展加法器、所述电压转移器、所述数模转换器以及所述输出缓存器之间串行连接，
    所述数据寄存器用于在所述移位寄存器的配合下，接收所述时序控制芯片所发送的串行的像素点的灰度值，将串行的像素点的灰度值转变为并行的像素点的灰度值，并发送给所述行数据锁存器；
    所述行数据锁存器用于锁存所述数据寄存器所发送的并行的像素点的灰度值，并发送给所述扩展加法器；
    所述扩展加法器用于将所述数据寄存器发送的并行的像素点的灰度输出到所述电压转移器，并将相邻的像素点的灰度进行相加，并将相加后的结果取高八位输出到所述电压转移器以作为中间像素点的灰度值；
    所述电压转移器用于将所述扩展加法器输出的像素点的灰度值的电压进行转移，并输出到所述模数转换器；
    所述模数转换器用于将所述电压转移器输出的电压转移后的像素点的灰度值转变为模拟信号，并发送给所述输出缓存器；
    所述输出缓存器用于将模拟的像素点的灰度值进行输出以驱动像素点。
  9. 根据权利要求8所述的驱动装置，其特征在于，所述扩展加法器的第一输入端用于输入第一相邻像素点的子像素的灰度值，所述扩展加法器的第二输入端用于输入第二相邻像素点的同一颜色的子像素的灰度值，所述扩展加法器的第一输出端用于直接输出所述第一相邻像素点的子像素的灰度值，所述扩展加法器的第二输出端用于输出第二相邻像素点的子像素的灰度值，所述扩展加法器的第三输出端用于输出所述第一相邻像素点的子像素的灰度值和所述第二相邻像素点的同一颜色的子像素的灰度值之和的高八位。
  10. 一种液晶显示器，其特征在于，包括背板以及液晶面板，所述液晶面 板包括驱动装置，所述驱动装置包括包括：时序控制芯片以及数据驱动芯片，所述时序控制芯片连接所述数据驱动芯片，
    所述时序控制芯片用于从数量为第一值的像素点的灰度值中选择性接收数量为第二值的像素点的灰度值，并发送给所述数据驱动芯片，其中，所述第一值和所述第二值均为正整数，所述第一值大于所述第二值；
    所述数据驱动芯片用于接收所述时序控制芯片发送的数量为第二值的像素点的灰度值，并根据数量为第二值的像素点的灰度值得到数量为第一值的像素点的灰度值，并输出得到的数量为第一值像素点的灰度值对所述液晶显示器进行驱动。
  11. 根据权利要求10所述的液晶显示器，其特征在于，所述第一值为2a*b，所述第二值为a*b，或，所述第一值为a*2b，所述第二值为a*b，其中，a为液晶显示器的第一维坐标的像素点的数量，b为所述液晶显示器的第二维坐标的像素点的数量。
  12. 根据权利要求11所述的液晶显示器，其特征在于，所述时序控制芯片具体用于从数量为2a*b的像素点的灰度值中隔行接收像素点的灰度值，从而获得数量为a*b的像素点的灰度值，或者，从数量为2a*b的像素点的灰度值中隔列接收像素点的灰度值，从而获得数量为a*b的像素点的灰度值。
  13. 根据权利要求11所述的液晶显示器，其特征在于，所述数据驱动芯片具体用于根据相邻的像素点的灰度值插值出中间像素点的灰度值，从而将数量为a*b的像素点的灰度值插值成数量为2a*b的像素点的灰度值，或者，将数量为a*b的像素点的灰度值插值成数量为a*2b的像素点的灰度值。
  14. 根据权利要求13所述的液晶显示器，其特征在于，所述相邻的像素点为左右相邻的像素点、上下相邻的像素点、四邻域相邻的像素点中的任意一种。
  15. 根据权利要求13所述的液晶显示器，其特征在于，所述数据驱动芯片具体用于根据相邻的红色子像素的灰度值插值出中间像素点的红色子像素的灰度值，根据相邻的绿色子像素的灰度值插值出中间像素点的绿色子像素的灰度值，根据相邻的蓝色子像素的灰度值插值出中间像素点的蓝色子像素的灰度值。
  16. 根据权利要求15所述的液晶显示器，其特征在于，所述数据驱动芯片还具体用于根据相邻的白色子像素的灰度值插值出中间像素点的白色子像素的灰度值。
  17. 根据权利要求13所述的液晶显示器，其特征在于，所述数据驱动芯片包括：移位寄存器、数据寄存器、行数据锁存器、扩展加法器、电压转移器、数模转换器以及输出缓存器，其中，所述移位寄存器、所述数据寄存器、所述行数据锁存器、所述扩展加法器、所述电压转移器、所述数模转换器以及所述输出缓存器之间串行连接，
    所述数据寄存器用于在所述移位寄存器的配合下，接收所述时序控制芯片所发送的串行的像素点的灰度值，将串行的像素点的灰度值转变为并行的像素点的灰度值，并发送给所述行数据锁存器；
    所述行数据锁存器用于锁存所述数据寄存器所发送的并行的像素点的灰度值，并发送给所述扩展加法器；
    所述扩展加法器用于将所述数据寄存器发送的并行的像素点的灰度输出到所述电压转移器，并将相邻的像素点的灰度进行相加，并将相加后的结果取高八位输出到所述电压转移器以作为中间像素点的灰度值；
    所述电压转移器用于将所述扩展加法器输出的像素点的灰度值的电压进行转移，并输出到所述模数转换器；
    所述模数转换器用于将所述电压转移器输出的电压转移后的像素点的灰度值转变为模拟信号，并发送给所述输出缓存器；
    所述输出缓存器用于将模拟的像素点的灰度值进行输出以驱动像素点。
  18. 根据权利要求17所述的液晶显示器，其特征在于，所述扩展加法器的第一输入端用于输入第一相邻像素点的子像素的灰度值，所述扩展加法器的第二输入端用于输入第二相邻像素点的同一颜色的子像素的灰度值，所述扩展加法器的第一输出端用于直接输出所述第一相邻像素点的子像素的灰度值，所述扩展加法器的第二输出端用于输出第二相邻像素点的子像素的灰度值，所述扩展加法器的第三输出端用于输出所述第一相邻像素点的子像素的灰度值和所述第二相邻像素点的同一颜色的子像素的灰度值之和的高八位。
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