WO2017045237A1 - 非晶硅半导体tft背板结构 - Google Patents

非晶硅半导体tft背板结构 Download PDF

Info

Publication number
WO2017045237A1
WO2017045237A1 PCT/CN2015/091806 CN2015091806W WO2017045237A1 WO 2017045237 A1 WO2017045237 A1 WO 2017045237A1 CN 2015091806 W CN2015091806 W CN 2015091806W WO 2017045237 A1 WO2017045237 A1 WO 2017045237A1
Authority
WO
WIPO (PCT)
Prior art keywords
amorphous silicon
layer
silicon layer
doped amorphous
semiconductor
Prior art date
Application number
PCT/CN2015/091806
Other languages
English (en)
French (fr)
Inventor
吕晓文
苏智昱
蒙艳红
梅文淋
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US14/787,772 priority Critical patent/US9741858B2/en
Publication of WO2017045237A1 publication Critical patent/WO2017045237A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H01L29/78627—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile with a significant overlap between the lightly doped drain and the gate electrode, e.g. GOLDD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78609—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an amorphous silicon semiconductor TFT backplane structure.
  • the flat panel display device has many advantages such as thin body, power saving, no radiation, and has been widely used.
  • the conventional flat panel display device mainly includes a liquid crystal display (LCD), an organic light emitting display (OLED), and the like.
  • TFTs Thin Film Transistors
  • LCDs LCDs, OLEDs, and electrophoretic display devices (EPDs).
  • EPDs electrophoretic display devices
  • the TFT can be generally classified into an amorphous silicon (A-Si) semiconductor TFT, a polycrystalline silicon (Poly-Si) semiconductor TFT, and an oxide semiconductor TFT.
  • Amorphous silicon is the most widely used in the semiconductor industry.
  • Amorphous silicon semiconductor TFTs have the advantages of simple process, low cost, and easy large-area process. Therefore, flat-panel display devices are most commonly used in amorphous silicon semiconductor TFTs.
  • the semiconductor layer is generally contacted.
  • the surface of the metal layer is heavily doped with N-type, that is, the surface of the semiconductor layer contacting the metal layer is doped with a high concentration of phosphorus (P) element to reduce the contact resistance between the metal layer and the semiconductor layer.
  • amorphous silicon semiconductor TFT backplane structure including a substrate 10, a gate electrode 20, a gate insulating layer 30, an amorphous silicon semiconductor layer 40, a source 60, and a drain 70.
  • the amorphous silicon semiconductor layer 40 is a two-layer structure in which the bottom layer contacting the gate insulating layer 30 is a pure amorphous silicon layer 41 without any treatment, and the top layer contacting the source 60 and the drain 70 is N-type heavily doped.
  • a hetero-amorphous silicon layer 42 is a two-layer structure in which the bottom layer contacting the gate insulating layer 30 is a pure amorphous silicon layer 41 without any treatment, and the top layer contacting the source 60 and the drain 70 is N-type heavily doped.
  • the N-type heavily doped amorphous silicon layer 42 forms an ohmic contact with the source 60 and the drain 70, which reduces the contact resistance between the source 60, the drain 70 and the semiconductor layer 40, improves current efficiency, and increases the on state. Current (I on ).
  • the above-mentioned amorphous silicon semiconductor TFT backplane structure as shown in FIG. 1 has a certain problem while increasing the on-state current, as shown by the dotted-line TFT current curve in FIG.
  • the gate voltage (Vg) is a negative voltage, and when the negative voltage is increased to a certain extent, more positive charges are excited to form a hole conduction channel, resulting in a large hole current I (Hole current I off ).
  • the reliability of the TFT is lowered, and the electrical stability of the TFT is lowered.
  • the present invention provides an amorphous silicon semiconductor TFT backplane structure including a substrate, a gate disposed on the substrate, a gate insulating layer covering the gate and the substrate, and the gate a semiconductor layer disposed on the gate insulating layer, and a source layer and a drain disposed on the gate insulating layer respectively contacting the upper surface of the semiconductor layer;
  • the semiconductor layer is a multilayer structure including a bottom amorphous silicon layer contacting the gate insulating layer, an N-type heavily doped amorphous silicon layer contacting the source and drain electrodes, and being sandwiched between the underlying amorphous silicon At least two N-type lightly doped amorphous silicon layers between the layer and the N-type heavily doped amorphous silicon layer, and the first intermediate amorphous silicon separated by each adjacent two layers of lightly doped amorphous silicon layers a layer, and a second intermediate amorphous silicon layer separating the N-type heavily doped amorphous silicon layer from the lightly doped amorphous silicon layer closest to the N-type heavily doped amorphous silicon layer;
  • the track region penetrates the N-type heavily doped amorphous silicon layer, the second intermediate amorphous silicon layer, the first intermediate amorphous silicon layer, and all of the N-type lightly doped amorphous silicon layers in the middle of the semiconductor layer.
  • the number of the N-type lightly doped amorphous silicon layers is two.
  • the ion doping concentration of the lightly doped amorphous silicon layer adjacent to the N-type heavily doped amorphous silicon layer is higher than the ion doping concentration of the lightly doped amorphous silicon layer adjacent to the underlying amorphous silicon layer.
  • the N-type lightly doped amorphous silicon layer is equal in thickness to the N-type heavily doped amorphous silicon layer.
  • the semiconductor layer is fabricated by a chemical vapor deposition process or an etching process.
  • the substrate is a glass substrate.
  • the material of the gate, source, and drain is a stack combination of one or more of molybdenum, titanium, aluminum, and copper.
  • the material of the gate insulating layer is silicon nitride, silicon oxide, or a combination of the two.
  • the present invention also provides an amorphous silicon semiconductor TFT backplane structure, comprising: a substrate, a gate electrode disposed on the substrate, a gate insulating layer covering the gate and the substrate, and being disposed above the gate electrode a semiconductor layer on the gate insulating layer, and a source and a drain provided on the gate insulating layer respectively contacting the upper surface of the semiconductor layer;
  • the semiconductor layer is a multilayer structure including a bottom amorphous silicon layer contacting the gate insulating layer, an N-type heavily doped amorphous silicon layer contacting the source and drain electrodes, and being sandwiched between the underlying amorphous silicon At least two N-type lightly doped amorphous silicon layers between the layer and the N-type heavily doped amorphous silicon layer, and the first intermediate amorphous silicon separated by each adjacent two layers of lightly doped amorphous silicon layers Layer, and the N-type heavily doped amorphous silicon layer a second intermediate amorphous silicon layer spaced apart from the lightly doped amorphous silicon layer closest to the N-type heavily doped amorphous silicon layer; a channel region penetrating the N-type heavy in the middle of the semiconductor layer Doping an amorphous silicon layer, a second intermediate amorphous silicon layer, a first intermediate amorphous silicon layer, and all N-type lightly doped amorphous silicon layers;
  • the number of the N-type lightly doped amorphous silicon layers is two layers;
  • the substrate is a glass substrate
  • the material of the gate, the source, and the drain is a stack combination of one or more of molybdenum, titanium, aluminum, and copper;
  • the material of the gate insulating layer is silicon nitride, silicon oxide, or a combination of the two.
  • an amorphous silicon semiconductor TFT backplane structure wherein a semiconductor layer is provided in a multilayer structure, and is sandwiched between an underlying amorphous silicon layer and an N-type heavily doped amorphous silicon layer. At least two layers of N-type lightly doped amorphous silicon layers, each adjacent two layers of lightly doped amorphous silicon layers are separated by a first intermediate amorphous silicon layer, an N-type heavily doped amorphous silicon layer and the most The lightly doped amorphous silicon layer adjacent to the N-type heavily doped amorphous silicon layer is spaced apart by the second intermediate amorphous silicon layer, which further reduces the energy barrier between the source drain and the semiconductor layer. It makes the electron injection easier, ensures that the on-state current will not decrease, and can increase the potential of hole transport, and divide more voltage between the gate and source of the TFT, thereby reducing leakage current and improving the reliability of the TFT. Sexual and electrical stability.
  • FIG. 1 is a schematic cross-sectional view showing a structure of a conventional amorphous silicon semiconductor TFT backplane
  • FIG. 2 is a schematic cross-sectional view showing a structure of a back sheet of an amorphous silicon semiconductor TFT according to the present invention
  • FIG. 3 is a schematic view showing a comparison of TFT current curves of the amorphous silicon semiconductor TFT backplane structure of the present invention and the conventional amorphous silicon semiconductor TFT backplane structure shown in FIG. 1.
  • the present invention provides an amorphous silicon semiconductor TFT backplane structure, including: a substrate 1, a gate 2 disposed on the substrate 1, and a gate insulating layer covering the gate 2 and the substrate 1. 3.
  • a semiconductor layer 4 disposed on the gate insulating layer 3 above the gate electrode 2, and a source layer 6 and a drain electrode 7 respectively disposed on the gate insulating layer 3 contacting the upper surface of the semiconductor layer 4.
  • the semiconductor layer 4 is a multi-layered structure including an underlying amorphous silicon layer 41 contacting the gate insulating layer 3 and N-type heavily doped amorphous silicon contacting the source and drain electrodes 6 and 7. a layer 42 and at least two N-type lightly doped amorphous silicon layers 43 sandwiched between the underlying amorphous silicon layer 41 and the N-type heavily doped amorphous silicon layer 42 and lightly doped each adjacent two layers
  • the first intermediate amorphous silicon layer 44 separated by the hetero-amorphous silicon layer 43 and the lightly doped with the N-type heavily doped amorphous silicon layer 42 and the closest to the N-type heavily doped amorphous silicon layer 42 a second intermediate amorphous silicon layer 45 separated by an amorphous silicon layer 43; a channel region 46 penetrating the N-type heavily doped amorphous silicon layer 42 and the second intermediate amorphous silicon in a middle portion of the semiconductor layer 4 Layer 45, first intermediate amorphous silicon layer 44, and
  • the number of the N-type lightly doped amorphous silicon layers 43 is two, and the two N-type lightly doped amorphous silicon layers 43 are separated by the first intermediate amorphous silicon layer 44.
  • the lightly doped amorphous silicon layer 43 adjacent to the N-type heavily doped amorphous silicon layer 42 has a higher phosphorus ion doping concentration than the lightly doped amorphous silicon layer 43 adjacent to the underlying amorphous silicon layer 41. Phosphorus ion doping concentration.
  • the number of the N-type lightly doped amorphous silicon layer 43 may also be three layers, four layers or even more, and a first intermediate amorphous layer is disposed between each adjacent two layers of the lightly doped amorphous silicon layer 43.
  • the silicon layers 44 are spaced apart, and the multi-layer N-type lightly doped amorphous silicon layer 43 sequentially increases the phosphorus ion doping concentration in order from bottom to top.
  • the N-type lightly doped amorphous silicon layer 43 and the N-type heavily doped amorphous silicon layer 42 have the same thickness.
  • the semiconductor layer 4 is first deposited by a chemical vapor deposition (CVD) process to form an underlying amorphous silicon layer 41, an N-type lightly doped non- a crystalline silicon layer 43, a first intermediate amorphous silicon layer 44, an N-type lightly doped amorphous silicon layer 43, a second intermediate amorphous silicon layer 45, and an N-type heavily doped amorphous silicon layer 42 are deposited underlying amorphous
  • CVD chemical vapor deposition
  • a phosphorus-containing gas is introduced while the amorphous silicon is deposited, and different phosphorus ion doping concentrations are controlled by adjusting the concentration and flow rate of the phosphorus-containing gas; after the deposition is completed, The channel region 46 is etched by an etching process.
  • the substrate 1 is a glass substrate;
  • the material of the gate 2, the source 6 and the drain 7 is one of molybdenum (Mo), titanium (Ti), aluminum (Al), and copper (Cu).
  • Mo molybdenum
  • Ti titanium
  • Al aluminum
  • Cu copper
  • the material of the gate insulating layer 3 is silicon nitride (SiNx), silicon oxide (SiOx), or a combination of the two.
  • the solid line type shows the TFT of the amorphous silicon semiconductor TFT backplane structure of the present invention.
  • the current curve compared with the TFT current curve of the existing amorphous silicon semiconductor TFT backplane structure represented by the dotted line type, the TFT on-state current of the amorphous silicon semiconductor TFT backplane structure of the present invention is improved, when the gate of the TFT is When the pole voltage Vg is a negative voltage and the negative voltage is increased to a certain extent, the leakage current is lowered because the semiconductor layer 4 is provided in a multilayer structure in the underlying amorphous silicon layer 41 and the N-type heavily doped amorphous silicon.
  • At least two layers of N-type lightly doped amorphous silicon layer 43 are interposed between the layers 42, and each adjacent two layers of lightly doped amorphous silicon layers 43 are separated by a first intermediate amorphous silicon layer 44, and the N-type heavy
  • the doped amorphous silicon layer 42 is spaced apart from the lightly doped amorphous silicon layer 43 closest to the N-type heavily doped amorphous silicon layer 42 by a second intermediate amorphous silicon layer 45, which further reduces the source. 6.
  • the energy barrier between the drain 7 and the semiconductor layer 4 makes electron injection easier, ensuring that the on-state current does not decrease, and at the same time, the potential of the hole transport can be increased, and more TFT gates are separated. The voltage between the sources, thereby reducing leakage current, improving the reliability and electrical stability of the TFT.
  • the amorphous silicon semiconductor TFT backplane structure of the present invention has a semiconductor layer disposed in a multi-layered structure, and at least two layers of N are interposed between the underlying amorphous silicon layer and the N-type heavily doped amorphous silicon layer.
  • a lightly doped amorphous silicon layer each adjacent two layers of lightly doped amorphous silicon layers are separated by a first intermediate amorphous silicon layer, and an N-type heavily doped amorphous silicon layer is closest to the N-type
  • the lightly doped amorphous silicon layer heavily doped with the amorphous silicon layer is spaced apart by the second intermediate amorphous silicon layer.
  • This structure further reduces the energy barrier between the source and drain and the semiconductor layer, making electron injection more It is easy to ensure that the on-state current will not decrease, and at the same time, the potential of hole transport can be increased, and more voltage between the gate and source of the TFT can be divided, thereby reducing leakage current and improving TFT reliability and electrical stability. Sex.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种非晶硅半导体TFT背板结构，其半导体层（4）为多层结构，包括接触栅极绝缘层（3）的底层非晶硅（41）、接触源极（6）与漏极（7）的N型重掺杂非晶硅层（42）、夹设于底层非晶硅层（41）与N型重掺杂非晶硅层（42）之间的至少两层N型轻掺杂非晶硅层（43）、将每相邻两层轻掺杂非晶硅层（43）间隔开的第一中间非晶硅层（44）、及将N型重掺杂非晶硅层（42）与最靠近该N型重掺杂非晶硅层（42）的轻掺杂非晶硅层（43）间隔开的第二中间非晶硅层（45）；这种结构进一步降低了漏源极和半导体层之间的能量势垒，使电子注入更加容易，保证了开态电流不会降低，同时可以提高空穴传输的势垒，降低漏电流，提高TFT的可靠性和电学稳定性。

Description

非晶硅半导体TFT背板结构 技术领域
本发明涉及显示技术领域，尤其涉及一种非晶硅半导体TFT背板结构。
背景技术
平板显示装置具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。现有的平板显示装置主要包括液晶显示装置(Liquid Crystal Display，LCD)及有机电致发光显示装置(Organic Light Emitting Display，OLED)等。
薄膜晶体管(Thin Film Transistor，TFT)是平板显示装置的重要组成部分，可形成在玻璃基板或塑料基板上，通常作为开关器件和驱动器件用在诸如LCD、OLED、电泳显示装置(EPD)上。
按照TFT内半导体材料的不同，TFT通常可分成非晶硅(A-Si)半导体TFT、多晶硅(Poly-Si)半导体TFT、及氧化物半导体TFT。非晶硅在目前的半导体行业中应用最为广泛，非晶硅半导体TFT具有制程简单、成本低、易于进行大面积制程等优点，因此，平板显示装置采用非晶硅半导体TFT最为普遍。
由于非晶硅材料与金属接触时存在较大的势能差，二者之间难以形成欧姆接触，在实际应用中，为了获得金属和非晶硅半导体层之间的欧姆接触，一般对半导体层接触金属层的表面进行N型重掺杂，即对半导体层接触金属层的表面掺杂高浓度的磷(P)元素，以降低金属层和半导体层的接触阻抗。
图1所示为一种现有的非晶硅半导体TFT背板结构，包括基板10、栅极20、栅极绝缘层30、非晶硅半导体层40、源极60、及漏极70。所述非晶硅半导体层40为双层结构，其中接触栅极绝缘层30的底层为未经任何处理的纯非晶硅层41，接触源极60与漏极70的顶层为N型重掺杂非晶硅层42。N型重掺杂非晶硅层42与源极60、及漏极70形成欧姆接触，降低了源极60、漏极70与半导体层40的接触阻抗，提高了电流效率，增大了开态电流(Ion)。
但是上述现有的如图1所示的非晶硅半导体TFT背板结构在增大开态电流的同时，也存在一定的问题，如图3中虚线线型的TFT电流曲线所示，当TFT的栅极电压(Vg)为负电压，且负电压增大到一定程度时，会激发 出较多的正电荷形成空穴导电通道，导致产生较大的空穴漏电流(Hole current Ioff)，降低了TFT的可靠性，使得TFT的电学稳定性下降。
发明内容
本发明的目的在于提供一种非晶硅半导体TFT背板结构，能够在不降低开态电流的前提下，降低漏电流，提高TFT的可靠性和电学稳定性。
为实现上述目的，本发明提供了一种非晶硅半导体TFT背板结构，包括基板、设于所述基板上的栅极、覆盖所述栅极与基板的栅极绝缘层、于所述栅极上方设于栅极绝缘层上的半导体层、及设于所述栅极绝缘层上分别接触半导体层上表面的源级与漏极；
所述半导体层为多层结构，包括接触栅极绝缘层的底层非晶硅层、接触所述源级与漏极的N型重掺杂非晶硅层、夹设于所述底层非晶硅层与N型重掺杂非晶硅层之间的至少两层N型轻掺杂非晶硅层、将每相邻两层轻掺杂非晶硅层间隔开的第一中间非晶硅层、及将所述N型重掺杂非晶硅层与最靠近该N型重掺杂非晶硅层的轻掺杂非晶硅层间隔开的第二中间非晶硅层；一沟道区于所述半导体层的中部贯穿所述N型重掺杂非晶硅层、第二中间非晶硅层、第一中间非晶硅层、与全部N型轻掺杂非晶硅层。
所述N型轻掺杂非晶硅层的数量为两层。
靠近所述N型重掺杂非晶硅层的轻掺杂非晶硅层的离子掺杂浓度高于靠近所述底层非晶硅层的轻掺杂非晶硅层的离子掺杂浓度。
所述N型轻掺杂非晶硅层与N型重掺杂非晶硅层的厚度相等。
所述半导体层通过化学气相沉积工艺、蚀刻工艺制作。
所述基板为玻璃基板。
所述栅极、源级、与漏极的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
所述栅极绝缘层的材料为氮化硅、氧化硅、或二者的组合。
本发明还提供一种非晶硅半导体TFT背板结构，包括：基板、设于所述基板上的栅极、覆盖所述栅极与基板的栅极绝缘层、于所述栅极上方设于栅极绝缘层上的半导体层、及设于所述栅极绝缘层上分别接触半导体层上表面的源级与漏极；
所述半导体层为多层结构，包括接触栅极绝缘层的底层非晶硅层、接触所述源级与漏极的N型重掺杂非晶硅层、夹设于所述底层非晶硅层与N型重掺杂非晶硅层之间的至少两层N型轻掺杂非晶硅层、将每相邻两层轻掺杂非晶硅层间隔开的第一中间非晶硅层、及将所述N型重掺杂非晶硅层 与最靠近该N型重掺杂非晶硅层的轻掺杂非晶硅层间隔开的第二中间非晶硅层；一沟道区于所述半导体层的中部贯穿所述N型重掺杂非晶硅层、第二中间非晶硅层、第一中间非晶硅层、与全部N型轻掺杂非晶硅层；
其中，所述N型轻掺杂非晶硅层的数量为两层；
其中，所述基板为玻璃基板；
其中，所述栅极、源级、与漏极的材料为钼、钛、铝、铜中的一种或多种的堆栈组合；
其中，所述栅极绝缘层的材料为氮化硅、氧化硅、或二者的组合。
本发明的有益效果：本发明提供的一种非晶硅半导体TFT背板结构，其半导体层设置为多层结构，在底层非晶硅层与N型重掺杂非晶硅层之间夹设至少两层N型轻掺杂非晶硅层，每相邻两层轻掺杂非晶硅层之间通过第一中间非晶硅层间隔开，N型重掺杂非晶硅层与最靠近该N型重掺杂非晶硅层的轻掺杂非晶硅层通过第二中间非晶硅层间隔开，这种结构进一步降低了源漏极和半导体层之间的能量势垒，使电子注入更加容易，保证了开态电流不会降低，同时可以提高空穴传输的势垒，分掉更多的TFT栅极与源极之间的电压，从而降低漏电流，提高TFT的可靠性和电学稳定性。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为一种现有的非晶硅半导体TFT背板结构的剖面示意图；
图2为本发明的非晶硅半导体TFT背板结构的剖面示意图；
图3为本发明的非晶硅半导体TFT背板结构与图1所示的现有的非晶硅半导体TFT背板结构的TFT电流曲线的对比示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图2，本发明提供一种非晶硅半导体TFT背板结构，包括：基板1、设于所述基板1上的栅极2、覆盖所述栅极2与基板1的栅极绝缘层 3、于所述栅极2上方设于栅极绝缘层3上的半导体层4、及设于所述栅极绝缘层3上分别接触半导体层4上表面的源级6与漏极7。
重点需要说明的是，所述半导体层4为多层结构，包括接触栅极绝缘层3的底层非晶硅层41、接触所述源级6与漏极7的N型重掺杂非晶硅层42、夹设于所述底层非晶硅层41与N型重掺杂非晶硅层42之间的至少两层N型轻掺杂非晶硅层43、将每相邻两层轻掺杂非晶硅层43间隔开的第一中间非晶硅层44、及将所述N型重掺杂非晶硅层42与最靠近该N型重掺杂非晶硅层42的轻掺杂非晶硅层43间隔开的第二中间非晶硅层45；一沟道区46于所述半导体层4的中部贯穿所述N型重掺杂非晶硅层42、第二中间非晶硅层45、第一中间非晶硅层44、与全部N型轻掺杂非晶硅层43。
优选的，如图2所示，所述N型轻掺杂非晶硅层43的数量为两层，该两层N型轻掺杂非晶硅层43被第一中间非晶硅层44间隔开，靠近所述N型重掺杂非晶硅层42的轻掺杂非晶硅层43的磷离子掺杂浓度高于靠近所述底层非晶硅层41的轻掺杂非晶硅层43的磷离子掺杂浓度。当然，所述N型轻掺杂非晶硅层43的数量还可为三层、四层甚至更多，每相邻两层轻掺杂非晶硅层43之间设置一第一中间非晶硅层44进行间隔，多层N型轻掺杂非晶硅层43按照从下到上的顺序依次提高磷离子掺杂浓度。
具体地，所述N型轻掺杂非晶硅层43与N型重掺杂非晶硅层42的厚度相等。
以图2所示的非晶硅半导体TFT背板结构为例，所述半导体层4先通过化学气相沉积(Chemical Vapor Deposition，CVD)工艺依次沉积底层非晶硅层41、N型轻掺杂非晶硅层43、第一中间非晶硅层44、N型轻掺杂非晶硅层43、第二中间非晶硅层45、与N型重掺杂非晶硅层42，沉积底层非晶硅层41、第一中间非晶硅层44、第二中间非晶硅层45的时候仅沉积纯非晶硅，而沉积两层N型轻掺杂非晶硅层43、N型重掺杂非晶硅层42的时候在沉积非晶硅的同时，通入含磷离子的气体，并通过调节含磷离子的气体的浓度与流量来控制不同的磷离子掺杂浓度；沉积完成后，再通过蚀刻工艺蚀刻出所述沟道区46。
进一步地，所述基板1为玻璃基板；所述栅极2、源级6、与漏极7的材料为钼(Mo)、钛(Ti)、铝(Al)、铜(Cu)中的一种或多种的堆栈组合；所述栅极绝缘层3的材料为氮化硅(SiNx)、氧化硅(SiOx)、或二者的组合。
请参阅图3，实线线型表示本发明的非晶硅半导体TFT背板结构的TFT 电流曲线，与虚线线型所表示的现有的非晶硅半导体TFT背板结构的TFT电流曲线相比，本发明的非晶硅半导体TFT背板结构的TFT开态电流提高，当TFT的栅极电压Vg为负电压且负电压增大到一定程度时，漏电流降低，这是由于所述半导体层4设置为多层结构，在底层非晶硅层41与N型重掺杂非晶硅层42之间夹设至少两层N型轻掺杂非晶硅层43，每相邻两层轻掺杂非晶硅层43之间通过第一中间非晶硅层44间隔开，N型重掺杂非晶硅层42与最靠近该N型重掺杂非晶硅层42的轻掺杂非晶硅层43通过第二中间非晶硅层45间隔开，这种结构进一步降低了源极6、漏极7和半导体层4之间的能量势垒，使电子注入更加容易，保证了开态电流不会降低，同时可以提高空穴传输的势垒，分掉更多的TFT栅极与源极之间的电压，从而降低漏电流，提高TFT的可靠性和电学稳定性。
综上所述，本发明的非晶硅半导体TFT背板结构，其半导体层设置为多层结构，在底层非晶硅层与N型重掺杂非晶硅层之间夹设至少两层N型轻掺杂非晶硅层，每相邻两层轻掺杂非晶硅层之间通过第一中间非晶硅层间隔开，N型重掺杂非晶硅层与最靠近该N型重掺杂非晶硅层的轻掺杂非晶硅层通过第二中间非晶硅层间隔开，这种结构进一步降低了源漏极和半导体层之间的能量势垒，使电子注入更加容易，保证了开态电流不会降低，同时可以提高空穴传输的势垒，分掉更多的TFT栅极与源极之间的电压，从而降低漏电流，提高TFT的可靠性和电学稳定性。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (12)

  1. 一种非晶硅半导体TFT背板结构，包括：基板、设于所述基板上的栅极、覆盖所述栅极与基板的栅极绝缘层、于所述栅极上方设于栅极绝缘层上的半导体层、及设于所述栅极绝缘层上分别接触半导体层上表面的源级与漏极；
    所述半导体层为多层结构，包括接触栅极绝缘层的底层非晶硅层、接触所述源级与漏极的N型重掺杂非晶硅层、夹设于所述底层非晶硅层与N型重掺杂非晶硅层之间的至少两层N型轻掺杂非晶硅层、将每相邻两层轻掺杂非晶硅层间隔开的第一中间非晶硅层、及将所述N型重掺杂非晶硅层与最靠近该N型重掺杂非晶硅层的轻掺杂非晶硅层间隔开的第二中间非晶硅层；一沟道区于所述半导体层的中部贯穿所述N型重掺杂非晶硅层、第二中间非晶硅层、第一中间非晶硅层、与全部N型轻掺杂非晶硅层。
  2. 如权利要求1所述非晶硅半导体TFT背板结构，其中，所述N型轻掺杂非晶硅层的数量为两层。
  3. 如权利要求2所述非晶硅半导体TFT背板结构，其中，靠近所述N型重掺杂非晶硅层的轻掺杂非晶硅层的离子掺杂浓度高于靠近所述底层非晶硅层的轻掺杂非晶硅层的离子掺杂浓度。
  4. 如权利要求2所述非晶硅半导体TFT背板结构，其中，所述N型轻掺杂非晶硅层与N型重掺杂非晶硅层的厚度相等。
  5. 如权利要求3所述非晶硅半导体TFT背板结构，其中，所述半导体层通过化学气相沉积工艺、蚀刻工艺制作。
  6. 如权利要求1所述非晶硅半导体TFT背板结构，其中，所述基板为玻璃基板。
  7. 如权利要求1所述非晶硅半导体TFT背板结构，其中，所述栅极、源级、与漏极的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
  8. 如权利要求1所述非晶硅半导体TFT背板结构，其中，所述栅极绝缘层的材料为氮化硅、氧化硅、或二者的组合。
  9. 一种非晶硅半导体TFT背板结构，包括：基板、设于所述基板上的栅极、覆盖所述栅极与基板的栅极绝缘层、于所述栅极上方设于栅极绝缘层上的半导体层、及设于所述栅极绝缘层上分别接触半导体层上表面的源级与漏极；
    所述半导体层为多层结构，包括接触栅极绝缘层的底层非晶硅层、接 触所述源级与漏极的N型重掺杂非晶硅层、夹设于所述底层非晶硅层与N型重掺杂非晶硅层之间的至少两层N型轻掺杂非晶硅层、将每相邻两层轻掺杂非晶硅层间隔开的第一中间非晶硅层、及将所述N型重掺杂非晶硅层与最靠近该N型重掺杂非晶硅层的轻掺杂非晶硅层间隔开的第二中间非晶硅层；一沟道区于所述半导体层的中部贯穿所述N型重掺杂非晶硅层、第二中间非晶硅层、第一中间非晶硅层、与全部N型轻掺杂非晶硅层；
    其中，所述N型轻掺杂非晶硅层的数量为两层；
    其中，所述基板为玻璃基板；
    其中，所述栅极、源级、与漏极的材料为钼、钛、铝、铜中的一种或多种的堆栈组合；
    其中，所述栅极绝缘层的材料为氮化硅、氧化硅、或二者的组合。
  10. 如权利要求9所述非晶硅半导体TFT背板结构，其中，靠近所述N型重掺杂非晶硅层的轻掺杂非晶硅层的离子掺杂浓度高于靠近所述底层非晶硅层的轻掺杂非晶硅层的离子掺杂浓度。
  11. 如权利要求9所述非晶硅半导体TFT背板结构，其中，所述N型轻掺杂非晶硅层与N型重掺杂非晶硅层的厚度相等。
  12. 如权利要求10所述非晶硅半导体TFT背板结构，其中，所述半导体层通过化学气相沉积工艺、蚀刻工艺制作。
PCT/CN2015/091806 2015-09-15 2015-10-13 非晶硅半导体tft背板结构 WO2017045237A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/787,772 US9741858B2 (en) 2015-09-15 2015-10-13 Amorphous silicon semiconductor TFT backboard structure

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510586074.2A CN105161503B (zh) 2015-09-15 2015-09-15 非晶硅半导体tft背板结构
CN201510586074.2 2015-09-15

Publications (1)

Publication Number Publication Date
WO2017045237A1 true WO2017045237A1 (zh) 2017-03-23

Family

ID=54802317

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/091806 WO2017045237A1 (zh) 2015-09-15 2015-10-13 非晶硅半导体tft背板结构

Country Status (3)

Country Link
US (1) US9741858B2 (zh)
CN (1) CN105161503B (zh)
WO (1) WO2017045237A1 (zh)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108064419A (zh) * 2016-12-29 2018-05-22 深圳市柔宇科技有限公司 薄膜晶体管和薄膜晶体管的制备方法和阵列基板
WO2019222910A1 (en) * 2018-05-22 2019-11-28 Boe Technology Group Co., Ltd. Array substrate, display apparatus, pixel driving circuit, method for driving image display in display apparatus, and method of fabricating array substrate
WO2020031309A1 (ja) * 2018-08-08 2020-02-13 堺ディスプレイプロダクト株式会社 薄膜トランジスタおよびその製造方法
CN109545751B (zh) * 2018-10-15 2022-02-22 Tcl华星光电技术有限公司 薄膜晶体管阵列基板制造方法
CN109545689B (zh) 2018-12-03 2021-05-25 惠科股份有限公司 主动开关及其制作方法、显示装置
CN109545690A (zh) * 2018-12-03 2019-03-29 惠科股份有限公司 薄膜晶体管结构及其制作方法、显示装置
CN109616510B (zh) 2018-12-03 2020-04-14 惠科股份有限公司 薄膜晶体管结构及其制作方法、显示装置
CN109713044B (zh) * 2018-12-25 2021-04-13 惠科股份有限公司 一种薄膜晶体管及制作方法和显示面板
CN109870769A (zh) * 2019-03-04 2019-06-11 南京大学 一种干法蚀刻制备二氧化硅光学微盘腔的方法
CN113345966A (zh) * 2020-02-18 2021-09-03 堺显示器制品株式会社 薄膜晶体管及其制造方法
CN113193049B (zh) * 2021-04-29 2024-04-26 Tcl华星光电技术有限公司 一种半导体器件及其制作方法、显示面板
US20240222511A1 (en) * 2021-09-29 2024-07-04 Ordos Yuansheng Optoelectronics Co., Ltd. Amorphous silicon thin-film transistor, method for preparing same, and display panel

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101499477A (zh) * 2005-02-18 2009-08-05 株式会社半导体能源研究所 半导体器件及其制造方法
CN102598281A (zh) * 2009-11-03 2012-07-18 应用材料公司 具有多个掺杂硅层的薄膜晶体管

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5198694A (en) * 1990-10-05 1993-03-30 General Electric Company Thin film transistor structure with improved source/drain contacts
JP2661594B2 (ja) * 1995-05-25 1997-10-08 日本電気株式会社 薄膜トランジスタおよびその製造方法
US8110829B2 (en) * 2007-05-31 2012-02-07 Lg Display Co., Ltd. Array substrate of liquid crystal display and method for fabricating the same
US7968885B2 (en) * 2007-08-07 2011-06-28 Semiconductor Energy Laboratory Co., Ltd. Display device and manufacturing method thereof
US8405085B2 (en) * 2010-12-01 2013-03-26 Au Optronics Corporation Thin film transistor capable of reducing photo current leakage
CN104282696B (zh) * 2014-10-22 2018-07-13 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
CN104576750A (zh) * 2014-12-02 2015-04-29 信利（惠州）智能显示有限公司 薄膜晶体管结构

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101499477A (zh) * 2005-02-18 2009-08-05 株式会社半导体能源研究所 半导体器件及其制造方法
CN102598281A (zh) * 2009-11-03 2012-07-18 应用材料公司 具有多个掺杂硅层的薄膜晶体管

Also Published As

Publication number Publication date
CN105161503B (zh) 2018-07-10
CN105161503A (zh) 2015-12-16
US9741858B2 (en) 2017-08-22
US20170162707A1 (en) 2017-06-08

Similar Documents

Publication Publication Date Title
WO2017045237A1 (zh) 非晶硅半导体tft背板结构
TWI555200B (zh) 偏移電極ｔｆｔ架構
CN105390551B (zh) 薄膜晶体管及其制造方法、阵列基板、显示装置
US20190198532A1 (en) Display panel and method for manufacturing thin film transistor substrate
CN107507841A (zh) 阵列基板及其制作方法、显示装置
WO2016173322A1 (zh) 一种阵列基板及其制作方法、及显示装置
US9240491B2 (en) Semiconductor device and method for manufacturing same
US8330166B2 (en) Thin-film semiconductor device for display apparatus thereof and manufacturing method thereof
US10121883B2 (en) Manufacturing method of top gate thin-film transistor
CN102646715A (zh) 薄膜晶体管及其制造方法
US10290665B2 (en) Array substrates, display devices, and the manufacturing methods thereof
WO2019134177A1 (zh) 显示面板和显示装置
US20160181290A1 (en) Thin film transistor and fabricating method thereof, and display device
US20170200829A1 (en) Thin-film transistor
WO2013065600A1 (ja) 薄膜トランジスタ、その製造方法、および表示装置
US10249763B2 (en) Array substrate, and display device, and fabrication methods
TW201515212A (zh) 薄膜電晶體及其製造方法
CN109616444B (zh) Tft基板的制作方法及tft基板
KR20160049172A (ko) 박막트랜지스터 어레이 기판 및 이를 포함하는 표시장치
KR20130029272A (ko) 박막 트랜지스터
CN118039702A (zh) 一种顶栅肖特基氧化物薄膜晶体管及制备方法
KR102382762B1 (ko) 실리콘계 박막 반도체 장치 및 실리콘계 박막 반도체 장치의 제조 방법
CN112289854B (zh) 一种阵列基板及其制备方法
KR20120132130A (ko) 박막트랜지스터 및 그의 제조방법
WO2019015023A1 (zh) 阵列基板及制作方法、显示面板

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14787772

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15903925

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15903925

Country of ref document: EP

Kind code of ref document: A1