WO2017028350A1 - 液晶显示装置及其goa扫描电路 - Google Patents

液晶显示装置及其goa扫描电路 Download PDF

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Publication number
WO2017028350A1
WO2017028350A1 PCT/CN2015/089432 CN2015089432W WO2017028350A1 WO 2017028350 A1 WO2017028350 A1 WO 2017028350A1 CN 2015089432 W CN2015089432 W CN 2015089432W WO 2017028350 A1 WO2017028350 A1 WO 2017028350A1
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Prior art keywords
thin film
film transistor
node
path
circuit unit
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PCT/CN2015/089432
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English (en)
French (fr)
Inventor
曹尚操
肖军城
Original Assignee
深圳市华星光电技术有限公司
武汉华星光电技术有限公司
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Priority to US14/787,033 priority Critical patent/US9799294B2/en
Publication of WO2017028350A1 publication Critical patent/WO2017028350A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0213—Addressing of scan or signal lines controlling the sequence of the scanning lines with respect to the patterns to be displayed, e.g. to save power
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a liquid crystal display device and a GOA scanning circuit thereof.
  • Liquid crystal display (Liquid Crystal Display, LCD) has many advantages such as thin body, power saving, no radiation, etc., and has been widely used. Such as: LCD TVs, mobile phones, personal digital assistants (PDAs), digital cameras, computer screens or laptop screens, etc., dominate the field of flat panel display.
  • LCD TVs Liquid Crystal Display
  • PDAs personal digital assistants
  • digital cameras computer screens or laptop screens, etc.
  • liquid crystal displays which include a liquid crystal display panel and a backlight module (backlight) Module).
  • the working principle of the liquid crystal display panel is Thin Film Transistor Array Substrate (TFT Array).
  • TFT Array Thin Film Transistor Array Substrate
  • Substrate) with color filter substrate Color filter substrate
  • the liquid crystal molecules are injected between the filter and the CF, and a driving voltage is applied to the two substrates to control the rotation direction of the liquid crystal molecules to refract the light of the backlight module to generate a picture.
  • each pixel is electrically connected to a thin film transistor (TFT), a gate of a thin film transistor is connected to a horizontal scanning line, and a drain is connected to a vertical data line, and a source (Source) ) is connected to the pixel electrode.
  • TFT thin film transistor
  • Source Source
  • the driving of the horizontal scanning line of the active liquid crystal display panel is mainly driven by an external integrated circuit board (Integrated Circuit, IC) to complete, the external IC can control the level of charge and discharge of the horizontal scanning lines.
  • IC Integrated Circuit
  • GOA technology Gate Driver on Array
  • the original array process of the liquid crystal display panel can be used to make the horizontal scanning line driving circuit on the substrate around the display area, so that it can replace the external IC to complete the horizontal scanning line driving.
  • GOA technology can reduce the bonding process of external ICs, have the opportunity to increase production capacity and reduce product cost, and can make LCD panels more suitable for making narrow-frame or borderless display products.
  • the GOA circuit includes the following: a GOA circuit based on a P-type thin film transistor, a CMOS-based GOA circuit, and a GOA circuit based on an N-type thin film transistor, wherein a GOA circuit based on a P-type thin film transistor, particularly a low temperature polysilicon (LTPS)
  • LTPS low temperature polysilicon
  • the material-based P-type thin film transistor-based GOA circuit has the characteristics of simple process and low leakage, and has a good development prospect.
  • the existing GOA scanning circuit with bidirectional scanning function requires more thin film transistors and uses more signal lines, resulting in more occupied display areas, which is not conducive to narrow border or borderless design.
  • the technical problem to be solved by the present invention is to provide a liquid crystal display device and a GOA scanning circuit thereof, which can realize a bidirectional scanning function while requiring fewer thin film transistors and signal lines.
  • a technical solution adopted by the present invention is to provide a GOA scanning circuit, wherein the GOA scanning circuit includes a plurality of cascaded GOA circuit units, nth stage (N ⁇ n ⁇ 1, and n is The positive integer) GOA circuit unit includes: a forward and reverse scan module, the forward and reverse scan module includes a first thin film transistor T1 and a second thin film transistor T2, and the two path ends of the first thin film transistor T1 are respectively connected to the first clock signal XCK and The first node Qn, the two path ends of the second thin film transistor T2 are respectively connected to the second clock signal CK and the first node Qn, and the control end of the first thin film transistor T1 is connected to the level signal STn-1 of the upper level GOA circuit unit.
  • the control terminal of the second thin film transistor T2 is connected to the level signal STn+1 of the next-stage GOA circuit unit, wherein the control terminal of the first thin film transistor T1 of the first-stage GOA circuit unit is connected to the forward scan trigger signal STV1,
  • the control terminal of the second thin film transistor T2 in the Nth stage GOA circuit unit is connected to the reverse scan trigger signal STV2; and the output module is connected to the first node Qn and used for outputting potential according to the first node Qn.
  • the control terminal of the transistor T4 is connected to the first node Qn, the first path end of the third thin film transistor T3 is connected to the second clock signal CK, and the second path end of the third thin film transistor T3 is used for outputting the level pass of the GOA circuit unit of the present stage.
  • the signal STn, the first path end of the fourth thin film transistor T4 is connected to the second clock signal CK, and the second path end of the fourth thin film transistor T4 is used for outputting the scan signal Gn of the GOA circuit unit of the current stage, and both ends of the first capacitor C1
  • the first node Qn and the second path end of the third thin film transistor T3 are respectively connected; the first clock signal XCK is inverted with the second clock signal CK.
  • the nth stage GOA circuit unit further includes a pull-down maintaining module, and the pull-down maintaining module includes a fifth thin film transistor T5, a sixth thin film transistor T6, and a seventh thin film transistor T7, a fifth thin film transistor T5, a sixth thin film transistor T6, and a seventh
  • the control terminals of the thin film transistor T7 are connected to the second node Pn.
  • the two path ends of the fifth thin film transistor T5 are respectively connected to the second path end of the third thin film transistor T3 and the first constant voltage VGH1, and the two paths of the sixth thin film transistor T6.
  • the terminals are respectively connected to the second path end of the fourth thin film transistor T4 and the first constant voltage VGH1, and the two path ends of the seventh thin film transistor T7 are respectively connected to the first node Qn and the second constant voltage VGH2.
  • the nth stage GOA circuit unit further includes a pull-down module, and the pull-down module includes an eighth thin film transistor T8 and a ninth thin film transistor T9.
  • the second pass end of the eighth thin film transistor T8 is connected to the second constant voltage, and the eighth thin film transistor T8
  • the control terminal is connected to the first node Qn, and the two path ends of the ninth thin film transistor T9 are respectively connected to the second node Pn and the second constant voltage VGH2, and the control end of the ninth thin film transistor T9 is connected to the first node Qn; the nth stage GOA circuit unit
  • the tenth thin film transistor T10, the eleventh thin film transistor T11, the twelfth thin film transistor T12, and the second capacitor C2 are further included.
  • the first path end of the tenth thin film transistor T10 is connected to the second clock signal CK and the second path end is connected.
  • the first path end of the eleventh thin film transistor T11, the second path end of the eleventh thin film transistor T11 is connected to the second node Pn and the control end thereof is connected to the second clock signal CK, and the control end of the tenth thin film transistor T10 is connected to the tenth a second path end of the second thin film transistor T12, the first path end and the control end of the twelfth thin film transistor T12 are connected to the first clock signal XCK and the second path end is connected
  • a first end and a second capacitor first terminal of the eighth thin film transistor T8 C2, the second terminal of the second capacitor C2 is connected to the second constant voltage VGH2.
  • a GOA scanning circuit including a plurality of cascaded GOA circuit units, nth stage (N ⁇ n ⁇ 1, and n is positive
  • the integer integer) GOA circuit unit includes: a forward and reverse scan module and an output module, the forward and reverse scan module includes a first thin film transistor T1 and a second thin film transistor T2, and the two path ends of the first thin film transistor T1 are respectively connected to the first clock signal XCK and the first node Qn, the two path ends of the second thin film transistor T2 are respectively connected to the second clock signal CK and the first node Qn, and the control end of the first thin film transistor T1 is connected to the level signal STn of the upper level GOA circuit unit.
  • the control end of the second thin film transistor T2 is connected to the level transfer signal STn+1 of the next stage GOA circuit unit, wherein the control end of the first thin film transistor T1 in the first stage GOA circuit unit is connected to the forward scan trigger signal STV1, the control terminal of the second thin film transistor T2 in the Nth stage GOA circuit unit is connected to the reverse scan trigger signal STV2; the output module is connected to the first node Qn and is used to output the current level G according to the potential of the first node Qn
  • the level signal STn of the OA circuit unit and the scan signal Gn of the GOA circuit unit of the current stage are output.
  • the output module includes a third thin film transistor T3, a fourth thin film transistor T4, and a first capacitor C1.
  • the control terminals of the third thin film transistor T3 and the fourth thin film transistor T4 are connected to the first node Qn, and the third thin film transistor T3
  • the second path end of the third thin film transistor T3 is used to output the level signal STn of the GOA circuit unit of the present stage, and the first path end of the fourth thin film transistor T4 is connected to the second clock signal CK.
  • the second path end of the fourth thin film transistor T4 is used for outputting the scan signal Gn of the GOA circuit unit of the current stage, and the two ends of the first capacitor C1 are respectively connected to the second end of the first node Qn and the third thin film transistor T3.
  • the nth stage GOA circuit unit further includes a pull-down maintaining module, and the pull-down maintaining module includes a fifth thin film transistor T5, a sixth thin film transistor T6, and a seventh thin film transistor T7, a fifth thin film transistor T5, a sixth thin film transistor T6, and a seventh
  • the control terminals of the thin film transistor T7 are connected to the second node Pn.
  • the two path ends of the fifth thin film transistor T5 are respectively connected to the second path end of the third thin film transistor T3 and the first constant voltage VGH1, and the two paths of the sixth thin film transistor T6.
  • the terminals are respectively connected to the second path end of the fourth thin film transistor T4 and the first constant voltage VGH1, and the two path ends of the seventh thin film transistor T7 are respectively connected to the first node Qn and the second constant voltage VGH2.
  • the nth stage GOA circuit unit further includes a pull-down module, the pull-down module includes an eighth thin film transistor T8 and a ninth thin film transistor T9, and the second pass end of the eighth thin film transistor T8 is connected to the second constant voltage VGH2, and the eighth thin film transistor T8
  • the control terminal is connected to the first node Qn, the two path ends of the ninth thin film transistor T9 are respectively connected to the second node Pn and the second constant voltage, and the control end of the ninth thin film transistor T9 is connected to the first node Qn; the nth stage GOA circuit unit
  • the tenth thin film transistor T10, the eleventh thin film transistor T11, the twelfth thin film transistor T12, and the second capacitor C2 are further included.
  • the first path end of the tenth thin film transistor T10 is connected to the second clock signal CK and the second path end is connected.
  • the first path end of the eleventh thin film transistor T11, the second path end of the eleventh thin film transistor T11 is connected to the second node Pn and the control end thereof is connected to the second clock signal CK, and the control end of the tenth thin film transistor T10 is connected to the tenth a second path end of the second thin film transistor T12, the first path end and the control end of the twelfth thin film transistor T12 are connected to the first clock signal XCK and the second path end is connected
  • a first end and a second capacitor first terminal of the eighth thin film transistor T8 C2, the second terminal of the second capacitor C2 is connected to the second constant voltage VGH2.
  • the first constant voltage VGH1 and the second constant voltage VGH2 are equal in magnitude.
  • the first constant voltage VGH1 is greater than the second constant voltage VGH2.
  • the first to twelfth thin film transistors T1 to T12 are all P-type thin film transistors.
  • the control terminals of the first to twelfth thin film transistors T1 to T12 are all gate electrodes.
  • the drain of the first thin film transistor T1 is connected to the first clock signal XCK and the source is connected to the first node Qn
  • the drain of the second thin film transistor T2 is connected to the second clock signal CK and the source is connected to the first node Qn
  • the first path end of the three thin film transistor T3 is a drain and the second path end thereof is a source
  • the first path end of the fourth thin film transistor T4 is a drain and the second path end thereof is a source
  • the fifth thin film transistor T5 The drain is connected to the second path end of the third thin film transistor T3, the source of the fifth thin film transistor T5 is connected to the first constant voltage
  • the drain of the sixth thin film transistor T6 is connected to the second path end of the fourth thin film transistor T4.
  • the source of the sixth thin film transistor T6 is connected to the first constant voltage VGH1
  • the drain of the seventh thin film transistor T7 is connected to the first node Qn and the source thereof is connected to the second constant voltage VGH2, and the first path end of the eighth thin film transistor T8 is drained.
  • the drain is The second path end is a source thereof, the first path end of the eleventh thin film transistor T11 is a drain and the second path end thereof is a source thereof, and the first path end of the eleventh thin film transistor T11 is a drain and The second path end is its source.
  • a liquid crystal display device including a GOA scanning circuit
  • the GOA scanning circuit includes a plurality of cascaded GOA circuit units, nth stage (N ⁇ n ⁇ 1, And n is a positive integer.
  • the GOA circuit unit includes: a forward-reverse scanning module and an output module.
  • the forward-reverse scanning module includes a first thin film transistor T1 and a second thin film transistor T2, and the two path ends of the first thin film transistor T1 are respectively connected.
  • the first clock signal XCK and the first node Qn, the two path ends of the second thin film transistor T2 are respectively connected to the second clock signal CK and the first node Qn, and the control end of the first thin film transistor T1 is connected to the upper level GOA circuit unit.
  • the control signal of the second thin film transistor T2 is connected to the level signal STn+1 of the next-stage GOA circuit unit, wherein the control terminal of the first thin film transistor T1 in the first-stage GOA circuit unit is connected positively.
  • the control terminal of the second thin film transistor T2 in the Nth stage GOA circuit unit is connected to the reverse scan trigger signal STV2; the output module is connected to the first node Qn and used according to the first node
  • the potential of Qn outputs the level-transmitting signal STn of the GOA circuit unit of the present stage and the scanning signal Gn of the GOA circuit unit of the present stage.
  • the output module includes a third thin film transistor T3, a fourth thin film transistor T4, and a first capacitor C1.
  • the control terminals of the third thin film transistor T3 and the fourth thin film transistor T4 are connected to the first node Qn, and the third thin film transistor T3
  • the second path end of the third thin film transistor T3 is used to output the level signal STn of the GOA circuit unit of the present stage, and the first path end of the fourth thin film transistor T4 is connected to the second clock signal CK.
  • the second path end of the fourth thin film transistor T4 is used for outputting the scan signal Gn of the GOA circuit unit of the current stage, and the two ends of the first capacitor C1 are respectively connected to the second end of the first node Qn and the third thin film transistor T3.
  • the nth stage GOA circuit unit further includes a pull-down maintaining module, and the pull-down maintaining module includes a fifth thin film transistor T5, a sixth thin film transistor T6, and a seventh thin film transistor T7, a fifth thin film transistor T5, a sixth thin film transistor T6, and a seventh
  • the control terminals of the thin film transistor T7 are connected to the second node Pn.
  • the two path ends of the fifth thin film transistor T5 are respectively connected to the second path end of the third thin film transistor T3 and the first constant voltage VGH1, and the two paths of the sixth thin film transistor T6.
  • the terminals are respectively connected to the second path end of the fourth thin film transistor T4 and the first constant voltage VGH1, and the two path ends of the seventh thin film transistor T7 are respectively connected to the first node Qn and the second constant voltage VGH2.
  • the nth stage GOA circuit unit further includes a pull-down module, the pull-down module includes an eighth thin film transistor T8 and a ninth thin film transistor T9, and the second pass end of the eighth thin film transistor T8 is connected to the second constant voltage VGH2, and the eighth thin film transistor T8
  • the control terminal is connected to the first node Qn, the two path ends of the ninth thin film transistor T9 are respectively connected to the second node Pn and the second constant voltage, and the control end of the ninth thin film transistor T9 is connected to the first node Qn; the nth stage GOA circuit unit
  • the tenth thin film transistor T10, the eleventh thin film transistor T11, the twelfth thin film transistor T12, and the second capacitor C2 are further included.
  • the first path end of the tenth thin film transistor T10 is connected to the second clock signal CK and the second path end is connected.
  • the first path end of the eleventh thin film transistor T11, the second path end of the eleventh thin film transistor T11 is connected to the second node Pn and the control end thereof is connected to the second clock signal CK, and the control end of the tenth thin film transistor T10 is connected to the tenth a second path end of the second thin film transistor T12, the first path end and the control end of the twelfth thin film transistor T12 are connected to the first clock signal XCK and the second path end is connected
  • a first end and a second capacitor first terminal of the eighth thin film transistor T8 C2, the second terminal of the second capacitor C2 is connected to the second constant voltage VGH2.
  • the first constant voltage VGH1 and the second constant voltage VGH2 are equal in magnitude.
  • the first constant voltage VGH1 is greater than the second constant voltage VGH2.
  • the first to twelfth thin film transistors T1 to T12 are all P-type thin film transistors.
  • the control terminals of the first to twelfth thin film transistors T1 to T12 are all gate electrodes.
  • the present invention provides a forward-reverse scanning module including a first thin film transistor T1 and a second thin film transistor T2, and the two path ends of the first thin film transistor T1 are respectively connected.
  • a clock signal XCK and a first node Qn the two path ends of the second thin film transistor T2 are respectively connected to the second clock signal CK and the first node Qn, and the control end of the first thin film transistor T1 is connected to the stage of the upper level GOA circuit unit
  • the signal STn-1 is transmitted, and the control end of the second thin film transistor T2 is connected to the level signal STn+1 of the next-stage GOA circuit unit, thereby reducing the number of signal lines and thin film transistors required for the GOA scanning circuit, and facilitating the narrow frame design. .
  • FIG. 1 is a circuit diagram of an nth stage scanning circuit unit of a GOA scanning circuit in accordance with a preferred embodiment of the present invention
  • FIG. 2 is a schematic structural view of an embodiment of a GOA scanning circuit of the present invention.
  • 3 is a timing diagram of each signal line when the GOA scanning circuit operates
  • Figure 4 is a schematic view of a liquid crystal display device of the present invention.
  • the GOA scanning circuit includes a plurality of cascaded GOA circuit units, the nth stage (N ⁇ n ⁇ 1, and n is a positive integer).
  • the GOA circuit unit includes: a forward/reverse scanning module 10 and an output module 11
  • the forward and reverse scan module 10 includes a first thin film transistor T1 and a second thin film transistor T2. The two path ends of the first thin film transistor T1 are respectively connected to the first clock signal XCK and the first node Qn, and the two second thin film transistors T2.
  • Each of the path ends is connected to the second clock signal CK and the first node Qn, the control end of the first thin film transistor T1 is connected to the level signal STn-1 of the upper level GOA circuit unit, and the control end of the second thin film transistor T2 is connected to the next end.
  • the level signal STn+1 of the stage GOA circuit unit wherein the control terminal of the first thin film transistor T1 in the first stage GOA circuit unit is connected to the forward scan trigger signal STV1, and the second thin film transistor in the Nth stage GOA circuit unit
  • the control terminal of T2 is connected to the reverse scan trigger signal STV2
  • the output module is connected to the first node Qn and is used for outputting the level signal STn of the GOA circuit unit of the present stage and the scan of the output GOA circuit unit according to the potential of the first node Qn.
  • Signal G n
  • the scanning signals G1 to GN are sequentially supplied to the corresponding pixel units in the order of the first to the Nth stage GOA circuit units, and the order from the Nth to the first level GOA circuit units in the reverse scanning.
  • the scan signals GN ⁇ G1 are sequentially supplied to the corresponding pixel units.
  • the output module 11 includes a third thin film transistor T3, a fourth thin film transistor T4, and a first capacitor C1.
  • the control terminals of the third thin film transistor T3 and the fourth thin film transistor T4 are connected to the first node Qn, and the third thin film transistor T3.
  • the first path end is connected to the second clock signal CK
  • the second path end of the third thin film transistor T3 is for outputting the level signal STn of the GOA circuit unit of the present stage
  • the first path end of the fourth thin film transistor T4 is connected to the second clock
  • the signal CK, the second path end of the fourth thin film transistor T4 is used for outputting the scan signal Gn of the GOA circuit unit of the current stage, and the two ends of the first capacitor C1 are respectively connected to the second path end of the first node Qn and the third thin film transistor T3. .
  • the nth stage GOA circuit unit further includes a pull-down maintaining module 12, and the pull-down maintaining module 12 includes a fifth thin film transistor T5, a sixth thin film transistor T6, and a seventh thin film transistor T7, a fifth thin film transistor T5, and a sixth thin film transistor T6.
  • the control terminal of the seventh thin film transistor T7 is connected to the second node Pn.
  • the two path ends of the fifth thin film transistor T5 are respectively connected to the second path end of the third thin film transistor T3 and the first constant voltage VGH1, and the sixth thin film transistor T6.
  • the two path ends are respectively connected to the second path end of the fourth thin film transistor T4 and the first constant voltage VGH1, and the two path ends of the seventh thin film transistor T7 are respectively connected to the first node Qn and the second constant voltage VGH2.
  • the nth stage GOA circuit unit further includes a pull-down module 13, the pull-down module 13 includes an eighth thin film transistor T8 and a ninth thin film transistor T9, and the second pass end of the eighth thin film transistor T8 is connected to the second constant voltage VGH2, the eighth The control terminal of the NMOS transistor T9 is connected to the second node Pn and the second constant voltage VGH2, and the control terminal of the ninth thin film transistor T9 is connected to the first node Qn;
  • the stage GOA circuit unit further includes a tenth thin film transistor T10, an eleventh thin film transistor T11, a twelfth thin film transistor T12, and a second capacitor C2.
  • the first path end of the tenth thin film transistor T10 is connected to the second clock signal CK and the first The second path end is connected to the first path end of the eleventh thin film transistor T11, the second path end of the eleventh thin film transistor T11 is connected to the second node Pn and the control end thereof is connected to the second clock signal CK, and the tenth thin film transistor T10 is controlled.
  • the terminal is connected to the second path end of the twelfth thin film transistor T12, and the first path end and the control end of the twelfth thin film transistor T12 are connected to the first clock signal XCK and the second pass thereof
  • the circuit end is connected to the first end of the second capacitor C2 and the first path end of the eighth thin film transistor T8, and the second end of the second capacitor C2 is connected to the second constant voltage VGH2.
  • the first constant voltage VGH1 and the second constant voltage VGH2 are equal in magnitude, and the first constant voltage VGH1 and the second constant voltage VGH2 may be connected to the same signal line VGH.
  • the first constant voltage VGH1 may be greater than the second constant voltage VGH2 to maintain a voltage difference Vgs>0 between the drain and the source of the first thin film transistor T1 during non-output, thereby reducing leakage.
  • the first to twelfth thin film transistors T1 to T12 are all P-type thin film transistors.
  • control terminals of the first to twelfth thin film transistors T1 to T12 are both gate electrodes.
  • the drain of the first thin film transistor T1 is connected to the first clock signal XCK and the source is connected to the first node Qn
  • the drain of the second thin film transistor T2 is connected to the second clock signal CK and the source is connected to the first node Qn
  • the first path end of the third thin film transistor T3 is a drain and the second path end thereof is a source
  • the first path end of the fourth thin film transistor T4 is a drain and the second path end thereof is a source
  • the fifth thin film transistor The drain of T5 is connected to the second path end of the third thin film transistor T3, the source of the fifth thin film transistor T5 is connected to the first constant voltage VGH1, and the drain of the sixth thin film transistor T6 is connected to the second path end of the fourth thin film transistor T4.
  • the source of the sixth thin film transistor T6 is connected to the first constant voltage VGH1
  • the drain of the seventh thin film transistor T7 is connected to the first node Qn and the source thereof is connected to the second constant voltage VGH2
  • the first pass end of the eighth thin film transistor T8 Is the drain and the second pass end is its source
  • the drain of the ninth thin film transistor T9 is connected to the second node Pn
  • the source of the ninth thin film transistor T9 is connected to the second constant voltage VGH2
  • the tenth thin film transistor T10 One channel end is leaky And the second path end of the eleventh thin film transistor T11 is a drain and the second path end of the eleventh thin film transistor T11 is a source thereof, and the first path end of the eleventh thin film transistor T11 is a drain And its second path end is its source.
  • the first clock signal XCK is inverted from the second clock signal CK.
  • the first stage when the forward scan is performed, the forward scan trigger signal STV1 turns on the first thin film transistor T1, and at this time, the potential of the first clock signal XCK connected to the drain of the first thin film transistor T1 of the first stage GOA circuit unit is Is low.
  • the first thin film transistor T1 is turned on, the second thin film transistor T2 is turned off, the first clock signal XCK is pulled low to the first node Q1 to the low potential, and the third thin film transistor T3 and the fourth thin film transistor T4 are turned on;
  • the first stage GOA circuit unit is The step signal ST1 and the scan signal G1 of the first stage GOA circuit unit both output a high potential, the eighth thin film transistor T8 and the ninth thin film transistor T9 are turned on, the second node P1 is raised in potential, and the seventh thin film transistor T7, fifth The thin film transistor T5 and the sixth thin film transistor T6 are turned off, and the first node Q1 point is kept at a low potential.
  • the second stage due to the high potential of ST1 and G1 in the first stage, the Q1 point is coupled to the lower potential through the capacitor C1, and the third thin film transistor T3 and the fourth thin film transistor T4 have a larger on-state current, and the second The clock signal CK is low in the second phase, so G1 outputs a low potential, driving the corresponding pixel unit (the low potential of the G1 output causes the thin film transistor in the pixel unit to be turned on and the data line to charge the liquid crystal capacitor in the pixel unit), and The second clock signal CK is low in the second phase so that ST1 outputs a low potential, while ST1 turns on the first thin film transistor T1 of the second-stage GOA circuit unit, and the first clock signal XCK passes through the first thin film transistor of the second-stage GOA circuit unit.
  • T1 charges the first node Q2 of the second stage.
  • the Q2 point of the second-stage GOA circuit unit is pulled low to drive the second-stage GOA circuit unit, and the principle is consistent with the above process.
  • the third stage: ST2 turns on the second thin film transistor T2 of the first stage GOA unit. Since the second clock signal CK is at a high potential in the third stage, the first node Q1 is raised in potential, and the third thin film transistor T3 and the fourth thin film transistor are T4 is turned off, and the fifth thin film transistor T5, the sixth thin film transistor T6, and the seventh thin film transistor T7 are turned on.
  • the fourth stage the second clock signal CK charges the second node P1 through the tenth thin film transistor T10 and the eleventh thin film transistor T11, and the second node P1 remains at a low potential for the remaining time of one frame, and the fifth thin film transistor T5, The sixth thin film transistor T6 and the seventh thin film transistor T7 are turned on to keep the Q1 point and the G1 point high (the high potential of the G1 output causes the thin film transistor in the pixel unit to be turned off, and the liquid crystal capacitor maintains the potential of the pixel electrode), corresponding pixel unit The potential is maintained.
  • ST2 drives the second-level GOA circuit unit, which is similar to the above process, and will not be described here.
  • the analogy STn drives the n+1th stage GOA circuit unit, similarly to the above process, and is passed to the Nth stage GOA circuit unit step by step.
  • STV2 first turns on T2 of the Nth stage GOA circuit unit, and at this time, the second clock signal CK connected to the drain of T2 is low, and the QN point is low, and the third thin film transistor T3 is turned on.
  • the fourth thin film transistor T4. The process is similar to the above process, and the details are not described herein.
  • the STN drives the N-1th GOA circuit unit, and the STN-1 drives the N-2th GOA circuit unit until it is passed to the level 1 GOA circuit unit.
  • FIG. 2 is a schematic structural diagram of an embodiment of a GOA scanning circuit of the present invention.
  • the first constant voltage VGH1 and the second constant voltage VGH2 are equal in magnitude and are supplied from the same signal line VGH. Since the forward and reverse scan module includes the first thin film transistor T1 and the second thin film transistor T2, the two path ends of the first thin film transistor T1 are respectively connected to the first clock signal XCK and the first node Qn, and two of the second thin film transistors T2.
  • the path end is connected to the second clock signal CK and the first node Qn, respectively, the control end of the first thin film transistor T1 is connected to the level signal STn-1 of the upper level GOA circuit unit, and the control end of the second thin film transistor T2 is connected to the next stage.
  • the level of the GOA circuit unit transmits a signal STn+1, so that forward and reverse scanning can be realized only by a set of clock signals, the first clock signal XCK and the second clock signal CK, and the forward scan trigger signal STV1 and the reverse scan trigger signal STV2.
  • the specific function please refer to the principle description of the GOA scanning circuit described above.
  • the GOA scanning circuit Compared with the existing forward-reverse scanning function, the GOA scanning circuit requires two sets of clock signals, and the signal line can be reduced, and the GOA scanning circuit realized by this method uses the number of thin film transistors compared with the existing one. There are fewer GOA scanning circuits for forward and reverse scanning functions. As shown in FIG. 2, the signal lines used by the GOA scanning circuit include a forward scan trigger signal STV1, a reverse scan trigger signal STV2, a first clock signal XCK, and a second clock signal CK, and fewer signal lines are required.
  • FIG. 3 is a timing diagram of each signal line when the GOA scanning circuit operates.
  • the first clock signal XCK is inverted from the second clock signal CK, that is, the potentials are opposite at any time.
  • the forward scan is triggered when the forward scan trigger signal STV1 is low, and the reverse scan is triggered when the direction scan signal STV2 is low.
  • the first-stage GOA circuit unit and the second-stage GOA circuit unit are still described as an example of forward scanning. As shown in FIG.
  • the forward scanning trigger signal STV1 is at a low potential
  • the first clock signal XCK is at a low potential
  • the second clock signal CK is at a high potential.
  • a node Q1 is low, G1 is high, G2 is high
  • the first clock signal XCK is high
  • the second clock signal CK is low
  • the first node Q1 is at the first
  • the first clock signal XCK is low, the second clock signal CK is high
  • the first node Q1 is high
  • G1 is The high potential, G2 is low
  • the fourth stage the first clock signal XCK is high, the second clock signal CK is low, and the first nodes Q1 and G1 are high.
  • STV2 first turns on T2 of the Nth stage GOA circuit unit, and at this time, the second clock signal CK connected to the drain of T2 is low, and the QN point is low, and the third thin film transistor T3 is turned on.
  • the fourth thin film transistor T4. The process is similar to the above process, and will not be described here.
  • STN drives the N-1th GOA circuit unit, and STN-1 drives the N-2th GOA circuit unit until it is passed to the first level GOA circuit unit.
  • the clock is flipped, there is a GOA circuit unit that outputs Gn low.
  • FIG. 4 is a schematic diagram of a liquid crystal display device of the present invention.
  • the liquid crystal display device includes a liquid crystal panel 1 and a GOA scanning circuit 2 on the side of the liquid crystal panel 1, wherein the GOA scanning circuit 2 is the GOA scanning circuit described in any of the above embodiments.
  • the present invention includes a first thin film transistor T1 and a second thin film transistor T2 by providing a forward and reverse scan module.
  • the two path ends of the first thin film transistor T1 are respectively connected to the first clock signal XCK and the first The node Qn
  • the two path ends of the second thin film transistor T2 are respectively connected to the second clock signal CK and the first node Qn
  • the control end of the first thin film transistor T1 is connected to the level signal STn-1 of the upper level GOA circuit unit
  • the control terminal of the second thin film transistor T2 is connected to the level transmission signal STn+1 of the next-stage GOA circuit unit, thereby reducing the number of signal lines and thin film transistors required for the GOA scanning circuit, and facilitating the narrow bezel design.

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Abstract

一种液晶显示装置及其GOA扫描电路，GOA扫描电路包括级联的多个GOA电路单元，第n级GOA电路单元包括：正反向扫描模块（10）和输出模块（11），正反向扫描模块（10）包括第一薄膜晶体管（T1）和第二薄膜晶体管（T2），第一薄膜晶体管（T1）的两个通路端分别连接第一时钟信号（XCK）和第一节点（Qn），第二薄膜晶体管（T2）的两个通路端分别连接第二时钟信号（CK）和第一节点（Qn），第一薄膜晶体管（T1）的控制端连接上一级GOA电路单元的级传信号（STn-1），第二薄膜晶体管（T2）的控制端连接下一级GOA电路单元的级传信号（STn+1）。

Description

液晶显示装置及其GOA扫描电路
【技术领域】
本发明涉及显示技术领域，特别是涉及一种液晶显示装置及其GOA扫描电路。
【背景技术】
液晶显示器(Liquid Crystal Display，LCD)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。如：液晶电视、移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕等，在平板显示领域中占主导地位。
现有市场上的液晶显示器大部分为背光型液晶显示器，其包括液晶显示面板及背光模组(backlight module)。液晶显示面板的工作原理是在薄膜晶体管阵列基板(Thin Film Transistor Array Substrate，TFT Array Substrate)与彩色滤光片基板(Color Filter，CF)之间灌入液晶分子，并在两片基板上施加驱动电压来控制液晶分子的旋转方向，以将背光模组的光线折射出来产生画面。
主动式液晶显示器中，每个像素电性连接一个薄膜晶体管(TFT)，薄膜晶体管的栅极(Gate)连接至水平扫描线，漏极(Drain)连接至垂直方向的数据线，源极(Source)则连接至像素电极。在水平扫描线上施加足够的电压，会使得电性连接至该条水平扫描线上的所有TFT打开，从而数据线上的信号电压能够写入像素，控制不同液晶的透光度进而达到控制色彩与亮度的效果。目前主动式液晶显示面板水平扫描线的驱动主要由外接的集成电路板(Integrated Circuit，IC)来完成，外接的IC可以控制各级水平扫描线的逐级充电和放电。而GOA技术(Gate Driver on Array)即阵列基板行驱动技术，可以运用液晶显示面板的原有阵列制程将水平扫描线的驱动电路制作在显示区周围的基板上，使之能替代外接IC来完成水平扫描线的驱动。GOA技术能减少外接IC的焊接(bonding)工序，有机会提升产能并降低产品成本，而且可以使液晶显示面板更适合制作窄边框或无边框的显示产品。
通常GOA电路包括以下几种：基于P型薄膜晶体管的GOA电路、基于CMOS的GOA电路、和基于N型薄膜晶体管的GOA电路，其中基于P型薄膜晶体管的GOA电路，尤其是以低温多晶硅(LTPS)为材料的基于P型薄膜晶体管的GOA电路具有工艺较为简单、漏电较低的特点，发展前景良好。但现有的具有双向扫描功能的GOA扫描电路需要的薄膜晶体管较多，且使用的信号线较多，导致非有效显示区占用较多，不利于窄边框或者无边框设计。
【发明内容】
本发明主要解决的技术问题是提供一种液晶显示装置及其GOA扫描电路，能够实现双向扫描功能，同时所需的薄膜晶体管和信号线较少。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种GOA扫描电路，其中，GOA扫描电路包括级联的多个GOA电路单元，第n级（N≥n≥1，且n为正整数）GOA电路单元包括：正反向扫描模块，正反向扫描模块包括第一薄膜晶体管T1和第二薄膜晶体管T2，第一薄膜晶体管T1的两个通路端分别连接第一时钟信号XCK和第一节点Qn，第二薄膜晶体管T2的两个通路端分别连接第二时钟信号CK和第一节点Qn，第一薄膜晶体管T1的控制端连接上一级GOA电路单元的级传信号STn-1，第二薄膜晶体管T2的控制端连接下一级GOA电路单元的级传信号STn+1，其中，第1级GOA电路单元中的第一薄膜晶体管T1的控制端连接正向扫描触发信号STV1，第N级GOA电路单元中的第二薄膜晶体管T2的控制端连接反向扫描触发信号STV2；输出模块，输出模块与第一节点Qn连接且用于根据第一节点Qn的电位输出本级GOA电路单元的级传信号STn和输出本级GOA电路单元的扫描信号Gn；输出模块包括第三薄膜晶体管T3、第四薄膜晶体管T4以及第一电容C1，第三薄膜晶体管T3和第四薄膜晶体管T4的控制端均连接第一节点Qn，第三薄膜晶体管T3的第一通路端连接第二时钟信号CK，第三薄膜晶体管T3的第二通路端用于输出本级GOA电路单元的级传信号STn，第四薄膜晶体管T4的第一通路端连接第二时钟信号CK，第四薄膜晶体管T4的第二通路端用于输出本级GOA电路单元的扫描信号Gn，第一电容C1的两端分别连接第一节点Qn和第三薄膜晶体管T3的第二通路端；第一时钟信号XCK与第二时钟信号CK反相。
其中，第n级GOA电路单元进一步包括下拉维持模块，下拉维持模块包括第五薄膜晶体管T5、第六薄膜晶体管T6以及第七薄膜晶体管T7，第五薄膜晶体管T5、第六薄膜晶体管T6以及第七薄膜晶体管T7的控制端均连接第二节点Pn，第五薄膜晶体管T5的两个通路端分别连接第三薄膜晶体管T3的第二通路端和第一恒定电压VGH1，第六薄膜晶体管T6的两通路端分别连接第四薄膜晶体管T4的第二通路端和第一恒定电压VGH1，第七薄膜晶体管T7的两个通路端分别连接第一节点Qn和第二恒定电压VGH2。
其中，第n级GOA电路单元进一步包括下拉模块，下拉模块包括第八薄膜晶体管T8和第九薄膜晶体管T9，第八薄膜晶体管T8的第二通路端连接第二恒定电压，第八薄膜晶体管T8的控制端连接第一节点Qn，第九薄膜晶体管T9的两通路端分别连接第二节点Pn和第二恒定电压VGH2，第九薄膜晶体管T9的控制端连接第一节点Qn；第n级GOA电路单元还包括第十薄膜晶体管T10、第十一薄膜晶体管T11、第十二薄膜晶体管T12以及第二电容C2，第十薄膜晶体管T10的第一通路端连接第二时钟信号CK且其第二通路端连接第十一薄膜晶体管T11的第一通路端，第十一薄膜晶体管T11的第二通路端连接第二节点Pn且其控制端连接第二时钟信号CK，第十薄膜晶体管T10的控制端连接第十二薄膜晶体管T12的第二通路端，第十二薄膜晶体管T12的第一通路端和控制端均连接第一时钟信号XCK且其第二通路端连接第二电容C2的第一端以及第八薄膜晶体管T8的第一通路端，第二电容C2的第二端连接第二恒定电压VGH2。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种GOA扫描电路，GOA扫描电路包括级联的多个GOA电路单元，第n级（N≥n≥1，且n为正整数）GOA电路单元包括：正反向扫描模块和输出模块，正反向扫描模块包括第一薄膜晶体管T1和第二薄膜晶体管T2，第一薄膜晶体管T1的两个通路端分别连接第一时钟信号XCK和第一节点Qn，第二薄膜晶体管T2的两个通路端分别连接第二时钟信号CK和第一节点Qn，第一薄膜晶体管T1的控制端连接上一级GOA电路单元的级传信号STn-1，第二薄膜晶体管T2的控制端连接下一级GOA电路单元的级传信号STn+1，其中，第1级GOA电路单元中的第一薄膜晶体管T1的控制端连接正向扫描触发信号STV1，第N级GOA电路单元中的第二薄膜晶体管T2的控制端连接反向扫描触发信号STV2；输出模块与第一节点Qn连接且用于根据第一节点Qn的电位输出本级GOA电路单元的级传信号STn和输出本级GOA电路单元的扫描信号Gn。
其中，输出模块包括第三薄膜晶体管T3、第四薄膜晶体管T4以及第一电容C1，第三薄膜晶体管T3和第四薄膜晶体管T4的控制端均连接第一节点Qn，第三薄膜晶体管T3的第一通路端连接第二时钟信号CK，第三薄膜晶体管T3的第二通路端用于输出本级GOA电路单元的级传信号STn，第四薄膜晶体管T4的第一通路端连接第二时钟信号CK，第四薄膜晶体管T4的第二通路端用于输出本级GOA电路单元的扫描信号Gn，第一电容C1的两端分别连接第一节点Qn和第三薄膜晶体管T3的第二通路端。
其中，第n级GOA电路单元进一步包括下拉维持模块，下拉维持模块包括第五薄膜晶体管T5、第六薄膜晶体管T6以及第七薄膜晶体管T7，第五薄膜晶体管T5、第六薄膜晶体管T6以及第七薄膜晶体管T7的控制端均连接第二节点Pn，第五薄膜晶体管T5的两个通路端分别连接第三薄膜晶体管T3的第二通路端和第一恒定电压VGH1，第六薄膜晶体管T6的两通路端分别连接第四薄膜晶体管T4的第二通路端和第一恒定电压VGH1，第七薄膜晶体管T7的两个通路端分别连接第一节点Qn和第二恒定电压VGH2。
其中，第n级GOA电路单元进一步包括下拉模块，下拉模块包括第八薄膜晶体管T8和第九薄膜晶体管T9，第八薄膜晶体管T8的第二通路端连接第二恒定电压VGH2，第八薄膜晶体管T8的控制端连接第一节点Qn，第九薄膜晶体管T9的两通路端分别连接第二节点Pn和第二恒定电压，第九薄膜晶体管T9的控制端连接第一节点Qn；第n级GOA电路单元还包括第十薄膜晶体管T10、第十一薄膜晶体管T11、第十二薄膜晶体管T12以及第二电容C2，第十薄膜晶体管T10的第一通路端连接第二时钟信号CK且其第二通路端连接第十一薄膜晶体管T11的第一通路端，第十一薄膜晶体管T11的第二通路端连接第二节点Pn且其控制端连接第二时钟信号CK，第十薄膜晶体管T10的控制端连接第十二薄膜晶体管T12的第二通路端，第十二薄膜晶体管T12的第一通路端和控制端均连接第一时钟信号XCK且其第二通路端连接第二电容C2的第一端以及第八薄膜晶体管T8的第一通路端，第二电容C2的第二端连接第二恒定电压VGH2。
其中，第一恒定电压VGH1和第二恒定电压VGH2的大小相等。
其中，第一恒定电压VGH1大于第二恒定电压VGH2。
其中，第一至第十二薄膜晶体管T1~T12均为P型薄膜晶体管。
其中，第一至第十二薄膜晶体管T1~T12的控制端均为栅极。
其中，第一薄膜晶体管T1的漏极连接第一时钟信号XCK且源极连接第一节点Qn，第二薄膜晶体管T2的漏极连接第二时钟信号CK和且源极连接第一节点Qn，第三薄膜晶体管T3的第一通路端为漏极且其第二通路端为源极，第四薄膜晶体管T4的第一通路端为漏极且其第二通路端为源极，第五薄膜晶体管T5的漏极连接第三薄膜晶体管T3的第二通路端，第五薄膜晶体管T5的源极连接第一恒定电压，第六薄膜晶体管T6的漏极连接第四薄膜晶体管T4的第二通路端，第六薄膜晶体管T6的源极连接第一恒定电压VGH1，第七薄膜晶体管T7的漏极连接第一节点Qn且其源极连接第二恒定电压VGH2，第八薄膜晶体管T8的第一通路端为漏极且其第二通路端为其源极，第九薄膜晶体管T9的漏极连接第二节点Pn，第九薄膜晶体管T9的源极连接第二恒定电压VGH2，第十薄膜晶体管T10的第一通路端为漏极且其第二通路端为其源极，第十一薄膜晶体管T11的第一通路端为漏极且其第二通路端为其源极，第十一薄膜晶体管T11的第一通路端为漏极且其第二通路端为其源极。
为解决上述技术问题，本发明采用的又一个技术方案是：提供一种液晶显示装置包括GOA扫描电路，GOA扫描电路包括级联的多个GOA电路单元，第n级（N≥n≥1，且n为正整数）GOA电路单元包括：正反向扫描模块和输出模块，正反向扫描模块包括第一薄膜晶体管T1和第二薄膜晶体管T2，第一薄膜晶体管T1的两个通路端分别连接第一时钟信号XCK和第一节点Qn，第二薄膜晶体管T2的两个通路端分别连接第二时钟信号CK和第一节点Qn，第一薄膜晶体管T1的控制端连接上一级GOA电路单元的级传信号STn-1，第二薄膜晶体管T2的控制端连接下一级GOA电路单元的级传信号STn+1，其中，第1级GOA电路单元中的第一薄膜晶体管T1的控制端连接正向扫描触发信号STV1，第N级GOA电路单元中的第二薄膜晶体管T2的控制端连接反向扫描触发信号STV2；输出模块与第一节点Qn连接且用于根据第一节点Qn的电位输出本级GOA电路单元的级传信号STn和输出本级GOA电路单元的扫描信号Gn。
其中，输出模块包括第三薄膜晶体管T3、第四薄膜晶体管T4以及第一电容C1，第三薄膜晶体管T3和第四薄膜晶体管T4的控制端均连接第一节点Qn，第三薄膜晶体管T3的第一通路端连接第二时钟信号CK，第三薄膜晶体管T3的第二通路端用于输出本级GOA电路单元的级传信号STn，第四薄膜晶体管T4的第一通路端连接第二时钟信号CK，第四薄膜晶体管T4的第二通路端用于输出本级GOA电路单元的扫描信号Gn，第一电容C1的两端分别连接第一节点Qn和第三薄膜晶体管T3的第二通路端。
其中，第n级GOA电路单元进一步包括下拉维持模块，下拉维持模块包括第五薄膜晶体管T5、第六薄膜晶体管T6以及第七薄膜晶体管T7，第五薄膜晶体管T5、第六薄膜晶体管T6以及第七薄膜晶体管T7的控制端均连接第二节点Pn，第五薄膜晶体管T5的两个通路端分别连接第三薄膜晶体管T3的第二通路端和第一恒定电压VGH1，第六薄膜晶体管T6的两通路端分别连接第四薄膜晶体管T4的第二通路端和第一恒定电压VGH1，第七薄膜晶体管T7的两个通路端分别连接第一节点Qn和第二恒定电压VGH2。
其中，第n级GOA电路单元进一步包括下拉模块，下拉模块包括第八薄膜晶体管T8和第九薄膜晶体管T9，第八薄膜晶体管T8的第二通路端连接第二恒定电压VGH2，第八薄膜晶体管T8的控制端连接第一节点Qn，第九薄膜晶体管T9的两通路端分别连接第二节点Pn和第二恒定电压，第九薄膜晶体管T9的控制端连接第一节点Qn；第n级GOA电路单元还包括第十薄膜晶体管T10、第十一薄膜晶体管T11、第十二薄膜晶体管T12以及第二电容C2，第十薄膜晶体管T10的第一通路端连接第二时钟信号CK且其第二通路端连接第十一薄膜晶体管T11的第一通路端，第十一薄膜晶体管T11的第二通路端连接第二节点Pn且其控制端连接第二时钟信号CK，第十薄膜晶体管T10的控制端连接第十二薄膜晶体管T12的第二通路端，第十二薄膜晶体管T12的第一通路端和控制端均连接第一时钟信号XCK且其第二通路端连接第二电容C2的第一端以及第八薄膜晶体管T8的第一通路端，第二电容C2的第二端连接第二恒定电压VGH2。
其中，第一恒定电压VGH1和第二恒定电压VGH2的大小相等。
其中，第一恒定电压VGH1大于第二恒定电压VGH2。
其中，第一至第十二薄膜晶体管T1~T12均为P型薄膜晶体管。
其中，第一至第十二薄膜晶体管T1~T12的控制端均为栅极。
本发明的有益效果是：区别于现有技术的情况，本发明通过设置正反向扫描模块包括第一薄膜晶体管T1和第二薄膜晶体管T2，第一薄膜晶体管T1的两个通路端分别连接第一时钟信号XCK和第一节点Qn，第二薄膜晶体管T2的两个通路端分别连接第二时钟信号CK和第一节点Qn，第一薄膜晶体管T1的控制端连接上一级GOA电路单元的级传信号STn-1，第二薄膜晶体管T2的控制端连接下一级GOA电路单元的级传信号STn+1，从而能够减少GOA扫描电路所需的信号线和薄膜晶体管的数量，利于窄边框设计。
【附图说明】
图1是本发明优选实施例的GOA扫描电路的第n级扫描电路单元的电路示意图；
图2是本发明GOA扫描电路的实施例的结构示意图；
图3是GOA扫描电路工作时各信号线的时序图；
图4是本发明液晶显示装置的示意图。
【具体实施方式】
下面结合附图和实施例对本发明进行详细的说明。
参阅图1，图1是本发明优选实施例的GOA扫描电路的第n级扫描电路单元的电路示意图。在本实施例中，GOA扫描电路包括级联的多个GOA电路单元，第n级（N≥n≥1，且n为正整数）GOA电路单元包括：正反向扫描模块10和输出模块11，正反向扫描模块10包括第一薄膜晶体管T1和第二薄膜晶体管T2，第一薄膜晶体管T1的两个通路端分别连接第一时钟信号XCK和第一节点Qn，第二薄膜晶体管T2的两个通路端分别连接第二时钟信号CK和第一节点Qn，第一薄膜晶体管T1的控制端连接上一级GOA电路单元的级传信号STn-1，第二薄膜晶体管T2的控制端连接下一级GOA电路单元的级传信号STn+1，其中，第1级GOA电路单元中的第一薄膜晶体管T1的控制端连接正向扫描触发信号STV1，第N级GOA电路单元中的第二薄膜晶体管T2的控制端连接反向扫描触发信号STV2；输出模块与第一节点Qn连接且用于根据第一节点Qn的电位输出本级GOA电路单元的级传信号STn和输出本级GOA电路单元的扫描信号Gn。在正向扫描时，从第1级到第N级GOA电路单元的顺序依次向对应的像素单元提供扫描信号G1~GN，反向扫描时，从第N级到第1级GOA电路单元的顺序依次向对应的像素单元提供扫描信号GN~G1。
优选地，输出模块11包括第三薄膜晶体管T3、第四薄膜晶体管T4以及第一电容C1，第三薄膜晶体管T3和第四薄膜晶体管T4的控制端均连接第一节点Qn，第三薄膜晶体管T3的第一通路端连接第二时钟信号CK，第三薄膜晶体管T3的第二通路端用于输出本级GOA电路单元的级传信号STn，第四薄膜晶体管T4的第一通路端连接第二时钟信号CK，第四薄膜晶体管T4的第二通路端用于输出本级GOA电路单元的扫描信号Gn，第一电容C1的两端分别连接第一节点Qn和第三薄膜晶体管T3的第二通路端。
优选地，第n级GOA电路单元进一步包括下拉维持模块12，下拉维持模块12包括第五薄膜晶体管T5、第六薄膜晶体管T6以及第七薄膜晶体管T7，第五薄膜晶体管T5、第六薄膜晶体管T6以及第七薄膜晶体管T7的控制端均连接第二节点Pn，第五薄膜晶体管T5的两个通路端分别连接第三薄膜晶体管T3的第二通路端和第一恒定电压VGH1，第六薄膜晶体管T6的两通路端分别连接第四薄膜晶体管T4的第二通路端和第一恒定电压VGH1，第七薄膜晶体管T7的两个通路端分别连接第一节点Qn和第二恒定电压VGH2。
优选地，第n级GOA电路单元进一步包括下拉模块13，下拉模块13包括第八薄膜晶体管T8和第九薄膜晶体管T9，第八薄膜晶体管T8的第二通路端连接第二恒定电压VGH2，第八薄膜晶体管T8的控制端连接第一节点Qn，第九薄膜晶体管T9的两通路端分别连接第二节点Pn和第二恒定电压VGH2，第九薄膜晶体管T9的控制端连接第一节点Qn；第n级GOA电路单元还包括第十薄膜晶体管T10、第十一薄膜晶体管T11、第十二薄膜晶体管T12以及第二电容C2，第十薄膜晶体管T10的第一通路端连接第二时钟信号CK且其第二通路端连接第十一薄膜晶体管T11的第一通路端，第十一薄膜晶体管T11的第二通路端连接第二节点Pn且其控制端连接第二时钟信号CK，第十薄膜晶体管T10的控制端连接第十二薄膜晶体管T12的第二通路端，第十二薄膜晶体管T12的第一通路端和控制端均连接第一时钟信号XCK且其第二通路端连接第二电容C2的第一端以及第八薄膜晶体管T8的第一通路端，第二电容C2的第二端连接第二恒定电压VGH2。
优选地，第一恒定电压VGH1和第二恒定电压VGH2的大小相等，第一恒定电压VGH1和第二恒定电压VGH2可以是连接同一信号线VGH。在其他实施例中，第一恒定电压VGH1可以大于第二恒定电压VGH2，以保持在非输出期间第一薄膜晶体管T1的漏极与源极之间的压差Vgs>0，从而减小漏电。
优选地，第一至第十二薄膜晶体管T1~T12均为P型薄膜晶体管。
优选地，第一至第十二薄膜晶体管T1~T12的控制端均为栅极。
优选地，第一薄膜晶体管T1的漏极连接第一时钟信号XCK且源极连接第一节点Qn，第二薄膜晶体管T2的漏极连接第二时钟信号CK和且源极连接第一节点Qn，第三薄膜晶体管T3的第一通路端为漏极且其第二通路端为源极，第四薄膜晶体管T4的第一通路端为漏极且其第二通路端为源极，第五薄膜晶体管T5的漏极连接第三薄膜晶体管T3的第二通路端，第五薄膜晶体管T5的源极连接第一恒定电压VGH1，第六薄膜晶体管T6的漏极连接第四薄膜晶体管T4的第二通路端，第六薄膜晶体管T6的源极连接第一恒定电压VGH1，第七薄膜晶体管T7的漏极连接第一节点Qn且其源极连接第二恒定电压VGH2，第八薄膜晶体管T8的第一通路端为漏极且其第二通路端为其源极，第九薄膜晶体管T9的漏极连接第二节点Pn，第九薄膜晶体管T9的源极连接第二恒定电压VGH2，第十薄膜晶体管T10的第一通路端为漏极且其第二通路端为其源极，第十一薄膜晶体管T11的第一通路端为漏极且其第二通路端为其源极，第十一薄膜晶体管T11的第一通路端为漏极且其第二通路端为其源极。
优选地，第一时钟信号XCK与第二时钟信号CK反相。
下面结合上述实施例对本发明GOA扫描电路的原理进行说明。以第1级GOA电路单元和第2级GOA电路单元且为正向扫描时为例进行说明。
第一阶段：当其正向扫描时正向扫描触发信号STV1打开第一薄膜晶体管T1，此时第一级GOA电路单元的第一薄膜晶体管T1的漏极连接的第一时钟信号XCK所对应电位为低电位。第一薄膜晶体管T1打开，第二薄膜晶体管T2关闭，第一时钟信号XCK拉低第一节点Q1点到低电位，第三薄膜晶体管T3和第四薄膜晶体管T4打开；第1级GOA电路单元的级传信号ST1和第1级GOA电路单元的扫描信号G1均输出高电位，第八薄膜晶体管T8和第九薄膜晶体管T9打开，第二节点P1点电位抬高，第七薄膜晶体管T7、第五薄膜晶体管T5和第六薄膜晶体管T6关闭，第一节点Q1点保持低电位。
第二阶段：由于第一阶段中ST1和G1输出高电位，通过电容C1，Q1点耦合到更低电位，第三薄膜晶体管T3和第四薄膜晶体管T4有较大的开态电流，而第二时钟信号CK在第二阶段为低电位因此G1输出低电位，驱动对应的像素单元（G1输出的低电位使像素单元中的薄膜晶体管开启从而数据线为像素单元中的液晶电容充电），而第二时钟信号CK在第二阶段为低电位因此ST1输出低电位，同时ST1打开第2级GOA电路单元的第一薄膜晶体管T1，第一时钟信号XCK通过第2级GOA电路单元的第一薄膜晶体管T1对第2级的第一节点Q2点充电，下一阶段第一时钟信号XCK翻转时，第二级GOA电路单元的Q2点拉低，驱动第2级GOA电路单元，原理与上述过程一致。
第三阶段：ST2打开第1级GOA单元的第二薄膜晶体管T2，由于第三阶段第二时钟信号CK为高电位，第一节点Q1点电位抬高，第三薄膜晶体管T3和第四薄膜晶体管T4关闭，第五薄膜晶体管T5、第六薄膜晶体管T6和第七薄膜晶体管T7打开。
第四阶段：第二时钟信号CK通过第十薄膜晶体管T10和第十一薄膜晶体管T11对第二节点P1点充电，第二节点P1点在一帧剩余时间保持低电位，第五薄膜晶体管T5、第六薄膜晶体管T6和第七薄膜晶体管T7打开保持Q1点和G1点为高电位（G1输出的高电位使像素单元中的薄膜晶体管关闭，液晶电容使像素电极的电位得以保持），对应像素单元电位得以保持。
依次类推，ST2驱动第2级GOA电路单元，与上述过程类似，此处不再赘述。依次类推STn驱动第n+1级GOA电路单元，与上述过程类似，逐级传递至第N级GOA电路单元。
类似的，反向扫描的时STV2先打开第N级GOA电路单元的T2，此时T2的漏极接的第二时钟信号CK为低电位，QN点为低电位，打开第三薄膜晶体管T3和第四薄膜晶体管T4。具过程与上述过程类似，此处不再赘述，STN驱动第N-1级GOA电路单元，STN-1驱动第N-2级GOA电路单元，直至传递至第1级GOA电路单元。
请进一步参阅图2，图2是本发明GOA扫描电路的实施例的结构示意图。在本实施例中，第一恒定电压VGH1和第二恒定电压VGH2的大小相等，由同一信号线VGH提供。由于正反向扫描模块包括第一薄膜晶体管T1和第二薄膜晶体管T2，第一薄膜晶体管T1的两个通路端分别连接第一时钟信号XCK和第一节点Qn，第二薄膜晶体管T2的两个通路端分别连接第二时钟信号CK和第一节点Qn，第一薄膜晶体管T1的控制端连接上一级GOA电路单元的级传信号STn-1，第二薄膜晶体管T2的控制端连接下一级GOA电路单元的级传信号STn+1，从而仅通过一组时钟信号第一时钟信号XCK和第二时钟信号CK以及正向扫描触发信号STV1和反向扫描触发信号STV2即可以实现正反向扫描的功能，具体的原理请参见上文所述的GOA扫描电路的原理说明。相比现有的正反向扫描功能的GOA扫描电路需要两组时钟信号的情况，可以减少信号线，且通过这种方式实现的GOA扫描电路，其采用的薄膜晶体管数量相比现有的具有正反向扫描功能的GOA扫描电路的少。如图2所示，GOA扫描电路运用的信号线有正向扫描触发信号STV1、反向扫描触发信号STV2、第一时钟信号XCK以及第二时钟信号CK，需要的信号线较少。
请进一步参阅图3，图3是GOA扫描电路工作时各信号线的时序图。如图3所示，第一时钟信号XCK与第二时钟信号CK反相，即在任意时刻二者电位均相反。正向扫描触发信号STV1为低电位时触发正向扫描，方向扫描信号STV2为低电位时触发反向扫描。结合上文中所述的GOA扫描电路的原理，仍然以第1级GOA电路单元和第2级GOA电路单元且为正向扫描时为例进行说明。如图3所示在正向扫描时，如前所述，在第一阶段，正向扫描触发信号STV1为低电位，第一时钟信号XCK为低电位，第二时钟信号CK为高电位，第一节点Q1为低电位，G1为高电位，G2为高电位；在第二阶段，第一时钟信号XCK为高电位，第二时钟信号CK为低电位，第一节点Q1为比其在第一阶段时更低的电位，G1为低电位，G2为高电位；在第三阶段，第一时钟信号XCK为低电位，第二时钟信号CK为高电位，第一节点Q1为高电位，G1为高电位，G2为低电位；在第四阶段，第一时钟信号XCK为高电位，第二时钟信号CK为低电位，第一节点Q1和G1为高电位。其中，在第二阶段，如上文所述，ST1打开第2级GOA电路单元的第一薄膜晶体管T1，第一时钟信号XCK通过第2级GOA电路单元的第一薄膜晶体管T1对第2级的第一节点Q2点充电，下一阶段（即第三阶段）第一时钟信号XCK翻转时，第二级GOA电路单元的Q2点拉低，驱动第2级GOA电路单元，原理与上述过程一致。如图3所示依次从第1级到第N级GOA电路单元，在每次时钟翻转时均有一个GOA电路单元输出Gn为低电平。类似的，反向扫描的时STV2先打开第N级GOA电路单元的T2，此时T2的漏极接的第二时钟信号CK为低电位，QN点为低电位，打开第三薄膜晶体管T3和第四薄膜晶体管T4。具过程与上述过程类似，此处不再赘述，STN驱动第N-1级GOA电路单元，STN-1驱动第N-2级GOA电路单元，直至传递至第1级GOA电路单元，在每次时钟翻转时均有一个GOA电路单元输出Gn为低电平。
请进一步参阅图4，图4是本发明液晶显示装置的示意图。在本实施例中，液晶显示装置包括液晶面板1和位于液晶面板1一侧的GOA扫描电路2，其中该GOA扫描电路2为上述任一实施例所述的GOA扫描电路。
区别于现有技术的情况，本发明通过设置正反向扫描模块包括第一薄膜晶体管T1和第二薄膜晶体管T2，第一薄膜晶体管T1的两个通路端分别连接第一时钟信号XCK和第一节点Qn，第二薄膜晶体管T2的两个通路端分别连接第二时钟信号CK和第一节点Qn，第一薄膜晶体管T1的控制端连接上一级GOA电路单元的级传信号STn-1，第二薄膜晶体管T2的控制端连接下一级GOA电路单元的级传信号STn+1，从而能够减少GOA扫描电路所需的信号线和薄膜晶体管的数量，利于窄边框设计。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种GOA扫描电路，其中，所述GOA扫描电路包括级联的多个GOA电路单元，第n级（N≥n≥1，且n为正整数）所述GOA电路单元包括：
    正反向扫描模块，所述正反向扫描模块包括第一薄膜晶体管T1和第二薄膜晶体管T2，所述第一薄膜晶体管T1的两个通路端分别连接第一时钟信号XCK和第一节点Qn，所述第二薄膜晶体管T2的两个通路端分别连接第二时钟信号CK和所述第一节点Qn，所述第一薄膜晶体管T1的控制端连接上一级GOA电路单元的级传信号STn-1，所述第二薄膜晶体管T2的控制端连接下一级所述GOA电路单元的级传信号STn+1，其中，第1级所述GOA电路单元中的所述第一薄膜晶体管T1的控制端连接正向扫描触发信号STV1，第N级所述GOA电路单元中的所述第二薄膜晶体管T2的控制端连接反向扫描触发信号STV2；
    输出模块，所述输出模块与所述第一节点Qn连接且用于根据第一节点Qn的电位输出本级所述GOA电路单元的级传信号STn和输出本级所述GOA电路单元的扫描信号Gn；所述输出模块包括第三薄膜晶体管T3、第四薄膜晶体管T4以及第一电容C1，所述第三薄膜晶体管T3和第四薄膜晶体管T4的控制端均连接所述第一节点Qn，所述第三薄膜晶体管T3的第一通路端连接所述第二时钟信号CK，所述第三薄膜晶体管T3的第二通路端用于输出本级所述GOA电路单元的级传信号STn，所述第四薄膜晶体管T4的第一通路端连接所述第二时钟信号CK，所述第四薄膜晶体管T4的第二通路端用于输出本级所述GOA电路单元的扫描信号Gn，所述第一电容C1的两端分别连接所述第一节点Qn和所述第三薄膜晶体管T3的第二通路端；第一时钟信号XCK与第二时钟信号CK反相。
  2. 根据权利要求1所述的GOA扫描电路，其中，第n级所述GOA电路单元进一步包括下拉维持模块，所述下拉维持模块包括第五薄膜晶体管T5、第六薄膜晶体管T6以及第七薄膜晶体管T7，所述第五薄膜晶体管T5、所述第六薄膜晶体管T6以及所述第七薄膜晶体管T7的控制端均连接所述第二节点Pn，所述第五薄膜晶体管T5的两个通路端分别连接所述第三薄膜晶体管T3的第二通路端和第一恒定电压VGH1，所述第六薄膜晶体管T6的两通路端分别连接所述第四薄膜晶体管T4的第二通路端和所述第一恒定电压VGH1，所述第七薄膜晶体管T7的两个通路端分别连接所述第一节点Qn和第二恒定电压VGH2。
  3. 根据权利2所述的GOA扫描电路，其中，第n级所述GOA电路单元进一步包括下拉模块，所述下拉模块包括第八薄膜晶体管T8和第九薄膜晶体管T9，所述第八薄膜晶体管T8的第二通路端连接所述第二恒定电压，所述第八薄膜晶体管T8的控制端连接所述第一节点Qn，所述第九薄膜晶体管T9的两通路端分别连接所述第二节点Pn和所述第二恒定电压VGH2，所述第九薄膜晶体管T9的控制端连接所述第一节点Qn；第n级所述GOA电路单元还包括第十薄膜晶体管T10、第十一薄膜晶体管T11、第十二薄膜晶体管T12以及第二电容C2，所述第十薄膜晶体管T10的第一通路端连接所述第二时钟信号CK且其第二通路端连接所述第十一薄膜晶体管T11的第一通路端，所述第十一薄膜晶体管T11的第二通路端连接所述第二节点Pn且其控制端连接所述第二时钟信号CK，所述第十薄膜晶体管T10的控制端连接所述第十二薄膜晶体管T12的第二通路端，所述第十二薄膜晶体管T12的第一通路端和控制端均连接所述第一时钟信号XCK且其第二通路端连接所述第二电容C2的第一端以及所述第八薄膜晶体管T8的第一通路端，所述第二电容C2的第二端连接所述第二恒定电压VGH2。
  4. 一种GOA扫描电路，其中，所述GOA扫描电路包括级联的多个GOA电路单元，第n级（N≥n≥1，且n为正整数）所述GOA电路单元包括：
    正反向扫描模块，所述正反向扫描模块包括第一薄膜晶体管T1和第二薄膜晶体管T2，所述第一薄膜晶体管T1的两个通路端分别连接第一时钟信号XCK和第一节点Qn，所述第二薄膜晶体管T2的两个通路端分别连接第二时钟信号CK和所述第一节点Qn，所述第一薄膜晶体管T1的控制端连接上一级GOA电路单元的级传信号STn-1，所述第二薄膜晶体管T2的控制端连接下一级所述GOA电路单元的级传信号STn+1，其中，第1级所述GOA电路单元中的所述第一薄膜晶体管T1的控制端连接正向扫描触发信号STV1，第N级所述GOA电路单元中的所述第二薄膜晶体管T2的控制端连接反向扫描触发信号STV2；
    输出模块，所述输出模块与所述第一节点Qn连接且用于根据第一节点Qn的电位输出本级所述GOA电路单元的级传信号STn和输出本级所述GOA电路单元的扫描信号Gn。
  5. 根据权利要求4所述的GOA扫描电路，其中，所述输出模块包括第三薄膜晶体管T3、第四薄膜晶体管T4以及第一电容C1，所述第三薄膜晶体管T3和第四薄膜晶体管T4的控制端均连接所述第一节点Qn，所述第三薄膜晶体管T3的第一通路端连接所述第二时钟信号CK，所述第三薄膜晶体管T3的第二通路端用于输出本级所述GOA电路单元的级传信号STn，所述第四薄膜晶体管T4的第一通路端连接所述第二时钟信号CK，所述第四薄膜晶体管T4的第二通路端用于输出本级所述GOA电路单元的扫描信号Gn，所述第一电容C1的两端分别连接所述第一节点Qn和所述第三薄膜晶体管T3的第二通路端。
  6. 根据权利要求5所述的GOA扫描电路，其中，第n级所述GOA电路单元进一步包括下拉维持模块，所述下拉维持模块包括第五薄膜晶体管T5、第六薄膜晶体管T6以及第七薄膜晶体管T7，所述第五薄膜晶体管T5、所述第六薄膜晶体管T6以及所述第七薄膜晶体管T7的控制端均连接所述第二节点Pn，所述第五薄膜晶体管T5的两个通路端分别连接所述第三薄膜晶体管T3的第二通路端和第一恒定电压VGH1，所述第六薄膜晶体管T6的两通路端分别连接所述第四薄膜晶体管T4的第二通路端和所述第一恒定电压VGH1，所述第七薄膜晶体管T7的两个通路端分别连接所述第一节点Qn和第二恒定电压VGH2。
  7. 根据权利6所述的GOA扫描电路，其中，第n级所述GOA电路单元进一步包括下拉模块，所述下拉模块包括第八薄膜晶体管T8和第九薄膜晶体管T9，所述第八薄膜晶体管T8的第二通路端连接所述第二恒定电压，所述第八薄膜晶体管T8的控制端连接所述第一节点Qn，所述第九薄膜晶体管T9的两通路端分别连接所述第二节点Pn和所述第二恒定电压VGH2，所述第九薄膜晶体管T9的控制端连接所述第一节点Qn；第n级所述GOA电路单元还包括第十薄膜晶体管T10、第十一薄膜晶体管T11、第十二薄膜晶体管T12以及第二电容C2，所述第十薄膜晶体管T10的第一通路端连接所述第二时钟信号CK且其第二通路端连接所述第十一薄膜晶体管T11的第一通路端，所述第十一薄膜晶体管T11的第二通路端连接所述第二节点Pn且其控制端连接所述第二时钟信号CK，所述第十薄膜晶体管T10的控制端连接所述第十二薄膜晶体管T12的第二通路端，所述第十二薄膜晶体管T12的第一通路端和控制端均连接所述第一时钟信号XCK且其第二通路端连接所述第二电容C2的第一端以及所述第八薄膜晶体管T8的第一通路端，所述第二电容C2的第二端连接所述第二恒定电压VGH2。
  8. 根据权利要求7所述的GOA扫描电路，其中，所述第一恒定电压VGH1和第二恒定电压VGH2的大小相等。
  9. 根据权利要求7所述的GOA扫描电路，其中，所述第一恒定电压VGH1大于所述第二恒定电压VGH2。
  10. 根据权利要求7所述的GOA扫描电路，其中，所述第一至第十二薄膜晶体管T1~T12均为P型薄膜晶体管。
  11. 根据权利要求7所述的GOA扫描电路，其中，所述第一至第十二薄膜晶体管T1~T12的控制端均为栅极。
  12. 根据权利要求11所述的GOA扫描电路，其中，所述第一薄膜晶体管T1的漏极连接第一时钟信号XCK且源极连接第一节点Qn，所述第二薄膜晶体管T2的漏极连接第二时钟信号CK和且源极连接所述第一节点Qn，所述第三薄膜晶体管T3的第一通路端为漏极且其第二通路端为源极，所述第四薄膜晶体管T4的第一通路端为漏极且其第二通路端为源极，所述第五薄膜晶体管T5的漏极连接所述第三薄膜晶体管T3的第二通路端，所述第五薄膜晶体管T5的源极连接所述第一恒定电压，所述第六薄膜晶体管T6的漏极连接所述第四薄膜晶体管T4的第二通路端，所述第六薄膜晶体管T6的源极连接所述第一恒定电压VGH1，所述第七薄膜晶体管T7的漏极连接所述第一节点Qn且其源极连接所述第二恒定电压VGH2，所述第八薄膜晶体管T8的第一通路端为漏极且其第二通路端为其源极，所述第九薄膜晶体管T9的漏极连接所述第二节点Pn，所述第九薄膜晶体管T9的源极连接所述第二恒定电压VGH2，所述第十薄膜晶体管T10的第一通路端为漏极且其第二通路端为其源极，所述第十一薄膜晶体管T11的第一通路端为漏极且其第二通路端为其源极，所述第十一薄膜晶体管T11的第一通路端为漏极且其第二通路端为其源极。
  13. 一种液晶显示装置，其中，所述液晶显示装置包括GOA扫描电路，所述GOA扫描电路包括级联的多个GOA电路单元，第n级（N≥n≥1，且n为正整数）所述GOA电路单元包括：
    正反向扫描模块，所述正反向扫描模块包括第一薄膜晶体管T1和第二薄膜晶体管T2，所述第一薄膜晶体管T1的两个通路端分别连接第一时钟信号XCK和第一节点Qn，所述第二薄膜晶体管T2的两个通路端分别连接第二时钟信号CK和所述第一节点Qn，所述第一薄膜晶体管T1的控制端连接上一级GOA电路单元的级传信号STn-1，所述第二薄膜晶体管T2的控制端连接下一级所述GOA电路单元的级传信号STn+1，其中，第1级所述GOA电路单元中的所述第一薄膜晶体管T1的控制端连接正向扫描触发信号STV1，第N级所述GOA电路单元中的所述第二薄膜晶体管T2的控制端连接反向扫描触发信号STV2；
    输出模块，所述输出模块与所述第一节点Qn连接且用于根据第一节点Qn的电位输出本级所述GOA电路单元的级传信号STn和输出本级所述GOA电路单元的扫描信号Gn。
  14. 根据权利要求13所述的液晶显示装置，其中，所述输出模块包括第三薄膜晶体管T3、第四薄膜晶体管T4以及第一电容C1，所述第三薄膜晶体管T3和第四薄膜晶体管T4的控制端均连接所述第一节点Qn，所述第三薄膜晶体管T3的第一通路端连接所述第二时钟信号CK，所述第三薄膜晶体管T3的第二通路端用于输出本级所述GOA电路单元的级传信号STn，所述第四薄膜晶体管T4的第一通路端连接所述第二时钟信号CK，所述第四薄膜晶体管T4的第二通路端用于输出本级所述GOA电路单元的扫描信号Gn，所述第一电容C1的两端分别连接所述第一节点Qn和所述第三薄膜晶体管T3的第二通路端。
  15. 根据权利要求14所述的液晶显示装置，其中，第n级所述GOA电路单元进一步包括下拉维持模块，所述下拉维持模块包括第五薄膜晶体管T5、第六薄膜晶体管T6以及第七薄膜晶体管T7，所述第五薄膜晶体管T5、所述第六薄膜晶体管T6以及所述第七薄膜晶体管T7的控制端均连接所述第二节点Pn，所述第五薄膜晶体管T5的两个通路端分别连接所述第三薄膜晶体管T3的第二通路端和第一恒定电压VGH1，所述第六薄膜晶体管T6的两通路端分别连接所述第四薄膜晶体管T4的第二通路端和所述第一恒定电压VGH1，所述第七薄膜晶体管T7的两个通路端分别连接所述第一节点Qn和第二恒定电压VGH2。
  16. 根据权利15所述的液晶显示装置，其中，第n级所述GOA电路单元进一步包括下拉模块，所述下拉模块包括第八薄膜晶体管T8和第九薄膜晶体管T9，所述第八薄膜晶体管T8的第二通路端连接所述第二恒定电压，所述第八薄膜晶体管T8的控制端连接所述第一节点Qn，所述第九薄膜晶体管T9的两通路端分别连接所述第二节点Pn和所述第二恒定电压VGH2，所述第九薄膜晶体管T9的控制端连接所述第一节点Qn；第n级所述GOA电路单元还包括第十薄膜晶体管T10、第十一薄膜晶体管T11、第十二薄膜晶体管T12以及第二电容C2，所述第十薄膜晶体管T10的第一通路端连接所述第二时钟信号CK且其第二通路端连接所述第十一薄膜晶体管T11的第一通路端，所述第十一薄膜晶体管T11的第二通路端连接所述第二节点Pn且其控制端连接所述第二时钟信号CK，所述第十薄膜晶体管T10的控制端连接所述第十二薄膜晶体管T12的第二通路端，所述第十二薄膜晶体管T12的第一通路端和控制端均连接所述第一时钟信号XCK且其第二通路端连接所述第二电容C2的第一端以及所述第八薄膜晶体管T8的第一通路端，所述第二电容C2的第二端连接所述第二恒定电压VGH2。
  17. 根据权利要求16所述的液晶显示装置，其中，所述第一恒定电压VGH1和第二恒定电压VGH2的大小相等。
  18. 根据权利要求16所述的液晶显示装置，其中，所述第一恒定电压VGH1大于所述第二恒定电压VGH2。
  19. 根据权利要求16所述的液晶显示装置，其中，所述第一至第十二薄膜晶体管T1~T12均为P型薄膜晶体管。
  20. 根据权利要求16所述的液晶显示装置，其中，所述第一至第十二薄膜晶体管T1~T12的控制端均为栅极。
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