WO2017008539A1 - 一种led外延结构的制作方法 - Google Patents
一种led外延结构的制作方法 Download PDFInfo
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- WO2017008539A1 WO2017008539A1 PCT/CN2016/077840 CN2016077840W WO2017008539A1 WO 2017008539 A1 WO2017008539 A1 WO 2017008539A1 CN 2016077840 W CN2016077840 W CN 2016077840W WO 2017008539 A1 WO2017008539 A1 WO 2017008539A1
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- epitaxial
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 238000000034 method Methods 0.000 claims abstract description 54
- 230000008569 process Effects 0.000 claims abstract description 34
- 238000003892 spreading Methods 0.000 claims abstract description 14
- 230000000903 blocking effect Effects 0.000 claims description 49
- 239000000463 material Substances 0.000 claims description 26
- 239000000758 substrate Substances 0.000 claims description 15
- 230000007480 spreading Effects 0.000 claims description 12
- 238000006243 chemical reaction Methods 0.000 claims description 7
- 150000004767 nitrides Chemical class 0.000 claims description 6
- 239000012535 impurity Substances 0.000 claims description 2
- 238000011065 in-situ storage Methods 0.000 abstract description 7
- 230000000694 effects Effects 0.000 abstract description 6
- 230000004888 barrier function Effects 0.000 abstract description 5
- 238000000407 epitaxy Methods 0.000 abstract description 3
- 229910002601 GaN Inorganic materials 0.000 description 31
- 238000005530 etching Methods 0.000 description 9
- 230000004913 activation Effects 0.000 description 7
- 230000007547 defect Effects 0.000 description 7
- 230000008859 change Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910002704 AlGaN Inorganic materials 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 230000010287 polarization Effects 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 230000006798 recombination Effects 0.000 description 2
- 238000005215 recombination Methods 0.000 description 2
- 230000005428 wave function Effects 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000002427 irreversible effect Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
- H01L33/145—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
Definitions
- the present invention relates to the field of semiconductor optoelectronic devices, and in particular, to a method for fabricating an LED epitaxial structure.
- Gallium nitride-based light-emitting diodes have become an irreversible trend as a new light source instead of the traditional light source. Luminous efficiency has become a bottleneck affecting the performance of LEDs, affecting the application of products, how to reduce the operating voltage of the device, and achieve higher light efficiency. Light-emitting diodes have become a hot spot in current technology research.
- Chinese Patent Publication No. CN101866831A discloses an epitaxial substrate having a low surface defect density and a method of fabricating the same, which is formed by laterally epitaxially degrading a layer of lattice mismatched substrate to form a layer having a plurality of defects.
- the first epitaxial layer having a reduced surface defect is further subjected to defect selective etching from a plane of the first epitaxial layer, and the plurality of first recesses are etched from the defect, so that the first epitaxial layer has a defined An epitaxial layer plane of the first recess, the first recess has a diameter width close to each other, and then a barrier layer filling the first recess is formed to block the differential row and extend upward, and then uniform by chemical mechanical polishing The excess barrier layer is removed until the epitaxial layer plane is exposed and made flatter, with the epitaxial layer plane defining a complete and flat epitaxial base surface together with the remaining barrier layer surface.
- the epitaxial substrate having a low surface defect density and a method of manufacturing the same according to the present invention can effectively reduce the defect density and improve the subsequent epitaxial quality.
- this patent etches a cavity after an epitaxy, and then fills in, grinds, and then double-extends. The process is complicated. In addition, the cavity is completed in the process of chip fabrication, not in situ etching.
- the object of the present invention is to provide a method for fabricating an LED epitaxial structure, forming a cavity in situ by an epitaxial process, and filling a cavity with a current blocking dielectric layer to form a current spreading layer, which has a current spreading effect and can be effective. Improve the uniformity of electron or hole current, increase the brightness of the light and reduce the working voltage.
- a method for fabricating an LED epitaxial structure includes the following process steps: Providing a substrate; forming a first epitaxial layer over the substrate; forming a first recess through an epitaxial process on the first epitaxial layer; filling a first current in the first recess by an epitaxial process Blocking the dielectric layer; forming a second epitaxial layer over the first recess and the first current blocking dielectric layer.
- a method for fabricating an LED epitaxial structure includes the following steps: providing a substrate; forming a first epitaxial layer over the substrate; and forming the first epitaxial layer Forming a first recess through an epitaxial process; filling a first current blocking dielectric layer in the first recess by an epitaxial process; forming a second epitaxy on the first recess and the first current blocking dielectric layer a second recess is formed on the second epitaxial layer by an epitaxial process; a second current blocking dielectric layer is filled in the second recess by an epitaxial process; and the second recess and the second A third epitaxial layer is formed over the current blocking dielectric layer.
- the material of the first epitaxial layer is GaN.
- the second epitaxial layer/third epitaxial layer comprises a nitride light emitting epitaxial layer.
- the material of the current blocking dielectric layer is InAlGaN with low concentration or no miscellaneous.
- the conductivity of the InAlGaN material is less than that of the corresponding epitaxial layer filled with the cavity, and the current blocking effect is exerted.
- the current blocking dielectric layer and the epitaxial layer having a recess form a current spreading layer.
- the current spreading layer may be a single or a plurality of laminated structures.
- the epitaxial process of forming the first recess over the first epitaxial layer is: during the epitaxial growth of the first epitaxial layer, by lowering the growth temperature (below 900 ° C), high reaction chamber pressure ( 300torr or more), low NH 3 and H 2 partial pressure (11 2 partial pressure less than 30%), high growth rate (greater than 2 ⁇ /1 ⁇ ), thereby reducing the lateral epitaxial ability of the first epitaxial layer, using threading dislocations
- the first epitaxial layer surface forms a first recess.
- the epitaxial process of filling the first current blocking dielectric layer in the first recess is: epitaxially growing a thin first current blocking medium on the first epitaxial layer having the first recess a layer (thickness less than ⁇ . ⁇ ), which is quickly filled by adjusting the growth rate, temperature, and pressure conditions; and then etching the upper epitaxial layer by controlling epitaxial growth conditions The first current blocks the dielectric layer such that the first current blocking dielectric layer is filled only in the first recess.
- the epitaxial growth method of the first current blocking dielectric layer is: growing a low-difficult or unhealthy InAlGaN material in the first cavity by adjusting the growth temperature (above 1100 ° C), low Reaction chamber pressure Force (less than lOOtorr), high NH 3 and H 2 partial pressure (H 2 partial pressure greater than 50%), low growth rate (far lower than the first epitaxial layer growth rate), thereby improving the lateral epitaxial growth ability of InAlGaN materials,
- the first cavity is quickly filled under a very thin thickness (thickness less than ⁇ . ⁇ ) grown on the C-plane (GaN (0001) plane).
- the etching method of the first current blocking dielectric layer over the first epitaxial layer is: interrupting growth after the first current blocking dielectric layer fills the first recess, Close the ⁇ 3 source, reduce the pressure in the reaction chamber, and perform in-situ etching, since the InAlGaN material is pure 11 2
- decomposition occurs along the C-plane (GaN (0001) plane), so that the In AlGaN material located above the first epitaxial layer is all decomposed, and the inside of the first recess is still filled with the InAlGaN material.
- the present invention includes at least the following technical effects:
- the cavity is generated by using threading dislocations in the epitaxial layer, and the density above leScm - 2 is easily realized, and the distribution is relatively uniform, and is completely realized by the epitaxial process in situ, and does not require a chip process, and does not need to be Adding a mask layer;
- (4) a plurality of stacked current spreading layers can effectively improve current spreading effect, effectively improve electron or hole current uniformity, and improve light emitting brightness and Reduce the operating voltage.
- substrate 1 InAlGaN buffer layer 2; U-GaN layer 3; first N-GaN layer 4; second N-Ga N layer 5; first current blocking dielectric layer 6; superlattice 7; luminescent epitaxial layer 8 (MQW); P-GaN layer 9;
- P-type contact layer 10 third N-GaN layer 11; second current blocking dielectric layer 12; second P-GaN layer 13.
- FIG. 5 are schematic diagrams showing a process flow for fabricating an epitaxial structure of an LED according to Embodiment 1 of the present invention.
- FIG. 6 is a schematic diagram of fabricating an epitaxial structure of an LED according to Embodiment 2 of the present invention.
- FIG. 7 is a schematic diagram of fabricating an epitaxial structure of an LED according to Embodiment 3 of the present invention.
- this embodiment provides a method for fabricating an LED epitaxial structure, which includes the following process steps:
- a flat sapphire or PSS substrate 1 is provided; a first epitaxial layer is grown on the substrate 1, and in this embodiment, the InAlGaN buffer layer 2, U is preferably grown on the substrate 1 in this order.
- a first recess is formed on the second N-GaN layer 5 by an epitaxial process.
- an epitaxial process for forming the first recess is: in the second N-GaN During the epitaxial growth of layer 5, by lowering the growth temperature (below 900 ° C), high reaction chamber pressure (above 300 torr), low NH 3 and H 2 partial pressure (H 2 partial pressure less than 30%), high growth rate (greater than 2 ⁇ ), thereby reducing the lateral epitaxial ability of the first epitaxial layer, forming a first pit 5 ⁇ on the upper surface of the second N-GaN layer 5 by using threading dislocations; since the pit is generated by using threading dislocations in GaN It is easy to realize the density of leScm - 2 or more, and the distribution is relatively uniform.
- the first recess 5A is filled with a first current blocking dielectric layer, and its epitaxial process
- a thin first current blocking dielectric layer 6 (thickness less than ⁇ . ⁇ ) is epitaxially grown on the second N-GaN layer 5 having the first recess, and the material of the first current blocking dielectric layer 6 is selected to be low.
- miscellaneous or unhealthy In AlGaN by adjusting the growth temperature (above 1100 ° C), low reaction chamber pressure (below lOOtorr), high NH 3 and H 2 partial pressure (H 2 partial pressure greater than 50%), low growth The rate (which is much lower than the growth rate of the first epitaxial layer), thereby improving the lateral epitaxial growth ability of the InAlGaN material, and rapidly filling the C-plane (GaN (0001) plane) with a very thin thickness (thickness less than ⁇ . ⁇ ) The first cavity.
- the conductivity of the InAlGaN material that emphasizes the first current blocking dielectric layer is smaller than the epitaxial layer (second N-GaN layer) corresponding to the filled recess, and the current blocking dielectric layer has a recess.
- the epitaxial layer constitutes a current spreading layer, thereby exerting a current blocking effect; since the conductivity of the InAlGaN material is affected by the concentration of the damaging medium and the activation efficiency of the catastrophic medium, the change in the composition of the InAlGaN material A1 changes the forbidden band width of the material. Therefore, the activation energy and activation efficiency of the catastrophic medium are changed.
- the inhomogeneous medium and concentration of the InAlGaN material and the control of the A1 component can, on the one hand, simply reduce the concentration of the turbulent medium (below the concentration in the second N-GaN layer) or reduce the electron concentration of the InAlGaN material.
- the A1 component lowers the activation efficiency and the like to achieve a net electron concentration and conductivity lower than that of the second N - GaN layer as a barrier dielectric layer, thereby exerting a current blocking effect.
- the second layer is located in the second
- the InAlGaN material on the N-GaN layer 5 is completely decomposed, and the inside of the first cavity is still filled with InAlGaN material; since the current blocking dielectric layer is filled in the cavity, it is not necessary to add a mask layer through the chip process. Grinding, etching, etc., simplify the process.
- the second epitaxial layer is then grown.
- This embodiment preferably fills the first N-GaN layer 5 of the first current blocking dielectric layer 6 in the first recess 5A.
- the embodiment is different from Embodiment 1 in that: the current spreading layer is two stacked structures (located in the same polarity epitaxial layer), and the third epitaxial layer includes a light emitting epitaxial layer nitride, located at Above the two laminate structures.
- the third N-GaN layer 11 is epitaxially grown again, and a second recess is formed by an epitaxial process, and The second current blocking dielectric layer 12 is filled therein.
- the pit Since the pit is generated by using threading dislocations in GaN, and the threading dislocations are difficult to propagate strictly along the C direction (perpendicular to the C plane) inside the first epitaxial layer, it occurs during the growth of the first epitaxial layer. With a certain tilt and twist, a dot matrix pit is grown multiple times inside the first epitaxial layer, and the upper and lower layers form a lattice overlap, so that the two pits overlap to some extent, and the two layers of the current blocking dielectric layer are complementary. Overlap can better improve electron current expansion, improve current uniformity and luminous efficiency.
- this embodiment is different from Embodiment 1 in that: the current spreading layer is two stacked structures (each located in an opposite polarity epitaxial layer), and the second epitaxial layer includes a light emitting epitaxial layer nitride. Located between two laminated structures.
- the second current blocking dielectric layer 12 of the present embodiment is filled in the second P-GaN layer 13 having the second recess structure, which is mainly used to improve the uniformity of the hole current, so that on the one hand, it can be simple. Reduce the concentration of the turbid medium (below the peculiar concentration in the P-GaN layer) or not to reduce the hole concentration of the InAlGaN material.
- a recess is formed in both the first epitaxial layer (N polarity) and the third epitaxial layer (P polarity), and is distributed on both sides of the second epitaxial layer (nitride luminescent epitaxial layer), in the concave
- the current blocking dielectric layer filled in the hole can improve the uniformity of electron and hole current spreading, and the effect is better than that of the first epitaxial layer (N polarity) on one side.
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Abstract
本发明提供一种LED外延结构的制作方法,通过外延制程原位形成凹洞,再在凹洞中填满电流阻挡介质层,从而构成电流扩展层,具有电流扩展效果,可以有效提高电子或空穴电流均匀性,提高发光亮度及降低工作电压。
Description
一种 LED外延结构的制作方法 技术领域
[0001] 本发明涉及半导体光电器件领域, 尤其涉及一种 LED外延结构的制作方法。
背景技术
[0002] 氮化镓基发光二极管作为新型光源替代传统光源已成为不可逆转的趋势, 发光 效率已成为影响发光二极管性能的瓶颈, 影响产品的用途拓展, 如何降低器件 的工作电压, 实现更高光效的发光二极管已经成为目前的技术研究热点。
[0003] 中国专利文献 CN101866831A公幵了一种低表面缺陷密度的外延基板及其制造 方法, 该制造方法先自一层晶格不匹配的基材侧向外延, 形成一层具有多个缺 陷处且表面缺陷降低的第一外延层, 再自该第一外延层的平面进行缺陷选择性 蚀刻, 将所述缺陷处蚀刻出多个第一凹洞, 使该第一外延层具有一界定所述第 一凹洞的外延层平面, 所述第一凹洞的径宽彼此相近, 然后形成一填满所述第 一凹洞的阻挡层, 以阻隔差排向上延伸, 再利用化学机械研磨法均匀地移除多 余阻挡层, 至该外延层平面裸露并使得其更加平坦, 而使该外延层平面与剩下 的该阻挡层表面共同定义出一面完整且平坦的外延基面。 该发明所述低表面缺 陷密度的外延基板及其制造方法, 能够有效地降低缺陷密度, 且能提高后续外 延品质。 但是该专利是在一次外延后腐蚀出凹洞, 再填埋、 研磨, 然后二次外 延, 工艺较为复杂, 此外凹洞是在芯片工艺制成中完成的, 并非是原位腐蚀形 成。
技术问题
问题的解决方案
技术解决方案
[0004] 本发明目的在于: 提供 LED外延结构的制作方法, 通过外延制程原位形成凹洞 , 再在凹洞中填满电流阻挡介质层, 从而构成电流扩展层, 具有电流扩展效果 , 可以有效提高电子或空穴电流均匀性, 提高发光亮度及降低工作电压。
[0005] 本发明的第一方面, 提供一种 LED外延结构的制作方法, 包括以下工艺步骤:
提供一基板; 在所述基板之上形成第一外延层; 在所述第一外延层之上通过外 延制程形成第一凹洞; 在所述第一凹洞中通过外延制程填满第一电流阻挡介质 层; 在所述第一凹洞与第一电流阻挡介质层之上形成第二外延层。
[0006] 本发明的第二方面, 再提供一种 LED外延结构的制作方法, 包括以下工艺步骤 : 提供一基板; 在所述基板之上形成第一外延层; 在所述第一外延层之上通过 外延制程形成第一凹洞; 在所述第一凹洞中通过外延制程填满第一电流阻挡介 质层; 在所述第一凹洞与第一电流阻挡介质层之上形成第二外延层; 在所述第 二外延层之上通过外延制程形成第二凹洞; 在所述第二凹洞中通过外延制程填 满第二电流阻挡介质层; 在所述第二凹洞与第二电流阻挡介质层之上形成第三 外延层。
[0007] 优选地, 所述第一外延层的材料为 GaN。
[0008] 优选地, 所述第二外延层 /第三外延层包括氮化物发光外延层。
[0009] 优选地, 所述电流阻挡介质层的材料为低浓度惨杂或者不惨杂的 InAlGaN。
[0010] 优选地, 通过控制 InAlGaN材料的惨杂介质和浓度及 A1组分, 使得 InAlGaN材 料的电导率小于所填满凹洞对应的外延层, 发挥电流阻挡作用。
[0011] 优选地, 所述电流阻挡介质层与具有凹洞的外延层构成电流扩展层。
[0012] 优选地, 所述电流扩展层可以为单个或多个叠层结构。
[0013] 优选地, 所述第一外延层之上形成第一凹洞的外延制程为: 在第一外延层外延 生长过程中, 通过降低生长温度 (900°C以下) 、 高反应室压力 (300torr以上) 、 低 NH 3和 H 2分压 (11 2分压小于 30%) 、 高生长速率 (大于 2μηι/1ι) , 从而降低 第一外延层的侧向外延能力, 利用穿透位错在第一外延层表面形成第一凹洞。
[0014] 优选地, 在所述第一凹洞中填满第一电流阻挡介质层的外延制程为: 在具有第 一凹洞的第一外延层之上先外延生长薄的第一电流阻挡介质层 (厚度小于 Ο.ΐμηι ) , 通过调整生长速率、 温度、 压力条件控制, 迅速把所述第一凹洞填满; 再 通过控制外延生长条件, 刻蚀位于所述第一外延层之上的第一电流阻挡介质层 , 使得仅在所述第一凹洞中填满所述第一电流阻挡介质层。
[0015] 优选地, 第一电流阻挡介质层的外延生长方法为: 在所述第一凹洞中生长低惨 杂或者不惨杂的 InAlGaN材料, 通过调整生长温度 (1100°C以上) 、 低反应室压
力 (lOOtorr以下) 、 高 NH 3和 H 2分压 (H 2分压大于 50%) 、 低生长速率 (远低 于第一外延层生长速率) , 从而提高 InAlGaN材料的侧向外延生长能力, 在 C面 (GaN (0001) 面) 生长非常薄的厚度 (厚度小于 Ο.ΐμηι) 下迅速填满所述第一 凹洞。
[0016] 优选地, 位于所述第一外延层之上的第一电流阻挡介质层的刻蚀方法为: 在所 述第一电流阻挡介质层填满所述第一凹洞之后, 中断生长, 关闭 ΝΗ 3源, 降低 反应室压力, 进行原位刻蚀, 由于 InAlGaN材料在纯11 2
条件下沿 C面 (GaN (0001) 面) 发生分解, 使得位于所述第一外延层之上的 In AlGaN材料全部分解, 而位于所述第一凹洞内部依然填满 InAlGaN材料。
发明的有益效果
有益效果
[0017] 本发明相对于现有技术, 至少包括以下技术效果:
[0018] (1) 凹洞是利用外延层中的穿透位错产生, 很容易实现 leScm -2以上的密度, 分布比较均匀, 完全通过外延过程原位实现, 不需要芯片工艺制程, 不需要增 设掩膜层;
[0019] (2) 通过外延制程形成凹洞, 可以有效释放膜内应力, 降低发光外延层内建 电场和极化电荷密度, 增大电子空穴波函数交叠, 提高辐射复合几率;
[0020] (3) 在凹洞中填满电流阻挡介质层, 不需要通过芯片工艺增设掩膜层再研磨
、 蚀刻等, 简化了工艺流程;
[0021] (4) 多个叠层结构的电流扩展层 (电流阻挡介质层与具有凹洞的外延层) , 可以有效改善电流扩展效果, 有效提高电子或空穴电流均匀性, 提高发光亮度 及降低工作电压。
对附图的简要说明
附图说明
[0022] 附图用来提供对本发明的进一步理解, 并且构成说明书的一部分, 与本发明实 施例一起用于解释本发明, 并不构成对本发明的限制。 此外, 附图数据是描述 概要, 不是按比例绘制。
[0023] 图中标示: 衬底 1 ; InAlGaN缓冲层 2; U-GaN层 3; 第一 N-GaN层 4; 第二 N-Ga
N层 5; 第一电流阻挡介质层 6; 超晶格 7; 发光外延层 8 (MQW) ; P-GaN层 9;
P型接触层 10; 第三 N-GaN层 11 ; 第二电流阻挡介质层 12; 第二 P-GaN层 13。
[0024] 图 1~图5为本发明实施例 1制作 LED外延结构的工艺流程示意图。
[0025] 图 6为本发明实施例 2制作 LED外延结构的示意图。
[0026] 图 7为本发明实施例 3制作 LED外延结构的示意图。
本发明的实施方式
[0027] 下面结合示意图对本发明进行详细的描述, 在进一步介绍本发明之前, 应当理 解, 由于可以对特定的实施例进行改造, 因此, 本发明并不限于下述的特定实 施例。 还应当理解, 由于本发明的范围只由所附权利要求限定, 因此所采用的 实施例只是介绍性的, 而不是限制性的。 除非另有说明, 否则这里所用的所有 技术和科学用语与本领域的普通技术人员所普遍理解的意义相同。
[0028] 实施例 1
[0029] 如图 1~5所示, 本实施例提供一种 LED外延结构的制作方法, 包括以下工艺步 骤:
[0030] (1) 如图 1所示, 提供一平片蓝宝石或者 PSS衬底 1 ; 在衬底 1上生长第一外延 层, 本实施例优选依次在衬底 1上生长 InAlGaN缓冲层 2、 U-GaN层 3、 第一 N-Ga N层 4和第二 N-GaN层 5; 第一凹洞 5A。
[0031] (2) 如图 2所示, 在第二 N-GaN层 5上通过外延制程形成第一凹洞, 具体来说 , 形成第一凹洞的外延制程为: 在第二 N-GaN层 5外延生长过程中, 通过降低生 长温度 (900°C以下) 、 高反应室压力 (300torr以上) 、 低 NH 3和 H 2分压 (H 2分 压小于 30%) 、 高生长速率 (大于 2μηι) , 从而降低第一外延层的侧向外延能力 , 利用穿透位错在第二 N-GaN层 5上表面形成第一凹洞 5Α; 由于凹洞是利用 GaN 中的穿透位错产生, 很容易实现 leScm -2以上的密度, 分布比较均匀, 完全通过 外延过程原位实现, 不需要芯片工艺制程, 不需要增设掩膜层; 此外, 通过外 延制程形成凹洞, 可以有效释放膜内应力, 降低发光外延层内建电场和极化电 荷密度, 增大电子空穴波函数交叠, 提高辐射复合几率。
[0032] (3) 如图 3所示, 在所述第一凹洞 5A中填满第一电流阻挡介质层, 其外延制程
为: 在具有第一凹洞的第二 N-GaN层 5之上先外延生长薄的第一电流阻挡介质层 6 (厚度小于 Ο.ΐμηι) , 第一电流阻挡介质层 6的材料选用低 Ν惨杂或者不惨杂的 In AlGaN, 通过调整生长温度 (1100°C以上) 、 低反应室压力 (lOOtorr以下) 、 高 NH 3和H 2分压 (H 2分压大于 50%) 、 低生长速率 (远低于第一外延层生长速率 ) , 从而提高 InAlGaN材料的侧向外延生长能力, 在 C面 (GaN (0001) 面) 生 长非常薄的厚度 (厚度小于 Ο.ΐμηι) 下迅速填满所述第一凹洞。
[0033] 需要进一步说明的是, 强调第一电流阻挡介质层的 InAlGaN材料的电导率要小 于所填满凹洞对应的外延层 (第二 N-GaN层) , 电流阻挡介质层与具有凹洞的外 延层构成电流扩展层, 从而发挥电流阻挡作用; 由于 InAlGaN材料的电导率受惨 杂介质的浓度和惨杂介质的激活效率共同影响, 而 InAlGaN材料 A1组分变化会改 变材料的禁带宽度从而改变惨杂介质的激活能和激活效率, 不同种类惨杂介质 在 InAlGaN材料禁带中的位置不同而具有不同的激活能和激活效率, 所以对于第 一电流阻挡介质层的电导率可以通过控制 InAlGaN材料的惨杂介质和浓度及 A1组 分进行控制, 一方面可以简单降低惨杂介质的浓度 (低于第二 N-GaN层中惨杂浓 度) 或者不惨杂来降低 InAlGaN材料的电子浓度, 另外一方面也可以通过改变惨 杂介质种类 (使用或增加 C或其他等深能级惨杂介质) 或者提高 A1组分降低激活 效率等办法实现作为阻挡介质层的净电子浓度和电导率低于第二 N-GaN层, 从而 发挥电流阻挡作用。
[0034] (4) 如图 4所示, 再通过控制外延生长条件, 刻蚀位于所述第二 N-GaN层 5之 上的第一电流阻挡介质层 6, 使得仅在所述第一凹洞 5A中填满所述第一电流阻挡 介质层 6, 位于所述第二 N-GaN层 5之上的第一电流阻挡介质层 6的刻蚀方法为: 在所述第一电流阻挡介质层填满所述第一凹洞之后, 中断生长, 关闭 NH 3源, 降低反应室压力, 进行原位刻蚀, 由于 InAlGaN材料在纯 11 2条件下沿 C面发生分 解, 使得位于所述第二 N-GaN层 5之上的 InAlGaN材料全部分解, 而位于所述第 一凹洞内部依然填满 InAlGaN材料; 由于在凹洞中填满电流阻挡介质层, 不需要 通过芯片工艺增设掩膜层再研磨、 蚀刻等, 简化了工艺流程。
[0035] (5) 如图 5所示, 然后再继续生长第二外延层, 本实施例优选依次在第一凹洞 5A中填满第一电流阻挡介质层 6的第一 N-GaN层 5之上生长超晶格 7、 发光外延层
8 (MQW) 、 P-GaN层 9及 P型接触层 10。
[0036] 实施例 2
[0037] 如图 6所示, 本实施例区别于实施例 1在于: 电流扩展层为两个叠层结构 (位于 同极性外延层) , 且第三外延层包括发光外延层氮化物, 位于两个叠层结构之 上。 具体来说, 本实施例在形成填满第一电流阻挡介质层 6的第二 N-GaN层 13之 后, 再次外延生长第三 N-GaN层 11, 并通过外延制程形成第二凹洞, 并在其中填 满第二电流阻挡介质层 12。 由于凹洞是利用 GaN中的穿透位错产生, 而穿透位错 在第一外延层内部很难严格沿 C向 (垂直于 C面) 传播, 所以在第一外延层生长 过程中会发生一定的倾斜和扭转, 在第一外延层内部多次生长点阵式的凹洞, 上下层形成点阵交叠, 如此两层凹洞会发生一定程度的交叠, 两层电流阻挡介 质层互补交叠, 可以更好地改善电子电流扩展, 提高电流均匀性和发光效率。
[0038] 实施例 3
[0039] 如图 7所示, 本实施例区别于实施例 1在于: 电流扩展层为两个叠层结构 (分别 位于异极性外延层) , 且第二外延层包括发光外延层氮化物, 位于两个叠层结 构之间。 具体来说, 本实施例的第二电流阻挡介质层 12填充于具有第二凹洞结 构的第二 P-GaN层 13中, 其主要用于改善空穴电流的均匀性, 所以一方面可以简 单降低惨杂介质的浓度 (低于 P-GaN层中惨杂浓度) 或者不惨杂来降低 InAlGaN 材料的空穴浓度, 另外一方面也可以通过改变惨杂介质种类 (使用或增加 C或其 他等深能级惨杂介质) 或者提高 A1组分降低激活效率等办法实现作为电流阻挡 介质层的净空穴浓度和电导率低于 P-GaN层, 从而发挥电流阻挡作用。 本实施例 通过在第一外延层 (N极性) 和第三外延层 (P极性) 中均有形成凹洞, 分布于 第二外延层 (氮化物发光外延层) 的两侧, 在凹洞中填满的电流阻挡介质层可 以改善电子和空穴电流扩展均匀性, 效果会比第一外延层 (N极性) 单侧的电流 扩展效果更好。
[0040] 以上所述仅是本发明的优选实施方式, 应当指出, 对于本技术领域的普通技术 人员, 在不脱离本发明原理的前提下, 还可以做出若干改进和润饰, 这些改进 和润饰也应视为本发明的保护范围。
Claims
[权利要求 1] 一种 LED外延结构的制作方法, 包括以下工艺步骤:
提供一基板; 在所述基板之上形成第一外延层; 在所述第一外延层之 上通过外延制程形成第一凹洞; 在所述第一凹洞中通过外延制程填满 第一电流阻挡介质层; 在所述第一凹洞与第一电流阻挡介质层之上形 成第二外延层。
[权利要求 2] —种 LED外延结构的制作方法, 包括以下工艺步骤:
提供一基板; 在所述基板之上形成第一外延层; 在所述第一外延层之 上通过外延制程形成第一凹洞; 在所述第一凹洞中通过外延制程填满 第一电流阻挡介质层; 在所述第一凹洞与第一电流阻挡介质层之上形 成第二外延层; 在所述第二外延层之上通过外延制程形成第二凹洞; 在所述第二凹洞中通过外延制程填满第二电流阻挡介质层; 在所述第 二凹洞与第二电流阻挡介质层之上形成第三外延层。
[权利要求 3] 根据权利要求 1或 2所述的一种 LED外延结构的制作方法, 其特征在于
: 所述第一外延层的材料为 GaN。
[权利要求 4] 根据权利要求 1所述的一种 LED外延结构的制作方法, 其特征在于: 所述第二外延层包括氮化物发光外延层。
[权利要求 5] 根据权利要求 2所述的一种 LED外延结构的制作方法, 其特征在于: 所述第二外延层或第三外延层包括氮化物发光外延层。
[权利要求 6] 根据权利要求 1或 2所述的一种 LED外延结构的制作方法, 其特征在于
: 所述电流阻挡介质层的材料为低浓度惨杂或者不惨杂的 InAlGaN。
[权利要求 7] 根据权利要求 6所述的一种 LED外延结构的制作方法, 其特征在于: 通过控制 InAlGaN材料的惨杂介质和浓度及 A1组分, 使得 InAlGaN材 料的电导率小于所填满凹洞对应的外延层, 发挥电流阻挡作用。
[权利要求 8] 根据权利要求 1或 2所述的一种 LED外延结构的制作方法, 其特征在于
: 所述电流阻挡介质层与具有凹洞的外延层构成电流扩展层。
[权利要求 9] 根据权利要求 8所述的一种 LED外延结构的制作方法, 其特征在于: 所述电流扩展层为单个或多个叠层结构。
[权利要求 10] 根据权利要求 1或 2所述的一种 LED外延结构的制作方法, 其特征在于 : 所述第一外延层之上形成第一凹洞的外延制程为: 在第一外延层外 延生长过程中, 通过降低生长温度 (900°C以下) 、 高反应室压力 (3 OOtorr以上) 、 低 NH 3和 H 2分压 (H 2分压小于 30%) 、 高生长速率 、. 大于 2μητ/1ι) , 从而降低第一外延层的侧向外延能力, 利用穿透位错 在第一外延层表面形成第一凹洞。
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