WO2017004949A1 - 阵列基板、显示面板以及显示装置 - Google Patents

阵列基板、显示面板以及显示装置 Download PDF

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Publication number
WO2017004949A1
WO2017004949A1 PCT/CN2015/098270 CN2015098270W WO2017004949A1 WO 2017004949 A1 WO2017004949 A1 WO 2017004949A1 CN 2015098270 W CN2015098270 W CN 2015098270W WO 2017004949 A1 WO2017004949 A1 WO 2017004949A1
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Prior art keywords
electrode
array substrate
strips
spacer
disposed
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PCT/CN2015/098270
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English (en)
French (fr)
Inventor
胡伟
杨妮
邱海军
Original Assignee
京东方科技集团股份有限公司
重庆京东方光电科技有限公司
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Priority to US15/101,662 priority Critical patent/US10317737B2/en
Publication of WO2017004949A1 publication Critical patent/WO2017004949A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G02F1/13394—Gaskets; Spacers; Sealing of cells spacers regularly patterned on the cell subtrate, e.g. walls, pillars
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/133707—Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/122—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode having a particular pattern
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/124—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode interdigital

Definitions

  • At least one embodiment of the present invention is directed to an array substrate, a display panel, and a display device.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • Array Substrate a Color Filter Substrate
  • a liquid crystal sandwiched between two substrates (Liquid) Crystal) layer Also included in the display device are pixel electrodes and common electrodes for controlling liquid crystal deflection.
  • the control of the intensity of the light is controlled by controlling the deflection of the liquid crystal molecules, and then the color image display is realized by the filtering action of the color filter substrate.
  • the TFT-LCD includes an In-Plane Switching (IPS) mode and an Advanced-Super Dimensional Switching (ADS) mode.
  • IPS In-Plane Switching
  • ADS Advanced-Super Dimensional Switching
  • a parallel electric field generated by the edge of the pixel electrode or the common electrode and a longitudinal electric field generated between the pixel electrode and the common electrode form a multi-dimensional electric field, so that the pixel electrode or the common electrode in the liquid crystal cell, the pixel electrode or the common All of the aligned liquid crystal molecules directly above the electrode can generate a rotation conversion, thereby improving the working efficiency of the planar orientation liquid crystal and increasing the light transmission efficiency.
  • At least one embodiment of the present invention provides an array substrate, a display panel, and a display device, by forming a spacer strip for a pixel electrode and a common electrode protrusion on the array substrate, thereby enhancing a horizontal electric field and suppressing a vertical electric field, thereby improving transmittance. .
  • An embodiment of the present invention provides an array substrate including a substrate substrate and a plurality of sub-pixels disposed on the substrate, each of the sub-pixels including a first electrode, a second electrode, and a plurality of spacer strips, A plurality of spacer strips are disposed below the first electrode and the second electrode.
  • the spacer strip includes any one of a linear shape, a polygonal line shape, a wave shape, a zigzag shape, and an arc shape.
  • the plurality of spacer strips are a plurality of linear spacer strips disposed in parallel.
  • the first electrode and the second electrode each include a portion corresponding to the plurality of spacer strips.
  • a portion of the first electrode and the second electrode corresponding to the plurality of spacer strips is a protruding portion.
  • the first electrode and the second electrode are disposed in different layers, and a first insulating layer is disposed between the first electrode and the second electrode, a second electrode is located above the first electrode, and in each of the sub-pixels, the second electrode includes a plurality of second electrode strips, and in the layer where the second electrode is located, corresponding to the plurality of At the position of the spacer strip, one of the second electrode strips is disposed for each of the spacer strips.
  • the first electrode is a planar electrode or the first electrode includes a plurality of first electrode strips;
  • the first electrode includes a plurality of first electrode strips
  • the layer where the first electrode is located at a position corresponding to the plurality of spacer strips, one spacer is disposed for each of the spacer strips
  • the first electrode strip is described, and the adjacent two strips correspond to the first electrode strip and the second electrode strip, respectively.
  • the second electrode is a slit electrode or a comb electrode.
  • the first electrode and the second electrode are disposed in the same layer.
  • the first electrode includes a plurality of first electrode strips.
  • the second electrode includes a plurality of second electrode strips, in a layer where the first electrode and the second electrode are located, at positions corresponding to the plurality of spacer strips, alternately arranged or every other one
  • the spacer strip alternately sets the first electrode strip and the second electrode strip.
  • the first electrode and the second electrode have a zigzag structure in a cross section in a direction perpendicular to the plurality of spacer strips.
  • the cross section of the spacer strip includes any one of a trapezoidal shape, a triangular shape, a semicircular shape, a stepped shape, and a mountain shape.
  • an array substrate provided by an embodiment of the present invention further includes a second insulating layer and a gate insulating layer, the second insulating layer being located above the gate insulating layer and located at the first electrode and the second Below the electrode, the plurality of spacer strips are formed by a portion of the second insulating layer.
  • an array substrate provided by an embodiment of the present invention further includes a gate insulating layer under the first electrode and the second electrode, and the plurality of spacer strips pass through the gate A portion of the pole insulating layer is formed.
  • an array substrate provided by an embodiment of the present invention further includes a plurality of data lines and a plurality of gate lines disposed on the substrate, and each of the sub-pixels includes a plurality of spacer strips extending in parallel In an extending direction of the gate line or the data line, or an angle between an extending direction of the plurality of spacer strips and an extending direction of the gate line or the data line, or each of the sub-pixels
  • the plurality of spacer strips included include at least two groups, and the spacer strips in different groups extend in different directions.
  • the plurality of data lines and the plurality of gate lines intersect to define a plurality of the plurality of sub-pixels arranged in an array.
  • At least one embodiment of the present invention also provides a display panel including any of the above array substrates.
  • At least one embodiment of the present invention also provides a display device including any of the above display panels.
  • FIG. 1 is a schematic diagram of an ADS mode array substrate
  • FIG. 2a is a schematic diagram of an array substrate according to an embodiment of the invention.
  • 2b is a schematic diagram of a pixel electrode and a common electrode in an array substrate according to an embodiment of the invention
  • 2c is a schematic diagram of a linear spacer strip in an array substrate according to an embodiment of the invention.
  • FIG. 2 is a schematic diagram of a line-shaped spacer strip in an array substrate according to an embodiment of the invention
  • Figure 3a is a schematic view of the array substrate A-A' of Figure 2a (ADS mode);
  • FIG. 3b is a schematic cross-sectional view of an array substrate (ADS mode) according to an embodiment of the present invention.
  • Figure 3c is a schematic view of the A-A' of the array substrate of the first electrode and the second electrode of Figure 2a including a plurality of electrode strips (ADS mode);
  • FIG. 4a is another schematic view of the array substrate A-A' of FIG. 2a (IPS mode);
  • 4b is an alternate arrangement of the first electrode in every other spacer strip in the IPS mode array substrate of FIG. 2a A-A' schematic view of the strip and the second electrode strip;
  • FIG. 5 is a schematic diagram of a display panel according to an embodiment of the invention.
  • FIG. 6 is a schematic diagram showing a horizontal electric field intensity distribution of a display panel
  • FIG. 7 is a schematic diagram of horizontal electric field intensity distribution of a display panel according to an embodiment of the present invention.
  • FIG. 8 is a schematic diagram of horizontal electric field intensity distribution of a display panel according to another embodiment of the present invention.
  • the pixel electrode and the common electrode are each formed on a corresponding planar structure layer.
  • the fringe electric field formed by the potential difference between the pixel electrode and the common electrode includes two components, one is a horizontal electric field that is favorable for horizontal deflection of the liquid crystal, and the other is One is a longitudinal electric field that acts as a disturbance.
  • the horizontal electric field is weak, and the longitudinal electric field is strong, resulting in a correspondingly small transmittance, and ultimately affecting the transmittance of the entire liquid crystal panel.
  • the common electrode may be a slit electrode
  • the pixel electrode may be a planar electrode. This situation Next, in the middle region on the slit of the common electrode, and the intermediate region between the slits, the horizontal electric field is weak, and the longitudinal electric field is strong, which may also cause the transmittance to be relatively small, and finally affect the penetration of the entire liquid crystal panel. Over rate.
  • the pixel electrode and the common electrode are formed on the same planar structure layer.
  • the pixel electrode and the common electrode each include a plurality of electrode strips, and the fringe electric field formed by the potential difference between the pixel electrode and the common electrode includes two components, one is a horizontal electric field that is favorable for horizontal deflection of the liquid crystal, and the other is interference.
  • Vertical electric field In the middle region of each electrode strip of the pixel electrode and the middle portion of each electrode strip of the common electrode, the horizontal electric field is weak, the longitudinal electric field is strong, and the transmittance is correspondingly small, and finally affects the transmission of the entire liquid crystal panel. rate.
  • a partial cross-sectional view of an array substrate of an ADS mode is provided with a gate electrode 108 on the substrate substrate 100.
  • a gate insulating layer 107 is disposed over the layer on which the gate electrode 108 is located.
  • An active layer 109 is disposed on the gate insulating layer 107.
  • a source 110 and a drain 111 are disposed on the active layer 109.
  • the source 110 and the drain 111 are both connected to the active layer 109, and the source 110 and the drain 111 are provided on both sides of the active layer 109. There is a space between the source 110 and the drain 111 to define a channel region.
  • the thin film transistor includes a gate electrode 108, a gate insulating layer 107, an active layer 109, a source 110, and a drain 111.
  • a second insulating layer 106 is disposed over the layer on which the source 110 and the drain 111 are located.
  • a first electrode 102 is disposed on the second insulating layer 106.
  • a first insulating layer 105 is disposed over the layer on which the first electrode 102 is located.
  • a second electrode 103 is disposed on the first insulating layer 105.
  • the second electrode 103 includes a plurality of second electrode strips 1031. The second electrode 103 is connected to the drain 111 of the thin film transistor through the via 113.
  • the second electrode 103 may be a pixel electrode, and correspondingly, the first electrode 102 is a common electrode.
  • the first electrode 102 and the second electrode 103 are both disposed on a planar structure.
  • the horizontal electric field drive is achieved by controlling the potential difference formed between the pixel electrode and the common electrode.
  • the present embodiment provides an array substrate, as shown in FIG. 2a, which includes a base substrate 100 and a plurality of sub-pixels 101 arranged in an array disposed on the base substrate 100.
  • each sub-pixel includes a first electrode 102, a second electrode 103, and a plurality of spacer strips 104, and a plurality of spacer strips 104 are disposed on the first electrode 102 and the second electrode 103.
  • the first electrode 102 and the second electrode 103 each include a portion corresponding to the plurality of spacer strips 104.
  • the second electrode 103 includes a plurality of second electrode strips 1031 disposed corresponding to a portion of the plurality of spacer strips.
  • a second electrode strip 1031 is disposed corresponding to each of the spacer strips 104 on the plurality of spacer strips 104.
  • the first electrode 102 is a planar electrode, but the shape of the first electrode is not limited thereto.
  • the first electrode 102 can also include a plurality of first electrode strips.
  • the first electrode 102 includes a plurality of first electrode strips corresponding to the plurality of spacer strips.
  • each sub-pixel 101 includes a first electrode 102 and a second electrode 103, and the first electrode 102 and the second electrode 103 may be disposed in the same layer. (as shown in Figures 4a and 4b) or a different layer arrangement (as shown in Figures 3a and 3b), a plurality of spacer strips 104 are disposed within each sub-pixel 101 on the substrate.
  • the first electrode 102 and the second electrode 103 are disposed over a layer on which the plurality of spacer strips 104 are located.
  • the first electrode 102 and the second electrode 103 each include a portion correspondingly disposed above the plurality of spacer strips 104.
  • a portion of the first electrode 102 and the second electrode 103 correspondingly disposed above the plurality of spacer strips 104 is a protrusion (protrusion) portion.
  • a portion of the first electrode 102 and the second electrode 103 correspondingly disposed above the plurality of spacer strips 104 is a protruding portion with respect to a portion not disposed above the plurality of spacer strips 104.
  • the first electrode is the pixel electrode 123
  • the second electrode is a common electrode
  • the first electrode is connected to the drain of the thin film transistor through the hole 113.
  • the first electrode is a common electrode
  • the second electrode is a pixel electrode 123
  • the second electrode is connected to a drain of the thin film transistor through the hole.
  • the array substrate provided in the first embodiment further includes a plurality of data lines 114 and a plurality of gate lines 115 disposed on the base substrate 100, a plurality of data lines 114 and a plurality of gates.
  • the lines 115 are insulated from each other, and the plurality of data lines 114 and the plurality of gate lines 115 intersect to define a plurality of sub-pixels 101 arranged in an array.
  • the sub-pixel 101 may be defined by a plurality of gate lines 115 and a plurality of data lines 114, but is not limited thereto.
  • One sub-pixel 101 includes, for example, a gate line, a data line, a pixel electrode, and a switching element.
  • the sub-pixel 101 is the smallest of the array substrates for display. unit.
  • the spacer strip 104 includes a linear shape, a polygonal line shape, or the like, and may have a shape of a wave shape, a zigzag shape, an arc shape, or the like.
  • the shape of the electrode strip corresponding to the plurality of spacer strips included in the first electrode and/or the second electrode corresponds to the shape of the plurality of spacer strips.
  • the plurality of spacer strips are a plurality of linear spacer strips disposed in parallel, and correspondingly, the first electrode and/or the second electrode may include a plurality of linear electrode strips disposed in parallel.
  • the direction in which the plurality of spacer strips 104 extend is parallel to the direction in which the data lines 115 extend.
  • the direction in which the plurality of spacer strips 104 extend is parallel to the direction in which the gate lines 114 extend.
  • the angle between the extending direction of the plurality of spacer strips and the extending direction of the gate lines or the data lines is an acute angle, or the plurality of spacer strips included in each sub-pixel include at least two groups, and the spacer strips in different groups
  • the direction of extension is different.
  • the first electrode and the second electrode on each set of spacer strips correspond to one domain.
  • the second electrode may be a slit electrode or a comb electrode, and each includes a plurality of second electrode strips.
  • the slit electrode can be, for example, as shown in Fig. 2a.
  • the pixel electrode 123 is a slit-shaped electrode and includes a plurality of slits 1232.
  • the electrode strips 1231 are between the adjacent two slits.
  • the first electrode can be a planar electrode as shown in Figure 3a. Or the first electrode may be a slit electrode or a comb electrode.
  • the plurality of comb teeth of the comb electrode are a plurality of electrode strips.
  • the first electrode and the second electrode may be comb electrodes, each of which includes a plurality of electrode strips.
  • the comb electrode can for example be as shown in Figure 2b.
  • the common electrode 122 and the pixel electrode 123 are both comb electrodes, the common electrode 122 includes a plurality of electrode strips 1221, and the pixel electrode 123 includes a plurality of electrode strips 1231.
  • a first insulating layer 105 is disposed between the first electrode and the second electrode, and the second electrode 103 is located at the first electrode 102.
  • the second electrode 103 includes a plurality of second electrode strips 1031, and in the layer in which the second electrode is located, at a position corresponding to the plurality of spacer strips 104, each interval is separated
  • the spacer 104 is provided with a second electrode strip 1031.
  • the first electrode is a planar electrode or the first electrode includes a plurality of first electrode strips.
  • the first In the case where the electrode includes a plurality of first electrode strips, as shown in FIG. 3c, in the layer in which the first electrode 102 is located, at a position corresponding to the plurality of spacer strips 104, a first spacer strip 104 is disposed first.
  • the electrode strips, and the adjacent two spacer strips respectively correspond to the first electrode strip of the first electrode and the second electrode strip of the second electrode, but are not limited thereto.
  • the first electrode 102 and the second electrode 103 are disposed in the same layer, in each sub-pixel 101, the first electrode 102 includes a plurality of first electrode strips 1021, and the second electrode 103 includes a plurality of
  • the second electrode strip 1031 has a first electrode strip 1021 and a second electrode strip 1031 alternately disposed at a position corresponding to the plurality of spacer strips 104 in a layer where the first electrode and the second electrode are located, as shown in FIG. 4a. .
  • the first electrode strip 1021 and the second electrode strip 1031 are alternately disposed every other spacer strip 104 as shown in FIG. 4b.
  • the arrangement shown in Figure 4b facilitates the separation of two adjacent electrode strips.
  • the first electrode 102 and the second electrode 103 are in a cross section perpendicular to a plurality of spacer strips (for example, a plurality of spacer strips are disposed in parallel) 104.
  • the zigzag structure can be as shown in Figures 3a, 3b, 4a and 4b.
  • the first electrode 102 and/or the second electrode 103 have protrusions (protrusions) at positions corresponding to the respective spacer strips 104.
  • the cross section of the spacer strip includes any one of a trapezoidal shape, a triangular shape, a semicircular shape, a stepped shape, and a mountain shape. This is not limited.
  • the cross section of the spacer strip is trapezoidal as an example.
  • the array substrate provided in the first embodiment further includes a second insulating layer 106 and a gate insulating layer 107.
  • the second insulating layer 106 is located above the gate insulating layer 107 and under the first electrode 102 and the second electrode 103, and the plurality of spacer strips 104 are formed by a portion of the second insulating layer 106. That is, the plurality of spacer strips are formed of a film forming the second insulating layer.
  • the array substrate provided in the example of the embodiment further includes a plurality of thin film transistors 112.
  • each of the thin film transistors includes a gate electrode 108, a gate insulating layer 107, an active layer 109, a source 110, and a drain 111.
  • the gate insulating layer 107 is located under the first electrode 102 and the second electrode 103.
  • a plurality of spacer strips 104 may be formed through a portion of the gate insulating layer 107.
  • the plurality of spacer strips 104 in FIG. 3a are replaced by a portion of the gate insulating layer 107. That is, a plurality of spacer strips are formed of a thin film forming a gate insulating layer.
  • the present embodiment provides a display panel, as shown in FIG. 5, including the array substrate 10 of any of the first embodiments.
  • the display panel further includes an opposite substrate 20, and the opposite substrate is disposed opposite to the array substrate.
  • the opposite substrate and the array substrate are respectively upper and lower substrates of the display panel, and a thin film transistor is generally formed on the array substrate.
  • a display structure such as an array forms a color resin on the opposite substrate.
  • the opposite substrate is a color film substrate.
  • a black matrix 202 and a color film 201 are provided on the opposite substrate 20.
  • a liquid crystal layer 30 is provided between the array substrate 10 and the counter substrate 20.
  • the embodiment provides a display device, including the display panel of any of the second embodiment.
  • the display device may be a liquid crystal display and any display product or component such as a television, a digital camera, a mobile phone, a watch, a tablet, a notebook computer, a navigator, or the like including the display device.
  • a display product or component such as a television, a digital camera, a mobile phone, a watch, a tablet, a notebook computer, a navigator, or the like including the display device.
  • FIG. 6 is a schematic diagram of a horizontal electric field intensity distribution of a typical low power ADS technology TFT-LCD (for example, in the case where the pixel electrode and the common electrode as shown in FIG. 1 are each formed on a corresponding planar structure layer).
  • the horizontal electric field intensity distribution 131 on a typical technical pixel is shown by the dashed line in FIG.
  • the horizontal electric field is the weakest and the transmittance is relatively small, which ultimately affects the transmittance of the entire panel.
  • the w1 and w2 width corresponding regions are regions where the horizontal electric field intensity is smaller than the reference electric field intensity value (Eth), and in order to achieve high transmittance, w1 and w2 widths are required to be as small as possible.
  • FIG. 7 is a schematic cross-sectional view showing a pixel of a low power consumption ADS type TFT-LCD according to an embodiment of the present invention.
  • the array substrate structure thereof may be as shown in FIG. 3a, but is not limited thereto.
  • the horizontal electric field intensity distribution 132 on the pixel of the embodiment of the present invention is shown by the upper solid line in FIG.
  • the dashed line in Figure 7 is the horizontal electric field strength distribution 131 on a typical technical pixel.
  • Eth reference electric field intensity value
  • the corresponding horizontal electric field intensity on the upper region is smaller than the reference electric field intensity value Eth (w1, w2). In the entire pixel region, the horizontal electric field intensity is greater, and the transmittance of the pixel is thus greatly improved.
  • the cross section of the pixel electrode and the common electrode in a direction perpendicular to the plurality of spacer strips has a zigzag structure.
  • the array substrate of the structure can enhance the horizontal electric field in the pixel region, suppress the longitudinal electric field, and reduce the area of the intermediate region between the electrode strips of the pixel electrode and the intermediate region between the electrode strips having a weak horizontal electric field region, thereby Increase transmission rate.
  • the storage capacitance between the pixel electrode and the common electrode can also be increased.
  • the area where the horizontal electric field intensity is less than the reference electric field intensity value (Eth) may be correspondingly reduced, in the entire pixel area. Inside, the horizontal electric field intensity is greater, and the transmittance of the pixel is thus greatly improved.
  • Embodiments of the present invention enhance the horizontal electric field by suppressing the longitudinal electric field by forming a spacer strip for the pixel electrode and/or the common electrode protrusion on the array substrate, thereby increasing the transmittance.
  • the number of electrode strips and electrode strips included in the electrode strip, the second electrode (pixel electrode) included in the first electrode (common electrode) in the drawings of the embodiments of the present invention is not limited to the number described in the drawing. .
  • the shapes of the first electrode (common electrode) and the second electrode (pixel electrode) are also not limited to the shapes described in the drawings.
  • each of the sub-pixels included in the array substrate may include a plurality of spacer strips, or some of the sub-pixels included in the array substrate may include A plurality of spacer strips are not limited thereto.

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Abstract

一种阵列基板、显示面板以及显示装置。该阵列基板包括衬底基板(100)以及设置在衬底基板(100)上的多个子像素(101)，各子像素(101)包括第一电极(102)、第二电极(103)和多个隔垫条(104)，多个隔垫条(104)设置在第一电极(102)和第二电极(103)的下方。通过在阵列基板上形成让像素电极和公共电极突起的隔垫条，来增强水平电场，抑制纵向电场，从而提高透过率。

Description

阵列基板、显示面板以及显示装置 技术领域
本发明至少一实施例涉及一种阵列基板、显示面板以及显示装置。
背景技术
薄膜晶体管液晶显示器(Thin Film Transistor Liquid Crystal Display，TFT-LCD)，其基本结构包括阵列基板(Array Substrate)、彩膜基板(Color Filter Substrate)、以及夹设在两片基板之间的液晶(Liquid Crystal)层。显示器件中还包括用于控制液晶偏转的像素电极和公共电极。通常的TFT-LCD中，通过控制液晶分子的偏转，从而实现对光线强弱的控制，然后通过彩膜基板的滤光作用，实现彩色图像显示。
TFT-LCD包括面内开关(In-Plane Switching，IPS)模式和高级超维场(Advanced-super Dimensional Switching，ADS)模式。在IPS模式和ADS中，通过像素电极或公共电极边缘所产生的平行电场以及像素电极与公共电极间产生的纵向电场形成多维电场，使液晶盒内像素电极或公共电极之间、像素电极或公共电极正上方所有取向液晶分子都能够产生旋转转换，从而可提高平面取向系液晶工作效率并增大透光效率。
然而，随着技术的进步，消费者对电子产品的显示效果提出了更高的要求。人们不断追求显示器件可具有更好的显示效果，更高的透过率。
发明内容
本发明至少一实施例提供一种阵列基板、显示面板以及显示装置，通过在阵列基板上形成让像素电极和公共电极突起的隔垫条，来增强水平电场，抑制纵向电场，从而提高透过率。
本发明实施例提供一种阵列基板，包括衬底基板以及设置在所述衬底基板上的多个子像素，各所述子像素包括第一电极、第二电极和多个隔垫条，所述多个隔垫条设置在所述第一电极和所述第二电极的下方。
例如，在本发明一实施例提供的阵列基板中，所述隔垫条包括直线形、折线形、波浪形、锯齿形、弧形中的任意一种。
例如，在本发明一实施例提供的阵列基板中，所述多个隔垫条为多个平行设置的直线形隔垫条。
例如，在本发明一实施例提供的阵列基板中，各所述子像素内，所述第一电极和所述第二电极均包括对应设置在所述多个隔垫条之上的部分。
例如，在本发明一实施例提供的阵列基板中，所述第一电极和所述第二电极对应设置在所述多个隔垫条之上的部分为突起部分。
例如，在本发明一实施例提供的阵列基板中，所述第一电极和所述第二电极异层设置，所述第一电极和所述第二电极之间设置第一绝缘层，所述第二电极位于所述第一电极之上，在各所述子像素内，所述第二电极包括多个第二电极条，并且在所述第二电极所在的层中，对应所述多个隔垫条的位置处，每间隔一个所述隔垫条设置一个所述第二电极条。
例如，在本发明一实施例提供的阵列基板中，所述第一电极为面状电极或者所述第一电极包括多个第一电极条；
所述第一电极包括多个第一电极条的情况下，在所述第一电极所在的层中，对应所述多个隔垫条的位置处，每间隔一个所述隔垫条设置一个所述第一电极条，并且，相邻两个隔垫条分别对应所述第一电极条和所述第二电极条。
例如，在本发明一实施例提供的阵列基板中，所述第二电极为狭缝状电极或梳状电极。
例如，在本发明一实施例提供的阵列基板中，所述第一电极和所述第二电极同层设置，在各所述子像素内，所述第一电极包括多个第一电极条，所述第二电极包括多个第二电极条，在所述第一电极和所述第二电极所在的层中，对应所述多个隔垫条的位置处，交替设置或每隔一个所述隔垫条交替设置所述第一电极条和所述第二电极条。
例如，在本发明一实施例提供的阵列基板中，所述第一电极和所述第二电极在沿垂直于所述多个隔垫条的方向上的截面呈锯齿形结构。
例如，在本发明一实施例提供的阵列基板中，所述隔垫条的截面包括梯形、三角形、半圆形、台阶形、山峰形中的任意一种。
例如，本发明一实施例提供的阵列基板还包括第二绝缘层和栅极绝缘层，所述第二绝缘层位于所述栅极绝缘层之上并且位于所述第一电极和所述第二 电极之下，所述多个隔垫条通过所述第二绝缘层的一部分来形成。
例如，本发明一实施例提供的阵列基板还包括栅极绝缘层，所述栅极绝缘层位于所述第一电极和所述第二电极之下，所述多个隔垫条通过所述栅极绝缘层的一部分来形成。
例如，本发明一实施例提供的阵列基板还包括设置在所述衬底基板上的多条数据线和多条栅线，各所述子像素包括的所述多个隔垫条的延伸方向平行于所述栅线或所述数据线的延伸方向，或者所述多个隔垫条的延伸方向与所述栅线或所述数据线的延伸方向的夹角为锐角，或者各所述子像素包括的所述多个隔垫条包括至少两个组，不同组中的隔垫条的延伸方向不同。
例如，在本发明一实施例提供的阵列基板中，所述多条数据线和所述多条栅线交叉限定多个呈阵列排列的所述多个子像素。
本发明至少一实施例还提供一种显示面板，包括任一上述的阵列基板。
本发明至少一实施例还提供一种显示装置，包括任一上述的显示面板。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为一种ADS模式阵列基板示意图；
图2a为本发明一实施例提供的一种阵列基板示意图；
图2b为本发明一实施例提供的一种阵列基板中像素电极和公共电极示意图；
图2c为本发明一实施例提供的一种阵列基板中直线形隔垫条的示意图；
图2d为本发明一实施例提供的一种阵列基板中折线形隔垫条的示意图；
图3a为一种图2a中阵列基板A-A’示意图(ADS模式)；
图3b本发明一实施例提供的一种阵列基板剖面示意图(ADS模式)；
图3c为一种图2a中第一电极和第二电极均包括多个电极条的阵列基板的A-A’示意图(ADS模式)；
图4a为另一种图2a中阵列基板A-A’示意图(IPS模式)；
图4b为图2a中IPS模式阵列基板中每隔一个隔垫条交替设置第一电极 条和第二电极条的A-A’示意图；
图5为本发明一实施例提供的一种显示面板示意图；
图6为一种显示面板水平电场强度分布示意图；
图7为本发明一实施例提供的一种显示面板水平电场强度分布示意图；
图8为本发明另一实施例提供的一种显示面板水平电场强度分布示意图。
附图标记：
10-阵列基板；20-对置基板；100-阵列基板的衬底基板；101-子像素；102-第一电极；1021-第一电极条(第一电极的电极条)；103-第二电极；1031-第二电极条(第二电极的电极条)；104-隔垫条；105-第一绝缘层；106-第二绝缘层；107-栅极绝缘层；108-栅极；109-有源层；110-源极；111-漏极；112-薄膜晶体管；113-过孔；114-数据线；115-栅线；122-公共电极；1221-公共电极的电极条；123-像素电极；1231-像素电极的电极条；1232-像素电极的狭缝；131-通常技术中显示面板内水平电场强度分布；132-本发明实施例显示面板内水平电场强度分布；200-对置基板的衬底基板；201-彩膜层；202-黑矩阵；30-液晶层。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
对于通常的低功耗ADS技术，像素电极和公共电极各自形成在相应的平面结构层上。例如，像素电极为狭缝状电极，公共电极为面状电极的情况下，像素电极与公共电极的电势差所形成的边缘电场包括两个分量，一个是有利于液晶水平方向偏转的水平电场，另一个是起干扰作用的纵向电场。在像素电极狭缝上的中间区域，以及各个狭缝之间的中间区域，水平电场较弱，纵向电场较强，导致透过率相应较小，并且最终影响整个液晶面板的透过率。需要说明的是，亦可公共电极为狭缝状电极，像素电极为面状电极。此情况 下，在公共电极狭缝上的中间区域，以及各个狭缝之间的中间区域，水平电场较弱，纵向电场较强，亦可导致透过率相应较小，并且最终影响整个液晶面板的透过率。
对于通常的IPS技术，像素电极和公共电极形成在同一平面结构层上。例如，像素电极和公共电极均包括多个电极条，像素电极与公共电极的电势差所形成的边缘电场包括两个分量，一个是有利于液晶水平方向偏转的水平电场，另一个是起干扰作用的纵向电场。在像素电极的每个电极条的中间区域和公共电极的每个电极条的中间区域，水平电场较弱，纵向电场较强，导致透过率相应较小，并且最终影响整个液晶面板的透过率。
例如，如图1所示，为一种ADS模式的阵列基板的局部剖视图，衬底基板100上设置有栅极108。栅极108所在的层之上设置栅极绝缘层107。栅极绝缘层107上设置有源层109。有源层109上设置源极110和漏极111。源极110和漏极111均与有源层109相连，源极110和漏极111分设在有源层109的两侧。源极110和漏极111之间具有间隔以界定沟道区域。薄膜晶体管包括栅极108、栅极绝缘层107、有源层109、源极110和漏极111。在源极110和漏极111所在的层之上设置第二绝缘层106。在第二绝缘层106上设置第一电极102。在第一电极102所在的层之上设置第一绝缘层105。第一绝缘层105上设置第二电极103。第二电极103包括多个第二电极条1031。第二电极103通过过孔113与薄膜晶体管的漏极111相连。例如，第二电极103可以为像素电极，相应的，第一电极102为公共电极。第一电极102和第二电极103均设置在平面结构上。通过控制像素电极与公共电极形成的电势差，实现水平电场驱动。
随着显示面板市场的不断发展，高PPI(Pixel Per Inch)产品成为显示产品发展的重要方向。然而高PPI产品意味着像素更小，这对像素的存储电容提出了更大的要求。虽然可以将第一绝缘层105薄化来提高存储电容，但这样大大降低第一绝缘层对线路的保护功能。
以下通过几个具体的实施例进行说明。
实施例一
本实施例提供一种阵列基板，如图2a所示，其包括衬底基板100以及设置在衬底基板100上的多个按阵列排布的子像素101。
如图3a、3b、4a和4b所示，各子像素包括第一电极102、第二电极103和多个隔垫条104，多个隔垫条104设置在第一电极102和第二电极103的下方。
例如，本实施例的一个示例中，如图3a、3b所示，各子像素内，第一电极102和第二电极103均包括与多个隔垫条104对应的部分。第二电极103包括与多个隔垫条中的部分隔垫条对应设置的多个第二电极条1031。例如，在多个隔垫条104上每间隔一个隔垫条104对应设置一个第二电极条1031。第一电极102为面状电极，但第一电极的形状不限于此。例如，第一电极102也可包括多个第一电极条。例如，第一电极102包括与多个隔垫条对应的多个第一电极条。
例如，本实施例的一个示例中，如图3a、3b、4a和4b所示，各子像素101包括第一电极102和第二电极103，第一电极102和第二电极103可同层设置(如图4a和4b所示)或者异层设置(如图3a和3b所示)，在衬底基板上各子像素101内设置有多个隔垫条104。第一电极102和第二电极103设置在多个隔垫条104所在的层之上。第一电极102和第二电极103均包括对应设置在多个隔垫条104之上的部分。例如，第一电极102和第二电极103对应设置在多个隔垫条104之上的部分为突起(凸起)部分。例如，第一电极102和第二电极103对应设置在多个隔垫条104之上的部分相对于未设置在多个隔垫条104之上的部分为突起部分。
例如，如图2a所示，第一电极为像素电极123，则第二电极为公共电极，第一电极经过孔113与薄膜晶体管的漏极相连。
例如，第一电极为公共电极，第二电极为像素电极123，第二电极经过孔与薄膜晶体管的漏极相连。
例如，如图2a-2d所示，本实施例一示例提供的阵列基板还包括设置在衬底基板100上的多条数据线114和多条栅线115，多条数据线114和多条栅线115相互绝缘，多条数据线114和多条栅线115交叉限定多个呈阵列排列的子像素101。
需要说明的是，子像素101可以由多条栅线115和多条数据线114限定而得，但不限于此。一个子像素101例如包括一条栅线、一条数据线、一个像素电极和一个开关元件。子像素101为阵列基板中最小的用以进行显示的 单元。
例如，如图2c-2d所示，隔垫条104包括直线形、折线形等形状，亦可以为波浪形、锯齿形、弧形等形状。对此不作限定。相应的，第一电极和/或第二电极包括的与多个隔垫条对应的电极条的形状与多个隔垫条的形状相对应。例如，多个隔垫条为多个平行设置的直线形隔垫条，相应的，第一电极和/或第二电极可包括多个平行设置的直线形电极条。
例如，如图2c所示，多个隔垫条104的延伸方向平行于数据线115的延伸方向。亦可多个隔垫条104的延伸方向平行于栅线114的延伸方向。当然，亦可为其它任意方向。例如，多个隔垫条的延伸方向与栅线或数据线的延伸方向的夹角为锐角，或者各子像素包括的多个隔垫条包括至少两个组，不同组中的隔垫条的延伸方向不同。例如，每组隔垫条上的第一电极和第二电极对应一个畴。
例如，在本实施例一示例提供的阵列基板中，第一电极和第二电极异层设置的情况下，第二电极可为狭缝状电极或梳状电极，均包括多个第二电极条。狭缝状电极例如可如图2a所示。图2a中，像素电极123为狭缝状电极，包括多个狭缝1232，相邻两个狭缝之间为电极条1231。第一电极可为面状电极，如图3a所示。或者第一电极可为狭缝状电极或梳状电极。梳状电极的多个梳齿即为多个电极条。
例如，在本实施例一示例提供的阵列基板中，第一电极和第二电极同层设置的情况下，第一电极和第二电极可为梳状电极，均包括多个电极条。梳状电极例如可如图2b所示。图2b中，公共电极122和像素电极123均为梳状电极，公共电极122包括多个电极条1221，像素电极123包括多个电极条1231。
如图3a、3b所示，第一电极102和第二电极103异层设置的情况下，第一电极和第二电极之间设置第一绝缘层105，第二电极103位于第一电极102所在的层之上，在各子像素101内，第二电极103包括多个第二电极条1031，并且在第二电极所在的层中，对应多个隔垫条104的位置处，每间隔一个隔垫条104设置一个第二电极条1031。
例如，在本实施例一示例提供的阵列基板中，第一电极和第二电极异层设置的情况下，第一电极为面状电极或第一电极包括多个第一电极条。第一 电极包括多个第一电极条的情况下，如图3c所示，在第一电极102所在的层中，对应多个隔垫条104的位置处，每间隔一个隔垫条104设置一个第一电极条，并且，相邻两个隔垫条分别对应第一电极的第一电极条和第二电极的第二电极条，但不限于此。
如图4a、4b所示，第一电极102和第二电极103同层设置的情况下，在各子像素101内，第一电极102包括多个第一电极条1021，第二电极103包括多个第二电极条1031，在第一电极和第二电极所在的层中，对应多个隔垫条104的位置处，交替设置第一电极条1021和第二电极条1031，如图4a所示。或者，每隔一个隔垫条104交替设置第一电极条1021和第二电极条1031，如图4b所示。图4b所示的设置方式有利于隔开相邻的两个电极条。
例如，在本实施例一示例提供的阵列基板中，第一电极102和第二电极103在沿垂直于多个隔垫条(例如，多个隔垫条平行设置)104的方向上的截面呈锯齿形结构，可如图3a、3b、4a和4b所示。例如，第一电极102和/或第二电极103在对应各隔垫条104的位置处具有突起(凸起)。
例如，在本实施例一示例提供的阵列基板中，隔垫条的截面包括梯形、三角形、半圆形、台阶形、山峰形中的任意一种。对此不作限定。本发明各实施例中以隔垫条的截面为梯形为例进行说明。
例如，如图3a、3b、4a和4b所示，本实施例一示例提供的阵列基板还包括第二绝缘层106和栅极绝缘层107。第二绝缘层106位于栅极绝缘层107之上并且位于第一电极102和第二电极103之下，多个隔垫条104通过第二绝缘层106的一部分来形成。即，多个隔垫条由形成第二绝缘层的薄膜来形成。
例如，如图2a所示，本实施例一示例提供的阵列基板还包括多个薄膜晶体管112。
如图3b所示，每个薄膜晶体管包括栅极108、栅极绝缘层107、有源层109、源极110和漏极111。
如图3a、3b、4a和4b所示，栅极绝缘层107位于第一电极102和第二电极103之下。多个隔垫条104可通过栅极绝缘层107的一部分来形成。例如，图3a中的多个隔垫条104替换为通过栅极绝缘层107的一部分来形成。即，多个隔垫条由形成栅极绝缘层的薄膜来形成。
实施例二
本实施例提供一种显示面板，如图5所示，包括任一实施例一所述的阵列基板10。
例如，如图5所示，显示面板还包括对置基板20，对置基板与阵列基板相对设置，对置基板和阵列基板分别为显示面板的上下两个基板，通常在阵列基板上形成薄膜晶体管阵列等显示结构，在对置基板上形成彩色树脂。
例如，对置基板为彩膜基板。例如，在对置基板20上设置有黑矩阵202和彩膜201。在阵列基板10和对置基板20之间设置有液晶层30。
实施例三
本实施例提供一种显示装置，包括任一实施例二所述的显示面板。
例如，所述显示装置可以为液晶显示器以及包括这些显示器件的电视、数码相机、手机、手表、平板电脑、笔记本电脑、导航仪等任何具有显示功能的产品或者部件。
以下对包含本发明各实施例提供的阵列基板的显示面板透过率提高的原因进行描述。
图6为通常的低功耗ADS技术TFT-LCD水平电场强度分布示意图(例如，如图1所示的像素电极和公共电极各自形成在相应的平面结构层上的情况下)。通常技术像素上的水平电场强度分布131如图6中虚线所示。在像素电极的电极条上的中间区域，以及各个电极条之间的中间区域，水平电场最弱，透过率相应较小，最终影响整个面板的透过率。在图6中，w1和w2宽度对应区域即为水平电场强度小于参考电场强度值(Eth)的区域，为了实现高透过率，需要w1和w2宽度尽量小。
图7为本发明实施例低功耗ADS型TFT-LCD像素截面示意图。例如，其阵列基板结构可如图3a所示，但不限于此。本发明实施例像素上的水平电场强度分布132如图7中最上方的实线所示。图7中的虚线为通常技术像素上的水平电场强度分布131。在相同的电压条件下，在像素电极的电极条的中间区域，以及各个电极条之间的中间区域，水平电场强度小于参考电场强度值Eth的区域(w1’、w2’)明显小于通常技术像素上的对应的水平电场强度小于参考电场强度值Eth的区域(w1、w2)。在整个像素区内，水平电场强度更大，像素的透过率也因此具有较大的提升。
像素电极与公共电极沿垂直于多个隔垫条的方向上的截面呈锯齿形结构。该结构的阵列基板可以增强像素区内的水平方向电场，抑制纵向电场，同时减小像素电极各个电极条的中间区域和各电极条之间的中间区域的具有较弱水平电场区域的面积，从而提高透过率。
另外，因像素电极与公共电极呈锯齿形结构，还可以增加像素电极与公共电极之间的存储电容。
与此类似，如图8所示，包括本发明实施例提供的阵列基板的IPS模式的显示面板中，也可以相应减小水平电场强度小于参考电场强度值(Eth)的区域，在整个像素区内，水平电场强度更大，像素的透过率也因此具有较大的提升。
本发明的实施例通过在阵列基板上形成让像素电极和/或公共电极突起的隔垫条，来增强水平电场，抑制纵向电场，从而提高透过率。
有以下几点需要说明：
(1)除非另作定义，此处使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“多个”例如表示大于一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
(2)本发明各实施例及其附图中，只涉及到与本发明实施例涉及到的结构，其他结构可参考通常设计。
(3)为了清晰起见，在用于描述本发明的实施例的附图中，层或区域的厚度被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
(4)本发明各实施例附图中的第一电极(公共电极)包括的电极条、第二电极(像素电极)包括的电极条以及隔垫条的数量不以图中描述的数量为限。第一电极(公共电极)、第二电极(像素电极)的形状也不限于图中描述的形状。
(5)本公开的阵列基板中，可以该阵列基板包括的全部的子像素中的每个子像素均包括多个隔垫条，也可以该阵列基板包括的全部的子像素中的部分子像素包括多个隔垫条，对此不作限定。
(6)在不冲突的情况下，本发明的实施例及实施例中的特征可以相互组合。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。
本专利申请要求于2015年7月7日递交的中国专利申请第201510393397.X号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (17)

  1. 一种阵列基板，包括衬底基板以及设置在所述衬底基板上的多个子像素，其中，各所述子像素包括第一电极、第二电极和多个隔垫条，所述多个隔垫条设置在所述第一电极和所述第二电极的下方。
  2. 根据权利要求1所述的阵列基板，其中，所述隔垫条包括直线形、折线形、波浪形、锯齿形、弧形中的任意一种。
  3. 根据权利要求1或2所述的阵列基板，其中，所述多个隔垫条为多个平行设置的直线形隔垫条。
  4. 根据权利要求1-3任一项所述的阵列基板，其中，各所述子像素内，所述第一电极和所述第二电极均包括对应设置在所述多个隔垫条之上的部分。
  5. 根据权利要求4所述的阵列基板，其中，所述第一电极和所述第二电极对应设置在所述多个隔垫条之上的部分为突起部分。
  6. 根据权利要求1-5任一项所述的阵列基板，其中，所述第一电极和所述第二电极异层设置，所述第一电极和所述第二电极之间设置第一绝缘层，所述第二电极位于所述第一电极之上，在各所述子像素内，所述第二电极包括多个第二电极条，并且在所述第二电极所在的层中，对应所述多个隔垫条的位置处，每间隔一个所述隔垫条设置一个所述第二电极条。
  7. 根据权利要求6所述的阵列基板，其中，所述第一电极为面状电极或者所述第一电极包括多个第一电极条；
    所述第一电极包括多个第一电极条的情况下，在所述第一电极所在的层中，对应所述多个隔垫条的位置处，每间隔一个所述隔垫条设置一个所述第一电极条，并且，相邻两个隔垫条分别对应所述第一电极条和所述第二电极条。
  8. 根据权利要求1-7任一项所述的阵列基板，其中，所述第二电极为狭缝状电极或梳状电极。
  9. 根据权利要求1-5任一项所述的阵列基板，其中，所述第一电极和所述第二电极同层设置，在各所述子像素内，所述第一电极包括多个第一电极条，所述第二电极包括多个第二电极条，在所述第一电极和所述第二电极所 在的层中，对应所述多个隔垫条的位置处，交替设置或每隔一个所述隔垫条交替设置所述第一电极条和所述第二电极条。
  10. 根据权利要求1-9任一项所述的阵列基板，其中，所述第一电极和所述第二电极在沿垂直于所述多个隔垫条的方向上的截面呈锯齿形结构。
  11. 根据权利要求1-10任一项所述的阵列基板，其中，所述隔垫条的截面包括梯形、三角形、半圆形、台阶形、山峰形中的任意一种。
  12. 根据权利要求1-11任一项所述的阵列基板，还包括第二绝缘层和栅极绝缘层，其中，所述第二绝缘层位于所述栅极绝缘层之上并且位于所述第一电极和所述第二电极之下，所述多个隔垫条通过所述第二绝缘层的一部分来形成。
  13. 根据权利要求1-11任一项所述的阵列基板，还包括栅极绝缘层，其中，所述栅极绝缘层位于所述第一电极和所述第二电极之下，所述多个隔垫条通过所述栅极绝缘层的一部分来形成。
  14. 根据权利要求1-13任一项所述的阵列基板，还包括设置在所述衬底基板上的多条数据线和多条栅线，各所述子像素包括的所述多个隔垫条的延伸方向平行于所述栅线或所述数据线的延伸方向，或者所述多个隔垫条的延伸方向与所述栅线或所述数据线的延伸方向的夹角为锐角，或者各所述子像素包括的所述多个隔垫条包括至少两个组，不同组中的隔垫条的延伸方向不同。
  15. 根据权利要求14所述的阵列基板，其中，所述多条数据线和所述多条栅线交叉限定多个呈阵列排列的所述多个子像素。
  16. 一种显示面板，包括权利要求1-15任一项所述的阵列基板。
  17. 一种显示装置，包括权利要求16所述的显示面板。
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