WO2016197600A1 - 一种通过内存总线访问的存储装置 - Google Patents

一种通过内存总线访问的存储装置 Download PDF

Info

Publication number
WO2016197600A1
WO2016197600A1 PCT/CN2016/070062 CN2016070062W WO2016197600A1 WO 2016197600 A1 WO2016197600 A1 WO 2016197600A1 CN 2016070062 W CN2016070062 W CN 2016070062W WO 2016197600 A1 WO2016197600 A1 WO 2016197600A1
Authority
WO
WIPO (PCT)
Prior art keywords
register
read
command
interface
cpu
Prior art date
Application number
PCT/CN2016/070062
Other languages
English (en)
French (fr)
Inventor
李延松
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP16806498.8A priority Critical patent/EP3296883B1/en
Publication of WO2016197600A1 publication Critical patent/WO2016197600A1/zh
Priority to US15/834,016 priority patent/US10489320B2/en

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/062—Securing storage systems
    • G06F3/0622—Securing storage systems in relation to access
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G06F3/0688—Non-volatile semiconductor memory arrays
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/24—Interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/28—DMA
    • G06F2213/2806—Space or buffer allocation for DMA transfers

Definitions

  • the present invention relates to the field of communications technologies, and in particular, to a storage device accessed through a memory bus.
  • Video data is the main part, and large-capacity, high-performance storage systems are urgently needed to effectively save and quickly access such data.
  • SSDs use semiconductor non-volatile memory to store data.
  • non-volatile memory such as flash memory is used. It has advantages in performance, power consumption, and reliability, but it is costly. It is usually used as a cache for mechanical hard disks. With the continuous improvement of the semiconductor process, the cost of flash memory continues to decline, and sooner or later it will replace the mechanical hard disk.
  • SSD Solid State Drive
  • SATA Serial Advanced Technology Attachment
  • SAS Serial Attached Small Computer System Interface
  • the SATA or SAS cable is connected to the computer system and can be plugged directly into the hard drive slot on the server.
  • Solid state drives typically contain a controller, cache, and flash memory, and the controller is connected to the computer system via a SAS/SATA interface.
  • the cache is used to temporarily save the data to be written to the flash memory or the data read from the flash memory. It can also be used as the controller's memory to store the code and data required for its operation (there are cpu in the controller).
  • the flash memory is used to store all the data of the SSD and can accept the read and write access of the controller.
  • This form of solid state drive is bulky, and the bandwidth of the SAS/SATA interface generally does not exceed 6 Gbps, and the performance is low.
  • PCIe Peripheral Component Interconnect Express
  • the difference between the SSD and the SAS interface SSD is mainly related to the computer system.
  • the interfaces are different and the internal structure is basically the same. Since the PCIe interface has a signal rate of up to 8 Gbps and a bit width of 16 bits, the bandwidth is up to 128 Gbps and the delay is low.
  • This form of solid state drive is still large, and the computer system has fewer PCIe slots, which limits installation density and capacity.
  • the prior art adopts a memory strip type flash memory strip to solve the problem of the density and capacity of the solid state disc installation. Since it is directly mounted on the memory strip slot, the installation is simple, space saving, and storage density is high.
  • the CPU directly accesses the flash memory, that is, the CPU sends the target address and command to be accessed directly through the signal line in an access cycle, and the storage controller forwards the signal to the storage module, and the storage module receives the signal. And perform the appropriate action.
  • This access mode maps the memory modules on the storage device directly to the addressing space of the CPU, and thus is limited by the address space of the CPU.
  • the 300GB flash memory is used on a CPU with an address range of only 4GB, the actual use of the 300G flash memory will not exceed 4GB. If the address range of the CPU is 1TB, the total capacity of the SSD cannot exceed 1TB. This type of access limits the storage capacity in the device.
  • the embodiment of the present invention provides a storage device accessed through a memory bus.
  • the storage device mentioned in the present invention may include a phase change memory, a variable resistance memory, and the like in addition to the flash memory. Loss of storage media.
  • a storage device accessed through a memory bus includes an interface controller, a storage module, and a storage controller, wherein the device includes an interface controller and a storage module.
  • a memory controller the device further comprising a command register, a status register; and the interface controller is electrically connectable to a memory module interface of the computer system;
  • the interface controller is configured to receive an access command sent by the cpu to access the storage module;
  • the interface controller is configured to write the access command into the command register;
  • the storage controller is configured to use an access command according to the command register And performing corresponding read and write operations on the storage module.
  • the apparatus further includes a switching control register, a read buffer, and a write buffer; wherein the read buffer is configured to save read from the storage module
  • the write buffer is configured to save data to be written into the storage module;
  • the switch control register is configured to set an MRS command according to a mode register sent by the cpu, and perform corresponding on the storage module
  • switching between the command register and the read cache to electrically connect one of the command register and the read buffer to a memory module interface of the computer system, or in the command Switching between the register and the write cache electrically connects one of the command register and the write cache to a memory bank interface of the computer system.
  • the switching control register, the read buffer, the write cache, and the The command register is time-divisionally connected to the memory module interface of the computer system.
  • the read cache, the write cache, and the command register are searched for in the CPU
  • the starting address in the address space is the same.
  • the access command includes the logical block address that the cpu is to access the storage module.
  • the storage device further includes a status register, the status register is used to indicate Whether the current working state of the storage module is idle or busy; wherein the idle indicates that the storage module is not currently performing read and write operations, and the busy indicates that the storage module is currently performing read and write operations.
  • the storage device is installed in a memory module slot of the computer system
  • the storage device through which the interface controller passes is electrically connected to a memory module interface provided by the CPU.
  • the computer system further includes a dedicated controller
  • the storage device Installed in a memory module slot of the computer system the interface controller is electrically coupled to a memory module interface provided by a dedicated controller of the computer system.
  • the interface controller is coupled to the dedicated controller, A dedicated controller is connected to the CPU via a peripheral component interconnect PCI fast channel.
  • the device further includes an electrically erasable, programmable read only And a memory EEPROM, wherein the EEPROM includes a type identifier of the storage device, so that when the computer system is started, the CPU can identify, by the type identifier, a storage type of a storage device that the CPU is accessing.
  • the interface controller is further configured to read and write on the storage device. After the operation is completed, the cpu read/write operation is completed by the interrupt signal, and the interrupt signal is selected by the user according to a predetermined rule in the electrical signal corresponding to the memory module interface.
  • the memory module interface of the computer system includes DDR, DDR2, DDR3, or DDR4 interface.
  • a computer system comprising the implementation of any of the possible storage devices mentioned in the first aspect.
  • the storage device can be electrically connected to the memory module interface of the computer system, and the size is small, space is saved, and the number of devices that can be installed in the computer system is increased.
  • the installation density and storage capacity of the storage device direct access through the memory module interface, high bandwidth and less latency of cpu read and write data; by increasing the command register and status register, the storage data access space is no longer sought by the cpu.
  • the limit of the address space is
  • FIG. 1 is a schematic block diagram of an application of a flash memory module combined with specific hardware according to an embodiment of the present invention
  • FIG. 2 is a schematic diagram of a logical structure of a flash memory module according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram of a CPU assigning an address to a single flash memory module according to an embodiment of the present invention
  • FIG. 4 is a schematic diagram of a CPU assigning addresses to two flash modules according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of a format of a mode register according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of address overlap allocation of a flash memory module according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of an application block diagram of another flash memory module according to an embodiment of the present invention.
  • Embodiments of the present invention provide a storage device and system accessed through a memory bus.
  • the storage device mentioned in the present invention includes a non-volatile memory such as a flash memory, a phase change memory PCRAM, a variable resistance memory ReRAM, etc.; since the read and write operations of the memory in the computer system are similar, the specific implementation is In the process, the principle is equivalent and replacement, so in order to avoid redundant space, only the flash module is used as an example.
  • a non-volatile memory such as a flash memory, a phase change memory PCRAM, a variable resistance memory ReRAM, etc.
  • FIG. 1 is a schematic block diagram of a flash module application combined with specific hardware according to an embodiment of the present invention.
  • Common computer system structures include: cpu, memory, bridge, network card, BIOS, flash memory module, etc., which work together to complete the data processing of the computer.
  • each memory channel can support multiple memory modules.
  • an x86 processor supports 4 memory channels, and each channel supports up to 3 memory modules, so that a total of 12 memory modules can be supported. If the capacity of each memory bank is 16GB, then the total capacity is 192GB.
  • the interface of the memory module has been developed and updated for many years.
  • the mainstream is the double rate DDR3 (Double Data Rate 3) interface
  • the rate is up to 1.6GT/s
  • the data line width is 64 bits
  • the total bandwidth is (64*1.6).
  • /8 12.8GB/s
  • the DDR4 interface is also gaining popularity.
  • the following uses the memory module of the DDR3 interface as an example.
  • the DDR3 interface includes the following 18 sets of signals (the DDR3 memory stick has a total of 240 pins, ie, signal contacts):
  • the address signal A[0:15] is used to provide the address of the memory chip, such as the row address and the column address;
  • bank address used to select the logical bank inside the memory chip
  • bank can be understood to some extent as a sub-unit of the memory chip
  • CK0, CK0# differential clock, providing timing synchronization function for memory chip access
  • RAS#, CAS#, WE# are row strobe signals, column strobe signals and write signals, respectively, for combining into various operation command words;
  • SA[2:0] used to configure the electrically erasable, programmable read only memory EEPROM (Electrically Erasable and Programmable Read Only Memory) and I2C address of the temperature sensor;
  • power signal includes the memory chip's 1.5V core voltage, 0.75V reference voltage, 0.75V termination voltage and 3.3V EEPROM, temperature sensor operating voltage.
  • the flash memory module of the invention adopts the shape and interface signal of the memory bar, and can be directly inserted into the existing memory module socket, the hardware of the computer system does not need any modification, and only the software can be modified, which is specifically described below.
  • the flash module adopts a dual in-line memory module DIMM (Dual Inline Memory Module) shape similar to a memory module, and can be inserted into an existing memory module slot.
  • DIMM Dual Inline Memory Module
  • the flash module only needs to implement some necessary signals, such as address signals A[0:15], BA[2:0], data signal DQ[ 63:0], control signals CS[3:0]#, RAS#, CAS#, WE#, and power signals and clock signals, etc., and some signals are optional, such as check signal CB[7:0] , Par_In; can be connected to the signal contact, can be left floating, can also be connected but not used.
  • I2C bus interface on the memory stick, including SCL, SDA and address signals SA[2:0], which are used to connect the EEPROM and temperature sensor on the memory stick.
  • the former stores some parameters of the memory stick, such as memory type and memory stick. Specifications, storage capacity, data bus width, timing parameters, cache capacity parameters, etc., the latter is used to detect the temperature of the memory module, when the temperature exceeds the threshold, the alarm can be reported.
  • the flash memory module of the present invention also has an EEPROM thereon, and the saved information is basically the same, but since the module type is different from the memory stick, a value can be defined in the third byte (DRAM Device Type) of the EEPROM, for example, the type identifier of the DDR3 is 0x0B, the type identification of the flash memory can be defined as 0x10, which means flash memory; in the specific implementation process, the byte position and numerical definition of the EEPROM can be flexibly set.
  • the BIOS initializes the processor and peripheral devices, and the CPU can read the above values from the EEPROM of the flash module to identify whether it is a normal DDR3 memory stick or a flash memory module, and perform different processing. There will be instructions.
  • FIG. 2 is a logic structure of a flash memory module according to an embodiment of the present invention.
  • the logical structure of the flash module includes: interface controller, command register, status register, read/write cache, switch control register, flash controller, and flash memory.
  • the interface controller, switching control register, command/status register and flash controller can be integrated in the same chip.
  • the functions of each module are as follows.
  • the interface controller is connected to the memory bus, and the CPU issues various read/write commands according to the timing of the memory interface, the interface controller decodes the command, recognizes the read command, the write command or the mode register setting command, and combines the address and the data signal. Complete the corresponding read and write operations.
  • Command/status register generally two registers, the status register is read-only, the command register is write-only, they can share an address, the command register and the status register can be switched access; the status register and the command register can It is distinguished by read and write commands, so there is no need to occupy an additional address.
  • the contents of the status register are set by the flash controller on the flash module.
  • the content of the first command register includes the 48-bit logical block address (LBA) (used to provide an interface to the software, equivalent to a starting address). 16-bit read/write length (indicating how much data can be read and written).
  • LBA logical block address
  • 16-bit read/write length indicating how much data can be read and written.
  • the content of the second command register is an operation command, which can be selected to be consistent with the ATA command set.
  • Read Sector is 0x20
  • Read Multiple is 0xC4
  • Write Sector is 0x30
  • Write Multiple is 0xC5 and so on.
  • the status register including at least two bits, is used to save the working state of the flash module, such as busy or idle, data error or the like.
  • the read/write cache, the read cache and the write cache may be physically located in the same memory chip, or may be located in two different memory chips, both of which are time-sharing; they may belong to the same cache address space. This cache space can be read and written in a time-sharing manner; it is also possible to have multiple cache spaces.
  • the read/write cache is used to hold data to be written to the flash memory or data read from the flash memory.
  • the cache space is within the address space of the cpu, and the read/write cache and the command register are switched by the switch control register according to the command written by the cpu, and the address conversion is performed (the read/write address sent by the cpu is converted into the read/write cache). Corresponding address).
  • the device of the present invention may further include a switching control register, which is new in the present invention.
  • An additional register is used to control the switching between the command/status register and the read/write buffer.
  • the switching control register controls the multiplexer through the MRS command sent by the cpu, and at any time, the only one of the read buffer, the write cache, the command register, and the status register is connected to the memory module interface of the computer system;
  • the implementation is characterized by time-sharing between these caches and registers.
  • the read and write caches are generally the same address space, and the command register and the status register also have the same address space or partially overlapping address space.
  • the flash controller performs a corresponding operation on the flash memory according to the contents of the command register, and reads and stores the data of the flash memory in the read buffer for the read operation, and writes the contents of the write cache to the flash memory for the write operation. After the operation is completed, set the status bit of the status register. When the cpu queries the status register, it can know whether the operation is completed or not.
  • the flash controller also needs to complete the mapping of the LBA to the physical address of the flash memory, as well as the wear leveling and bad block management of the flash memory to ensure reliability.
  • Flash memory used to save data.
  • the address, the data length and the command are provided by the cpu to the command/status register, and the flash memory is indirectly accessed through the command/status register.
  • the command register has two 64-bit registers
  • the status register has one 64-bit register
  • the read and write cache also takes up a portion of the addressing space.
  • FIG. 3 is a schematic diagram of a case where a CPU allocates an address for a single flash memory module according to an embodiment of the present invention. If the address of the read and write cache is multiplexed, only 256MB of address space is needed.
  • FIG. 4 is a schematic diagram of a CPU assigning addresses to two flash modules according to an embodiment of the present invention.
  • This address allocation method makes the read/write cache address space of multiple flash modules discontinuous.
  • the address space of the command/status register must be skipped, which increases the complexity of the program design and affects the access. performance.
  • the solution of the present invention can perform time-sharing control through a switch control register, for example, cpu access at a certain time.
  • the command register or status register is accessed by the same address at the same time.
  • This switching control register preferably does not occupy the address space, so as to avoid the similar problem of the above mentioned read/write cache address discontinuity.
  • MRS Mode Register Set
  • This command is generated when the memory port interface signal shows a combination of "CS# is low, RAS# is low, CAS# is low, and WE# is low", and the address on the address bus is generated.
  • the signal is written to the mode register of the memory chip as data.
  • mode registers There are four mode registers, MR0, MR1, MR2 and MR3, which are used to configure different parameters (burst access mode, burst length selection, DLL enable control).
  • Each register has 17 The bits, from bit16 to bit0, correspond to BA2 (alternate), BA1, BA0, A13, A12...A0, respectively.
  • MRS Mode Register Settings
  • FIG. 5 is a schematic diagram of a format of a mode register according to an embodiment of the present invention.
  • the present invention only needs to use a mode register as a switching control register.
  • MR0 as an example, for example, setting bit 0 of MR0 to 0 indicates that the memory bank interface is connected to the command/status register, and setting bit 0 of MR0 to 1 indicates that the read/write buffer is turned on.
  • FIG. 6 is a schematic diagram of address overlap allocation of a flash memory module according to an embodiment of the present invention.
  • the switch control register is indicated by a dashed box to illustrate that it does not occupy the address space.
  • the final function to be implemented is that the CPU can read and write data operations; the following describes the communication flow of read operations and write operations in detail.
  • the CPU writes the starting LBA address, sector length and operation command of the flash module to be read into the command register, such as the address assigned by the cpu to the register on the flash bar is 0 to 15;
  • the flash controller receives and sets the flag bit in the status register to "busy” according to the command and address of the command register in (2), and then starts reading data from the flash memory and saving it to the read buffer.
  • the starting address is generally 0, but is not limited to 0;
  • the CPU sends the data to be written to the flash module to the write buffer, and the starting address is 0, but is not limited to 0;
  • the CPU writes the starting LBA address, sector length and operation command of the flash module to be written into the command register, such as the address assigned by the cpu to the register on the flash bar is 0 to 15;
  • the flash controller receives and sets the flag bit in the status register to "busy” according to the command and address of the write command register in (4), and then starts reading data from the write buffer and writing to the flash memory.
  • the starting address is 0, but not limited to 0;
  • the cpu will continuously read the status bit of the status register after issuing the write command, so when the cpu detects that the status changes from busy to idle, it is ready to perform the next write operation.
  • the selection of the mode register the selection of the bit in the mode register, the setting of the eigenvalue of the bit in the mode register, and the eigenvalue setting of the "busy" and "idle” in the status register are all available.
  • the user's needs and the characteristics of the computer used are flexibly selected and set.
  • the cpu determines whether the flash controller completes the read/write operation, and can continuously read the status bit of the status register or the interrupt mode by the above mentioned, which is beneficial to save the CPU time.
  • the interrupt signal can be determined according to the specific conditions of the user's use of the signal and their own needs. For example, there is an EVENT# signal on the memory module interface, which is used to refer to The temperature of the memory stick is turned low after the threshold is exceeded, and the present invention can use it as an interrupt signal.
  • the flash controller completes the read and write operations, on one hand, the flag of the status register is set to idle, and on the other hand, EVENT# is driven low to issue an interrupt to the CPU.
  • the CPU responds to the interrupt, it reads the status register of the flash module (different interrupt causes correspond to different bits), and can identify whether the interrupt is caused by the temperature exceeding the threshold or the flash controller has completed the read and write operations.
  • the module type is read from the EEPROM on the flash module when the BIOS starts. When the type is a flash module, it is not reported to the operating system as memory. Because the address of each flash module's command/status register overlaps with the read/write cache and does not occupy additional address space, the read/write cache addresses of multiple flash modules are contiguous if the first flash module
  • the read/write cache capacity is 512MB, and the second capacity is 1GB.
  • the first flash module has a read/write cache address range of 0 to 512MB-1, and the second address range is 512MB to 1.5GB-1. .
  • the first flash module has an address range of 0 to 15, and the second address range is 512MB to 512MB+15.
  • the BIOS can derive the respective read/write cache address range and address range of the command/status register by the number of flash modules and the cache capacity parameters stored in the EEPROM, so as to address when accessing the data of the flash module.
  • different flash modules When accessing different flash modules, different flash modules may be on different memory modules or channels, and each corresponds to one memory controller; or multiple memory controllers through the same memory module interface
  • the chip select signal CS# selects the corresponding flash module (for example, CS0# selects the first flash module, CS1# selects the second flash module), and accesses the memory module in the same way.
  • the structure of each flash module is the same, both have the structure of Figure 2.
  • the CPU handles the same data processing method for each flash module, except that the CPU first uses different chip select signals to different flash modules. To perform the above steps of the read and write operations.
  • the flash memory module can be connected to a dedicated controller.
  • FIG. 7 is an implementation of the present invention.
  • the dedicated controller in the computer system is connected to the CPU through the PCIe interface, and then connected to the flash module through the memory module interface. If the PCIe interface conforms to the PCIe 3.0 specification, the rate is 8 GT/s. When the bit width is 16 bits, the bandwidth is 16 GB/s, which is equivalent to 64-bit width.
  • the DDR3 interface at a rate of 1.6 GT/s has a high bandwidth and therefore does not become a performance bottleneck.
  • the LBA address, sector length, and read/write commands are sent to the dedicated controller through the PCIe interface, and the latter is forwarded to the flash module through the memory module interface.
  • the subsequent operations are the same as described above.
  • the flash memory module used in the invention adopts the outer shape structure of the memory stick, has a small size, saves space, and can be installed in the computer system, thereby increasing the installation density and the storage capacity of the flash memory; Access, bandwidth is larger, cpu read and write data delay is smaller; the structure of the flash module can be directly inserted into the memory slot, no other hardware, only need to modify the corresponding software; increase the command register by setting And the status register, so that the data access space of the flash memory is no longer limited by the address space provided by the cpu, the cpu only needs to provide a small number of register address space and a little read/write cache address space, such as providing address, data
  • the length and read and write commands to the command/status register allow indirect access to the flash via the command/status register; in addition, the "mode register set" command enables time-switched command/status registers and read/write buffers, as well as switching control registers Does not occupy the address space of the cpu itself, so that multiple flash modules

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Memory System (AREA)
  • Read Only Memory (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

公开了一种通过内存总线访问的存储装置。该装置包括接口控制器、存储模块、存储控制器、命令寄存器、状态寄存器、缓存；且接口控制器能够与计算机***的内存条接口电气连接；接口控制器接收cpu发送的访问存储模块的访问命令；接口控制器将访问命令写入命令寄存器并通过状态寄存器记录当前的访问状态或结果；存储控制器根据命令寄存器中的访问命令，对状态寄存器进行状态置位，并对存储模块执行相应的读写操作。本方案能够与计算机***的内存条接口电气连接，尺寸较小，节省空间，提高了存储装置的安装密度和存储容量，通过设置增加命令寄存器和状态寄存器，使得存储装置的数据访问空间不再受到cpu提供的寻址空间的限制。

Description

一种通过内存总线访问的存储装置 技术领域
本发明涉及通信技术领域，尤其涉及一种通过内存总线访问的存储装置。
背景技术
随着信息技术的发展，特别是互联网的普及，各种类型的数据量迅速增长，其中视频数据占主要部分，迫切需要大容量、高性能的存储***来有效保存和快速访问这些数据。
传统的机械硬盘虽然技术成熟、成本低、容量大，但是性能存在瓶颈，而且功耗较大，已经逐渐让位于固态硬盘。固态硬盘使用半导体非易失存储器来保存数据，目前使用的是闪存等非易失性存储器，在性能、功耗、可靠性方面具有优势，但是成本较高，通常作为机械硬盘的缓存使用，随着半导体工艺的不断改进，闪存的成本在持续下降，迟早会取代机械硬盘。
固态硬盘(SSD，Solid State Drive)常见的一种形态与机械硬盘类似，例如都采用SATA(Serial Advanced Technology Attachment)或SAS(Serial Attached Small Computer System Interface)接口，尺寸为2.5或3.5寸，可以通过SATA或SAS电缆与计算机***相连，也可以直接***服务器上的硬盘插槽。
固态硬盘通常包含控制器、缓存和闪存，控制器通过SAS/SATA接口与计算机***相连。缓存用来暂时保存待写入闪存的数据或者从闪存读出的数据，也可以作为控制器的内存保存它运行所需的代码和数据(控制器里面有cpu)。闪存作为存储介质用来保存固态硬盘的所有数据，能够接受控制器的读写访问。这种形态的固态硬盘体积较大，而且SAS/SATA接口的带宽一般不超过6Gbps，性能较低。
另一种常见的固态硬盘采用PCIe(Peripheral Component Interconnect express)插卡的形态，与上述SATA或SAS接口的固态硬盘的区别主要是与计算机***的 接口不同，而内部结构基本相同。由于PCIe接口的信号速率可达8Gbps，位宽可选16位，因此带宽可达128Gbps，而且延时低。这种形态的固态硬盘体积仍然较大，而且计算机***的PCIe插槽较少，限制了安装密度和容量的提升。
现有技术中，为了解决安装密度和容量小的问题，还采取了一种内存条式的固态硬盘，以实现在相同体积的服务器内，能装入更多的固态硬盘，进而增大存储容量。
现有技术采用了内存条式的闪存条来解决固态盘安装密度和容量的问题，由于直接安装在内存条插槽上，因此安装简便，而且节省空间，存储密度高。但是现有技术都是cpu直接访问闪存，即cpu在一个访问周期内，把要访问的目标地址、命令等通过信号线直接送出，存储控制器把这个信号转发给存储模块，存储模块接收这个信号并执行相应操作。这种访问方式把存储装置上的存储模块直接映射到cpu的寻址空间，因此会受限于cpu的寻址空间范围。例如300GB的闪存如果应用在寻址范围只有4GB的cpu上，那么300G闪存的实际使用不会超过4GB；再如若cpu的寻址范围是1TB，那么固态盘的总容量就不能超过1TB。这种访问方式使得设备中的存储容量受限。
发明内容
有鉴于此，本发明实施例提供了一种通过内存总线访问的存储装置，本发明中所提到的存储装置除了包括闪存之外，还可以包括相变存储器、可变电阻式存储器等非易失性存储介质。通过设置增加命令寄存器和状态寄存器，采用寄存器这样的间接访问方式，使得存储数据访问空间不再受到cpu提供的寻址空间的限制。
根据本发明实施例的第一方面，提供了一种通过内存总线访问的存储装置，上述装置包括接口控制器、存储模块、存储控制器，其特征在于，所述装置包括接口控制器、存储模块、存储控制器，其特征在于，所述装置还包括命令寄存器、状态寄存器；且所述接口控制器能够与计算机***的内存条接口电气连接；所述 接口控制器用于接收cpu发送的访问所述存储模块的访问命令；所述接口控制器用于将所述访问命令写入所述命令寄存器；所述存储控制器用于根据所述命令寄存器中的访问命令，对所述存储模块执行相应的读写操作。
结合第一方面，在第一方面的第一种可能的实现方式中，所述装置还包括切换控制寄存器、读缓存、写缓存；其中所述读缓存用于保存从所述存储模块中已读出的数据；所述写缓存用于保存待写入所述存储模块的数据；所述切换控制寄存器用于根据所述cpu发送的模式寄存器设置MRS命令，在所述对所述存储模块执行相应的读写操作过程中：在所述命令寄存器和所述读缓存中切换使所述命令寄存器和所述读缓存中的一个电气连接到所述计算机***的内存条接口上，或者在所述命令寄存器和所述写缓存中切换使所述命令寄存器和所述写缓存中的一个电气连接到所述计算机***的内存条接口上。
结合第一方面，或者结合第一方面的第一种可能的实现方式，在第一方面的第二种可能的实现方式中，所述切换控制寄存器将所述读缓存、所述写缓存和所述命令寄存器分时连接到所述计算机***的内存条接口上。
结合第一方面，或者结合第一方面的上述任何一种可能的实现方式，在第一方面的第三种可能的实现方式中，上述读缓存、上述写缓存、上述命令寄存器在上述cpu的寻址空间内的起始地址相同。
结合第一方面，或者结合第一方面的上述任何一种可能的实现方式，在第一方面的第四种可能的实现方式中，上述访问命令中包含上述cpu将要访问上述存储模块的逻辑块地址LBA地址、数据长度和读写命令。
结合第一方面，或者结合第一方面的上述任何一种可能的实现方式，在第一方面的第五种可能的实现方式中，所述存储装置还包括状态寄存器，所述状态寄存器用于指示所述存储模块当前的工作状态是空闲还是忙碌；其中所述空闲表示所述存储模块当前没有进行读写操作，所述忙碌表示所述存储模块当前正在进行读写操作。
结合第一方面，或者结合第一方面的上述任何一种可能的实现方式，在第一方面的第六种可能的实现方式中，所述存储装置安装在所述计算机***的内存条插槽内，所述接口控制器通过的所述存储装置与所述cpu提供的内存条接口电气连接。
结合第一方面，或者结合第一方面的上述任何一种可能的实现方式，在第一方面的第七种可能的实现方式中，当所述计算机***还包括专用控制器时，所述存储装置安装在所述计算机***的内存条插槽内，所述接口控制器与所述计算机***的专用控制器提供的内存条接口电气连接。
结合第一方面，或者结合第一方面的上述任何一种可能的实现方式，在第一方面的第八种可能的实现方式中，所述接口控制器连接在所述专用控制器上，所述专用控制器通过周边元件互联PCI快速通道与所述cpu连接。
结合第一方面，或者结合第一方面的上述任何一种可能的实现方式，在第一方面的第九种可能的实现方式中，所述装置中还包含可电擦除、可编程的只读存储器EEPROM，所述EEPROM中含有所述存储装置的类型标识，使得在计算机***启动时，所述cpu能够通过所述类型标识识别出所述cpu正在访问的存储装置的存储类型。
结合第一方面，或者结合第一方面的上述任何一种可能的实现方式，在第一方面的第十种可能的实现方式中，所述接口控制器还用于在所述存储装置的读写操作完成后，通过中断信号上报所述cpu读写操作完成；所述中断信号是用户根据预设规则在所述内存条接口对应的电气信号中选择出来的。
结合第一方面，或者结合第一方面的上述任何一种可能的实现方式，在第一方面的第十一种可能的实现方式中，上述计算机***的内存条接口包括DDR、DDR2、DDR3或DDR4接口。
根据本发明实施例的第二方面，提供了一种计算机***，上述***包括第一方面中提到的任意一种可能的存储装置的实现方式。
根据本发明实施例提供的技术方案，存储装置能够与计算机***的内存条接口电气连接，尺寸较小，节省空间，在计算机***内可以安装的数量更多，提高 了存储装置的安装密度和存储容量；通过内存条接口直接访问，带宽高且cpu读写数据延时更小；通过设置增加命令寄存器和状态寄存器，使得存储数据访问空间不再受到cpu提供的寻址空间的限制。
附图说明
图1为本发明实施例中一种结合具体硬件的闪存模块应用框图示意图；
图2为本发明实施例中一种闪存模块的逻辑结构示意图；
图3为本发明实施例中一种cpu为单个闪存模块分配地址的示意图；
图4为本发明实施例中一种cpu为两个闪存模块分配地址的示意图；
图5为本发明实施例中一种模式寄存器的格式示意图；
图6为本发明实施例中一种闪存模块的地址重叠分配的示意图；
图7为本发明实施例中另一种闪存模块的应用框图示意图。
具体实施方式
本发明实施例提供了一种通过内存总线访问的存储装置与***。
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分优选实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明中所提到的存储装置包括闪存、相变存储器PCRAM、可变电阻式存储器ReRAM等非易失性存储器；由于这几种存储器在计算机***中的读写操作原理相通，在具体实现的过程中多为原理的等同和替换，因此为了避免冗余的篇幅，下文中仅用闪存模块来举例。
如图1所示，图1为本发明实施例中一种结合具体硬件的闪存模块应用框图示意图。常见的计算机***结构中包括：cpu、内存、桥片、网卡、BIOS、闪存模块等，它们共同协作完成计算机的数据处理。
目前常见的cpu都集成了内存控制器，例如x86处理器，可以直接连接内存条。为了提高性能和内存容量，通常支持多个内存通道，每个内存通道又可以支持多个内存条。例如某款x86处理器支持4个内存通道，每个通道最多支持3个内存条，这样总共可以支持12个内存条。如果每个内存条的容量是16GB，那么总容量是192GB。
内存条的接口经过多年的发展和更新换代，目前主流的是双倍速率DDR3(Double Data Rate 3)接口，速率可达1.6GT/s，数据线宽度64位，总带宽为(64*1.6)/8＝12.8GB/s，而DDR4接口也正在普及中。下面以DDR3接口的内存条为例进行说明。
DDR3接口包括以下18组信号(DDR3内存条共有240个管脚，即信号触点)：
1、地址信号A[0:15]，用来提供内存芯片的地址，例如行地址和列地址；
2、BA[2:0]，bank地址，用来选择内存芯片内部的逻辑bank；bank在某种程度上可以理解为内存芯片的子单元；
3、CK0，CK0#，差分时钟，提供内存芯片访问的时序同步功能；
4、CKE[0:1]，时钟使能信号；
5、ODT[0:1]，信号端接使能信号；
6、Par_In，地址信号、写信号WE#、行选通信号RAS#、列选通信号CAS#的校验位；
7、RAS#、CAS#、WE#，分别是行选通信号、列选通信号和写信号，用来组合成各种操作命令字；
8、RESET#，复位信号；
9、CS[3:0]#，片选信号；
10、SA[2:0]：用来配置内存条上的可电擦除、可编程的只读存储器EEPROM(Electrically Erasable and Programmable Read Only Memory)和温度传感器的I2C地址；
11、SCL，SDA，I2C总线信号，连接内存条上的EEPROM和温度传感器；
12、CB[7:0]，数据校验信号；
13、DQ[63:0],数据信号；
14、DQS[8:0]，DQS[8:0]#，数据选通信号；
15、DM[8:0]，数据屏蔽信号；
16、Err_Out#，低电平表示地址和命令信号校验出错；
17、EVENT#，低电平表示内存条的温度超出了门限；
18、电源和地，电源信号包括内存芯片的1.5V核心电压，0.75V的参考电压、0.75V的端接电压和3.3V的EEPROM、温度传感器工作电压。
本发明的闪存模块采用了内存条的外形和接口信号，可以直接插到现有的内存条插座上，计算机***的硬件不需要任何修改，仅修改软件即可，下面具体说明。
闪存模块采用类似于内存条的双列直插的存储模块DIMM(Dual Inline Memory Module)外形，可以***现有的内存条插槽中。对于DDR3内存条插槽来说，一共有240个信号触点，但是闪存模块只需要实现部分必备的信号，例如地址信号A[0:15]、BA[2:0]，数据信号DQ[63:0]，控制信号CS[3:0]#、RAS#、CAS#、WE#以及电源信号和时钟信号等，而有的信号是可选的，例如校验信号CB[7:0]、Par_In；对于信号触点可以连接、可以悬空、也可以连接但不使用。
内存条上有一个I2C总线接口，包括SCL、SDA和地址信号SA[2:0]，用来连接内存条上的EEPROM和温度传感器，前者保存着内存条的一些参数，例如存储器类型、内存条规格、存储容量、数据总线宽度、时序参数、缓存容量参数等，后者用来检测内存条的温度，当温度超出门限后可以上报告警。本发明的闪存模块上面也有一个EEPROM，保存的信息基本相同，但是由于模块类型不同于内存条，所以可以在EEPROM的第三个字节(DRAM Device Type)定义一个数值，例如DDR3的类型标识是0x0B，闪存的类型标识可以定义为0x10，表示闪存；在具体实现过程中EEPROM的字节位置与数值定义都是可以进行灵活设置的。当计算机***启动时，BIOS对处理器、***设备进行初始化，cpu可以从闪存模块的EEPROM中读取上述数值，从而识别它是普通的DDR3内存条，还是闪存模块，并进行不同的处理，下面会有说明。
如图2所示，图2为本发明实施例中一种闪存模块的逻辑结构。闪存模块的逻辑结构中包括：接口控制器，命令寄存器、状态寄存器，读/写缓存，切换控制寄存器，闪存控制器，以及闪存等。其中，接口控制器、切换控制寄存器、命令/状态寄存器和闪存控制器可以集成在同一个芯片里面。各模块功能如下。
接口控制器，与内存总线相连，cpu按内存条接口时序下发各种读写命令，接口控制器对命令进行译码，识别出读命令、写命令或模式寄存器设置命令，结合地址、数据信号完成对应的读写操作。
命令/状态寄存器，一般情况下这是两种寄存器，状态寄存器是只读的，命令寄存器是只写的，它们可以共用一个地址，命令寄存器和状态寄存器可以进行切换访问；状态寄存器和命令寄存器可以通过读写命令来区分，因此不用额外占用地址。状态寄存器的内容是闪存模块上的闪存控制器设置的。命令寄存器有两个，都是64位，第一个命令寄存器的内容包括48位的起始逻辑块地址LBA(logical block address)地址(用于给软件提供一个接口，相当于一个起始地址)、16位的读写长度(表示能够读写多少数据量)，第二个命令寄存器的内容是操作命令，可以选择与ATA命令集一致，例如Read Sector是0x20，Read Multiple是0xC4，Write Sector是0x30，Write Multiple是0xC5等。状态寄存器，包括至少两个bit，用来保存闪存模块的工作状态，例如忙或空闲，数据是否出错等。
读/写缓存，读缓存和写缓存可以在物理上位于同一个存储芯片中，也可以分别位于两个不同的存储芯片中，两种情况都是分时使用；可以属于同一个缓存地址空间，这个缓存空间可以分时读写；存在多个缓存空间也是可以的。读/写缓存用来保存即将写入闪存的数据，或者从闪存读出的数据。读写缓存有多种实现方式，例如可以用两个独立的芯片分别作为读缓存和写缓存，还可以用同一个芯片，将该芯片划分为两个区域，分别作为读缓存和写缓存，此时cpu在访问的时候还要发送一个相应的读写信号。另外缓存空间在cpu的寻址空间之内，由切换控制寄存器根据cpu写入的命令来切换读/写缓存和命令寄存器，并且执行地址转换(将cpu送来的读写地址转换为读写缓存的对应地址)。
作为可选的，本发明的装置中还可以包括切换控制寄存器，这是本发明中新 增的一个寄存器，用来控制命令/状态寄存器与读/写缓存之间的切换。切换控制寄存器通过cpu下发的MRS命令，进而控制多路复用器，在任一时刻，使得读缓存、写缓存、命令寄存器和状态寄存器中的唯一一个连接到计算机***的内存条接口上；具体实现过程中表现为在这些缓存和寄存器彼此之间进行分时切换。其中，读写缓存一般为同一个地址空间，命令寄存器和状态寄存器也具有相同的地址空间或部分重叠的地址空间。
闪存控制器，根据命令寄存器的内容对闪存执行对应的操作，对于读操作，将闪存的数据读出并保存在读缓存里；对于写操作，将写缓存的内容写入闪存。操作完成后，设置状态寄存器的状态位，当cpu查询状态寄存器时可以获知操作是否完成或是否出错。闪存控制器还需要完成LBA到闪存物理地址的映射，以及闪存的磨损平衡、坏块管理等功能，保证可靠性。
闪存，用来保存数据。
为了不受cpu寻址空间的限制，本发明的技术方案中是由cpu提供地址、数据长度和命令给命令/状态寄存器，通过命令/状态寄存器间接访问闪存。例如命令寄存器有2个64位的寄存器，状态寄存器有1个64位的寄存器，一共是3个64位寄存器。但是因为状态寄存器和命令寄存器的地址是共用的，所以地址上只有2*8＝16个字节地址。此外读写缓存也要占用一部分寻址空间。由于访问长度是16位，相当于最大访问范围是64K，而闪存的最小寻址单位是一个扇区(4KB)，因此至少需要的读或写缓存容量是64K*4KB＝256MB，读写缓存的总容量至少是512MB，如果将一次访问分为多次访问，限制每次读写的数据量，那么缓存容量可以更小一些。由于命令/状态寄存器和读/写缓存的地址空间是由cpu独立分配的，为了避免地址冲突，它们的地址应该错开，例如最前面的16个字节分配给命令/状态寄存器，后面的512MB分配给读/写缓存，如图3所示，图3为本发明实施例中一种cpu为单个闪存模块分配地址的情形。如果读写缓存的地址复用，那么只需要256MB的地址空间。
但是通常服务器的闪存容量需求很大，所以同一个服务器上会需要很多个闪存模块，如果同时有多个闪存模块安装在内存总线上，多个闪存模块的地址连续 排列；然而闪存模块的连续使用使得多个闪存模块中的读/写缓存的地址不连续，被命令/状态寄存器间隔开了，因为地址不连续，当cpu需要同时访问多个闪存模块时，不能在一次访问中完成，只能分多次完成，影响了数据的读写性能。如图4所示，图4为本发明实施例中一种cpu为两个闪存模块分配地址的示意图。
这种地址分配方式使得多个闪存模块的读/写缓存地址空间不连续，cpu访问它们的缓存时必须跳过命令/状态寄存器所在的地址空间，增加了程序设计的复杂度，还会影响访问性能。
因此可以考虑将命令/状态寄存器与读/写缓存的地址重叠，针对多个闪存模块同时使用的情形，本发明的方案中可以通过一个切换控制寄存器进行分时访问控制，例如某一时刻cpu访问的是命令寄存器或状态寄存器，而另一时刻通过同一个地址访问的却是读缓存或者写缓存。而这个切换控制寄存器最好不占用地址空间，以免出现上面提到的读/写缓存地址不连续的类似问题。
对于内存条接口来说，它支持一个特殊的命令叫“模式寄存器设置”(Mode Register Set，MRS)，用来对内存条上的内存芯片进行初始化配置，例如配置它们的突发访问顺序和长度，延时参数等。当内存条接口信号出现“CS#为低电平、RAS#为低电平、CAS#为低电平、WE#为低电平”的组合时就会产生这个命令，将地址总线上的地址信号作为数据写入内存芯片的模式寄存器。模式寄存器一共有4个，分别是MR0、MR1、MR2和MR3，分别用来配置不同的参数(突发访问的方式，突发长度的选择，DLL的使能控制)，每个寄存器都有17位，从bit16到bit0分别对应于BA2(备用)、BA1、BA0、A13、A12…A0，通过BA1和BA0的组合来选择不同的模式寄存器，例如BA1、BA0＝00选择的是MR0，BA1、BA0＝01选择的是MR1，而A13到A0一一对应于模式寄存器的bit13到bit0，将这些地址线上的信号分别写入模式寄存器的对应位。由此可见，模式寄存器是不需要地址的，而是通过控制信号的组合来寻址，并且将地址线上的信号当作数据来写入，因此符合我们对切换控制寄存器的要求，可以借用现有的“模式寄存器设置”命令(MRS)来设置其内容。
使用切换控制寄存器来实现切换的另一个好处是速度快，因为它是通过内存 条接口来访问的，时钟频率可达800MHz以上。如果用内存条接口的I2C总线来完成此操作就太慢了，它的时钟频率只有400KHz。模式寄存器的内容如图5所示，图5为本发明实施例中一种模式寄存器的格式示意图。
本发明只需要使用一个模式寄存器即可，该模式寄存器作为切换控制寄存器。以MR0为例，例如将MR0的bit0设置为0时表示将内存条接口与命令/状态寄存器接通，将MR0的bit0设置为1时表示接通读/写缓存。
根据以上描述，命令/状态寄存器与读/写缓存的地址分配如图6所示，图6为本发明实施例中一种闪存模块的地址重叠分配的示意图。图6中，切换控制寄存器用虚线框表示，是为了说明它不占用地址空间。
对于闪存来说，最终要实现的功能就是cpu能够对其进行读写数据操作；下面分别详细介绍读操作和写操作的通信流程。
在对闪存模块进行读操作时，按以下步骤执行：
(1)cpu通过MRS命令设置切换控制寄存器，使bit0＝0，将内存条接口切换到命令/状态寄存器；
(2)cpu将待读取的闪存模块的起始LBA地址、扇区长度和操作命令写入命令寄存器，如cpu分配给闪存条上寄存器的地址为0到15；
(3)闪存控制器接收并根据(2)中命令寄存器的命令和地址，先将状态寄存器中的标志位设置为“忙”，然后开始从闪存中读取数据并保存到读缓存中，起始地址一般为0，但不限于0；
(4)闪存控制器完成数据的读取和保存到读缓存后，将状态寄存器的标志位设置为“空闲”；
(5)由于cpu在发出读命令后会不断地读取状态寄存器的状态位，因此当cpu检测到状态从忙变为空闲后(例如0表示空闲，1表示忙)，通过MRS命令设置切换控制寄存器，使bit0＝1，将内存条接口切换到读/写缓存；
(6)cpu从读缓存中将数据取走，保存到自己的内存里，可以进行后续处理；
(7)cpu通过MRS命令设置切换控制寄存器，使bit0＝0，将内存条接口切换到命令/状态寄存器，准备执行下一次读操作。
在对闪存模块进行写操作时，按以下步骤执行：
(1)cpu通过MRS命令设置切换控制寄存器，使bit0＝1，将内存条接口切换到读/写缓存；
(2)cpu将待写入闪存模块的数据送到写缓存中，起始地址为0，但不限于0；
(3)cpu通过MRS命令设置切换控制寄存器，使bit0＝0，将内存条接口切换到命令/状态寄存器；
(4)cpu将待写入的闪存模块的起始LBA地址、扇区长度和操作命令写入命令寄存器，如cpu分配给闪存条上寄存器的地址为0到15；
(5)闪存控制器接收并根据(4)中写入命令寄存器的命令和地址，先将状态寄存器中的标志位设置为“忙”，然后开始从写缓存中读取数据并写入到闪存中，起始地址是0，但不限于0；
(6)闪存控制器完成数据搬移后，将状态寄存器的标志位设置为“空闲”；
(7)cpu在发出写命令后会不断地读取状态寄存器的状态位，因此当cpu检测到状态从忙变为空闲后，准备执行下一次写操作。
在以上的读写操作过程中，模式寄存器的选择、模式寄存器中位的选择、模式寄存器中位的特征值的设置与状态寄存器中标识“忙”与“空闲”的特征值设置都是可以根据用户的需求以及使用的计算机的特性进行灵活选择和设置的。
其中，cpu判断闪存控制器是否完成读写操作的方法，既可以通过上述提到的不断地读取状态寄存器的状态位的查询方式，也可以采用中断方式，这样有利于节省cpu的时间。在具体实现过程中，中断信号可以根据用户使用信号的具体情况以及自己的需求来决定。例如内存条接口上有一个EVENT#信号，本用于指 示内存条的温度，超出门限后变为低电平，本发明可以将它作为中断信号。当闪存控制器完成读写操作后，一方面设置状态寄存器的标志位为空闲，另一方面将EVENT#驱动为低电平，向cpu发出中断。cpu响应中断后读取闪存模块的状态寄存器(不同的中断原因对应于不同的比特位)，可以识别出中断原因是温度超出门限还是闪存控制器已完成读写操作。
如果cpu的某个内存通道上安装了多个闪存模块，BIOS启动时从闪存模块上的EEPROM读取模块类型，检测到类型为闪存模块后则不会将它作为内存上报给操作***。因为每个闪存模块的命令/状态寄存器的地址与读/写缓存是重叠的，不会占用额外的地址空间，所以多个闪存模块的读/写缓存地址是连续的，如果第一个闪存模块的读/写缓存容量是512MB，第二个的容量是1GB，那么第一个闪存模块的读/写缓存地址范围是0到512MB-1，第二个的地址范围是512MB到1.5GB-1。对于命令/状态寄存器，第一个闪存模块的地址范围是0到15，第二个的地址范围是512MB到512MB+15。BIOS可以通过各个闪存模块的数量和EEPROM里面保存的缓存容量参数，推算出各自的读/写缓存地址范围和命令/状态寄存器的地址范围，以便在访问闪存模块的数据时进行寻址。
在访问不同的闪存模块时，可以是不同的闪存模块在不同的内存条接口或通道上，且各对应于一个内存控制器；也可以是同一个内存控制器通过同一个内存条接口的多个片选信号CS#来选择对应的闪存模块(例如CS0#选择第一个闪存模块，CS1#选择第二个闪存模块)，与内存条的访问方式相同。每个闪存模块的组成结构都是相同的，都具有图2的结构，cpu处理每一个闪存模块时都是采用同样的数据处理方式，只是cpu首先通过不同的片选信号来对不同的闪存模块来执行上述读写操作的步骤。
除了安装在与cpu直接连接的内存条插槽上之外，闪存模块还可以连接在一个专用控制器上，本发明的另一个实施例实现中，如图7所示，图7为本发明实施例中另一种闪存模块的应用框图示意图。计算机***中的专用控制器通过PCIe接口连接到cpu上，然后通过内存条接口与闪存模块相连。如果PCIe接口符合PCIe3.0规范，那么速率是8GT/s，当位宽为16位时带宽为16GB/s，比64位宽度、等效 速率为1.6GT/s的DDR3接口带宽还高，因此不会成为性能瓶颈。cpu访问闪存模块时，先要通过PCIe接口将LBA地址、扇区长度和读写命令发送给专用控制器，后者再通过内存条接口转发给闪存模块，后面的操作与前面的描述相同。
本发明中所采用的闪存模块采用了内存条的外形结构，尺寸较小，节省空间，在计算机***内可以安装的数量更多，因此提高了闪存的安装密度和存储容量；通过内存条接口直接访问，带宽更大，cpu读写数据延时更小；该结构的闪存模块能够直接***内存条插槽中，也不需要其他的硬件，只需要修改相应的软件即可；通过设置增加命令寄存器和状态寄存器，使得闪存的数据访问空间不再受到cpu提供的寻址空间的限制，cpu只需要提供少数的寄存器的寻址空间和少许的读/写缓存的寻址空间，如提供地址、数据长度和读写命令给命令/状态寄存器，就可以通过命令/状态寄存器间接访问闪存；此外，通过“模式寄存器设置”命令能够分时切换命令/状态寄存器与读/写缓存，同时由于切换控制寄存器本身不占用cpu的寻址空间，使得多个闪存模块安装在内存总线上时，不会出现读/写缓存地址不连续的状况，减少了程序设计的复杂度，改善了闪存的访问性能。
本领域普通技术人员可知，上述方法中的全部或部分步骤可以通过程序指令相关的硬件完成，该程序可以存储于一计算机可读存储介质中。通过以上的实施方式的描述，所属领域的技术人员可以清楚地了解到本发明可以用硬件实现，或固件实现，或它们的组合方式来实现。
以上实施例仅为本发明技术方案的较佳实施例而已，并非用于限定本发明的保护范围。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围。

Claims (12)

  1. 一种通过内存总线访问的存储装置，所述装置包括接口控制器、存储模块、存储控制器，其特征在于，所述装置还包括命令寄存器、状态寄存器；且所述接口控制器能够与计算机***的内存条接口电气连接；
    所述接口控制器用于接收cpu发送的访问所述存储模块的访问命令；
    所述接口控制器用于将所述访问命令写入所述命令寄存器；
    所述存储控制器用于根据所述命令寄存器中的访问命令，对所述存储模块执行相应的读写操作。
  2. 如权利要求1所述装置，其特征在于，所述装置还包括切换控制寄存器、读缓存、写缓存；其中所述读缓存用于保存从所述存储模块中已读出的数据；所述写缓存用于保存待写入所述存储模块的数据；
    所述切换控制寄存器用于根据所述cpu发送的模式寄存器设置MRS命令，
    在所述命令寄存器和所述读缓存中切换，使所述命令寄存器和所述读缓存先后电气连接到所述计算机***的内存条接口上，或者
    在所述命令寄存器和所述写缓存中切换，使所述写缓存和所述命令寄存器先后电气连接到所述计算机***的内存条接口上。
  3. 如权利要求2所述装置，其特征在于，所述切换控制寄存器用于控制所述读缓存、所述写缓存和所述命令寄存器的切换，使所述读缓存、或所述写缓存、或所述命令寄存器连接到所述计算机***的内存条接口上。
  4. 如权利要求2或3所述装置，其特征在于，所述读缓存、所述写缓存、所述命令寄存器在所述cpu的寻址空间内的起始地址相同。
  5. 如权利要求1-4任一项所述装置，其特征在于，所述存储装置还包括状态寄存 器，所述状态寄存器用于指示所述存储模块当前的工作状态是空闲还是忙碌；其中所述空闲表示所述存储模块当前没有进行读写操作，所述忙碌表示所述存储模块当前正在进行读写操作。
  6. 如权利要求1-5任一项所述装置，其特征在于，所述存储装置安装在所述计算机***的内存条插槽内，所述接口控制器通过的所述存储装置与所述cpu提供的内存条接口电气连接。
  7. 如权利要求1-6任一项所述装置，其特征在于，所述计算机***还包括专用控制器，所述存储装置安装在所述计算机***的内存条插槽内，所述接口控制器与所述计算机***的专用控制器提供的内存条接口电气连接。
  8. 如权利要求7所述装置，其特征在于，所述接口控制器连接在所述专用控制器上，所述专用控制器通过周边元件互联PCI快速通道与所述cpu连接。
  9. 如权利要求1-8任一项所述装置，其特征在于，所述装置中还包含可电擦除、可编程的只读存储器EEPROM，所述EEPROM中含有所述存储装置的类型标识，以在计算机***启动时，使所述cpu能够根据所述类型标识识别出所述cpu正在访问的存储装置的存储类型。
  10. 如权利要求1-9任一项所述装置，其特征在于，所述接口控制器还用于在所述存储装置的读写操作完成后，通过中断信号上报所述cpu读写操作完成；所述中断信号是用户根据预设规则在所述内存条接口对应的电气信号中选择出来的。
  11. 如权利要求1-10任一项所述装置，其特征在于，所述计算机***的内存条接口包括DDR、DDR2、DDR3或DDR4接口。
  12. 一种计算机***，其特征在于，所述计算机***中包括如权利要求1-11中任意一项所述的存储装置。
PCT/CN2016/070062 2015-06-06 2016-01-04 一种通过内存总线访问的存储装置 WO2016197600A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP16806498.8A EP3296883B1 (en) 2015-06-06 2016-01-04 Storage apparatus accessed via memory bus
US15/834,016 US10489320B2 (en) 2015-06-06 2017-12-06 Storage apparatus accessed by using memory bus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510308517.1A CN104951412B (zh) 2015-06-06 2015-06-06 一种通过内存总线访问的存储装置
CN201510308517.1 2015-06-06

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US15/834,016 Continuation US10489320B2 (en) 2015-06-06 2017-12-06 Storage apparatus accessed by using memory bus

Publications (1)

Publication Number Publication Date
WO2016197600A1 true WO2016197600A1 (zh) 2016-12-15

Family

ID=54166078

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/070062 WO2016197600A1 (zh) 2015-06-06 2016-01-04 一种通过内存总线访问的存储装置

Country Status (4)

Country Link
US (1) US10489320B2 (zh)
EP (1) EP3296883B1 (zh)
CN (1) CN104951412B (zh)
WO (1) WO2016197600A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112650439A (zh) * 2019-10-10 2021-04-13 上海磁宇信息科技有限公司 Mram-nand控制器及其数据写入方法
CN114036096A (zh) * 2021-11-04 2022-02-11 珠海一微半导体股份有限公司 一种基于总线接口的读控制器

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104951412B (zh) 2015-06-06 2018-01-02 华为技术有限公司 一种通过内存总线访问的存储装置
CN105512007B (zh) * 2015-12-17 2018-12-04 英业达科技有限公司 一种pcie硬盘状态灯的控制方法及***
CN105608027B (zh) * 2015-12-18 2018-10-19 华为技术有限公司 非易失存储设备和访问非易失存储设备的方法
CN105681485B (zh) * 2016-01-05 2019-01-08 英业达科技有限公司 用于防止地址冲突的***及其方法
CN105760310B (zh) * 2016-02-05 2018-12-14 华为技术有限公司 地址分配方法及ddr控制器
WO2017177400A1 (zh) * 2016-04-13 2017-10-19 华为技术有限公司 一种数据处理方法及***
CN107783727B (zh) * 2016-08-31 2022-01-14 华为技术有限公司 一种内存设备的访问方法、装置和***
CN107315699B (zh) * 2017-06-12 2021-04-23 记忆科技(深圳)有限公司 一种tf卡
US10388362B1 (en) * 2018-05-08 2019-08-20 Micron Technology, Inc. Half-width, double pumped data path
KR102495712B1 (ko) 2018-06-27 2023-02-06 후아웨이 테크놀러지 컴퍼니 리미티드 스토리지 시스템 및 스토리지 시스템의 작동 모드를 전환하기 위한 방법
CN109165177A (zh) * 2018-09-21 2019-01-08 郑州云海信息技术有限公司 一种pcie接口的通信方法及相关装置
WO2020118713A1 (zh) * 2018-12-14 2020-06-18 深圳市汇顶科技股份有限公司 位宽匹配电路、数据写入装置、数据读出装置和电子设备
TWI698120B (zh) * 2019-02-27 2020-07-01 瑞昱半導體股份有限公司 多媒體串流及網路裝置
US11392470B2 (en) * 2019-05-15 2022-07-19 Dell Products L.P. Information handling system to allow system boot when an amount of installed memory exceeds processor limit
US12001355B1 (en) * 2019-05-24 2024-06-04 Pure Storage, Inc. Chunked memory efficient storage data transfers
CN110164394B (zh) * 2019-06-04 2021-08-06 Tcl华星光电技术有限公司 时序控制器及时序控制板
CN110716894B (zh) * 2019-09-24 2023-07-04 深圳忆联信息***有限公司 一种ssd多核sram加速***及其工作方法
WO2021128249A1 (zh) * 2019-12-27 2021-07-01 深圳市大疆创新科技有限公司 处理器、任务响应方法、可移动平台、及相机
US12001365B2 (en) * 2020-07-07 2024-06-04 Apple Inc. Scatter and gather streaming data through a circular FIFO
CN112131150B (zh) * 2020-09-15 2023-10-03 北京神州飞航科技有限责任公司 一种多片外存储器控制方法和装置
CN112346660B (zh) * 2020-11-13 2024-05-14 北京泽石科技有限公司 数据存储方法及装置、数据读取方法及装置
CN112486574B (zh) * 2020-12-16 2024-07-05 江苏国科微电子有限公司 一种完成队列的回复管理方法、装置、设备及存储介质
US11586393B2 (en) * 2020-12-30 2023-02-21 Macronix International Co., Ltd. Control method for requesting status of flash memory, flash memory die and flash memory with the same
US11755489B2 (en) * 2021-08-31 2023-09-12 Apple Inc. Configurable interface circuit
CN115543898B (zh) * 2022-09-26 2023-06-27 南京国电南自维美德自动化有限公司 一种通信总线扩展方法及装置
CN116680088B (zh) * 2023-08-03 2023-10-13 青岛本原微电子有限公司 一种针对多寄存器存储的多模块同时访问***及访问方法
CN117406934B (zh) * 2023-12-13 2024-04-30 深圳市思远半导体有限公司 闪存数据访问方法、电量计算方法、装置及存储介质

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101620581A (zh) * 2008-07-03 2010-01-06 西安奇维测控科技有限公司 双口ram实现闪存控制器缓存的结构及实现该缓存的方法
US8006045B2 (en) * 2009-02-27 2011-08-23 Atmel Rousset S.A.S. Dummy write operations
CN103348331A (zh) * 2010-10-27 2013-10-09 尹摩特斯公司 具数据管理的层级式数据储存***及其操作方法
CN104951412A (zh) * 2015-06-06 2015-09-30 华为技术有限公司 一种通过内存总线访问的存储装置

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003141888A (ja) * 2001-11-01 2003-05-16 Mitsubishi Electric Corp 不揮発性半導体記憶装置
US20130086311A1 (en) * 2007-12-10 2013-04-04 Ming Huang METHOD OF DIRECT CONNECTING AHCI OR NVMe BASED SSD SYSTEM TO COMPUTER SYSTEM MEMORY BUS
US8359423B2 (en) 2008-03-14 2013-01-22 Spansion Llc Using LPDDR1 bus as transport layer to communicate to flash
US8713379B2 (en) * 2011-02-08 2014-04-29 Diablo Technologies Inc. System and method of interfacing co-processors and input/output devices via a main memory system
US9575908B2 (en) * 2011-02-08 2017-02-21 Diablo Technologies Inc. System and method for unlocking additional functions of a module
US9552175B2 (en) * 2011-02-08 2017-01-24 Diablo Technologies Inc. System and method for providing a command buffer in a memory system
US8607089B2 (en) * 2011-05-19 2013-12-10 Intel Corporation Interface for storage device access over memory bus
WO2013101053A1 (en) * 2011-12-29 2013-07-04 Intel Corporation Non-volatile ram disk
US20160232103A1 (en) * 2013-09-26 2016-08-11 Mark A. Schmisseur Block storage apertures to persistent memory
CN203838698U (zh) * 2014-05-12 2014-09-17 浪潮电子信息产业股份有限公司 一种多功能io扩展卡
SG11201702584UA (en) * 2014-10-05 2017-04-27 Amazon Tech Inc Emulated endpoint configuration
US9898218B2 (en) * 2016-02-05 2018-02-20 International Business Machines Corporation Memory system with switchable operating bands

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101620581A (zh) * 2008-07-03 2010-01-06 西安奇维测控科技有限公司 双口ram实现闪存控制器缓存的结构及实现该缓存的方法
US8006045B2 (en) * 2009-02-27 2011-08-23 Atmel Rousset S.A.S. Dummy write operations
CN103348331A (zh) * 2010-10-27 2013-10-09 尹摩特斯公司 具数据管理的层级式数据储存***及其操作方法
CN104951412A (zh) * 2015-06-06 2015-09-30 华为技术有限公司 一种通过内存总线访问的存储装置

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112650439A (zh) * 2019-10-10 2021-04-13 上海磁宇信息科技有限公司 Mram-nand控制器及其数据写入方法
CN112650439B (zh) * 2019-10-10 2023-03-21 上海磁宇信息科技有限公司 Mram-nand控制器及其数据写入方法
CN114036096A (zh) * 2021-11-04 2022-02-11 珠海一微半导体股份有限公司 一种基于总线接口的读控制器
CN114036096B (zh) * 2021-11-04 2024-05-03 珠海一微半导体股份有限公司 一种基于总线接口的读控制器

Also Published As

Publication number Publication date
CN104951412B (zh) 2018-01-02
US10489320B2 (en) 2019-11-26
CN104951412A (zh) 2015-09-30
US20180113826A1 (en) 2018-04-26
EP3296883A1 (en) 2018-03-21
EP3296883B1 (en) 2020-03-11
EP3296883A4 (en) 2018-05-16

Similar Documents

Publication Publication Date Title
WO2016197600A1 (zh) 一种通过内存总线访问的存储装置
US10691626B2 (en) Memory channel that supports near memory and far memory access
EP3382564B1 (en) Non-volatile storage device and method for accessing non-volatile storage device
US9164679B2 (en) System, method and computer program product for multi-thread operation involving first memory of a first memory class and second memory of a second memory class
US9182914B1 (en) System, method and computer program product for multi-thread operation involving first memory of a first memory class and second memory of a second memory class
US9064560B2 (en) Interface for storage device access over memory bus
US9170744B1 (en) Computer program product for controlling a flash/DRAM/embedded DRAM-equipped system
US20110208900A1 (en) Methods and systems utilizing nonvolatile memory in a computer system main memory
US11709777B2 (en) Memory system
US9158546B1 (en) Computer program product for fetching from a first physical memory between an execution of a plurality of threads associated with a second physical memory
US20170109077A1 (en) Memory system
US9176671B1 (en) Fetching data between thread execution in a flash/DRAM/embedded DRAM-equipped system
WO2024063822A1 (en) Partial speed changes to improve in-order transfer
WO2008025238A1 (fr) Dispositif de stockage avec une grande capacité et procédé basé sur une mémoire flash
CN110413234B (zh) 一种固态硬盘
US20220229575A1 (en) Dynamic multilevel memory system
US20220222178A1 (en) Selective fill for logical control over hardware multilevel memory
WO2024054280A1 (en) Adaptive tuning of memory device clock rates based on dynamic parameters

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16806498

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 2016806498

Country of ref document: EP