WO2016192176A1 - 一种扫描驱动电路 - Google Patents

一种扫描驱动电路 Download PDF

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Publication number
WO2016192176A1
WO2016192176A1 PCT/CN2015/084072 CN2015084072W WO2016192176A1 WO 2016192176 A1 WO2016192176 A1 WO 2016192176A1 CN 2015084072 W CN2015084072 W CN 2015084072W WO 2016192176 A1 WO2016192176 A1 WO 2016192176A1
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WO
WIPO (PCT)
Prior art keywords
switch tube
signal
scan
output end
pull
Prior art date
Application number
PCT/CN2015/084072
Other languages
English (en)
French (fr)
Inventor
肖军城
颜尧
Original Assignee
武汉华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US14/772,386 priority Critical patent/US9865213B2/en
Publication of WO2016192176A1 publication Critical patent/WO2016192176A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers

Definitions

  • the present invention relates to the field of display driving, and more particularly to a scan driving circuit.
  • Gate Driver On Array is a driving circuit for forming a scan driving circuit on an array substrate of an existing thin film transistor liquid crystal display to realize progressive scanning of a scanning line.
  • the existing scan driving circuit includes a pull-down control module, a pull-down module, a downlink module, a reset control module, a bootstrap capacitor, and a reset control module.
  • An embodiment of the present invention provides a scan driving circuit for driving a cascaded scan line, which includes:
  • a pull-down control module configured to receive a scan signal of the upper stage or a scan signal of the lower stage, and generate a scan level signal of a low level of the corresponding scan line according to the scan signal of the upper stage or the scan signal of the lower stage;
  • a pull-down module configured to pull down a scan signal of the corresponding scan line according to the scan level signal
  • a reset control module configured to receive a clock signal of the upper stage or a clock signal of the lower stage, and generate a corresponding reset signal of the scan line according to the clock signal of the upper stage or the clock signal of the lower stage;
  • a reset module configured to pull up a scan signal of the corresponding scan line according to the reset signal
  • a downlink module configured to generate and send a clock signal of the current stage and a pull-down control signal according to the scan signal of the scan line;
  • a first bootstrap capacitor for generating a low level or a high level of a scan level signal of the scan line
  • a constant voltage low level source for providing the low level signal
  • the pull-down control module includes a twelfth switch tube, a control signal of the twelfth switch tube inputs a scan signal of a low level, and an input end of the twelfth switch tube inputs a scan signal of the lower stage;
  • the output end of the twelfth switch tube is connected to the pull-down module;
  • the reset control module includes a thirteenth switch tube, the control end of the thirteenth switch tube inputs the scan signal of the low level, and the input end of the thirteenth switch tube inputs the clock signal of the upper stage, The output end of the thirteenth switch tube outputs a reset signal of the scan line.
  • the pull-down control module includes a first switch tube, a control signal of the first switch tube inputs a scan signal of a low level, and an input end of the first switch tube The scan signal of the upper stage is described; the output end of the first switch tube is connected to the pull-down module.
  • the pull-down module includes a second switch tube, and the control end of the second switch tube inputs a pull-down control signal of a previous stage, and an input end of the second switch tube The output end of the first switch tube is connected, and the output end of the second switch tube outputs a scan level signal of a low level of the scan line.
  • the reset control module includes a third switch tube, and the control end of the third switch tube inputs the scan signal of the low level, and the input end of the third switch tube And inputting a clock signal of the lower stage, and an output end of the third switch tube outputs a reset signal of the scan line.
  • the reset module includes a fourth switch tube, a fifth switch tube, a sixth switch tube, a seventh switch tube, and an eighth switch tube;
  • a control end of the fourth switch tube is connected to an output end of the third switch tube, an input end of the fourth switch tube is connected to the constant voltage low level source, and an output end of the fourth switch tube Connecting to the control end of the fifth switch tube, the control end of the eighth switch tube, the output end of the sixth switch tube, and the output end of the seventh switch tube;
  • An input end of the fifth switch tube is connected to the constant voltage high level source, and an output end of the fifth switch tube is connected to an output end of the second switch tube;
  • the control end of the sixth switch tube inputs the pull-down control signal of the current stage, and the input end of the sixth switch tube is connected to the constant voltage high level source;
  • the control end of the seventh switch tube inputs the pull-down control signal of the previous stage, and the input end of the seventh switch tube is connected to the constant voltage high level source;
  • the input end of the eighth switch tube is connected to the constant voltage high level source, and the output end of the eighth switch tube outputs a scan signal of the current stage of the scan line.
  • the reset module further includes a fourteenth switch tube
  • a control end of the fourteenth switch tube is connected to an output end of the fourth switch tube, and an input end of the fourteenth switch tube is connected to the constant voltage high level source, the fourteenth switch tube The output end is connected to the control end of the sixth switch tube.
  • the reset module further includes a fifteenth switch tube, and the control end of the fifteenth switch tube inputs the pull-down control signal of the upper stage, the fifteenth switch An input end of the tube is connected to the constant voltage high level source, and an output end of the fifteenth switch tube is connected to an output end of the fourth switch tube.
  • the pull-down module further includes a sixteenth switch tube, and the control end of the sixteenth switch tube inputs the pull-down control signal of the upper stage, the sixteenth switch The input end of the tube is connected to the constant voltage low level source, and the output end of the sixteenth switch tube is connected to the output end of the second switch tube.
  • the downlink module includes a ninth switch tube and an eleventh switch tube, and a control end of the ninth switch tube is connected to an output end of the second switch tube.
  • An input end of the ninth switch tube is connected to an output end of the eighth switch tube, and an output end of the ninth switch tube outputs a clock signal of the current stage;
  • a control end of the eleventh switch tube is connected to an output end of the second switch tube, and an input end of the eleventh switch tube is connected to an output end of the ninth switch tube, the eleventh switch The output of the tube outputs the pull-down control signal of this stage.
  • the reset module further includes a fourteenth switch tube and a fifteenth switch tube
  • a control end of the fourteenth switch tube is connected to an output end of the fourth switch tube, and an input end of the fourteenth switch tube is connected to the constant voltage high level source, the fourteenth switch tube The output end is connected to the control end of the sixth switch tube;
  • the control end of the fifteenth switch tube inputs the pull-down control signal of the upper stage, and the input end of the fifteenth switch tube is connected to the constant voltage high level source, and the fifteenth switch tube The output end is connected to the output end of the fourth switch tube.
  • the pull-down module further includes a sixteenth switch tube, and the control end of the sixteenth switch tube inputs the pull-down control signal of the upper stage, the sixteenth switch The input end of the tube is connected to the constant voltage low level source, and the output end of the sixteenth switch tube is connected to the output end of the second switch tube.
  • An embodiment of the present invention provides a scan driving circuit for driving a cascaded scan line, which includes:
  • a pull-down control module configured to receive a scan signal of the upper stage or a scan signal of the lower stage, and generate a scan level signal of a low level of the corresponding scan line according to the scan signal of the upper stage or the scan signal of the lower stage;
  • a pull-down module configured to pull down a scan signal of the corresponding scan line according to the scan level signal
  • a reset control module configured to receive a clock signal of the upper stage or a clock signal of the lower stage, and generate a corresponding reset signal of the scan line according to the clock signal of the upper stage or the clock signal of the lower stage;
  • a reset module configured to pull up a scan signal of the corresponding scan line according to the reset signal
  • a downlink module configured to generate and send a clock signal of the current stage and a pull-down control signal according to the scan signal of the scan line;
  • a first bootstrap capacitor for generating a low level or a high level of a scan level signal of the scan line
  • a constant voltage low level source for providing the low level signal
  • a constant voltage high level source for providing the high level signal.
  • the pull-down control module includes a first switch tube, a control signal of the first switch tube inputs a scan signal of a low level, and an input end of the first switch tube The scan signal of the upper stage is described; the output end of the first switch tube is connected to the pull-down module.
  • the pull-down module includes a second switch tube, and the control end of the second switch tube inputs a pull-down control signal of a previous stage, and an input end of the second switch tube The output end of the first switch tube is connected, and the output end of the second switch tube outputs a scan level signal of a low level of the scan line.
  • the reset control module includes a third switch tube, and the control end of the third switch tube inputs the scan signal of the low level, and the input end of the third switch tube And inputting a clock signal of the lower stage, and an output end of the third switch tube outputs a reset signal of the scan line.
  • the reset module includes a fourth switch tube, a fifth switch tube, a sixth switch tube, a seventh switch tube, and an eighth switch tube;
  • a control end of the fourth switch tube is connected to an output end of the third switch tube, an input end of the fourth switch tube is connected to the constant voltage low level source, and an output end of the fourth switch tube Connecting to the control end of the fifth switch tube, the control end of the eighth switch tube, the output end of the sixth switch tube, and the output end of the seventh switch tube;
  • An input end of the fifth switch tube is connected to the constant voltage high level source, and an output end of the fifth switch tube is connected to an output end of the second switch tube;
  • the control end of the sixth switch tube inputs the pull-down control signal of the current stage, and the input end of the sixth switch tube is connected to the constant voltage high level source;
  • the control end of the seventh switch tube inputs the pull-down control signal of the previous stage, and the input end of the seventh switch tube is connected to the constant voltage high level source;
  • the input end of the eighth switch tube is connected to the constant voltage high level source, and the output end of the eighth switch tube outputs a scan signal of the current stage of the scan line.
  • the reset module further includes a fourteenth switch tube
  • a control end of the fourteenth switch tube is connected to an output end of the fourth switch tube, and an input end of the fourteenth switch tube is connected to the constant voltage high level source, the fourteenth switch tube The output end is connected to the control end of the sixth switch tube.
  • the reset module further includes a fifteenth switch tube, and the control end of the fifteenth switch tube inputs the pull-down control signal of the upper stage, the fifteenth switch An input end of the tube is connected to the constant voltage high level source, and an output end of the fifteenth switch tube is connected to an output end of the fourth switch tube.
  • the pull-down module further includes a sixteenth switch tube, and the control end of the sixteenth switch tube inputs the pull-down control signal of the upper stage, the sixteenth switch The input end of the tube is connected to the constant voltage low level source, and the output end of the sixteenth switch tube is connected to the output end of the second switch tube.
  • the downlink module includes a ninth switch tube and an eleventh switch tube, and a control end of the ninth switch tube is connected to an output end of the second switch tube.
  • An input end of the ninth switch tube is connected to an output end of the eighth switch tube, and an output end of the ninth switch tube outputs a clock signal of the current stage;
  • a control end of the eleventh switch tube is connected to an output end of the second switch tube, and an input end of the eleventh switch tube is connected to an output end of the ninth switch tube, the eleventh switch The output of the tube outputs the pull-down control signal of this stage.
  • the scan driving circuit of the present invention improves the reliability of the scan driving circuit by the setting of the pull-down control module and the reset control module, and the structure of the entire scan driving circuit is simple; The technical problem of the structure of the scan driving circuit is complicated and the reliability is low.
  • FIG. 1 is a schematic structural view of a preferred embodiment of a scan driving circuit of the present invention
  • FIG. 2A is a detailed circuit configuration diagram of a first preferred embodiment of a scan driving circuit of the present invention
  • 2B is a signal waveform diagram of a first preferred embodiment of the scan driving circuit of the present invention.
  • FIG. 3 is a detailed circuit configuration diagram of a second preferred embodiment of the scan driving circuit of the present invention.
  • 4A is a detailed circuit configuration diagram of a third preferred embodiment of the scan driving circuit of the present invention.
  • 4B is a signal waveform diagram of a third preferred embodiment of the scan driving circuit of the present invention.
  • 5A is a structural diagram of a specific circuit of a fourth preferred embodiment of the scan driving circuit of the present invention.
  • Fig. 5B is a signal waveform diagram of a fourth preferred embodiment of the scan driving circuit of the present invention.
  • FIG. 1 is a schematic structural view of a preferred embodiment of a scan driving circuit of the present invention.
  • the scan driving circuit 10 of the preferred embodiment is configured to perform a driving operation on the cascaded scan lines.
  • the scan driving circuit 10 includes a pull-down control module 11, a pull-down module 12, a reset control module 13, a reset module 14, and a downlink module 15.
  • the leakage prevention module 16 the first bootstrap capacitor C1, the constant voltage low level source VGL, and the constant voltage high level source VGH.
  • the pull-down control module 11 is configured to receive the scan signal G_N-1 of the previous stage, and generate a scan level signal of a low level of the corresponding scan line according to the scan signal G_N-1 of the previous stage.
  • the pull-down module 12 is configured to pull down the scan signal G_N of the corresponding scan line according to the scan level signal.
  • the reset control module 13 is configured to receive the clock signal CK_N+1 of the next stage, and generate a reset signal of the corresponding scan line according to the clock signal CK_N+1 of the next stage.
  • the reset module 14 is configured to pull up the scan signal G_N of the corresponding scan line according to the reset signal.
  • the downlink module 15 is configured to generate and transmit the clock signal CK_N of the current stage according to the scan signal G_N of the scan line.
  • the first bootstrap capacitor C1 is used to generate a low level or a high level of the scan level signal of the scan line.
  • the constant voltage low level source VGL is used to provide a low level signal; the constant voltage high level source VGH is used to provide a high level signal.
  • FIG. 2 is a specific circuit configuration diagram of a first preferred embodiment of the scan driving circuit of the present invention
  • FIG. 2B is a signal waveform diagram of the first preferred embodiment of the scan driving circuit of the present invention.
  • the pull-down control module 11 includes a first switch tube PT1, and the control end of the first switch tube PT1 inputs a scan signal D2U of a low level, and the input end of the first switch tube PT1 inputs a scan signal of the previous stage.
  • G_N-1 the output end of the first switch PT1 is connected to the pull-down module 12, and the scan signal G_N-1 of the previous stage is output to the pull-down module 12.
  • the pull-down module 12 includes a second switch tube PT2, the control end of the second switch tube PT2 is connected to the output end of the first switch tube PT1, the input end of the second switch tube PT2 is connected to the output end of the first switch tube PT1, and the second The output terminal of the switching transistor PT2 outputs a low-level scanning signal G_N-1 of the previous scanning line.
  • the reset control module 13 includes a third switch tube PT3, the control end of the third switch tube PT3 inputs a low level scan signal D2U, and the input end of the third switch tube PT3 inputs a clock signal CK_N+1 of the next stage, the third switch The output end of the tube PT3 outputs a reset signal of the scan line, that is, outputs the clock signal CK_N+1 of the next stage.
  • the reset module 14 includes a fourth switch tube PT4, a fifth switch tube PT5, a sixth switch tube PT6, a seventh switch tube PT7, and a second bootstrap capacitor C2.
  • the control end of the fourth switch tube PT4 is connected to the output end of the third switch tube PT3, the input end of the fourth switch tube PT4 is connected to the constant voltage low level source VGL, and the output end of the fourth switch tube PT4 is respectively connected to the fifth switch
  • the control end of the tube PT5, the control end of the seventh switch tube PT7, the output end of the sixth switch tube PT6, and the control end of the tenth switch tube PT8 are connected.
  • the input end of the fifth switch tube PT5 is connected to the constant voltage high level source VGH, and the output end of the fifth switch tube PT5 is connected to the output end of the second switch tube PT2.
  • the control terminal of the sixth switching transistor PT6 is input to the pull-down control signal ST_N of the current stage, and the input terminal of the sixth switching transistor PT6 is connected to the constant voltage high-level source VGH.
  • the input end of the seventh switch tube PT7 inputs the pull-down control signal ST_N-1 of the previous stage, and the input end of the seventh switch tube PT7 is connected to the constant voltage high level source VGH.
  • the input end of the eighth switch tube PT8 is connected to the constant voltage high level source VGH, and the output end of the eighth switch tube PT8 outputs the scan signal G_N of the current stage of the scan line.
  • One end of the second bootstrap capacitor C2 is connected to the constant voltage high level source VGH, and the other end of the second bootstrap capacitor C2 is connected to the output end of the fourth switch tube PT4.
  • the downlink module 15 includes a ninth switch tube PT9 and an eleventh switch tube PT11.
  • the control end of the ninth switch tube PT9 is connected to the output end of the second switch tube PT2, and the input end of the ninth switch tube PT9 and the eighth switch tube
  • the output end of the PT8 is connected, and the output end of the ninth switch tube PT9 outputs the clock signal CK_N of the current stage.
  • the control end of the eleventh switch tube PT11 is connected to the output end of the second switch tube PT2, the input end of the eleventh switch tube PT11 is connected to the output end of the ninth switch tube PT9, and the output end of the eleventh switch tube PT11 is output.
  • the pull-down control signal ST_N of this stage is connected to the output end of the second switch tube PT2
  • the input end of the eleventh switch tube PT11 is connected to the output end of the ninth switch tube PT9
  • the output end of the eleventh switch tube PT11 is output.
  • One end of the first bootstrap capacitor C1 is connected to the output end of the second switch tube PT2, and the other end of the first bootstrap capacitor C1 is connected to the output end of the eighth switch tube PT8.
  • the leakage prevention module 16 includes a tenth switch tube PT10, the control end of the tenth switch tube PT10 is connected with the constant voltage low level source VGL, and the input end of the tenth switch tube PT10 is connected with the output end of the second switch tube PT2, the tenth The output end of the switch tube PT10 is connected to the output end of the eighth switch tube PT8 through the first bootstrap capacitor C1.
  • the clock signal CK_N is output in two groups, that is, the waveforms of CK_N and CK_N+2 are the same.
  • the scan signal G_N-1 of the previous stage outputs a low-level signal.
  • the first switch PT1 of the pull-down control module 11 is in an on state under the control of the low-level scan signal D2U;
  • the output end of the tube PT1 inputs the scan signal G_N-1 of the previous stage to the input end of the second switch tube PT2 of the pull-down module 12.
  • the pull-down control signal ST_N-1 of the upper stage also outputs a low-level signal.
  • the second switch tube PT2 and the seventh switch tube PT7 are turned on, and the output end of the second switch tube PT2 outputs a low-level signal G_N-1. .
  • the seventh switch tube PT7 of the reset module 14 is turned on, and the control end of the fifth switch tube PT5 and the control end of the eighth switch tube PT8 are respectively connected to the constant voltage high level source VGH through the seventh switch tube PT7, so the fifth switch The tube PT5 and the eighth switch tube PT8 are disconnected.
  • the tenth switch tube PT10 of the anti-leakage module 16 is turned on under the control of the constant voltage low level source VGL, and the low level signal G_N-1 outputted by the second switch tube PT2 of the pull-down module 12 acts on the tenth switch tube PT10.
  • the first bootstrap capacitor C1 makes the potential of Q_N lower, so that G_N also outputs a low-level signal, and at the same time, the ninth switch PT9 of the module 15 is turned on, and is also turned on under the control of Q_N, and the ninth switch PT9
  • the output terminal outputs the low-level clock signal CK_N of the current stage to the driving circuit of the scan line of the previous stage.
  • the eleventh switch tube PT11 is also turned on under the control of Q_N, the output end of the eleventh switch tube PT11 outputs the low level pull-down control signal ST_N of the current level, and the sixth switch tube PT6 is controlled by the pull-down control signal ST_N.
  • the control end of the fifth switch tube PT5 and the control end of the eighth switch tube PT8 are respectively connected to the constant voltage high level source VGH through the sixth switch tube PT6, so the fifth switch tube PT5 and the eighth switch tube PT8 remain Disconnected, thus ensuring the low-level output of G_N, avoiding the influence of the leakage of the eighth switching transistor PT8 on the low-level output of G_N.
  • the third switching transistor PT3 of the reset control module 13 inputs the clock signal CK_N+1 of the next stage under the control of the scanning signal U2D of the low level.
  • the output end of the third switch PT3 outputs the clock signal CK_N+1, that is, the reset signal to the reset module 14.
  • the fourth switch tube PT4 of the reset module 14 is turned on under the control of the reset signal, at which time the pull-down control signal ST_N-1 of the previous stage is turned into a high level signal, so the seventh switch tube PT7 is turned off, at this time
  • the five switch tube PT5 and the eighth switch tube PT8 are turned on under the control of the reset signal, and the high level signal of the constant voltage high level source VGH is input to the Q point through the fifth switch tube PT5, and Q_N is pulled high.
  • the high-level signal of the constant-voltage high-level source VGH is input to G_N through the eighth switch tube PT8, and G_N is pulled high, and at the same time, since the ninth switch tube PT9 and the eleventh switch tube PT11 are disconnected, the clock signal CK_N and the present The level pull-down control signal ST_N also goes high.
  • the sixth switch tube PT6 is turned off under the control of the pull-down control signal ST_N of the current stage, further avoiding the influence of the constant voltage high-level source VGH on the fifth switch tube PT5 and the eighth switch tube PT8.
  • the setting of the second bootstrap capacitor C2 in the reset module 14 can better pull up the potential of the control end of the fifth switch tube PT5 and the control end of the eighth switch tube PT8, thereby better ensuring the Q_N point. Low potential.
  • the pull-down control module 11 of the preferred embodiment further includes a twelfth switch tube PT12, the control end of the twelfth switch tube PT12 inputs a low-level scan signal U2D, and the input end of the twelfth switch tube PT12 inputs
  • the scan signal G_N+1 of the next stage is connected to the pull-down module 12 at the output of the twelfth switch PT12.
  • the pull-down control module 11 can receive the scan signal G_N+1 of the next stage, and generate a scan level signal of a low level of the corresponding scan line according to the scan signal G_N+1 of the next stage.
  • the reset control module 13 of the preferred embodiment further includes a thirteenth switch tube PT13, the control end of the thirteenth switch tube PT13 inputs a low level scan signal U2D, and the input end of the thirteenth switch tube PT13 is input to the previous one.
  • the reset control module 13 can receive the clock signal CK_N-1 of the previous stage and generate a reset signal of the corresponding scan line according to the clock signal CK_N-1 of the previous stage.
  • the drive scan circuit 10 of the preferred embodiment can also implement the function of reverse scan through the twelfth switch tube PT12 and the thirteenth switch tube PT13.
  • the scan driving circuit 10 of the preferred embodiment uses a P-type metal oxide semiconductor type transistor control pull-down control module 11, a pull-down module 12, a reset control module 13, and a reset module 14.
  • the N-type metal oxide semiconductor type transistor can also be used here to control the pull-down control module 11, the pull-down module 12, the reset control module 13, and the reset module 14.
  • the scan driving circuit of the present invention controls the sixth switching transistor PT6 and the seventh switching transistor PT7 by the pull-down control signals ST_N and ST_N-1, and can better ensure that the fifth switching transistor OT5 and the eighth switching transistor PT8 are charged at the Q point.
  • the off state ensures the low potential state of the Q point, improves the reliability of the scan driving circuit, and the structure of the entire scan driving circuit is simple.
  • FIG. 3 is a structural diagram of a specific circuit of a second preferred embodiment of the scan driving circuit of the present invention.
  • the scan driving circuit 20 of the preferred embodiment is based on the first preferred embodiment.
  • the reset module 24 further includes a fourteenth switch tube PT14.
  • the control end of the fourteenth switch tube PT14 is connected to the output end of the fourth switch tube PT4.
  • the input end of the fourteenth switch tube PT14 is connected to the constant voltage high level source, and the output end of the fourteenth switch tube PT14 is connected to the control end of the sixth switch tube PT6.
  • the preferred embodiment controls the conduction and disconnection of the sixth switch tube PT6 through the output of the fourteenth switch tube PT14, thereby avoiding the leakage phenomenon of the sixth switch tube PT6 caused by the instability of the pull-down control signal. Therefore, the preferred embodiment further improves the reliability of the scan driving circuit.
  • FIG. 4A is a detailed circuit configuration diagram of a third preferred embodiment of the scan driving circuit of the present invention
  • FIG. 4B is a signal waveform diagram of a third preferred embodiment of the scan driving circuit of the present invention.
  • the scanning drive circuit 30 of the preferred embodiment is based on the second preferred embodiment.
  • the reset module 34 further includes a fifteenth switch tube PT15.
  • the control end of the fifteenth switch tube PT15 inputs a pull-down control signal ST_N of the previous stage. 1.
  • the input end of the fifteenth switch tube PT15 is connected to the constant voltage high level source, and the output end PT15 of the fifteenth switch tube is connected to the output end of the fourth switch tube PT4.
  • the clock signal CK_N is output in four groups, that is, the waveforms of CK_N and CK_N+4 are the same.
  • the fifteenth switch PT15 is also on
  • the one-stage pull-down control signal ST_N-1 is controlled to be turned on, so that the off state of the fifth switch tube PT5 and the eighth switch tube PT8 can be better ensured, and the low potential state of the Q point is ensured, in the second embodiment.
  • the reliability of the scan driving circuit is further improved.
  • FIG. 5A is a detailed circuit configuration diagram of a fourth preferred embodiment of the scan driving circuit of the present invention
  • FIG. 5B is a signal waveform diagram of a fourth preferred embodiment of the scan driving circuit of the present invention.
  • the scan driving circuit 40 of the preferred embodiment is based on the third preferred embodiment.
  • the pull-down module 42 further includes a sixteenth switch tube PT16.
  • the control end of the sixteenth switch tube PT16 inputs a pull-down control signal ST_N of the previous stage. 1.
  • the input end of the sixteenth switch tube PT16 is connected to the constant voltage low level source VGL, and the output end of the sixteenth switch tube PT16 is connected to the output end of the second switch tube PT2.
  • the constant voltage low level source VGL lowers the potential of the Q point through the sixteenth switch tube PT16, thereby ensuring the low potential state of the Q point, and further improves the scanning based on the third embodiment.
  • the reliability of the drive circuit is not limited to the constant voltage low level source VGL.
  • each stage of the driving circuit refers to a driving signal (such as a scanning signal or a pull-down control signal lamp) of the driving circuit of the previous stage.
  • the scan driving circuit of the present invention can also be used in the bilateral cascade driving circuit, that is, the driving circuit of each stage refers to the driving signals of the driving circuits of the first two machines.
  • the scan driving circuit of the invention improves the reliability of the scan driving circuit by the setting of the pull-down control module and the reset control module, and the structure of the whole scan driving circuit is simple; the structure of the existing scan driving circuit is complicated and the reliability is low. Technical problem.

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Abstract

提供了一种扫描驱动电路（10），用于对级联的扫描线进行驱动操作。该驱动电路（10）包括下拉控制模块（11），用于接收上级的扫描信号（G_N-1）或下级的扫描信号（G_N+1），并生成相应的扫描电平信号；下拉模块（12），用于拉低所述扫描线的扫描信号（G_N）；复位控制模块（13），用于接收上级的时钟信号（CK_N-1）或下级的时钟信号（CK_N+1），并生成相应的扫描线的复位信号；复位模块（14），用于根据复位信号，拉升相应的所述扫描线的扫描信号（G_N）；下传模块（15），用于根据所述扫描线的扫描信号（G_N），生成并发送本级的时钟信号（CK_N）以及下拉控制信号（ST_N）；还包括第一自举电容（C1）、恒压低电平源（VGL）以及恒压高电平源（VGH）。该扫描驱动电路（10）的整体结构简单，且能耗较小。

Description

一种扫描驱动电路 技术领域
本发明涉及显示驱动领域，特别是涉及一种扫描驱动电路。
 背景技术
Gate Driver On Array，简称GOA，即在现有薄膜晶体管液晶显示器的阵列基板上制作扫描驱动电路，实现对扫描线逐行扫描的驱动方式。现有扫描驱动电路包括下拉控制模块、下拉模块、下传模块、复位控制模块、自举电容以及复位控制模块。
该扫描驱动电路在高温状态下工作时，容易出现延时以及漏电的问题，从而影响该扫描驱动电路的可靠性。
故，有必要提供一种扫描驱动电路，以解决现有技术所存在的问题。
 技术问题
本发明的目的在于提供一种结构简单且可靠性高的扫描驱动电路，以解决现有的扫描驱动电路的结构复杂且可靠性低的技术问题。
 技术解决方案
为解决上述问题，本发明提供的技术方案如下：
本发明实施例提供一种扫描驱动电路，用于对级联的扫描线进行驱动操作，其包括：
下拉控制模块，用于接收上级的扫描信号或下级的扫描信号，并根据所述上级的扫描信号或所述下级的扫描信号生成相应的所述扫描线的低电平的扫描电平信号；
下拉模块，用于根据所述扫描电平信号，拉低相应的所述扫描线的扫描信号；
复位控制模块，用于接收上级的时钟信号或下级的时钟信号，并根据所述上级的时钟信号或所述下级的时钟信号，生成相应的所述扫描线的复位信号；
复位模块，用于根据复位信号，拉升相应的所述扫描线的扫描信号；
下传模块，用于根据所述扫描线的扫描信号，生成并发送本级的时钟信号以及下拉控制信号；
第一自举电容，用于生成所述扫描线的扫描电平信号的低电平或高电平；
恒压低电平源，用于提供所述低电平信号；以及
恒压高电平源，用于提供所述高电平信号；
其中所述下拉控制模块包括第十二开关管，所述第十二开关管的控制端输入低电平的扫描信号，所述第十二开关管的输入端输入所述下级的扫描信号；所述第十二开关管的输出端与所述下拉模块连接；
所述复位控制模块包括第十三开关管，所述第十三开关管的控制端输入所述低电平的扫描信号，所述第十三开关管的输入端输入所述上级的时钟信号，所述第十三开关管的输出端输出所述扫描线的复位信号。
在本发明所述的扫描驱动电路中，所述下拉控制模块包括第一开关管，所述第一开关管的控制端输入低电平的扫描信号，所述第一开关管的输入端输入所述上级的扫描信号；所述第一开关管的输出端与所述下拉模块连接。
在本发明所述的扫描驱动电路中，所述下拉模块包括第二开关管，所述第二开关管的控制端输入上一级的下拉控制信号，所述第二开关管的输入端与所述第一开关管的输出端连接，所述第二开关管的输出端输出所述扫描线的低电平的扫描电平信号。
在本发明所述的扫描驱动电路中，所述复位控制模块包括第三开关管，所述第三开关管的控制端输入所述低电平的扫描信号，所述第三开关管的输入端输入所述下级的时钟信号，所述第三开关管的输出端输出所述扫描线的复位信号。
在本发明所述的扫描驱动电路中，所述复位模块包括第四开关管、第五开关管、第六开关管、第七开关管以及第八开关管；
所述第四开关管的控制端与所述第三开关管的输出端连接，所述第四开关管的输入端与所述恒压低电平源连接，所述第四开关管的输出端分别与所述第五开关管的控制端、所述第八开关管的控制端、所述第六开关管的输出端以及所述第七开关管的输出端连接；
所述第五开关管的输入端与所述恒压高电平源连接，所述第五开关管的输出端与所述第二开关管的输出端连接；
所述第六开关管的控制端输入本级的所述下拉控制信号，所述第六开关管的输入端与所述恒压高电平源连接；
所述第七开关管的控制端输入上一级的所述下拉控制信号，所述第七开关管的输入端与所述恒压高电平源连接；
所述第八开关管的输入端与所述恒压高电平源连接，所述第八开关管的输出端输出所述扫描线的本级的扫描信号。
在本发明所述的扫描驱动电路中，所述复位模块还包括第十四开关管，
所述第十四开关管的控制端与所述第四开关管的输出端连接，所述第十四开关管的输入端与所述恒压高电平源连接，所述第十四开关管的输出端与所述第六开关管的控制端连接。
在本发明所述的扫描驱动电路中，所述复位模块还包括第十五开关管，所述第十五开关管的控制端输入上一级的所述下拉控制信号，所述第十五开关管的输入端与所述恒压高电平源连接，所述第十五开关管的输出端与所述第四开关管的输出端连接。
在本发明所述的扫描驱动电路中，所述下拉模块还包括第十六开关管，所述第十六开关管的控制端输入上一级的所述下拉控制信号，所述第十六开关管的输入端与所述恒压低电平源连接，所述第十六开关管的输出端与所述第二开关管的输出端连接。
在本发明所述的扫描驱动电路中，所述下传模块包括第九开关管和第十一开关管，所述第九开关管的控制端与所述第二开关管的输出端连接，所述第九开关管的输入端与所述第八开关管的输出端连接，所述第九开关管的输出端输出所述本级的时钟信号；
所述第十一开关管的控制端与所述第二开关管的输出端连接，所述第十一开关管的输入端与所述第九开关管的输出端连接，所述第十一开关管的输出端输出本级的下拉控制信号。
在本发明所述的扫描驱动电路中，所述复位模块还包括第十四开关管以及第十五开关管
所述第十四开关管的控制端与所述第四开关管的输出端连接，所述第十四开关管的输入端与所述恒压高电平源连接，所述第十四开关管的输出端与所述第六开关管的控制端连接；
所述第十五开关管的控制端输入上一级的所述下拉控制信号，所述第十五开关管的输入端与所述恒压高电平源连接，所述第十五开关管的输出端与所述第四开关管的输出端连接。
在本发明所述的扫描驱动电路中，所述下拉模块还包括第十六开关管，所述第十六开关管的控制端输入上一级的所述下拉控制信号，所述第十六开关管的输入端与所述恒压低电平源连接，所述第十六开关管的输出端与所述第二开关管的输出端连接。
本发明实施例提供一种扫描驱动电路，用于对级联的扫描线进行驱动操作，其包括：
下拉控制模块，用于接收上级的扫描信号或下级的扫描信号，并根据所述上级的扫描信号或所述下级的扫描信号生成相应的所述扫描线的低电平的扫描电平信号；
下拉模块，用于根据所述扫描电平信号，拉低相应的所述扫描线的扫描信号；
复位控制模块，用于接收上级的时钟信号或下级的时钟信号，并根据所述上级的时钟信号或所述下级的时钟信号，生成相应的所述扫描线的复位信号；
复位模块，用于根据复位信号，拉升相应的所述扫描线的扫描信号；
下传模块，用于根据所述扫描线的扫描信号，生成并发送本级的时钟信号以及下拉控制信号；
第一自举电容，用于生成所述扫描线的扫描电平信号的低电平或高电平；
恒压低电平源，用于提供所述低电平信号；以及
恒压高电平源，用于提供所述高电平信号。
在本发明所述的扫描驱动电路中，所述下拉控制模块包括第一开关管，所述第一开关管的控制端输入低电平的扫描信号，所述第一开关管的输入端输入所述上级的扫描信号；所述第一开关管的输出端与所述下拉模块连接。
在本发明所述的扫描驱动电路中，所述下拉模块包括第二开关管，所述第二开关管的控制端输入上一级的下拉控制信号，所述第二开关管的输入端与所述第一开关管的输出端连接，所述第二开关管的输出端输出所述扫描线的低电平的扫描电平信号。
在本发明所述的扫描驱动电路中，所述复位控制模块包括第三开关管，所述第三开关管的控制端输入所述低电平的扫描信号，所述第三开关管的输入端输入所述下级的时钟信号，所述第三开关管的输出端输出所述扫描线的复位信号。
在本发明所述的扫描驱动电路中，所述复位模块包括第四开关管、第五开关管、第六开关管、第七开关管以及第八开关管；
所述第四开关管的控制端与所述第三开关管的输出端连接，所述第四开关管的输入端与所述恒压低电平源连接，所述第四开关管的输出端分别与所述第五开关管的控制端、所述第八开关管的控制端、所述第六开关管的输出端以及所述第七开关管的输出端连接；
所述第五开关管的输入端与所述恒压高电平源连接，所述第五开关管的输出端与所述第二开关管的输出端连接；
所述第六开关管的控制端输入本级的所述下拉控制信号，所述第六开关管的输入端与所述恒压高电平源连接；
所述第七开关管的控制端输入上一级的所述下拉控制信号，所述第七开关管的输入端与所述恒压高电平源连接；
所述第八开关管的输入端与所述恒压高电平源连接，所述第八开关管的输出端输出所述扫描线的本级的扫描信号。
在本发明所述的扫描驱动电路中，所述复位模块还包括第十四开关管，
所述第十四开关管的控制端与所述第四开关管的输出端连接，所述第十四开关管的输入端与所述恒压高电平源连接，所述第十四开关管的输出端与所述第六开关管的控制端连接。
在本发明所述的扫描驱动电路中，所述复位模块还包括第十五开关管，所述第十五开关管的控制端输入上一级的所述下拉控制信号，所述第十五开关管的输入端与所述恒压高电平源连接，所述第十五开关管的输出端与所述第四开关管的输出端连接。
在本发明所述的扫描驱动电路中，所述下拉模块还包括第十六开关管，所述第十六开关管的控制端输入上一级的所述下拉控制信号，所述第十六开关管的输入端与所述恒压低电平源连接，所述第十六开关管的输出端与所述第二开关管的输出端连接。
在本发明所述的扫描驱动电路中，所述下传模块包括第九开关管和第十一开关管，所述第九开关管的控制端与所述第二开关管的输出端连接，所述第九开关管的输入端与所述第八开关管的输出端连接，所述第九开关管的输出端输出所述本级的时钟信号；
所述第十一开关管的控制端与所述第二开关管的输出端连接，所述第十一开关管的输入端与所述第九开关管的输出端连接，所述第十一开关管的输出端输出本级的下拉控制信号。
 有益效果
相较于现有的扫描驱动电路，本发明的扫描驱动电路通过下拉控制模块以及复位控制模块的设置，提高了扫描驱动电路的可靠性，同时整个扫描驱动电路的结构简单；解决了现有的扫描驱动电路的结构复杂且可靠性低的技术问题。
 附图说明
图1为本发明的扫描驱动电路的优选实施例的结构示意图；
图2A为本发明的扫描驱动电路的第一优选实施例的具体电路结构图；
图2B为本发明的扫描驱动电路的第一优选实施例的信号波形图；
图3为本发明的扫描驱动电路的第二优选实施例的具体电路结构图；
图4A为本发明的扫描驱动电路的第三优选实施例的具体电路结构图；
图4B为本发明的扫描驱动电路的第三优选实施例的信号波形图；
图5A为本发明的扫描驱动电路的第四优选实施例的具体电路结构图；
图5B为本发明的扫描驱动电路的第四优选实施例的信号波形图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
在图中，结构相似的单元是以相同标号表示。
请参照图1，图1为本发明的扫描驱动电路的优选实施例的结构示意图。本优选实施例的扫描驱动电路10用于对级联的扫描线进行驱动操作，该扫描驱动电路10包括下拉控制模块11、下拉模块12、复位控制模块13、复位模块14、下传模块15、防漏电模块16、第一自举电容C1、恒压低电平源VGL以及恒压高电平源VGH。
下拉控制模块11用于接收上一级的扫描信号G_N-1，并根据上一级的扫描信号G_N-1生成相应的扫描线的低电平的扫描电平信号。下拉模块12用于根据扫描电平信号，拉低相应的扫描线的扫描信号G_N。复位控制模块13用于接收下一级的时钟信号CK_N+1，并根据下一级的时钟信号CK_N+1，生成相应的扫描线的复位信号。复位模块14用于根据复位信号，拉升相应的扫描线的扫描信号G_N。下传模块15用于根据扫描线的扫描信号G_N，生成并发送本级的时钟信号CK_N。第一自举电容C1用于生成扫描线的扫描电平信号的低电平或高电平。恒压低电平源VGL用于提供低电平信号；恒压高电平源VGH用于提供高电平信号。
请参照图2A和图2B，图2为本发明的扫描驱动电路的第一优选实施例的具体电路结构图，图2B为本发明的扫描驱动电路的第一优选实施例的信号波形图。在本优选实施例中，下拉控制模块11包括第一开关管PT1，第一开关管PT1的控制端输入低电平的扫描信号D2U，第一开关管PT1的输入端输入上一级的扫描信号G_N-1,第一开关管PT1的输出端与下拉模块12连接，向下拉模块12输出上一级的扫描信号G_N-1。
下拉模块12包括第二开关管PT2，第二开关管PT2的控制端与第一开关管PT1的输出端连接，第二开关管PT2的输入端与第一开关管PT1的输出端连接，第二开关管PT2的输出端输出上一级扫描线的低电平的扫描信号G_N-1。
复位控制模块13包括第三开关管PT3，第三开关管PT3的控制端输入低电平的扫描信号D2U，第三开关管PT3的输入端输入下一级的时钟信号CK_N+1，第三开关管PT3的输出端输出扫描线的复位信号，即输出下一级的时钟信号CK_N+1。
复位模块14包括第四开关管PT4、第五开关管PT5、第六开关管PT6、第七开关管PT7以及第二自举电容C2。第四开关管PT4的控制端与第三开关管PT3的输出端连接，第四开关管PT4的输入端与恒压低电平源VGL连接，第四开关管PT4的输出端分别与第五开关管PT5的控制端、第七开关管PT7的控制端、第六开关管PT6的输出端以及第十开关管PT8的控制端连接。
第五开关管PT5的输入端与恒压高电平源VGH连接，第五开关管PT5的输出端与第二开关管PT2的输出端连接。
第六开关管PT6的控制端输入本级的下拉控制信号ST_N，第六开关管PT6的输入端与恒压高电平源VGH连接。
第七开关管PT7的输入端输入上一级的下拉控制信号ST_N-1，第七开关管PT7的输入端与恒压高电平源VGH连接。
第八开关管PT8的输入端与恒压高电平源VGH连接，第八开关管PT8的输出端输出扫描线的本级的扫描信号G_N。
第二自举电容C2的一端与恒压高电平源VGH连接，第二自举电容C2的另一端与第四开关管PT4的输出端连接。
下传模块15包括第九开关管PT9和第十一开关管PT11，第九开关管PT9的控制端与第二开关管PT2的输出端连接，第九开关管PT9的输入端与第八开关管PT8的输出端连接，第九开关管PT9的输出端输出本级的时钟信号CK_N。
第十一开关管PT11的控制端与第二开关管PT2的输出端连接，第十一开关管PT11的输入端与第九开关管PT9的输出端连接，第十一开关管PT11的输出端输出本级的下拉控制信号ST_N。
第一自举电容C1的一端与第二开关管PT2的输出端连接，第一自举电容C1的另一端与第八开关管PT8的输出端连接。
防漏电模块16包括第十开关管PT10，第十开关管PT10的控制端与恒压低电平源VGL连接，第十开关管PT10的输入端与第二开关管PT2的输出端连接，第十开关管PT10的输出端通过第一自举电容C1与第八开关管PT8的输出端连接。
下面结合图2A和图2B详细说明本优选实施例的扫描驱动电路的具体工作原理。其中时钟信号CK_N以两组为循环输出，即CK_N和CK_N+2的波形是相同的。首先上一级的扫描信号G_N-1输出低电平信号，这时由于下拉控制模块11的第一开关管PT1在低电平的扫描信号D2U的控制下，处于导通状态；因此第一开关管PT1的输出端向下拉模块12的第二开关管PT2的输入端输入上一级的扫描信号G_N-1。
同时上一级的下拉控制信号ST_N-1也输出低电平信号，这时第二开关管PT2和第七开关管PT7导通，第二开关管PT2的输出端输出低电平信号G_N-1。
复位模块14的第七开关管PT7导通，第五开关管PT5的控制端和第八开关管PT8的控制端分别通过第七开关管PT7与恒压高电平源VGH连接，因此第五开关管PT5和第八开关管PT8断开。
防漏电模块16的第十开关管PT10在恒压低电平源VGL的控制下导通，下拉模块12的第二开关管PT2输出的低电平信号G_N-1通过第十开关管PT10作用于第一自举电容C1上，使得Q_N的电位更低，这样G_N也输出低电平信号，同时下传模块15的第九开关管PT9，在Q_N的控制下也导通，第九开关管PT9的输出端输出本级的低电平的时钟信号CK_N至上一级的扫描线的驱动电路。
同时第十一开关管PT11在Q_N的控制下也导通，第十一开关管PT11的输出端输出本级的低电平的下拉控制信号ST_N，第六开关管PT6在下拉控制信号ST_N控制下导通，第五开关管PT5的控制端和第八开关管PT8的控制端分别通过第六开关管PT6与恒压高电平源VGH连接，因此第五开关管PT5和第八开关管PT8依旧断开，从而保证了G_N的低电平输出，避免了第八开关管PT8的漏电对G_N的低电平输出的影响。
当下一级的时钟信号CK_N+1转为低电平时，复位控制模块13的第三开关管PT3在低电平的扫描信号U2D的控制下输入下一级的时钟信号CK_N+1。第三开关管PT3的输出端输出该时钟信号CK_N+1，即复位信号至复位模块14。
复位模块14的第四开关管PT4在复位信号的控制下导通，这时上一级的下拉控制信号ST_N-1转为高电平信号，因此第七开关管PT7均断开，这时第五开关管PT5和第八开关管PT8在复位信号的控制下导通，恒压高电平源VGH的高电平信号通过第五开关管PT5输入到Q点，将Q_N拉高。同时恒压高电平源VGH的高电平信号通过第八开关管PT8输入到G_N，将G_N拉高，同时由于第九开关管PT9和第十一开关管PT11断开，钟信号CK_N和本级的下拉控制信号ST_N也转为高电平。第六开关管PT6在本级的下拉控制信号ST_N的控制下断开，进一步避免了恒压高电平源VGH对第五开关管PT5和第八开关管PT8的影响。
这样即完成了本优选实施例的扫描驱动电路10的低电平的扫描信号的级联输出过程。
优选的，复位模块14中的第二自举电容C2的设置，可以更好的拉高第五开关管PT5的控制端和第八开关管PT8的控制端的电位，从而可较好的保证Q_N点的低电位。
优选的，本优选实施例的下拉控制模块11还包括第十二开关管PT12，该第十二开关管PT12的控制端输入低电平的扫描信号U2D，第十二开关管PT12的输入端输入下一级的扫描信号G_N+1，第十二开关管PT12的输出端与下拉模块12连接。这样下拉控制模块11可接收下一级的扫描信号G_N+1，并根据下一级的扫描信号G_N+1生成相应的扫描线的低电平的扫描电平信号。
同时本优选实施例的复位控制模块13还包括第十三开关管PT13，该第十三开关管PT13的控制端输入低电平的扫描信号U2D，第十三开关管PT13的输入端输入上一级的时钟信号CK_N-1（或CK_N+3），第十三开关管PT13的输出端输出扫描线的复位信号。这样复位控制模块13可接收上一级的时钟信号CK_N-1，并根据上一级的时钟信号CK_N-1，生成相应的扫描线的复位信号。
这样本优选实施例的驱动扫描电路10还可通过第十二开关管PT12和第十三开关管PT13实现反向扫描的功能。
优选的，本优选实施例的扫描驱动电路10使用的是P型金属氧化物半导体类型的晶体管控制下拉控制模块11、下拉模块12、复位控制模块13以及复位模块14。当然这里还可使用N型金属氧化物半导体类型的晶体管控制下拉控制模块11、下拉模块12、复位控制模块13以及复位模块14。
本发明的扫描驱动电路通过下拉控制信号ST_N和ST_N-1控制第六开关管PT6和第七开关管PT7，可以较好的确保第五开关管OT5和第八开关管PT8在Q点充电时的断开状态，保证了Q点的低电位状态，提高了扫描驱动电路的可靠性，同时整个扫描驱动电路的结构简单。
请参照图3，图3为本发明的扫描驱动电路的第二优选实施例的具体电路结构图。本优选实施例的扫描驱动电路20在第一优选实施例的基础上，复位模块24还包括第十四开关管PT14，第十四开关管PT14的控制端与第四开关管PT4的输出端连接，第十四开关管PT14的输入端与恒压高电平源连接，第十四开关管PT14的输出端与第六开关管PT6的控制端连接。
本优选实施例通过第十四开关管PT14的输出来控制第六开关管PT6的导通以及断开，避免了下拉控制信号的不稳定造成的第六开关管PT6的漏电现象产生。因此本优选实施例进一步提高了扫描驱动电路的可靠性。
请参照图4A和图4B，图4A为本发明的扫描驱动电路的第三优选实施例的具体电路结构图；图4B为本发明的扫描驱动电路的第三优选实施例的信号波形图。本优选实施例的扫描驱动电路30在第二优选实施例的基础上，复位模块34还包括第十五开关管PT15，第十五开关管PT15的控制端输入上一级的下拉控制信号ST_N-1，第十五开关管PT15的输入端与恒压高电平源连接，第十五开关管的输出端PT15与第四开关管PT4的输出端连接。
在本优选实施例中，时钟信号CK_N以四组为循环输出，即CK_N和CK_N+4的波形是相同的。为了保证第二开关管PT2的输出的扫描电平信号的稳定性，在第二开关管PT2在上一级的下拉控制信号ST_N-1控制下导通时，第十五开关管PT15也在上一级的下拉控制信号ST_N-1控制下导通，从而可以较好的保证第五开关管PT5和第八开关管PT8的断开状态，保证了Q点的低电位状态，在第二实施例的基础上进一步提高了扫描驱动电路的可靠性。
请参照图5A和图5B，图5A为本发明的扫描驱动电路的第四优选实施例的具体电路结构图；图5B为本发明的扫描驱动电路的第四优选实施例的信号波形图。本优选实施例的扫描驱动电路40在第三优选实施例的基础上，下拉模块42还包括第十六开关管PT16，第十六开关管PT16的控制端输入上一级的下拉控制信号ST_N-1，第十六开关管PT16的输入端与恒压低电平源VGL连接，第十六开关管PT16的输出端与第二开关管PT2的输出端连接。
在本优选实施例中，恒压低电平源VGL通过第十六开关管PT16将Q点的电位拉低，保证了Q点的低电位状态，在第三实施例的基础上进一步提高了扫描驱动电路的可靠性。
上述优选实施例的扫描驱动电路均在单边级联驱动电路中使用，即每一级的驱动电路均引用前一级的驱动电路的驱动信号（如扫描信号或下拉控制信号灯）。同时本发明的扫描驱动电路也可使用在双边级联驱动电路中，即每一级的驱动电路均引用前两机的驱动电路的驱动信号。
本发明的扫描驱动电路通过下拉控制模块以及复位控制模块的设置，提高了扫描驱动电路的可靠性，同时整个扫描驱动电路的结构简单；解决了现有的扫描驱动电路的结构复杂且可靠性低的技术问题。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种扫描驱动电路，用于对级联的扫描线进行驱动操作，其包括：
    下拉控制模块，用于接收上级的扫描信号或下级的扫描信号，并根据所述上级的扫描信号或所述下级的扫描信号生成相应的所述扫描线的低电平的扫描电平信号；
    下拉模块，用于根据所述扫描电平信号，拉低相应的所述扫描线的扫描信号；
    复位控制模块，用于接收上级的时钟信号或下级的时钟信号，并根据所述上级的时钟信号或所述下级的时钟信号，生成相应的所述扫描线的复位信号；
    复位模块，用于根据复位信号，拉升相应的所述扫描线的扫描信号；
    下传模块，用于根据所述扫描线的扫描信号，生成并发送本级的时钟信号以及下拉控制信号；
    第一自举电容，用于生成所述扫描线的扫描电平信号的低电平或高电平；
    恒压低电平源，用于提供所述低电平信号；以及
    恒压高电平源，用于提供所述高电平信号；
    其中所述下拉控制模块包括第十二开关管，所述第十二开关管的控制端输入低电平的扫描信号，所述第十二开关管的输入端输入所述下级的扫描信号；所述第十二开关管的输出端与所述下拉模块连接；
    所述复位控制模块包括第十三开关管，所述第十三开关管的控制端输入所述低电平的扫描信号，所述第十三开关管的输入端输入所述上级的时钟信号，所述第十三开关管的输出端输出所述扫描线的复位信号。
  2. 根据权利要求1所述的扫描驱动电路，其中所述下拉控制模块包括第一开关管，所述第一开关管的控制端输入低电平的扫描信号，所述第一开关管的输入端输入所述上级的扫描信号；所述第一开关管的输出端与所述下拉模块连接。
  3. 根据权利要求2所述的扫描驱动电路，其中所述下拉模块包括第二开关管，所述第二开关管的控制端输入上一级的下拉控制信号，所述第二开关管的输入端与所述第一开关管的输出端连接，所述第二开关管的输出端输出所述扫描线的低电平的扫描电平信号。
  4. 根据权利要求3所述的扫描驱动电路，其中所述复位控制模块包括第三开关管，所述第三开关管的控制端输入所述低电平的扫描信号，所述第三开关管的输入端输入所述下级的时钟信号，所述第三开关管的输出端输出所述扫描线的复位信号。
  5. 根据权利要求4所述的扫描驱动电路，其中所述复位模块包括第四开关管、第五开关管、第六开关管、第七开关管以及第八开关管；
    所述第四开关管的控制端与所述第三开关管的输出端连接，所述第四开关管的输入端与所述恒压低电平源连接，所述第四开关管的输出端分别与所述第五开关管的控制端、所述第八开关管的控制端、所述第六开关管的输出端以及所述第七开关管的输出端连接；
    所述第五开关管的输入端与所述恒压高电平源连接，所述第五开关管的输出端与所述第二开关管的输出端连接；
    所述第六开关管的控制端输入本级的所述下拉控制信号，所述第六开关管的输入端与所述恒压高电平源连接；
    所述第七开关管的控制端输入上一级的所述下拉控制信号，所述第七开关管的输入端与所述恒压高电平源连接；
    所述第八开关管的输入端与所述恒压高电平源连接，所述第八开关管的输出端输出所述扫描线的本级的扫描信号。
  6. 根据权利要求5所述的扫描驱动电路，其中所述复位模块还包括第十四开关管，
    所述第十四开关管的控制端与所述第四开关管的输出端连接，所述第十四开关管的输入端与所述恒压高电平源连接，所述第十四开关管的输出端与所述第六开关管的控制端连接。
  7. 根据权利要求6所述的扫描驱动电路，其中所述复位模块还包括第十五开关管，所述第十五开关管的控制端输入上一级的所述下拉控制信号，所述第十五开关管的输入端与所述恒压高电平源连接，所述第十五开关管的输出端与所述第四开关管的输出端连接。
  8. 根据权利要求7所述的扫描驱动电路，其中所述下拉模块还包括第十六开关管，所述第十六开关管的控制端输入上一级的所述下拉控制信号，所述第十六开关管的输入端与所述恒压低电平源连接，所述第十六开关管的输出端与所述第二开关管的输出端连接。
  9. 根据权利要求5所述的扫描驱动电路，其中所述下传模块包括第九开关管和第十一开关管，所述第九开关管的控制端与所述第二开关管的输出端连接，所述第九开关管的输入端与所述第八开关管的输出端连接，所述第九开关管的输出端输出所述本级的时钟信号；
    所述第十一开关管的控制端与所述第二开关管的输出端连接，所述第十一开关管的输入端与所述第九开关管的输出端连接，所述第十一开关管的输出端输出本级的下拉控制信号。
  10. 根据权利要求9所述的扫描驱动电路，其中所述复位模块还包括第十四开关管以及第十五开关管
    所述第十四开关管的控制端与所述第四开关管的输出端连接，所述第十四开关管的输入端与所述恒压高电平源连接，所述第十四开关管的输出端与所述第六开关管的控制端连接；
    所述第十五开关管的控制端输入上一级的所述下拉控制信号，所述第十五开关管的输入端与所述恒压高电平源连接，所述第十五开关管的输出端与所述第四开关管的输出端连接。
  11. 根据权利要求10所述的扫描驱动电路，其中所述下拉模块还包括第十六开关管，所述第十六开关管的控制端输入上一级的所述下拉控制信号，所述第十六开关管的输入端与所述恒压低电平源连接，所述第十六开关管的输出端与所述第二开关管的输出端连接。
  12. 一种扫描驱动电路，用于对级联的扫描线进行驱动操作，其包括：
    下拉控制模块，用于接收上级的扫描信号或下级的扫描信号，并根据所述上级的扫描信号或所述下级的扫描信号生成相应的所述扫描线的低电平的扫描电平信号；
    下拉模块，用于根据所述扫描电平信号，拉低相应的所述扫描线的扫描信号；
    复位控制模块，用于接收上级的时钟信号或下级的时钟信号，并根据所述上级的时钟信号或所述下级的时钟信号，生成相应的所述扫描线的复位信号；
    复位模块，用于根据复位信号，拉升相应的所述扫描线的扫描信号；
    下传模块，用于根据所述扫描线的扫描信号，生成并发送本级的时钟信号以及下拉控制信号；
    第一自举电容，用于生成所述扫描线的扫描电平信号的低电平或高电平；
    恒压低电平源，用于提供所述低电平信号；以及
    恒压高电平源，用于提供所述高电平信号。
  13. 根据权利要求12所述的扫描驱动电路，其中所述下拉控制模块包括第一开关管，所述第一开关管的控制端输入低电平的扫描信号，所述第一开关管的输入端输入所述上级的扫描信号；所述第一开关管的输出端与所述下拉模块连接。
  14. 根据权利要求13所述的扫描驱动电路，其中所述下拉模块包括第二开关管，所述第二开关管的控制端输入上一级的下拉控制信号，所述第二开关管的输入端与所述第一开关管的输出端连接，所述第二开关管的输出端输出所述扫描线的低电平的扫描电平信号。
  15. 根据权利要求14所述的扫描驱动电路，其中所述复位控制模块包括第三开关管，所述第三开关管的控制端输入所述低电平的扫描信号，所述第三开关管的输入端输入所述下级的时钟信号，所述第三开关管的输出端输出所述扫描线的复位信号。
  16. 根据权利要求15所述的扫描驱动电路，其中所述复位模块包括第四开关管、第五开关管、第六开关管、第七开关管以及第八开关管；
    所述第四开关管的控制端与所述第三开关管的输出端连接，所述第四开关管的输入端与所述恒压低电平源连接，所述第四开关管的输出端分别与所述第五开关管的控制端、所述第八开关管的控制端、所述第六开关管的输出端以及所述第七开关管的输出端连接；
    所述第五开关管的输入端与所述恒压高电平源连接，所述第五开关管的输出端与所述第二开关管的输出端连接；
    所述第六开关管的控制端输入本级的所述下拉控制信号，所述第六开关管的输入端与所述恒压高电平源连接；
    所述第七开关管的控制端输入上一级的所述下拉控制信号，所述第七开关管的输入端与所述恒压高电平源连接；
    所述第八开关管的输入端与所述恒压高电平源连接，所述第八开关管的输出端输出所述扫描线的本级的扫描信号。
  17. 根据权利要求16所述的扫描驱动电路，其中所述复位模块还包括第十四开关管，
    所述第十四开关管的控制端与所述第四开关管的输出端连接，所述第十四开关管的输入端与所述恒压高电平源连接，所述第十四开关管的输出端与所述第六开关管的控制端连接。
  18. 根据权利要求17所述的扫描驱动电路，其中所述复位模块还包括第十五开关管，所述第十五开关管的控制端输入上一级的所述下拉控制信号，所述第十五开关管的输入端与所述恒压高电平源连接，所述第十五开关管的输出端与所述第四开关管的输出端连接。
  19. 根据权利要求18所述的扫描驱动电路，其中所述下拉模块还包括第十六开关管，所述第十六开关管的控制端输入上一级的所述下拉控制信号，所述第十六开关管的输入端与所述恒压低电平源连接，所述第十六开关管的输出端与所述第二开关管的输出端连接。
  20. 根据权利要求16所述的扫描驱动电路，其中所述下传模块包括第九开关管和第十一开关管，所述第九开关管的控制端与所述第二开关管的输出端连接，所述第九开关管的输入端与所述第八开关管的输出端连接，所述第九开关管的输出端输出所述本级的时钟信号；
    所述第十一开关管的控制端与所述第二开关管的输出端连接，所述第十一开关管的输入端与所述第九开关管的输出端连接，所述第十一开关管的输出端输出本级的下拉控制信号。
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