WO2016171157A1 - Photoelectric conversion device - Google Patents

Photoelectric conversion device Download PDF

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Publication number
WO2016171157A1
WO2016171157A1 PCT/JP2016/062471 JP2016062471W WO2016171157A1 WO 2016171157 A1 WO2016171157 A1 WO 2016171157A1 JP 2016062471 W JP2016062471 W JP 2016062471W WO 2016171157 A1 WO2016171157 A1 WO 2016171157A1
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semiconductor layer
layer
photoelectric conversion
conversion device
electrode
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PCT/JP2016/062471
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French (fr)
Japanese (ja)
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順次 荒浪
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京セラ株式会社
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K30/00—Organic devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation
    • H10K30/80—Constructional details
    • H10K30/84—Layers having high charge carrier mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
    • H01L31/0749—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type including a AIBIIICVI compound, e.g. CdS/CulnSe2 [CIS] heterojunction solar cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/541—CuInSe2 material PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells

Definitions

  • the present invention relates to a photoelectric conversion device including a compound semiconductor layer.
  • Such a photoelectric conversion device has a configuration in which a plurality of photoelectric conversion cells are arranged side by side in a plane.
  • Each photoelectric conversion cell includes a lower electrode such as a metal electrode on a substrate such as glass, a light absorption layer including a metal chalcogenide such as CIGS, and a buffer layer including indium sulfide heterojunction to the light absorption layer.
  • the upper electrode such as a transparent electrode or a metal electrode is laminated in this order.
  • the plurality of photoelectric conversion cells are electrically connected in series by electrically connecting the upper electrode of one adjacent photoelectric conversion cell and the lower electrode of the other photoelectric conversion cell by a connecting conductor. Yes.
  • the photoelectric conversion device includes an electrode layer, a first semiconductor layer, a second semiconductor layer, and an intermediate layer.
  • the first semiconductor layer is located on the electrode layer.
  • the first semiconductor layer is p-type or i-type and mainly contains a chalcopyrite compound or a perovskite compound.
  • the second semiconductor layer is n-type and is located on the first semiconductor layer.
  • the intermediate layer is located at the interface between the first semiconductor layer and the second semiconductor layer, and is an n-type semiconductor layer mainly containing silicon.
  • FIG. 1 is a perspective view showing the photoelectric conversion device according to the first embodiment, and FIG. 2 is a sectional view thereof.
  • the photoelectric conversion device 11 includes a plurality of photoelectric conversion cells 10 on a substrate 1. These photoelectric conversion cells 10 are arranged with a space P3 therebetween, and the adjacent photoelectric conversion cells 10 are electrically connected to each other. In FIG. 1, only two photoelectric conversion cells 10 are shown for convenience of illustration. However, in an actual photoelectric conversion device 11, a large number of photoelectric conversion cells are arranged in the horizontal direction of the drawing or in a direction perpendicular thereto. The cells 10 may be arranged in a plane (two-dimensionally).
  • the + Z direction in the figure is described as the upper side.
  • the + Z direction is not necessarily the upper side and may be the lower side.
  • the plurality of electrode layers 2 include electrode layers 2a to 2c arranged with a spacing P1 in one direction.
  • a first semiconductor layer 3, an intermediate layer 5a, and a second semiconductor layer 5 are sequentially stacked from the electrode layer 2a through the substrate 1 to the electrode layer 2b.
  • the connection conductor 7 is provided along or through the side surfaces of the first semiconductor layer 3 and the intermediate layer 5a.
  • the connection conductor 7 electrically connects the second semiconductor layer 5 and the electrode layer 2b.
  • the electrode layer 2, the first semiconductor layer 3, the intermediate layer 5 a, and the second semiconductor layer 5 constitute one photoelectric conversion cell 10, and adjacent photoelectric conversion cells 10 are connected in series via the connection conductor 7. As a result, a high-output photoelectric conversion device 11 is obtained.
  • the photoelectric conversion apparatus 11 in this embodiment assumes what light injects into the 1st semiconductor layer 3 from the 2nd semiconductor layer 5 side, it is not limited to this, The electrode layer 2 side The light may be incident on the first semiconductor layer 3.
  • the substrate 1 is for supporting the photoelectric conversion cell 10.
  • Examples of the material used for the substrate 1 include glass, ceramics, resin, and metal.
  • the electrode layer 2 (electrode layers 2a, 2b, 2c) is a conductor such as Mo, Al, Ti, or Au provided on the substrate 1.
  • the electrode layer 2 is formed to a thickness of about 0.2 ⁇ m to 1 ⁇ m using a known thin film forming method such as sputtering or vapor deposition.
  • the first semiconductor layer 3 is a semiconductor layer that functions to absorb light and generate carriers (electrons and holes), and is a so-called light absorption layer.
  • the first semiconductor layer 3 is a p-type or i-type semiconductor layer having a thickness of about 1 ⁇ m to 3 ⁇ m, for example.
  • the first semiconductor layer 3 mainly contains a chalcopyrite compound or mainly contains a perovskite compound. “Containing mainly chalcopyrite compounds” means containing at least 70 mol% of chalcopyrite compounds.
  • the phrase “mainly containing a perovskite compound” means containing 70 mol% or more of a perovskite compound.
  • the chalcopyrite compound is a compound having a chalcopyrite structure, and examples thereof include I-III-VI group compounds.
  • the group I-III-VI compound is a compound of a group 11 element (also referred to as a group IB element), a group 13 element (also referred to as a group III-B element), and a group 16 element.
  • Examples of the I-III-VI group compounds include CuInSe 2 (also referred to as copper indium diselenide, CIS), Cu (In, Ga) Se 2 (also referred to as copper indium diselenide / gallium, CIGS), Cu ( In, Ga) (Se, S) 2 (also referred to as diselene / copper indium / gallium / CIGSS).
  • the first semiconductor layer 3 may be composed of a multi-component compound semiconductor thin film such as copper indium selenide / gallium having a thin film of selenite / copper indium sulfide / gallium layer as a surface layer.
  • a multi-component compound semiconductor thin film such as copper indium selenide / gallium having a thin film of selenite / copper indium sulfide / gallium layer as a surface layer.
  • the perovskite compound is a compound having a perovskite structure, and examples thereof include organic-inorganic composite materials such as CH 3 NH 3 PbX 3 (X is a halogen element).
  • the organic-inorganic composite material is a material in which an organic component and an inorganic component are combined at the molecular level.
  • a structure containing no organic substance such as APbX 3 (A is an alkali metal element such as Cs and X is a halogen element) is also included in the perovskite compound.
  • a perovskite compound containing Pb and having X composed of a halogen element is preferably used.
  • the halogen element represented by X may include two or more elements, and an organic substance such as CH 3 NH 3 and an alkali metal such as Cs may also include two or more elements. .
  • an organic substance such as CH 3 NH 3 and an alkali metal such as Cs may also include two or more elements.
  • the first semiconductor layer 3 can be formed by a so-called vacuum process such as a sputtering method or an evaporation method, or can be formed by a process called a coating method or a printing method.
  • a process referred to as a coating method or a printing method is a process in which a complex solution of constituent elements of the first semiconductor layer 3 is applied on the intermediate layer 3a or the electrode layer 2, and then drying and heat treatment are performed.
  • the second semiconductor layer 5 is an n-type semiconductor layer having a thickness of about 0.05 to 3.0 ⁇ m, for example.
  • the second semiconductor layer 5 is for extracting the carriers generated in the first semiconductor layer 3 satisfactorily.
  • the electrical resistivity of the second semiconductor layer 5 is 1 ⁇ ⁇ cm or less, and the sheet resistance May be 50 ⁇ / ⁇ or less.
  • the second semiconductor layer 5 includes, for example, a metal oxide such as ZnO, In 2 O 3 , or SnO 2 , and includes Al, B, Ga, In, Sn, F, and the like in order to reduce the electrical resistivity. Any of these elements may be included. Specific examples of the metal oxide semiconductor containing such an element include, for example, AZO (Aluminum Zinc Oxide), BZO (Boron Zinc Oxide), GZO (Gallium Zinc Oxide), IZO (Indium Zinc Oxide), ITO ( Indium Tin Oxide) and FTO (Fluorine tin Oxide).
  • the first semiconductor layer 5 is formed by a sputtering method, a vapor deposition method, a CVD method, or the like.
  • the second semiconductor layer 5 may be a single layer or a laminate of two or more layers.
  • the second semiconductor layer is composed of two or more layers, at least one of the plurality of layers may be n-type. That is, the second semiconductor layer may be a stacked body of an n-type semiconductor layer and an i-type semiconductor layer, or may be a stacked body of an n-type semiconductor layer. Further, the second semiconductor layer 5 may be a stacked body of semiconductor layers having different electric resistivity, and in that case, it is possible to effectively reduce the occurrence of leakage current due to the semiconductor layer having a high electric resistivity. .
  • the intermediate layer 5 a is located at the interface between the first semiconductor layer 3 and the second semiconductor layer 5. That is, the first semiconductor layer 3 is electrically connected to the second semiconductor layer 5 via the intermediate layer 5a.
  • the intermediate layer 5a is an n-type semiconductor layer mainly containing silicon and has a thickness of about 30 to 2000 nm.
  • the intermediate layer 5a is an n-type semiconductor layer mainly containing silicon, the dopant concentration can be well controlled, and the carriers separated by charge in the first semiconductor layer 3 that is a chalcopyrite compound are used.
  • the intermediate layer 5a can enhance the effect of drawing a carrier by applying a strong electric field. As a result, carrier recombination can be reduced and conversion efficiency can be increased.
  • Examples of the intermediate layer 5a include a semiconductor mainly containing silicon (Si) doped with phosphorus (P) or the like. Note that “mainly containing Si” means containing 70 mol% or more of Si.
  • the intermediate layer 5a is formed by using a deposition method such as a vapor deposition method, a sputtering method, a sol-gel method, a screen printing method, a coating method, a plating method, a spray coating method, an inkjet coating method, a CVD method, a plasma CVD method, or a PVD method. can do.
  • the intermediate layer 3a may be formed into a desired pattern shape by combining a photolithography method, a lift-off method, a coating method using a dispenser, or a pattern forming method such as laser scribing.
  • a collector electrode 8 may be further formed on the second semiconductor layer 5.
  • the collecting electrode 8 is for taking out the carriers generated in the first semiconductor layer 3 more satisfactorily.
  • the collector electrode 8 is formed in a linear shape from one end of the photoelectric conversion cell 10 to the connection conductor 7.
  • the current generated in the first semiconductor layer 3 is collected by the current collecting electrode 8 through the first semiconductor layer 5, and the adjacent photoelectric conversion cell 10 is successfully energized through the connection conductor 7. .
  • the collecting electrode 8 may have a width of 50 to 400 ⁇ m from the viewpoint of increasing the light transmittance to the first semiconductor layer 3 and having good conductivity.
  • the current collecting electrode 8 may have a plurality of branched portions.
  • the current collecting electrode 8 is formed, for example, by printing a metal paste in which a metal powder such as Ag is dispersed in a resin binder or the like in a pattern and curing it.
  • connection conductor 7 is a conductor provided in a groove P2 that divides the first semiconductor layer 3, the intermediate layer 5a, and the second semiconductor layer 5.
  • the connection conductor 7 can be made of metal, conductive paste, or the like.
  • the collector electrode 8 is extended to form the connection conductor 7, but the present invention is not limited to this.
  • the second semiconductor layer 5 may be stretched.
  • FIG. 3 is a perspective view of the photoelectric conversion layer 21 of the second embodiment
  • FIG. 4 is a cross-sectional view thereof.
  • the same components as those of the photoelectric conversion device 11 of the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
  • Each photoelectric conversion cell 20 in the photoelectric conversion device 21 of the second embodiment further includes a buffer layer 4 at the interface between the first semiconductor layer 3 and the intermediate layer 5a.
  • the buffer layer 4 is a layer having a carrier density lower than that of the intermediate layer 5a.
  • the buffer layer 4 can satisfactorily fill defects on the surface of the first semiconductor layer 3, and further enhance the effect of extracting carriers by the intermediate layer 5a while further reducing carrier recombination. Can do. Further, when the intermediate layer 5 a is formed by a physical thin film forming method such as sputtering, damage to the first semiconductor layer 3 can be mitigated by the buffer layer 4, and the surface of the first semiconductor layer 3 can be reduced. It is possible to more effectively reduce the occurrence of defects.
  • the carrier density of the buffer layer 4 is about 1 ⁇ 10 10 to 1 ⁇ 10 16 cm ⁇ 3
  • the carrier density of the intermediate layer 5a May be about 1 ⁇ 10 20 to 1 ⁇ 10 22 cm ⁇ 3 .
  • the buffer layer 4 is a semiconductor layer or an insulating layer heterojunction with the first semiconductor layer 3 and has a thickness of 5 to 200 nm.
  • a metal sulfide such as CdS, ZnS, or In 2 S 3 is used.
  • the buffer layer 4 may be a mixed crystal containing at least one of a metal oxide and a metal hydroxide in addition to such a metal sulfide.
  • the buffer layer 4 is formed by, for example, a solution deposition method (CBD method), an ALD method, or an MOCVD method.
  • an n-type organic semiconductor may be used as the buffer layer 4.
  • an organic semiconductor include fullerene derivatives such as phenyl-C 61 -butyric acid methyl ester (PCBM) and fullerene C60.
  • PCBM phenyl-C 61 -butyric acid methyl ester
  • the buffer layer 4 can be formed by dissolving PCBM or the like in an organic solvent, applying this solution onto the first semiconductor layer 3, and then drying.
  • the buffer layer 4 may be formed by evaporating fullerene C60 or the like on the first semiconductor layer 3.
  • a protective layer is further provided on the buffer layer 4.
  • a buffer layer may be stacked.
  • the protective buffer layer include molybdenum oxide and tungsten oxide.
  • Such a protective buffer layer can be formed by sputtering or vapor deposition.
  • FIG. 5 is a perspective view of the photoelectric conversion layer 31 of the third embodiment
  • FIG. 6 is a cross-sectional view thereof.
  • the same components as those of the photoelectric conversion device 11 of the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
  • Each photoelectric conversion cell 30 in the photoelectric conversion device 31 of the third embodiment further includes a lower layer 6 at the interface between the electrode layer 2 and the first semiconductor layer 3. That is, the first semiconductor layer 3 is electrically connected to the electrode layer 2 via the lower layer 6.
  • the lower layer 6 is a p-type semiconductor having a crystal structure different from that of the first semiconductor layer 3, and has a carrier density higher than that of the first semiconductor layer 3.
  • the lower layer 6 has a thickness of about 30 to 2000 nm.
  • the carrier density of the first semiconductor layer 3 may be, for example, about 1 ⁇ 10 16 to 9 ⁇ 10 17 cm ⁇ 3 or less so as not to reveal recombination due to defects.
  • the lower layer 6 has a carrier density higher than that of the first semiconductor layer 3, for example, 1 ⁇ 10 18 to 9 ⁇ 10 18 cm ⁇ 3. It can be easily pulled out.
  • a p-type semiconductor having a crystal structure different from that of the first semiconductor layer 3 may be used from the viewpoint of easy control of the dopant.
  • Examples of the lower layer 6 include a semiconductor mainly containing silicon (Si) doped with other elements such as boron (B). Note that “mainly containing Si” means containing 70 mol% or more of Si. Further, as the other lower layer 6, a compound semiconductor such as zinc selenide having a carrier density of 1 ⁇ 10 18 to 9 ⁇ 10 18 cm ⁇ 3 and easily bonded to the first semiconductor layer 3 may be used. Good.
  • the first semiconductor layer 3 is a perovskite compound
  • a hole transport layer or the like can be used as the lower layer 6.
  • the hole transport layer include an organic hole transport layer obtained by adding a dopant such as Li-TFSI or F4-TCNQ to poly-3-hexylthiophene, or an inorganic hole transport layer such as nickel oxide.
  • the lower layer 6 is produced using a deposition method such as a vapor deposition method, a sputtering method, a sol-gel method, a screen printing method, a coating method, a plating method, a spray coating method, an inkjet coating method, a CVD method, a plasma CVD method, or a PVD method. can do. If necessary, the lower layer 6 may be formed into a desired pattern shape by combining a photolithography method, a lift-off method, a coating method using a dispenser, or a pattern forming method such as laser scribing.
  • a deposition method such as a vapor deposition method, a sputtering method, a sol-gel method, a screen printing method, a coating method, a plating method, a spray coating method, an inkjet coating method, a CVD method, a plasma CVD method, or a PVD method. can do.
  • the lower layer 6 may be formed into a desired pattern shape by combining
  • electrode layer 3 first semiconductor layer 4: buffer layer 5: second semiconductor layer 5a: intermediate layer 6: lower layer 11, 21, 31: photoelectric conversion device

Abstract

A photoelectric conversion device according to one embodiment of the present invention comprises an electrode layer, a first semiconductor layer, a second semiconductor layer, and an intermediate layer. The first semiconductor layer is disposed on the electrode layer. The first semiconductor layer is a p-type or i-type semiconductor layer comprising primarily a chalcopyrite compound or a perovskite compound. The second semiconductor layer is an n-type semiconductor layer and is disposed on the first semiconductor layer. The intermediate layer is positioned at the interface of the first semiconductor layer and second semiconductor layer and is an n-type semiconductor layer comprising primarily silicon.

Description

光電変換装置Photoelectric conversion device
　本発明は、化合物半導体層を具備する光電変換装置に関する。 The present invention relates to a photoelectric conversion device including a compound semiconductor layer.
　太陽光発電等に使用される光電変換装置として、カルコパイライト系化合物から成る半導体層を光吸収層として用いたものがある（特開２００３－２８２９０９号公報参照）。このような光電変換装置は、複数の光電変換セルが平面的に並設された構成を有する。各光電変換セルは、ガラス等の基板の上に、金属電極等の下部電極と、ＣＩＧＳなどの金属カルコゲナイドを含む光吸収層と、この光吸収層にヘテロ接合した、硫化インジウムを含むバッファ層と、透明電極や金属電極等の上部電極とが、この順に積層されて構成されている。また、複数の光電変換セルは、隣り合う一方の光電変換セルの上部電極と他方の光電変換セルの下部電極とが接続導体によって電気的に接続されることで、電気的に直列に接続されている。 As a photoelectric conversion device used for solar power generation or the like, there is one using a semiconductor layer made of a chalcopyrite compound as a light absorption layer (see Japanese Patent Application Laid-Open No. 2003-282909). Such a photoelectric conversion device has a configuration in which a plurality of photoelectric conversion cells are arranged side by side in a plane. Each photoelectric conversion cell includes a lower electrode such as a metal electrode on a substrate such as glass, a light absorption layer including a metal chalcogenide such as CIGS, and a buffer layer including indium sulfide heterojunction to the light absorption layer. The upper electrode such as a transparent electrode or a metal electrode is laminated in this order. In addition, the plurality of photoelectric conversion cells are electrically connected in series by electrically connecting the upper electrode of one adjacent photoelectric conversion cell and the lower electrode of the other photoelectric conversion cell by a connecting conductor. Yes.
　本発明の一態様に係る光電変換装置は、電極層と、第１の半導体層と、第２の半導体層と、中間層とを具備する。第１の半導体層は、電極層上に位置している。第１の半導体層は、ｐ型またはｉ型であり、カルコパイライト系化合物またはペロブスカイト系化合物を主として含んでいる。第２の半導体層は、ｎ型であり、第１の半導体層上に位置している。中間層は、第１の半導体層および第２の半導体層の界面に位置しており、シリコンを主として含むｎ型の半導体層である。 The photoelectric conversion device according to one embodiment of the present invention includes an electrode layer, a first semiconductor layer, a second semiconductor layer, and an intermediate layer. The first semiconductor layer is located on the electrode layer. The first semiconductor layer is p-type or i-type and mainly contains a chalcopyrite compound or a perovskite compound. The second semiconductor layer is n-type and is located on the first semiconductor layer. The intermediate layer is located at the interface between the first semiconductor layer and the second semiconductor layer, and is an n-type semiconductor layer mainly containing silicon.
第１実施形態の光電変換装置を示す斜視図である。It is a perspective view which shows the photoelectric conversion apparatus of 1st Embodiment. 図１の光電変換装置の断面図である。It is sectional drawing of the photoelectric conversion apparatus of FIG. 第２実施形態の光電変換装置を示す斜視図である。It is a perspective view which shows the photoelectric conversion apparatus of 2nd Embodiment. 図３の光電変換装置の断面図である。It is sectional drawing of the photoelectric conversion apparatus of FIG. 第３実施形態の光電変換装置を示す斜視図である。It is a perspective view which shows the photoelectric conversion apparatus of 3rd Embodiment. 図５の光電変換装置の断面図である。It is sectional drawing of the photoelectric conversion apparatus of FIG.
　以下に本開示の光電変換装置の実施形態について、図面を参照しながら詳細に説明する。 Hereinafter, embodiments of the photoelectric conversion device of the present disclosure will be described in detail with reference to the drawings.
　＜第１実施形態の光電変換装置＞
　図１は、第１実施形態に係る光電変換装置を示す斜視図であり、図２はその断面図である。光電変換装置１１は、基板１上に複数の光電変換セル１０を具備している。これらの光電変換セル１０は、互いに間隔Ｐ３をあけて並んでおり、隣接する光電変換セル１０同士が互いに電気的に接続されている。なお、図１においては図示の都合上、２つの光電変換セル１０のみを示しているが、実際の光電変換装置１１においては、図面左右方向、あるいはさらにこれに垂直な方向に、多数の光電変換セル１０が平面的に（二次元的に）配設されていてもよい。 <Photoelectric Conversion Device of First Embodiment>
FIG. 1 is a perspective view showing the photoelectric conversion device according to the first embodiment, and FIG. 2 is a sectional view thereof. The photoelectric conversion device 11 includes a plurality of photoelectric conversion cells 10 on a substrate 1. These photoelectric conversion cells 10 are arranged with a space P3 therebetween, and the adjacent photoelectric conversion cells 10 are electrically connected to each other. In FIG. 1, only two photoelectric conversion cells 10 are shown for convenience of illustration. However, in an actual photoelectric conversion device 11, a large number of photoelectric conversion cells are arranged in the horizontal direction of the drawing or in a direction perpendicular thereto. The cells 10 may be arranged in a plane (two-dimensionally).
　図１、図２において、基板１上に複数の電極層２が平面配置されている。なお、以下の説明においては、図の＋Ｚ方向を上側として説明するが、光電変換装置１１の使用においては、必ずしも＋Ｚ方向が上側である必要はなく、下側であってもよい。 1 and 2, a plurality of electrode layers 2 are arranged in a plane on a substrate 1. In the following description, the + Z direction in the figure is described as the upper side. However, in the use of the photoelectric conversion device 11, the + Z direction is not necessarily the upper side and may be the lower side.
　図１、図２において、複数の電極層２は、一方向に間隔Ｐ１をあけて並べられた電極層２ａ～２ｃを具備している。この電極層２ａ上から基板１上を経て電極層２ｂ上にかけて、第１の半導体層３、中間層５ａおよび第２の半導体層５が順に積層されている。さらに、電極層２ｂ上において、接続導体７が、第１の半導体層３および中間層５ａの側面に沿って、またはこれらを貫通して設けられている。この接続導体７は、第２の半導体層５と電極層２ｂとを電気的に接続している。これら電極層２、第１の半導体層３、中間層５ａおよび第２の半導体層５によって、１つの光電変換セル１０が構成され、隣接する光電変換セル１０同士が接続導体７を介して直列接続されることによって、高出力の光電変換装置１１となる。なお、本実施形態における光電変換装置１１は、第２の半導体層５側から第１の半導体層３へ光が入射されるものを想定しているが、これに限定されず、電極層２側から第１の半導体層３へ光が入射されるものであってもよい。 1 and 2, the plurality of electrode layers 2 include electrode layers 2a to 2c arranged with a spacing P1 in one direction. A first semiconductor layer 3, an intermediate layer 5a, and a second semiconductor layer 5 are sequentially stacked from the electrode layer 2a through the substrate 1 to the electrode layer 2b. Further, on the electrode layer 2b, the connection conductor 7 is provided along or through the side surfaces of the first semiconductor layer 3 and the intermediate layer 5a. The connection conductor 7 electrically connects the second semiconductor layer 5 and the electrode layer 2b. The electrode layer 2, the first semiconductor layer 3, the intermediate layer 5 a, and the second semiconductor layer 5 constitute one photoelectric conversion cell 10, and adjacent photoelectric conversion cells 10 are connected in series via the connection conductor 7. As a result, a high-output photoelectric conversion device 11 is obtained. In addition, although the photoelectric conversion apparatus 11 in this embodiment assumes what light injects into the 1st semiconductor layer 3 from the 2nd semiconductor layer 5 side, it is not limited to this, The electrode layer 2 side The light may be incident on the first semiconductor layer 3.
　基板１は、光電変換セル１０を支持するためのものである。基板１に用いられる材料としては、例えば、ガラス、セラミックス、樹脂および金属等が挙げられる。基板１としては、例えば、厚さ１～３ｍｍ程度の青板ガラス（ソーダライムガラス）を用いることができる。 The substrate 1 is for supporting the photoelectric conversion cell 10. Examples of the material used for the substrate 1 include glass, ceramics, resin, and metal. As the substrate 1, for example, blue plate glass (soda lime glass) having a thickness of about 1 to 3 mm can be used.
　電極層２（電極層２ａ、２ｂ、２ｃ）は、基板１上に設けられた、Ｍｏ、Ａｌ、ＴｉまたはＡｕ等の導電体である。電極層２は、スパッタリング法または蒸着法などの公知の薄膜形成手法を用いて、０．２μｍ～１μｍ程度の厚みに形成される。 The electrode layer 2 ( electrode layers 2a, 2b, 2c) is a conductor such as Mo, Al, Ti, or Au provided on the substrate 1. The electrode layer 2 is formed to a thickness of about 0.2 μm to 1 μm using a known thin film forming method such as sputtering or vapor deposition.
　第１の半導体層３は、光を吸収してキャリア（電子および正孔）を発生させる機能をする半導体層であり、いわゆる光吸収層である。第１の半導体層３は、例えば１μｍ～３μｍ程度の厚みのｐ型またはｉ型の半導体層である。また、第１の半導体層３は、カルコパイライト系化合物を主として含んでいるか、あるいはペロブスカイト系化合物を主として含んでいる。カルコパイライト系化合物を主として含むとは、カルコパイライト系化合物を７０ｍｏｌ％以上含むことをいう。また、ペロブスカイト系化合物を主として含むとは、ペロブスカイト系化合物を７０ｍｏｌ％以上含むことをいう。 The first semiconductor layer 3 is a semiconductor layer that functions to absorb light and generate carriers (electrons and holes), and is a so-called light absorption layer. The first semiconductor layer 3 is a p-type or i-type semiconductor layer having a thickness of about 1 μm to 3 μm, for example. Further, the first semiconductor layer 3 mainly contains a chalcopyrite compound or mainly contains a perovskite compound. “Containing mainly chalcopyrite compounds” means containing at least 70 mol% of chalcopyrite compounds. The phrase “mainly containing a perovskite compound” means containing 70 mol% or more of a perovskite compound.
　カルコパイライト系化合物とは、カルコパイライト構造を有する化合物であり、例えば、Ｉ－III－VI族化合物が挙げられる。Ｉ－III－VI族化合物とは、１１族元素（Ｉ－Ｂ族元素ともいう）と１３族元素（III－Ｂ族元素ともいう）と１６族元素との化合物である。Ｉ－III－VI族化合物としては、例えば、ＣｕＩｎＳｅ２（二セレン化銅インジウム、ＣＩＳともいう）、Ｃｕ（Ｉｎ，Ｇａ）Ｓｅ２（二セレン化銅インジウム・ガリウム、ＣＩＧＳともいう）、Ｃｕ（Ｉｎ，Ｇａ）（Ｓｅ，Ｓ）２（二セレン・イオウ化銅インジウム・ガリウム、ＣＩＧＳＳともいう）が挙げられる。あるいは、第１の半導体層３は、薄膜の二セレン・イオウ化銅インジウム・ガリウム層を表面層として有する二セレン化銅インジウム・ガリウム等の多元化合物半導体薄膜にて構成されていてもよい。 The chalcopyrite compound is a compound having a chalcopyrite structure, and examples thereof include I-III-VI group compounds. The group I-III-VI compound is a compound of a group 11 element (also referred to as a group IB element), a group 13 element (also referred to as a group III-B element), and a group 16 element. Examples of the I-III-VI group compounds include CuInSe 2 (also referred to as copper indium diselenide, CIS), Cu (In, Ga) Se 2 (also referred to as copper indium diselenide / gallium, CIGS), Cu ( In, Ga) (Se, S) 2 (also referred to as diselene / copper indium / gallium / CIGSS). Alternatively, the first semiconductor layer 3 may be composed of a multi-component compound semiconductor thin film such as copper indium selenide / gallium having a thin film of selenite / copper indium sulfide / gallium layer as a surface layer.
　ペロブスカイト系化合物とは、ペロブスカイト構造を有する化合物であり、例えばＣＨ３ＮＨ３ＰｂＸ３（Ｘはハロゲン元素である）等の有機無機複合材料が挙げられる。なお、有機無機複合材料とは、分子レベルで有機成分と無機成分とが複合された材料である。また、ＡＰｂＸ３（ＡはＣｓなどのアルカリ金属元素、Ｘはハロゲン元素である）のような有機物を含まない構造も、ペロブスカイト系化合物には含まれる。本開示に含まれる材料としては、Ｐｂを含み、ハロゲン元素でＸが構成されているペロブスカイト系化合物が好適に用いられる。さらには、Ｘで表したハロゲン元素は、２種類以上の元素が含まれても良く、ＣＨ３ＮＨ３などの有機物や、Ｃｓなどのアルカリ金属も、２種類以上の元素が含まれても良い。このように材料を多く混ぜることで、所望のバンドギャップや、耐熱性、耐電圧性が得られるようになり、タンデム化に適したペロブスカイト系太陽電池や、プロセスの自由度が高い、かつ長期信頼性に優れた太陽電池を得ることができるようになる。 The perovskite compound is a compound having a perovskite structure, and examples thereof include organic-inorganic composite materials such as CH 3 NH 3 PbX 3 (X is a halogen element). The organic-inorganic composite material is a material in which an organic component and an inorganic component are combined at the molecular level. In addition, a structure containing no organic substance such as APbX 3 (A is an alkali metal element such as Cs and X is a halogen element) is also included in the perovskite compound. As a material included in the present disclosure, a perovskite compound containing Pb and having X composed of a halogen element is preferably used. Furthermore, the halogen element represented by X may include two or more elements, and an organic substance such as CH 3 NH 3 and an alkali metal such as Cs may also include two or more elements. . By mixing a lot of materials like this, the desired band gap, heat resistance, and voltage resistance can be obtained, and perovskite solar cells suitable for tandemization, high degree of process freedom, and long-term reliability A solar cell with excellent properties can be obtained.
　第１の半導体層３は、スパッタリング法または蒸着法などのいわゆる真空プロセスによって形成可能であるほか、いわゆる塗布法あるいは印刷法と称されるプロセスによって形成することもできる。塗布法あるいは印刷法と称されるプロセスは、第１の半導体層３の構成元素の錯体溶液を中間層３ａまたは電極層２の上に塗布し、その後、乾燥・熱処理を行うプロセスである。 The first semiconductor layer 3 can be formed by a so-called vacuum process such as a sputtering method or an evaporation method, or can be formed by a process called a coating method or a printing method. A process referred to as a coating method or a printing method is a process in which a complex solution of constituent elements of the first semiconductor layer 3 is applied on the intermediate layer 3a or the electrode layer 2, and then drying and heat treatment are performed.
　第２の半導体層５は、例えば０．０５～３．０μｍ程度の厚みのｎ型の半導体層である。第２の半導体層５は、第１の半導体層３で生じたキャリアを良好に取り出すためのものであり、例えば、第２の半導体層５の電気抵抗率は１Ω・ｃｍ以下であり、シート抵抗は５０Ω／□以下であってもよい。 The second semiconductor layer 5 is an n-type semiconductor layer having a thickness of about 0.05 to 3.0 μm, for example. The second semiconductor layer 5 is for extracting the carriers generated in the first semiconductor layer 3 satisfactorily. For example, the electrical resistivity of the second semiconductor layer 5 is 1 Ω · cm or less, and the sheet resistance May be 50Ω / □ or less.
　第２の半導体層５は、例えば、ＺｎＯやＩｎ２Ｏ３、ＳｎＯ２等の金属酸化物を含み、電気抵抗率を低くするために、Ａｌ、Ｂ、Ｇａ、Ｉｎ、ＳｎおよびＦ等のうちの何れかの元素が含まれても良い。このような元素が含まれた金属酸化物半導体の具体例としては、例えば、ＡＺＯ（Aluminum Zinc Oxide）、ＢＺＯ（Boron Zinc Oxide）、ＧＺＯ（Gallium Zinc Oxide）、ＩＺＯ（Indium Zinc Oxide）、ＩＴＯ（Indium Tin Oxide）、ＦＴＯ（Fluorine tin Oxide）等がある。第１の半導体層５は、スパッタリング法、蒸着法またはＣＶＤ法等で形成される。 The second semiconductor layer 5 includes, for example, a metal oxide such as ZnO, In 2 O 3 , or SnO 2 , and includes Al, B, Ga, In, Sn, F, and the like in order to reduce the electrical resistivity. Any of these elements may be included. Specific examples of the metal oxide semiconductor containing such an element include, for example, AZO (Aluminum Zinc Oxide), BZO (Boron Zinc Oxide), GZO (Gallium Zinc Oxide), IZO (Indium Zinc Oxide), ITO ( Indium Tin Oxide) and FTO (Fluorine tin Oxide). The first semiconductor layer 5 is formed by a sputtering method, a vapor deposition method, a CVD method, or the like.
　また、第２の半導体層５は１層だけでもよく、２層以上の積層体であってもよい。第２の半導体層が２層以上の複数層から成る場合、その複数層のうちの少なくとも１層がｎ型であればよい。つまり、第２の半導体層は、ｎ型の半導体層とｉ型の半導体層の積層体であってもよく、ｎ型の半導体層の積層体であってもよい。また、第２の半導体層５は、電気抵抗率の異なる半導体層の積層体であってもよく、その場合、電気抵抗率の高い半導体層によってリーク電流が生じるのを有効に低減することができる。 Further, the second semiconductor layer 5 may be a single layer or a laminate of two or more layers. When the second semiconductor layer is composed of two or more layers, at least one of the plurality of layers may be n-type. That is, the second semiconductor layer may be a stacked body of an n-type semiconductor layer and an i-type semiconductor layer, or may be a stacked body of an n-type semiconductor layer. Further, the second semiconductor layer 5 may be a stacked body of semiconductor layers having different electric resistivity, and in that case, it is possible to effectively reduce the occurrence of leakage current due to the semiconductor layer having a high electric resistivity. .
　中間層５ａは、第１の半導体層３と第２の半導体層５との界面に位置している。つまり、第１の半導体層３は中間層５ａを介して第２の半導体層５と電気的に接続されている。中間層５ａはシリコンを主として含むｎ型の半導体層であり、３０～２０００ｎｍ程度の厚みを有する。 The intermediate layer 5 a is located at the interface between the first semiconductor layer 3 and the second semiconductor layer 5. That is, the first semiconductor layer 3 is electrically connected to the second semiconductor layer 5 via the intermediate layer 5a. The intermediate layer 5a is an n-type semiconductor layer mainly containing silicon and has a thickness of about 30 to 2000 nm.
　このような構成によって、第１の半導体層３の光電変換によって生じたキャリアの再結合を低減し、光電変換装置１１の光電変換効率を向上させることができる。つまり、中間層５ａがシリコンを主として含むｎ型の半導体層であることによって、ドーパント濃度を良好に制御することが可能となり、カルコパイライト系化合物である第１の半導体層３で電荷分離したキャリアに対し、中間層５ａによって強い電界をかけてキャリアを引き抜く効果を強めることができる。その結果、キャリアの再結合を低減して変換効率を高めることができる。 With such a configuration, recombination of carriers generated by photoelectric conversion of the first semiconductor layer 3 can be reduced, and the photoelectric conversion efficiency of the photoelectric conversion device 11 can be improved. That is, since the intermediate layer 5a is an n-type semiconductor layer mainly containing silicon, the dopant concentration can be well controlled, and the carriers separated by charge in the first semiconductor layer 3 that is a chalcopyrite compound are used. On the other hand, the intermediate layer 5a can enhance the effect of drawing a carrier by applying a strong electric field. As a result, carrier recombination can be reduced and conversion efficiency can be increased.
　このような中間層５ａとしては、リン（Ｐ）等をドーピングしたシリコン（Ｓｉ）を主として含む半導体等が挙げられる。なお、Ｓｉを主として含むとは、Ｓｉを７０ｍｏｌ％以上含むことをいう。 Examples of the intermediate layer 5a include a semiconductor mainly containing silicon (Si) doped with phosphorus (P) or the like. Note that “mainly containing Si” means containing 70 mol% or more of Si.
　中間層５ａは、蒸着法、スパッタリング法、ゾルゲル法、スクリーン印刷法、塗布法、めっき法、スプレー塗布法、インクジェット塗布法、ＣＶＤ法、プラズマＣＶＤ法またはＰＶＤ法等の成膜方法を用いて作製することができる。また、必要に応じて、フォトリソグラフィー法、リフトオフ法、ディスペンサーを用いた塗布法またはレーザスクライブ等のパターン形成法を組み合わせることによって、中間層３ａを所望のパターン形状にしてもよい。 The intermediate layer 5a is formed by using a deposition method such as a vapor deposition method, a sputtering method, a sol-gel method, a screen printing method, a coating method, a plating method, a spray coating method, an inkjet coating method, a CVD method, a plasma CVD method, or a PVD method. can do. If necessary, the intermediate layer 3a may be formed into a desired pattern shape by combining a photolithography method, a lift-off method, a coating method using a dispenser, or a pattern forming method such as laser scribing.
　また、図１、図２に示すように、第２の半導体層５上にさらに集電電極８が形成されていてもよい。集電電極８は、第１の半導体層３で生じたキャリアをさらに良好に取り出すためのものである。集電電極８は、例えば、図１に示すように、光電変換セル１０の一端から接続導体７にかけて線状に形成されている。これにより、第１の半導体層３で生じた電流が第１の半導体層５を介して集電電極８に集電され、接続導体７を介して隣接する光電変換セル１０に良好に通電される。 Further, as shown in FIGS. 1 and 2, a collector electrode 8 may be further formed on the second semiconductor layer 5. The collecting electrode 8 is for taking out the carriers generated in the first semiconductor layer 3 more satisfactorily. For example, as shown in FIG. 1, the collector electrode 8 is formed in a linear shape from one end of the photoelectric conversion cell 10 to the connection conductor 7. As a result, the current generated in the first semiconductor layer 3 is collected by the current collecting electrode 8 through the first semiconductor layer 5, and the adjacent photoelectric conversion cell 10 is successfully energized through the connection conductor 7. .
　集電電極８は、第１の半導体層３への光透過率を高めるとともに良好な導電性を有するという観点から、５０～４００μｍの幅を有していてもよい。また、集電電極８は、枝分かれした複数の分岐部を有していてもよい。 The collecting electrode 8 may have a width of 50 to 400 μm from the viewpoint of increasing the light transmittance to the first semiconductor layer 3 and having good conductivity. The current collecting electrode 8 may have a plurality of branched portions.
　集電電極８は、例えば、Ａｇ等の金属粉を樹脂バインダー等に分散させた金属ペーストがパターン状に印刷され、これが硬化されることによって形成される。 The current collecting electrode 8 is formed, for example, by printing a metal paste in which a metal powder such as Ag is dispersed in a resin binder or the like in a pattern and curing it.
　図１、図２において、接続導体７は、第１の半導体層３、中間層５ａおよび第２の半導体層５を分断する溝Ｐ２内に設けられた導体である。接続導体７は、金属や導電ペースト等が用いられ得る。図１、図２においては、集電電極８を延伸して接続導体７が形成されているが、これに限定されない。例えば、第２の半導体層５が延伸したものであってもよい。 1 and 2, the connection conductor 7 is a conductor provided in a groove P2 that divides the first semiconductor layer 3, the intermediate layer 5a, and the second semiconductor layer 5. The connection conductor 7 can be made of metal, conductive paste, or the like. In FIG. 1 and FIG. 2, the collector electrode 8 is extended to form the connection conductor 7, but the present invention is not limited to this. For example, the second semiconductor layer 5 may be stretched.
　なお、本発明は上述の実施の形態に限定されるものではなく、本発明の要旨を逸脱しない範囲において種々の変更、改良などが可能である。以下に種々の変形例を示す。 It should be noted that the present invention is not limited to the above-described embodiment, and various changes and improvements can be made without departing from the gist of the present invention. Various modifications are shown below.
　＜第２実施形態の光電変換装置＞
　図３は、第２実施形態の光電変換層２１の斜視図であり、図４はその断面図である。第２実施形態の光電変換装置２１において、第１実施形態の光電変換装置１１と同じ構成のものには同じ符号を付しており、詳細な説明は省略する。 <Photoelectric Conversion Device of Second Embodiment>
FIG. 3 is a perspective view of the photoelectric conversion layer 21 of the second embodiment, and FIG. 4 is a cross-sectional view thereof. In the photoelectric conversion device 21 of the second embodiment, the same components as those of the photoelectric conversion device 11 of the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
　第２実施形態の光電変換装置２１における各光電変換セル２０は、第１の半導体層３と中間層５ａとの界面にバッファ層４をさらに具備している。このバッファ層４は、中間層５ａよりもキャリア密度が低い層である。 Each photoelectric conversion cell 20 in the photoelectric conversion device 21 of the second embodiment further includes a buffer layer 4 at the interface between the first semiconductor layer 3 and the intermediate layer 5a. The buffer layer 4 is a layer having a carrier density lower than that of the intermediate layer 5a.
　このような構成によって、バッファ層４が第１の半導体層３の表面の欠陥を良好に埋めることができ、キャリアの再結合をより低減しながら、中間層５ａによってキャリアを引き抜く効果をさらに強めることができる。また、中間層５ａをスパッタリング法等の物理的薄膜形成方法で形成する際に、第１の半導体層３へのダメージをバッファ層４で緩和することができ、第１の半導体層３の表面に欠陥が生じるのをより有効に低減できる。 With such a configuration, the buffer layer 4 can satisfactorily fill defects on the surface of the first semiconductor layer 3, and further enhance the effect of extracting carriers by the intermediate layer 5a while further reducing carrier recombination. Can do. Further, when the intermediate layer 5 a is formed by a physical thin film forming method such as sputtering, damage to the first semiconductor layer 3 can be mitigated by the buffer layer 4, and the surface of the first semiconductor layer 3 can be reduced. It is possible to more effectively reduce the occurrence of defects.
　第１の半導体層３からのキャリアの引き抜きをより良好にするという観点からは、バッファ層４のキャリア密度は１×１０１０～１×１０１６ｃｍ－３程度であり、中間層５ａのキャリア密度は１×１０２０～１×１０２２ｃｍ－３程度であってもよい。 From the standpoint of improving carrier extraction from the first semiconductor layer 3, the carrier density of the buffer layer 4 is about 1 × 10 10 to 1 × 10 16 cm −3 , and the carrier density of the intermediate layer 5a May be about 1 × 10 20 to 1 × 10 22 cm −3 .
　バッファ層４は、第１の半導体層３にヘテロ接合された半導体層または絶縁層であり、５～２００ｎｍの厚みを有している。バッファ層４としては、例えば、ＣｄＳ、ＺｎＳまたはＩｎ２Ｓ３等の金属硫化物が用いられる。なお、バッファ層４は、このような金属硫化物に加えて、金属酸化物および金属水酸化物の少なくとも一方を含む混晶であってもよい。バッファ層４は、例えば溶液析出法（ＣＢＤ法）、ＡＬＤ法またはＭＯＣＶＤ法などで形成される。 The buffer layer 4 is a semiconductor layer or an insulating layer heterojunction with the first semiconductor layer 3 and has a thickness of 5 to 200 nm. As the buffer layer 4, for example, a metal sulfide such as CdS, ZnS, or In 2 S 3 is used. The buffer layer 4 may be a mixed crystal containing at least one of a metal oxide and a metal hydroxide in addition to such a metal sulfide. The buffer layer 4 is formed by, for example, a solution deposition method (CBD method), an ALD method, or an MOCVD method.
　また、第１の半導体層３がペロブスカイト系化合物を主として含む場合には、バッファ層４として、ｎ型の有機半導体を用いてもよい。このような有機半導体としては、フェニル－Ｃ６１－酪酸メチルエステル（ＰＣＢＭ）およびフラーレンＣ６０等のフラーレン誘導体等が挙げられる。バッファ層４として有機半導体を用いる場合、例えば、ＰＣＢＭ等を有機溶剤に溶解させ、この溶液を第１の半導体層３上に塗布した後、乾燥することによってバッファ層４を形成できる。もしくは、フラーレンＣ６０等を第１の半導体層３上に蒸着することによってバッファ層４を形成してもよい。また、第１の半導体層３またはバッファ層４に対して、中間層５ａまたは第２の半導体層５を形成する際のプロセスの影響を受けにくくするため、バッファ層４の上に、さらに保護用バッファ層を積層しても良い。この保護用バッファ層としては、酸化モリブデンおよび酸化タングステンなどが挙げられる。このような保護用バッファ層はスパッタリング法や蒸着法等で形成することができる。 In the case where the first semiconductor layer 3 mainly contains a perovskite compound, an n-type organic semiconductor may be used as the buffer layer 4. Examples of such an organic semiconductor include fullerene derivatives such as phenyl-C 61 -butyric acid methyl ester (PCBM) and fullerene C60. When an organic semiconductor is used as the buffer layer 4, for example, the buffer layer 4 can be formed by dissolving PCBM or the like in an organic solvent, applying this solution onto the first semiconductor layer 3, and then drying. Alternatively, the buffer layer 4 may be formed by evaporating fullerene C60 or the like on the first semiconductor layer 3. Further, in order to make the first semiconductor layer 3 or the buffer layer 4 less susceptible to the process of forming the intermediate layer 5a or the second semiconductor layer 5, a protective layer is further provided on the buffer layer 4. A buffer layer may be stacked. Examples of the protective buffer layer include molybdenum oxide and tungsten oxide. Such a protective buffer layer can be formed by sputtering or vapor deposition.
　＜第３実施形態の光電変換装置＞
　図５は、第３実施形態の光電変換層３１の斜視図であり、図６はその断面図である。第３実施形態の光電変換装置３１において、第１実施形態の光電変換装置１１と同じ構成のものには同じ符号を付しており、詳細な説明は省略する。 <Photoelectric Conversion Device of Third Embodiment>
FIG. 5 is a perspective view of the photoelectric conversion layer 31 of the third embodiment, and FIG. 6 is a cross-sectional view thereof. In the photoelectric conversion device 31 of the third embodiment, the same components as those of the photoelectric conversion device 11 of the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
　第３実施形態の光電変換装置３１における各光電変換セル３０は、電極層２と第１の半導体層３との界面に下部層６をさらに具備している。つまり、第１の半導体層３は下部層６を介して電極層２と電気的に接続されている。この下部層６は、第１の半導体層３とは異なる結晶構造を有するｐ型の半導体であり、第１の半導体層３よりもキャリア密度が高い。また、下部層６は３０～２０００ｎｍ程度の厚みを有する。 Each photoelectric conversion cell 30 in the photoelectric conversion device 31 of the third embodiment further includes a lower layer 6 at the interface between the electrode layer 2 and the first semiconductor layer 3. That is, the first semiconductor layer 3 is electrically connected to the electrode layer 2 via the lower layer 6. The lower layer 6 is a p-type semiconductor having a crystal structure different from that of the first semiconductor layer 3, and has a carrier density higher than that of the first semiconductor layer 3. The lower layer 6 has a thickness of about 30 to 2000 nm.
　このような構成によって、第１の半導体層３の光電変換によって生じたキャリアの再結合を低減し、光電変換装置１１の光電変換効率をさらに向上させることができる。つまり、第１の半導体層３で電荷分離したキャリアに対し、下部層６によって中間層５ａとは反対側からも強い電界をかけてキャリアを引き抜く効果を強めることができる。その結果、キャリアの再結合を低減して変換効率を高めることができる。 With such a configuration, recombination of carriers generated by photoelectric conversion of the first semiconductor layer 3 can be reduced, and the photoelectric conversion efficiency of the photoelectric conversion device 11 can be further improved. That is, it is possible to enhance the effect of extracting carriers by applying a strong electric field from the side opposite to the intermediate layer 5a to the carrier separated from the charge in the first semiconductor layer 3 by the lower layer 6. As a result, carrier recombination can be reduced and conversion efficiency can be increased.
　ここで、カルコパイライト系化合物およびペロブスカイト系化合物はドーパントの制御が難しく、欠陥の少ない状態でキャリア密度を所望の濃度に制御するのが難しい。そのため、第１の半導体層３のキャリア密度は、欠陥による再結合を顕在化させないように例えば１×１０１６～９×１０１７ｃｍ－３程度以下としてもよい。そして、下部層６は、第１の半導体層３よりもキャリア密度が例えば１×１０１８～９×１０１８ｃｍ－３と高くなっているので、電荷分離したキャリアを第１の半導体層３から引き抜き易くすることができる。このような中間層３ａとしては、ドーパントの制御が容易であるという観点からは、第１の半導体層３とは異なる結晶構造を有するｐ型の半導体が用いられてもよい。 Here, chalcopyrite compounds and perovskite compounds are difficult to control the dopant, and it is difficult to control the carrier density to a desired concentration with few defects. Therefore, the carrier density of the first semiconductor layer 3 may be, for example, about 1 × 10 16 to 9 × 10 17 cm −3 or less so as not to reveal recombination due to defects. The lower layer 6 has a carrier density higher than that of the first semiconductor layer 3, for example, 1 × 10 18 to 9 × 10 18 cm −3. It can be easily pulled out. As such an intermediate layer 3a, a p-type semiconductor having a crystal structure different from that of the first semiconductor layer 3 may be used from the viewpoint of easy control of the dopant.
　このような下部層６としては、ホウ素（Ｂ）等の他の元素をドーピングしたシリコン（Ｓｉ）を主として含む半導体等が挙げられる。なお、Ｓｉを主として含むとは、Ｓｉを７０ｍｏｌ％以上含むことをいう。また、他の下部層６としては、キャリア密度が１×１０１８～９×１０１８ｃｍ－３である、第１の半導体層３と接合し易いセレン化亜鉛等の化合物半導体などを用いてもよい。 Examples of the lower layer 6 include a semiconductor mainly containing silicon (Si) doped with other elements such as boron (B). Note that “mainly containing Si” means containing 70 mol% or more of Si. Further, as the other lower layer 6, a compound semiconductor such as zinc selenide having a carrier density of 1 × 10 18 to 9 × 10 18 cm −3 and easily bonded to the first semiconductor layer 3 may be used. Good.
　なお、第１の半導体層３がペロブスカイト系化合物である場合、下部層６として、ホール輸送層などを用いることもできる。ホール輸送層としては、ポリ－３－ヘキシルチオフェンにＬｉ－ＴＦＳＩ、Ｆ４－ＴＣＮＱなどのドーパントを添加した有機系ホール輸送層、あるいは、酸化ニッケル等の無機系ホール輸送層が挙げられる。 When the first semiconductor layer 3 is a perovskite compound, a hole transport layer or the like can be used as the lower layer 6. Examples of the hole transport layer include an organic hole transport layer obtained by adding a dopant such as Li-TFSI or F4-TCNQ to poly-3-hexylthiophene, or an inorganic hole transport layer such as nickel oxide.
　下部層６は、蒸着法、スパッタリング法、ゾルゲル法、スクリーン印刷法、塗布法、めっき法、スプレー塗布法、インクジェット塗布法、ＣＶＤ法、プラズマＣＶＤ法またはＰＶＤ法等の成膜方法を用いて作製することができる。また、必要に応じて、フォトリソグラフィー法、リフトオフ法、ディスペンサーを用いた塗布法またはレーザスクライブ等のパターン形成法を組み合わせることによって、下部層６を所望のパターン形状にしてもよい。 The lower layer 6 is produced using a deposition method such as a vapor deposition method, a sputtering method, a sol-gel method, a screen printing method, a coating method, a plating method, a spray coating method, an inkjet coating method, a CVD method, a plasma CVD method, or a PVD method. can do. If necessary, the lower layer 6 may be formed into a desired pattern shape by combining a photolithography method, a lift-off method, a coating method using a dispenser, or a pattern forming method such as laser scribing.
　２、２ａ、２ｂ、２ｃ：電極層
　３：第１の半導体層
　４：バッファ層
　５：第２の半導体層
　５ａ：中間層
　６：下部層
　１１、２１、３１：光電変換装置 2, 2a, 2b, 2c: electrode layer 3: first semiconductor layer 4: buffer layer 5: second semiconductor layer 5a: intermediate layer 6: lower layer 11, 21, 31: photoelectric conversion device

Claims (6)

  1. 　電極層と、
    該電極層上に位置する、カルコパイライト系化合物またはペロブスカイト系化合物を主として含む、ｐ型またはｉ型の第１の半導体層と、
    該第１の半導体層上に位置するｎ型の第２の半導体層と、
    前記第１の半導体層および前記第２の半導体層の界面に位置しており、シリコンを主として含むｎ型の中間層を具備する光電変換装置。     An electrode layer;
    A p-type or i-type first semiconductor layer mainly comprising a chalcopyrite compound or a perovskite compound located on the electrode layer;
    An n-type second semiconductor layer located on the first semiconductor layer;
    A photoelectric conversion device comprising an n-type intermediate layer mainly including silicon, which is located at an interface between the first semiconductor layer and the second semiconductor layer.
  2. 　前記第１の半導体層および前記中間層の界面に前記中間層よりもキャリア密度が低いバッファ層をさらに具備する、請求項１に記載の光電変換装置。 The photoelectric conversion device according to claim 1, further comprising a buffer layer having a carrier density lower than that of the intermediate layer at an interface between the first semiconductor layer and the intermediate layer.
  3. 　前記バッファ層のキャリア密度が１×１０１０～１×１０１６ｃｍ－３であり、前記中間層のキャリア密度が１×１０２０～１×１０２２ｃｍ－３である、請求項２に記載の光電変換装置。 The carrier density of the buffer layer is 1 × 10 10 to 1 × 10 16 cm −3 , and the carrier density of the intermediate layer is 1 × 10 20 to 1 × 10 22 cm −3 . Photoelectric conversion device.
  4. 　前記バッファ層は金属硫化物を含んでいる、請求項２または３に記載の光電変換装置。 The photoelectric conversion device according to claim 2 or 3, wherein the buffer layer includes a metal sulfide.
  5. 　前記電極層および前記第１の半導体層の界面に、前記第１の半導体層とは異なる結晶構造であり、前記第１の半導体層よりもキャリア密度の高いｐ型の下部層をさらに具備する、請求項１乃至４のいずれかに記載の光電変換装置。 A p-type lower layer having a crystal structure different from that of the first semiconductor layer and having a carrier density higher than that of the first semiconductor layer at the interface between the electrode layer and the first semiconductor layer; The photoelectric conversion device according to claim 1.
  6. 　前記第１の半導体層のキャリア密度が１×１０１６～９×１０１７ｃｍ－３であり、前記下部層のキャリア密度が１×１０１８～９×１０１８ｃｍ－３である、請求項５に記載の光電変換装置。 6. The carrier density of the first semiconductor layer is 1 × 10 16 to 9 × 10 17 cm −3 , and the carrier density of the lower layer is 1 × 10 18 to 9 × 10 18 cm −3. The photoelectric conversion device described in 1.
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