WO2016169463A1 - 一种整流和负载调制组合的射频前端电路和无源射频标签 - Google Patents

一种整流和负载调制组合的射频前端电路和无源射频标签 Download PDF

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Publication number
WO2016169463A1
WO2016169463A1 PCT/CN2016/079639 CN2016079639W WO2016169463A1 WO 2016169463 A1 WO2016169463 A1 WO 2016169463A1 CN 2016079639 W CN2016079639 W CN 2016079639W WO 2016169463 A1 WO2016169463 A1 WO 2016169463A1
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type mos
mos transistor
unit
drain
output
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PCT/CN2016/079639
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English (en)
French (fr)
Inventor
吴边
韩富强
王兴意
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卓捷创芯科技（深圳）有限公司
无锡智速科技有限公司
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Publication of WO2016169463A1 publication Critical patent/WO2016169463A1/zh
Priority to US15/789,404 priority Critical patent/US10157341B2/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/0723—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs

Definitions

  • the invention belongs to the field of radio frequency identification technology, and particularly relates to a passive radio frequency tag front end circuit using a combination of rectification and load modulation, and a passive radio frequency tag including the front end circuit.
  • the Radio Frequency Identification (RFID) tag itself does not have a battery, and it relies on the electromagnetic energy transmitted by the card reader. Because of its simple structure and economical utility, it has been widely used in logistics management, asset tracking and mobile medical.
  • the RF RF front-end circuit of the passive RFID tag has two input terminals respectively connected to the two ends of the external inductor coil, and is configured to receive the downlink signal and the RF field energy of the receiver and the tag from the card reader.
  • passive RFID tags absorb the electromagnetic energy emitted by the reader from the surrounding environment. After absorbing energy, the passive RFID tag rectifies a portion of the energy into a DC power source for operation by the passive RFID tag load circuit.
  • the passive radio frequency tag adopts a load modulation communication mode, that is, controls and changes the port of the radio frequency front end through the data information to be transmitted.
  • the change in impedance of the port causes a change in the current flowing through the inductor of the passive RF tag.
  • the voltage waveform across the inductor exhibits an amplitude modulated wave whose envelope changes according to the data to be transmitted.
  • the carrier frequency of the amplitude modulated wave is consistent with the frequency of the RF field carrier actively emitted by the card reader, and the envelope portion of the amplitude modulated wave is related to the change of the port impedance, that is, related to the data to be transmitted.
  • Such an amplitude modulated waveform causes electricity
  • the magnetic field caused by the sense coil changes.
  • the change of the magnetic field as the feedback data is received by the inductive coil of the card reader through the magnetic field coupling, that is, the task of data uplink communication is completed.
  • the design challenges of passive RF tags are multifaceted.
  • the challenge is first to achieve complex data transmission functions with low-power circuit technology to achieve passive design requirements.
  • Second, the challenge is also to use low-cost design techniques, that is, the smallest possible chip area, to achieve higher commercial profit and meet the physical requirements of small-size label packaging.
  • storage capacitors are inevitably used in passive tag designs.
  • the size of the storage capacitor determines the amount of power available in the circuit and is a key parameter that directly determines the performance of the circuit.
  • the size of the capacitor is infinitely proportional to the area occupied by it: the larger the chip area used, the larger the value of the storage capacitor and the better the circuit performance.
  • the key performance indicators of passive RF tags are communication sensitivity, which is the range of available distances for reliable communication and various read and write operations; the higher the sensitivity, the farther the distance, the RF tag products The better the performance.
  • the design challenge for the first challenge described above is a comprehensive low-power system design that includes system architecture, integrated manufacturing processes and the selection of integrated devices used, fine-grained design of circuit blocks, and optimized implementation of physical layouts. This is a broad and far-reaching subject and is outside the scope of the present invention.
  • the prior art relies on a large number of storage capacitors to be as low as possible.
  • the storage capacitor is often hung on the output of the low-dropout regulated power supply circuit that is connected after the rectified output.
  • the demodulation and modulation processes of various mode conversions and digital commands in the circuit generate pull-down fluctuations of instantaneous voltages with different pull-down amplitudes at the output node of the low-dropout regulated power supply, that is, instantaneous jumps of the power supply voltage.
  • Low-power, low-dropout regulated power supplies typically do not adequately reject these pull-down fluctuations by such error correction feedback loops within their circuits. The only alternative is to increase the connection on this node.
  • Storage capacitor Charge transfer stored by capacitors to alleviate the problem of pull-down fluctuations; the larger the capacitance, the better the effect of suppressing fluctuations.
  • the third design challenge mentioned above is to increase the communication sensitivity as much as possible, which is also related to the size of the on-chip storage capacitor.
  • the design technique directly related to the sensitivity lies in the implementation of the load modulation described above. Load modulation changes the equivalent load impedance across the coil to change the amount of current passing through the load, which in turn changes the magnetic field generated by the alternating current. The changed magnetic field is coupled to the coil of the card reader, ie the data transfer process is completed.
  • the demodulation capabilities of all readers are limited.
  • the limited demodulation capability determines that the above-mentioned magnetic field change must meet a minimum value in order to be correctly resolved at the reader end.
  • the modulation depth on the label coil determines whether the card reader can demodulate the data signal without error.
  • the greater the modulation depth the easier the card reader demodulates, and the farther the communication distance is, the higher the sensitivity.
  • the definition of modulation depth that the industry usually adopts is shown in Figure 1.
  • the values of the respective parameters of the modulated banner wave shown in Fig. 1 are as shown in the following table.
  • the modulation depth of the voltage on the RF tag coil itself is a parameter that decreases as the RF field energy increases.
  • the passive RF tag is issued by the reader.
  • the amplitude of the peak is often limited by the limiting circuit because of the reliability of preventing excessive voltage breakdown of the internal device; at this time, the trough is because of the strong field.
  • the combination of peaks and valleys affects the modulation depth in the near-field condition is not large enough, so many readers in the market that have limited demodulation capability due to low cost cannot correctly demodulate the RF tag chip.
  • the prior art load modulation adopts the method of modulating a pull-down resistor as shown in FIG. 2, that is, after a series connection device with a fixed resistance value is connected across two input terminals of the radio frequency tag, wherein the on and off of the switching device depends on
  • the polarity of the data to be transmitted for example, when the data is “0”, the switch is turned on, and the pull-down resistor is connected to both ends of the external inductor, forming a structure in which the pull-down resistor is connected in parallel with the equivalent impedance of the system on the inductor port, This reduces the coil impedance; conversely, when the data is "1", the switch is turned off, and the pull-down resistor does not affect the impedance of the external inductor.
  • the resistance of the pull-down resistor is expected to be small, but the valley is too low under the weak field condition, and the energy collection requirement cannot be satisfied; otherwise, when the pull-down resistance is too large, the strong The degree of pull-down under field conditions is not obvious, resulting in insufficient modulation depth. That is, the resistance of the pull-down resistor for load modulation in the prior art cannot meet the performance requirements under two different conditions of strong and weak fields, and the radio frequency tag chip cannot achieve high performance. Low-cost market demand.
  • the passive RF tag when the passive RF tag is far away from the reader, the passive RF tag is in a weak field environment, and the valley will be lowered to a relatively low level, thus causing difficulty in energy collection. Because during the valley of the covered line, the amplitude of the oscillation on the coil will be less than the sum of the threshold voltages required by the one-way conduction device inherent in the rectifier circuit. At this time, the rectifier stops working and the energy collection stops.
  • the RF tag chip only It works by the charge stored on the storage capacitor. In the existing passive RF tag circuit structure shown in FIG.
  • the charge-to-storage capacitor outputted by the rectifier during the peak period Charging causes a voltage increase including the storage capacitor and its associated nodes; during the valley period, the voltage at the coil port may be lower than the voltage at the current storage capacitor and its associated nodes.
  • the substrate node of the unidirectional conduction unit in the rectifying circuit usually composed of the MOS device has a voltage higher than the voltage of the source and drain diffusion regions in the connection method known in the industry, thereby causing the forward conduction path. .
  • the charge on the storage capacitor C1 will flow along the forward conduction current to the coil port, causing the loss of the stored energy.
  • the periodic loss affects the overall energy collection efficiency of the system, and the load circuit cannot work due to the low voltage.
  • the RF tag has no response at the far end, ie the sensitivity of the tag is reduced.
  • the width of the envelope and the width of the valley signal that is, the number of pulse periods equivalent to the carrier signal, respectively represent the digital information "1" and "0" to be transmitted ( Depending on the convention, the polarities of the peaks and troughs correspond to different polarities and are not described here.
  • the trough width is larger than the transmission protocol with a higher transmission rate; and when digital information represented by several trough pulse width signals is continuously transmitted (for example, several consecutive "0" digital information), This trough width can become very large, which is a great challenge for energy harvesting at this time.
  • the present invention aims to solve the problem that the performance and cost of the existing passive radio frequency tag products are contradictory, and proposes a combination of rectification and load modulation RF front-end circuit, which can solve the main problems faced by the radio frequency tag front-end circuit respectively. , able to effectively and accurately control the RF front-end data transmission Modulation depth to improve the communication sensitivity of the RF tag; second, it can improve the energy collection efficiency of the rectifier circuit in the RF front end, and minimize the need for the storage capacitor of the RF tag chip system to achieve low-cost product design requirements. .
  • a RF front-end circuit combined with rectification and load modulation comprising: a rectifying circuit, wherein the input end of the rectifying circuit is connected to the first antenna end and the second antenna end, and the output is The end is connected to the input end of the load circuit and the positive end of the storage capacitor, and the negative end of the storage capacitor is grounded.
  • a first modulating unit is connected between the output end of the rectifying circuit and the ground, and the first modulating unit is configured to short the second threshold unit by using the data to be transmitted as a logic control signal when the radio frequency tag is in a strong field environment or The voltage of the output end of the rectifier circuit is not short-circuited, so that the radio frequency tag has sufficient modulation depth, so that the reader end of the card reader can easily demodulate the uplink data information sent by the radio frequency tag;
  • a second modulating unit is connected between the first antenna end and the second antenna end, and the second modulating unit is configured to connect the pull-down resistor as a logic control signal by using data to be transmitted when the radio frequency tag is in a weak field environment Incoming or disconnecting to change the voltage across the inductive coil of the transmitting end of the radio frequency tag, so that the radio frequency tag has sufficient modulation depth, so that the receiving end of the card reader can easily demodulate the uplink data information sent by the radio frequency tag;
  • a unidirectional conduction unit is connected between the output end of the rectifier circuit and the input end of the load circuit and the positive end of the storage capacitor, and the input end of the unidirectional conduction unit is connected to the output end of the rectifier circuit, and the output end of the unidirectional conduction unit Connected to the input end of the load circuit and the positive end of the storage capacitor, the first control end and the second control end of the unidirectional conduction unit are respectively connected to the output end of the unidirectional conduction unit for use in the rectifier circuit and the load circuit
  • a unidirectional path is formed between the storage capacitors to prevent the current of the storage capacitor from flowing back to the rectification Circuit and coil ports.
  • the first modulation unit includes a first threshold unit, a second threshold unit, a second N-type MOS tube, and a seventh N-type MOS tube connected in series with each other,
  • the first threshold unit input is connected to the rectifier circuit output
  • the first threshold unit output is connected to the second threshold unit input
  • the second threshold unit output is connected to the seventh N-type MOS tube
  • the drain, the seventh N-type MOS transistor source is grounded, the gate is connected to the first enable signal terminal, the second N-type MOS transistor drain terminal is connected to the input end of the second threshold unit, and the second N-type MOS
  • the tube source is connected to the output of the second threshold unit, and the second N-type MOS tube is connected to the digital signal output.
  • the second modulation unit includes a third resistor, a fourth resistor, and a third N-type MOS transistor, a fourth N-type MOS transistor, and a fifth N-type MOS transistor. And a sixth N-type MOS tube,
  • the third resistance input end is connected to the first antenna end, the output end is connected to the drain of the third N-type MOS tube, and the source of the third N-type MOS tube is connected to the drain of the fourth N-type MOS tube
  • the source of the fourth N-type MOS transistor is grounded, the gate of the third N-type MOS transistor is connected to the digital signal output terminal, and the gate of the fourth N-type MOS transistor is connected to the second enable signal terminal;
  • the fourth resistance input end is connected to the second antenna end, the output end is connected to the drain of the fifth N-type MOS transistor, and the source of the fifth N-type MOS transistor is connected to the drain of the sixth N-type MOS transistor The source of the sixth N-type MOS transistor is grounded, the gate of the fifth N-type MOS transistor is connected to the digital signal output terminal, and the gate of the sixth N-type MOS transistor is connected to the second enable signal terminal.
  • the unidirectional conduction unit is a P-type MOS transistor, and a source of the P-type MOS transistor Connected to the output end of the rectifier circuit as an input terminal of the unidirectional conduction unit, the drain of the P-type MOS transistor is connected to the input end of the load circuit and the positive terminal of the storage capacitor as the output of the unidirectional conduction unit End, the gate of the P-type MOS transistor is connected to its drain, and the substrate of the P-type MOS transistor is connected to its drain;
  • the unidirectional conduction unit is an N-type MOS transistor, and the drain of the N-type MOS transistor is connected to an output end of the rectifier circuit as an input end of the unidirectional conduction unit, a source of the N-type MOS transistor Connected to the input end of the load circuit and the positive terminal of the storage capacitor as the output end of the unidirectional conduction unit, the gate of the N-type MOS transistor is connected to the drain thereof, and the substrate connection of the N-type MOS transistor To its drain.
  • Another object of embodiments of the present invention is to provide a passive radio frequency tag comprising a radio frequency front end circuit of the above-described combination of rectification and load modulation.
  • the invention relates to a rectifying and load modulation combined radio frequency front end circuit and a passive radio frequency tag, wherein a first modulation unit is arranged at an output end of the rectifying circuit, and a second modulation is arranged between the first antenna end and the second antenna end.
  • the first modulating unit and the second modulating unit respectively modulate the voltage across the inductive coil of the output end of the rectifying circuit or the transmitting end of the radio frequency tag when the tag is in a strong or weak field environment, thereby implementing passive radio frequency tag chip modulation
  • the depth adjustment achieves the purpose of easily demodulating the uplink data information sent by the radio frequency tag at the receiving end of the card reader, that is, improving the sensitivity of the passive radio frequency tag chip; meanwhile, the output end of the rectifying circuit and the input end of the load circuit and the energy storage
  • the unidirectional conduction unit connected between the positive terminals of the capacitors has a peak current during the RF field energy, and the rectified current is turned on and input to the load circuit and the storage capacitor to supply the load circuit, and the storage capacitor stores the electric charge.
  • the storage capacitor When the energy of the RF field is trough, the storage capacitor outputs a charge externally, because the one-way unit is in strict condition. Reverse bias state, so the charge can not flow backward to the rectifier circuit and the coil port, avoiding the loss of the stored energy.
  • the charge can only be input to the load circuit to supply the load circuit, which improves the energy storage charge utilization of the storage capacitor. , Reducing the number of storage capacitors used reduces the area of the tag chip and reduces the cost of the chip.
  • the invention effectively solves the problem that the cost and sensitivity of the existing passive radio frequency tag are contradictory, so that the tag chip meets the market demand of low cost and high performance.
  • Figure 1 is an envelope diagram of the field energy induced on a passive radio frequency tag coil
  • FIG. 2 is a structural diagram of a conventional passive radio frequency tag load modulation circuit
  • FIG. 3 is a structural diagram of a conventional passive radio frequency tag circuit
  • FIG. 4 is a block diagram showing the structure of a passive radio frequency tag circuit of the present invention.
  • Figure 5 is a circuit diagram of a first modulation unit of the present invention.
  • Figure 6 is a circuit diagram of a first embodiment of a first modulation unit and a one-way conduction unit of the present invention
  • Figure 7 is a circuit diagram of a second modulation unit of the present invention.
  • Figure 8 is a circuit diagram of a second embodiment of the one-way unit of the present invention.
  • FIG. 4 is a structural block diagram of a passive radio frequency tag circuit according to the present invention.
  • the RF front-end circuit of the rectification and load modulation combination includes a rectification circuit, and the input end of the rectification circuit is connected to the first antenna end ANTA1 and The second antenna terminal ANTB1, the output terminal is connected to the input end of the load circuit and the energy storage The positive terminal of the capacitor C1 and the negative terminal of the storage capacitor C1 are grounded.
  • a first modulating unit is connected between the output end of the rectifying circuit and the ground, and the first modulating unit is configured to short the second threshold unit by using the data to be transmitted as a logic control signal when the radio frequency tag is in a strong field environment or The voltage of the output end of the rectifier circuit is not short-circuited, so that the radio frequency tag has sufficient modulation depth, so that the reader end of the card reader can easily demodulate the uplink data information sent by the radio frequency tag;
  • a second modulating unit is connected between the first antenna end and the second antenna end, and the second modulating unit is configured to connect the pull-down resistor as a logic control signal by using data to be transmitted when the radio frequency tag is in a weak field environment Incoming or disconnecting to change the voltage across the inductive coil of the transmitting end of the radio frequency tag, so that the radio frequency tag has sufficient modulation depth, so that the receiving end of the card reader can easily demodulate the uplink data information sent by the radio frequency tag;
  • a unidirectional conduction unit is further connected between the output end of the rectifier circuit and the input end of the load circuit and the positive terminal of the storage capacitor C1, and the input end of the unidirectional conduction unit is connected to the output end of the rectifier circuit, and the unidirectional conduction unit
  • the output end is connected to the input end of the load circuit and the positive end of the storage capacitor C1
  • the first control end ctrl1 and the second control end ctrl2 of the unidirectional conduction unit are respectively connected to the output end of the unidirectional conduction unit, so that the structure is
  • the one-way conduction unit is formed as a one-way switch from the rectifier circuit output node to the load circuit and the storage capacitor C1.
  • the invention relates to a rectifying and load modulation combined radio frequency front end circuit and a passive radio frequency tag, wherein a first modulation unit is arranged at an output end of the rectifying circuit, and a second modulation is arranged between the first antenna end and the second antenna end.
  • the first modulating unit and the second modulating unit respectively modulate the voltage across the inductive coil of the output end of the rectifying circuit or the transmitting end of the radio frequency tag when the tag is in a strong or weak field environment, thereby implementing passive radio frequency tag chip modulation Depth adjustment, easy to demodulate the radio frequency standard at the receiver end of the reader
  • the purpose of signing the uplink data information is to increase the sensitivity of the passive radio frequency tag chip; at the same time, the single-conducting unit connected between the output end of the rectifying circuit and the input end of the load circuit and the positive end of the storage capacitor is in the radio frequency field.
  • the rectified current is turned on and input to the load circuit and the storage capacitor to supply the load circuit, and the storage capacitor stores the electric charge, and when the RF field energy is a trough, the storage capacitor discharges to the outside. Since the one-way conduction unit is in a strictly reverse bias state, the charge cannot flow backward to the rectifier circuit and the coil port, thereby avoiding the loss of the stored energy, and the charge can only be input to the load circuit to supply the load circuit, thereby improving
  • the energy storage charge utilization of the storage capacitor reduces the number of storage capacitors used, reduces the area of the tag chip, and reduces the cost of the chip.
  • the invention effectively solves the problem that the cost and sensitivity of the existing passive radio frequency tag are contradictory, so that the tag chip meets the market demand of low cost and high performance.
  • the first modulation unit includes a first threshold unit, a second threshold unit, a second N-type MOS tube NM2, and a seventh N-type MOS connected in series with each other.
  • the first threshold unit input is connected to the rectifier circuit output
  • the first threshold unit output is connected to the second threshold unit input
  • the second threshold unit output is connected to the seventh N-type MOS tube
  • the drain of the NM7, the source of the seventh N-type MOS transistor NM7 is grounded, the gate is connected to the first enable signal terminal enable1, and the drain terminal of the second N-type MOS transistor NM2 is connected to the input end of the second threshold unit
  • the N-type MOS transistor NM2 source terminal is connected to the output terminal of the second threshold unit
  • the second N-type MOS transistor NM2 gate is connected to the digital signal output terminal DATA.
  • the first threshold unit is at least one diode, or at least one P-type MOS tube, or at least one N-type MOS tube,
  • the cathode end of any diode is connected to the anode end of the adjacent diode to form a series structure, and the first diode anode end is connected to the output end of the rectifier circuit as the input end of the first threshold unit, and the last diode is cathode An extreme connection to the second threshold unit input is an output of the first threshold unit;
  • the drain terminal of any P-type MOS transistor is connected to the source terminal of the adjacent P-type MOS transistor to form a series structure, and the gate of each P-type MOS transistor is connected to the drain thereof, the first The source of the P-type MOS transistor is connected to the output end of the rectifier circuit as the input end of the first threshold unit, and the drain of the last P-type MOS transistor is connected to the input terminal of the second threshold unit as the first threshold unit Output
  • the source terminal of any N-type MOS transistor is connected to the drain terminal of the adjacent N-type MOS transistor to form a series structure, and the gate of each N-type MOS transistor is connected to the drain thereof, the first The drain of the N-type MOS transistor is connected to the output end of the rectifier circuit as the input end of the first threshold unit, and the source of the last N-type MOS transistor is connected to the input terminal of the second threshold unit as the first threshold unit The output.
  • the first threshold unit in this embodiment takes two P-type MOS transistors in series as an example.
  • the source of the second P-type MOS transistor PM2 is connected to the output end of the rectifier circuit as an input end of the first threshold unit.
  • the gate is connected to the drain and connected to the source terminal of the third P-type MOS transistor PM3, and the gate of the third P-type MOS transistor PM3 is connected to the drain and connected to the second threshold unit input as the first threshold unit The output.
  • the second threshold unit is at least one diode, or at least one P-type MOS transistor, or at least one N-type MOS transistor.
  • the cathode end of any of the diodes is connected to the anode end of the adjacent diode a series structure, a first diode anode end connected to the first threshold unit output end being the input end of the second threshold unit, and a last diode cathode end connected to the seventh N-type MOS tube drain being the second threshold unit Output
  • the drain terminal of any P-type MOS transistor is connected to the source terminal of the adjacent P-type MOS transistor to form a series structure, and the gate of each P-type MOS transistor is connected to the drain thereof, the first The source of the P-type MOS transistor is connected to the input end of the first threshold unit as the input end of the second threshold unit, and the drain of the last P-type MOS transistor is connected to the drain of the seventh N-type MOS transistor.
  • the source terminal of any N-type MOS transistor is connected to the drain terminal of the adjacent N-type MOS transistor to form a series structure, and the gate of each N-type MOS transistor is connected to the drain thereof, the first The drain of the N-type MOS transistor is connected to the input end of the first threshold unit as the input end of the second threshold unit, and the source of the last N-type MOS transistor is connected to the drain of the seventh N-type MOS transistor as the The output of the second threshold unit.
  • the second threshold unit of the embodiment is exemplified by two P-type MOS transistors in series.
  • the source of the fifth P-type MOS transistor PM5 is connected to the input of the first threshold unit as the input of the second threshold unit.
  • the gate is connected to the drain and connected to the source terminal of the sixth P-type MOS transistor PM6.
  • the gate of the sixth P-type MOS transistor PM6 is connected to the drain and connected to the drain of the seventh N-type MOS transistor NM7.
  • the output of the first threshold unit is described.
  • FIG. 7 is a circuit diagram of a second modulation unit according to the present invention.
  • the second modulation unit includes a third resistor R3 and a fourth resistor R4, and a third N-type MOS transistor NM3 and a fourth N-type MOS transistor NM4. a fifth N-type MOS transistor NM5 and a sixth N-type MOS transistor NM6,
  • the input end of the third resistor R3 is connected to the first antenna end ANTA1, and the output end is connected to the third N a drain of the MOS transistor NM3, a source of the third N-type MOS transistor NM3 is connected to a drain of the fourth N-type MOS transistor NM4, and a source of the fourth N-type MOS transistor NM4 is grounded, the The gate of the third N-type MOS transistor NM3 is connected to the digital signal output terminal DATA, and the gate of the fourth N-type MOS transistor NM4 is connected to the second enable signal terminal enable2;
  • the input terminal of the fourth resistor R4 is connected to the second antenna terminal ANTB1, the output terminal is connected to the drain of the fifth N-type MOS transistor NM5, and the source of the fifth N-type MOS transistor NM5 is connected to the sixth N-type MOS.
  • a drain of the transistor NM6, a source of the sixth N-type MOS transistor NM6 is grounded, a gate of the fifth N-type MOS transistor NM5 is connected to a digital signal output terminal DATA, and a gate of the sixth N-type MOS transistor NM6 Connect to the second enable signal terminal enable2.
  • the first modulation unit and the second modulation unit of the present invention can respectively modulate the uplink data information sent by the radio frequency label when the label is in a strong or weak field environment, so as to increase the modulation depth of the uplink data information.
  • the card reader receiving end easily demodulates the uplink data information sent by the radio frequency tag, that is, improves the sensitivity of the passive radio frequency tag chip.
  • the specific working principle of the first modulation unit and the second modulation unit is:
  • the passive RF tag When the passive RF tag is in a strong field environment, the voltage at the output point of the rectifier circuit is higher. In this case, in order to pull-down the voltage at the A point, the RF tag has a deeper modulation depth at both ends of the inductor, digital signal.
  • the output terminal DATA controls the second N-type MOS transistor NM2 to be closed to short-circuit the second threshold unit, and the first enable signal terminal enable1 controls the seventh N-type MOS transistor NM7 to be closed. At this time, only the first threshold is included in the first modulation unit.
  • the cell is connected in the circuit, therefore, the voltage at point A directly drops the threshold voltage (n ⁇ V th of the multiple of the number of unidirectionally pass devices in the second threshold cell, where n is the number of unidirectional devices in the second threshold cell)
  • the voltage at the output end of the rectifier circuit is changed, that is, the voltage across the inductor coil of the transmitting end is changed, and the modulation depth of the passive RF tag chip is adjusted.
  • the threshold voltage characteristic of the first threshold unit and the second threshold unit in the first modulating unit causes the voltage at point A to fail.
  • the second threshold unit has almost no influence on the voltage of point A, that is, the first modulation unit cannot realize the adjustment of the modulation depth of the passive radio frequency tag chip in a weak field environment.
  • the digital signal output terminal DATA controls the third N-type MOS transistor NM3 and the fifth N-type MOS transistor NM5 to be closed
  • the second enable signal terminal enable2 controls the fourth N-type MOS.
  • the tube NM4 and the sixth N-type MOS tube NM6 are closed, and a path is formed between the third resistor R3 and the fourth resistor R4 and the ground, and the voltage between the first antenna end ANTA1 and the second antenna end ANTB1 is pulled low to implement passive Adjustment of the modulation depth of the RF tag chip.
  • the modulation cannot be performed in the weak field, so that the sensitivity of the label is weak in the weak field; on the contrary, if only the second modulation unit is used, in order to increase the modulation depth in the strong field
  • the resistance values of the third resistor R3 and the fourth resistor R4 should be designed to be small values, but the second modulation unit of the smaller resistance value causes a low valley problem under weak field conditions, and cannot satisfy the energy collection.
  • the pull-down resistor value is designed to be a large value, which will cause the label to be pulled down under strong field conditions, so that the modulation depth is not enough, that is, if only used
  • the second modulation unit, the pull-down resistance of the load modulation can not balance the performance requirements under the two different conditions of the strong and weak field, so that the label has high sensitivity only in the strong field or only in the weak field, obviously such performance
  • the label is not market competitive. Therefore, the present invention adopts an alternate combination modulation mode of the first modulation unit and the second modulation unit, so that the label is adaptively modulated according to the strong field environment in which the label is located, so as to achieve the purpose of improving the overall performance of the label.
  • a unidirectional conduction unit is further connected between the output end of the rectifier circuit and the input end of the load circuit and the positive terminal of the storage capacitor C1, and the input end of the unidirectional conduction unit is connected to the output end of the rectifier circuit, and the unidirectional conduction unit
  • the output end is connected to the input end of the load circuit and the positive end of the storage capacitor C1
  • the first control end ctrl1 and the second control end ctrl2 of the unidirectional conduction unit are respectively connected to the output end of the unidirectional conduction unit, so that the structure is
  • the one-way conduction unit is formed as a one-way switch in the direction of the rectifier circuit toward the load circuit and the storage capacitor C1.
  • the rectified current can be input to the load circuit and the storage capacitor C1 through the one-way conduction unit to supply the load circuit, and the storage capacitor stores the charge; when the RF field energy is the trough period
  • the amplitude of the oscillation on the coil is smaller than the threshold voltage of all devices with unidirectional conduction characteristics in the rectifier circuit (such as the threshold voltage of the diode D4 during the positive half cycle period and the threshold voltage of the unidirectional conduction unit, or the threshold voltage of the diode D3 during the negative half cycle period) And the single-pass cell threshold voltage), when the energy collection stops, the radio frequency tag chip only works by the charge stored on the storage capacitor C1.
  • the charge on the storage capacitor C1 flows to the load circuit, and the supply load circuit continues to operate. Since the unidirectional conduction unit is in the reverse-off state, the charge cannot flow backward to the rectifier circuit and the coil port, thereby avoiding the charge. The loss increases the energy storage charge utilization of the storage capacitor C1, which is equivalent to reducing the number of storage capacitors. Under the premise of ensuring the cost of the chip, the label is realized at the far end (or weak field environment). The purpose of high sensitivity is to solve the problem that the cost and sensitivity of the existing passive RF tag are contradictory.
  • the unidirectional conduction unit is a P-type MOS transistor PM1, and a source of the P-type MOS transistor PM1 is connected to a rectifier circuit output.
  • the input terminal of the P-type MOS transistor PM1 is connected to the input end of the load circuit and the positive terminal of the storage capacitor as an output end of the unidirectional conduction unit, P
  • the gate of the MOS transistor PM1 is connected as a first control terminal ctrl1 of the unidirectional conduction unit to its drain.
  • the substrate of the P-type MOS transistor PM1 serves as a unidirectional conduction unit.
  • the second control terminal ctrl2 is connected to its drain.
  • the conventional connection of a P-type MOS transistor is to connect the substrate of the MOS transistor to the highest potential, that is, the source of the MOS transistor, which is called a reverse connection. This is because the substrate of the PMOS transistor is an N-type doped N-well region.
  • a parasitic current positive feedback loop is formed to minimize the substrate and surrounding NMOS transistors. The circuit triggers the occurrence of an irreversible latch-up, which needs to be connected to the highest voltage point, so that the substrate forms a strong reverse-biased diode to prevent deadlock.
  • the operating current of a passive RF tag is basically on the order of microamps (10 -6 amps) or even nanoamps (10 -9 amps), and the current of this order does not actually trigger a deadlock phenomenon;
  • the physical design of the layout corresponding to this design technique intentionally increases the distance between the surrounding guard-ring and the device that intentionally pulls out the parasitic positive feedback loop and the P-type MOS device, effectively reducing the possibility.
  • the gain coefficient of the formed feedback loop makes it impossible to achieve positive feedback.
  • the unidirectional conduction unit is an N-type MOS transistor NM1, and the drain of the N-type MOS transistor NM1 is connected to a rectifier circuit.
  • An output terminal of the N-type MOS transistor NM1 is connected to the input end of the load circuit and the positive terminal of the storage capacitor C1 as an output end of the unidirectional conduction unit,
  • the gate of the N-type MOS transistor NM1 is connected to the drain of the first control terminal ctrl1 as a unidirectional conduction unit.
  • the substrate of the N-type MOS transistor NM1 serves as a single guide.
  • the second control terminal ctrl2 of the pass unit is connected to its drain.
  • the N-type MOS transistor NM1 connects its substrate to the lowest potential according to the conventional connection method to avoid deadlock phenomenon, in the period of the valley, the positive terminal of the storage capacitor C1, that is, the N-type MOS transistor NM1 At the substrate end, the coil port is forward biased, and the charge on the capacitor will flow toward the coil port along the forward bias, resulting in a loss of stored charge. Therefore, in this patent, the structure opposite to the conventional connection method is adopted to avoid the leakage of the stored energy under the above-mentioned trough conditions, thereby improving the charge utilization ratio of the storage capacitor, that is, reducing the number of storage capacitors used to reduce the cost of the chip. .
  • the switch tube used in the embodiment of the present invention such as the second N-type MOS transistor NM2 in the first modulation unit, the seventh N-type MOS transistor NM7, and the third N-type MOS transistor in the second modulation unit.
  • NM3, fourth N-type MOS transistor NM4, fifth N-type MOS transistor NM5, and sixth N-type MOS transistor NM6 can all be replaced by P-type MOS transistors, and correspondingly, digital control signals of gate terminals of respective P-type MOS transistors Or the logic control signals are controlled by the opposite logic signals.
  • Another object of the embodiments of the present invention is to provide a passive radio frequency tag including a radio frequency front end circuit of the above rectification and load modulation combination, where a first modulation unit is disposed at an output end of the rectifying circuit, and the first antenna end and the second antenna are disposed at the output end of the rectifying circuit A second modulating unit is disposed between the ends, and the first modulating unit and the second modulating unit respectively change the voltage across the inductive coil of the output end of the rectifying circuit or the transmitting end of the radio frequency tag by modulation when the tag is in a strong or weak field environment.
  • the purpose of easily demodulating the uplink data information sent by the radio frequency tag to the receiving end of the card reader is to improve the sensitivity of the passive radio frequency tag chip; at the same time, the output end of the rectifying circuit and the input end of the load circuit and the positive end of the storage capacitor
  • the unidirectional conduction unit connected between the RF field energy is a peak period, and the rectified current is turned on and input to the load circuit and the storage capacitor, and the load circuit is operated, and the storage capacitor stores the charge; and in the RF field When the energy is in the trough period, the storage capacitor discharges to the outside.
  • the load circuit is supplied to the load circuit to improve the storage charge utilization of the storage capacitor, reduce the number of storage capacitors, reduce the area of the tag chip, and reduce the cost of the chip.
  • the invention effectively solves the problem that the cost and sensitivity of the existing passive radio frequency tag are contradictory, so that the tag chip meets the market demand of low cost and high performance.

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Abstract

一种整流和负载调制组合的射频前端电路和无源射频标签，在整流电路的输出端设置第一调制单元，在第一天线端与第二天线端之间设置有第二调制单元，所述第一调制单元与第二调制单元分别在标签处于强、弱场环境时，通过调制来改变整流电路输出端或射频标签发射端电感线圈两端的电压，实现无源射频标签芯片调制深度的调节；同时，整流电路输出端与负载电路输入端及储能电容的正极端之间连接的单向导通单元可在射频场能量为波谷时期避免储能电荷的损失，提高储能电荷利用率，降低了标签芯片的面积，达到降低芯片成本的目的。该技术方案有效解决了现有的无源射频标签成本与灵敏度相矛盾的问题，使得标签芯片满足低成本、高性能的市场需求。

Description

一种整流和负载调制组合的射频前端电路和无源射频标签 技术领域
本发明属于射频识别技术领域，具体是指一种采用整流和负载调制组合的无源射频标签前端电路，以及包含该前端电路的无源射频标签。
背景技术
无源射频识别(Radio Frequency Identification，RFID)标签本身不带电池，其依靠读卡器发送的电磁能量工作。由于它结构简单、经济实用，因而其在物流管理、资产追踪以及移动医疗领域获得了广泛的应用。
无源RFID标签的射频前端电路有两个输入端，分别与外部电感线圈的两端相连，是接收由读卡器所发出的下行(downlink)信号与射频场能量的接收端和标签向外发射反馈的上行(uplink)数据信号的发射端所共用的端口。首先，无源RFID标签工作时会从周围环境中吸收读卡器发送的电磁能量。无源RFID标签在吸收能量之后，将一部分能量整流为直流电源，以供无源RFID标签负载电路工作。其次，在从标签到读卡器设备发送数据信息的上行通讯过程中，无源射频标签采取负载调制(load modulation)的通讯方式，即通过所要发射出的数据信息来控制并改变射频前端的端口阻抗，该端口阻抗的变化会导致无源射频标签的电感线圈上流过的电流发生变化，在电感线圈两端的电压波形呈现出包络线依据所要发射的数据变化而变化的调幅调制波。其中，调幅调制波的载波频率与读卡器主动发出的射频场载波的频率一致，调幅调制波的包络线部分与端口阻抗变化有关，也即与所要发射出的数据有关。这样的调幅波形导致电 感线圈所引起的磁场发生变化。该磁场的变化作为反馈数据被读卡器的电感线圈通过磁场耦合的作用而接收，即完成数据上行通讯的任务。
无源射频标签的设计挑战是多方面的。其挑战首先在于用低功耗的电路技术实现复杂的数据传输功能，从而达到无源设计的要求。其次，挑战也在于用低成本设计技术，即尽可能小的芯片面积，达到较高的商业利润和满足小尺寸标签封装的物理要求。比如,在无源标签设计中不可避免地使用到储能电容。储能电容的大小决定电路中可用电能的多少，也是直接决定电路性能的关键参数。在现代的深亚微米集成制造工艺中，电容的大小毫无例外的与其所占用的面积成正比关系：所用芯片面积越大，储能电容值越大，电路性能越好。除了上述两者之外，更重要的，无源射频标签的关键性能指标为通讯灵敏度，即完成可靠通讯和各种读写操作的可用距离范围；灵敏度越高，距离越远，射频标签产品的性能越好。
应对上述第一个挑战的设计技术是全方位的低功耗***设计，包括***架构，集成制造工艺和所用集成器件的选取，电路模块的精细设计，以及物理版图的最优化实现等等。这是一个广泛而深远的课题，不在本发明专利所要讨论的范围之内。
应对上述第二个设计挑战,现有技术对大量的储能电容的依赖要尽可能的降低。储能电容往往挂在整流输出之后所接到的低压差稳压电源电路的输出端上。电路中各种模式转换和数字命令的解调和调制过程均会在低压差稳压电源的输出节点上产生下拉幅度不同的瞬间电压下拉波动，即电源电压的瞬间跳变。而低功耗的低压差稳压电源对此类瞬态跳变通常不能通过其电路内部的纠错反馈环路而充分抑制这些下拉波动。唯一可选的方法就是加大连接在该节点上的 储能电容。靠电容存储的电荷输送来缓解下拉波动的问题；电容越大，抑制波动的效果越好。
应对上述第三个设计挑战，即尽可能提高通讯灵敏度，也是和片上储能电容的大小相关的。储能电容越大,在同样的距离条件下的能量收集也会越多,也即灵敏度越高。除去片上储能电容的因素之外，与灵敏度，即通讯距离，直接相关的设计技术在于前面所述负载调制的实现。负载调制改变了线圈两端的等效负载阻抗，以改变负载上通过的电流大小，继而改变了交流电流所产生的磁场。改变的磁场耦合到读卡器的线圈上，即完成数据传输过程。但是，所有读卡器的解调能力都是有限的，有限的解调能力决定了上述磁场改变量必须满足一个最小的数值，才能在读卡器端被正确无误地解析出来。在耦合条件不变的情况下，即通讯距离一定的条件下，磁场的改变量是由标签线圈上的调制深度决定的。所以射频标签的发射端的调制深度决定了读卡器是否可以无误的解调出数据信号来。调制深度越大，读卡器解调越容易，通讯距离越远，灵敏度也越高。业界通常采取的调制深度的定义如图1。作为举例，图1中所示调制条幅波的各个参数的取值如下表所示。
参数符号 最小 最大
m＝(a-b)/(a+b) 90％ 100％
TF1 4*Tc 10*Tc
TF2 0 0.5*TF1
TF3 0 0.5*TFd0
X 0 0.05*a
Y 0 0.05*a
但是，射频标签线圈上电压的调制深度本身是一个随着射频场能量的增强而减小的参数。在读卡器与射频标签距离近时，无源射频标签处于读卡器发出 的较强的射频场中，在这样的强场环境下，因为防止过高的电压击穿内部器件的可靠性缘故，波峰的幅度往往受到限幅电路的限制；此时波谷因为强场的缘故而比弱场情况下高很多，这样的波峰波谷组合影响到近场情况下的调制深度不够大，使得市场上很多因为低成本而造成有限解调能力的读卡器不能正确解调射频标签芯片发出的上行数据。这就是业界通常遇到的近场条件下射频标签存在通讯应答盲区的主要原因之一。
现有技术的负载调制采用如图2所示的调制下拉电阻的做法，即用固定阻值的电阻串联开关器件之后跨接在射频标签两个输入端，其中开关器件的导通与关断取决于所要传输的数据的极性，比如，数据“0”时开关导通，下拉电阻得以接入外部电感线圈的两端，形成下拉电阻与电感线圈端口上的***等效阻抗并联的结构,以此降低了线圈阻抗；反之，数据“1”时开关关断，下拉电阻不影响外部电感线圈的阻抗。为了使得下拉效果明显而加大调制深度，该下拉电阻的阻值希望较小，但是在弱场条件下波谷过低，不能满足能量收集的要求；反之，下拉电阻阻值过大的时候，强场条件下的下拉程度不明显，导致调制深度不够，即，现有技术中负载调制用的下拉电阻阻值无法兼顾强弱场两种不同条件下的性能要求，射频标签芯片无法达到高性能、低成本的市场需求。
另一方面，在无源射频标签距离读卡器距离较远时，无源射频标签处于弱场环境下，这时波谷会降低到相对较低的水平，于是就带来能量收集上的困难，因为在包罗线的波谷期间，线圈上的震荡幅度会小于整流电路中所固有的单向导通器件所需要的阈值电压的总和，此时整流器停止工作，能量收集也随之停止，射频标签芯片仅仅靠储能电容上存储的电荷工作。在如图3所示的现有无源射频标签电路结构中，在波峰的时间段，通过整流器输出的电荷对储能电容 充电，导致包括储能电容及其周围相关节点的电压升高；在波谷的时间段，线圈端口的电压有可能低于当时储能电容及其周围相关节点的电压。此时，通常由MOS器件构成的整流电路中的单向导通单元的衬底节点，在业界公知的连接方式中，其电压会高于源、漏端扩散区的电压，从而造成正向导通通路。储能电容C1上的电荷会顺着正向导通电流流向线圈端口，造成储能电荷的损失，这样周期性的损失影响了***整体的能量收集效率,导致负载电路由于电压过低而无法工作，射频标签在远端无响应，即标签的灵敏度降低。
在含有脉宽调制信号的场能量载波信号中，包络的波峰和波谷信号的宽度,即其等同于载波信号的脉冲周期数，分别代表所要传输的数字信息“1”和“0”的(根据约定不同，波峰和波谷对应的信号极性有所不同，此处不再分别赘述)。对于传输速率低的传输协议，该波谷宽度会比传输速率高的传输协议更大；而且当连续传输若干个波谷脉宽信号所代表的数字信息时(比如连续几个“0”数字信息)，该波谷宽度会变得很大，对于此时的能量收集具有极大的挑战。
所以，无源射频标签上的储能电容的使用直接决定了无源射频标签***成本和灵敏度两个重要的性能指标，如何更加高效的利用储能电容，在有限的储能电容的前提下，最大限度的提高射频标签的灵敏度成为该领域的一个备受关注的研究课题。
发明内容
本发明目的在于针对现有无源射频标签产品性能与成本相互矛盾的问题，提出了一种整流和负载调制组合的射频前端电路，能够分别解决射频标签前端电路所面临的主要问题，即其一，能够有效并精确地控制射频前端发射数据时 的调制深度，以提高射频标签的通讯灵敏度；其二，能够提高射频前端中整流电路的能量收集效率，最大限度的减少射频标签芯片***对储能电容的需求，以达到低成本的产品设计要求。
为实现上述目的，本发明所采取的技术方案为：一种整流和负载调制组合的射频前端电路，包括，整流电路，所述整流电路输入端连接至第一天线端与第二天线端，输出端连接至负载电路输入端及储能电容的正极端，所述储能电容的负极端接地，
所述整流电路输出端与地之间连接有第一调制单元，所述第一调制单元用于在射频标签处于强场环境时，通过所要传输的数据作为逻辑控制信号将第二阈值单元短路或者不短路来改变所述整流电路输出端的电压，使得射频标签具有足够的调制深度，实现读卡器接收端容易地解调射频标签发送的上行数据信息的目的；
所述第一天线端与第二天线端之间连接有第二调制单元，所述第二调制单元用于在射频标签处于弱场环境时，通过所要传输的数据作为逻辑控制信号将下拉电阻接入或者断开来改变射频标签发射端电感线圈两端的电压，使得射频标签具有足够的调制深度，实现读卡器接收端容易地解调射频标签发送的上行数据信息的目的；
所述整流电路输出端与负载电路输入端及储能电容的正极端之间连接有单向导通单元，所述单向导通单元的输入端连接至整流电路输出端，单向导通单元的输出端连接至负载电路输入端及储能电容的正极端，单向导通单元的第一控制端与第二控制端分别连接至所述单向导通单元的输出端，用于在整流电路与负载电路和储能电容之间形成单向通路，以阻止储能电容的电流回流至整流 电路和线圈端口。
根据以上结构的本发明，其进一步的技术特征在于，所述第一调制单元包括相互串联的第一阈值单元、第二阈值单元、第二N型MOS管，和第七N型MOS管，
所述第一阈值单元输入端连接至所述整流电路输出端，所述第一阈值单元输出端连接至第二阈值单元输入端，所述第二阈值单元输出端连接至第七N型MOS管漏极，第七N型MOS管源极接地，栅极接第一使能信号端，所述第二N型MOS管漏极端连接至所述第二阈值单元的输入端，第二N型MOS管源极端连接至所述第二阈值单元的输出端，所述第二N型MOS管栅极连接至数字信号输出端。
根据以上结构的本发明，其进一步的技术特征在于，所述第二调制单元包括第三电阻、第四电阻，以及第三N型MOS管、第四N型MOS管、第五N型MOS管和第六N型MOS管，
所述第三电阻输入端连接至第一天线端，输出端连接至第三N型MOS管的漏极，所述第三N型MOS管的源极连接至第四N型MOS管的漏极，所述第四N型MOS管的源极接地，所述第三N型MOS管栅极连接至数字信号输出端，所述第四N型MOS管栅极连接至第二使能信号端；
所述第四电阻输入端连接至第二天线端，输出端连接至第五N型MOS管的漏极，所述第五N型MOS管的源极连接至第六N型MOS管的漏极，所述第六N型MOS管的源极接地，所述第五N型MOS管栅极连接至数字信号输出端，所述第六N型MOS管栅极连接至第二使能信号端。
更进一步的，所述单向导通单元为P型MOS管，所述P型MOS管的源极 连接至整流电路输出端，作为所述单向导通单元的输入端，所述P型MOS管的漏极连接至负载电路输入端及储能电容的正极端，作为所述单向导通单元的输出端，所述P型MOS管的栅极连接至其漏极，所述P型MOS管的衬底连接至其漏极；
或者是所述单向导通单元为N型MOS管，所述N型MOS管的漏极连接至整流电路输出端，作为所述单向导通单元的输入端，所述N型MOS管的源极连接至负载电路输入端及储能电容的正极端，作为所述单向导通单元的输出端，所述N型MOS管的栅极连接至其漏极，所述N型MOS管的衬底连接至其漏极。
本发明实施例的另一目的在于提供一种包括上述整流和负载调制组合的射频前端电路的无源射频标签。
本发明所述一种整流和负载调制组合的射频前端电路和无源射频标签，在整流电路的输出端设置第一调制单元，在第一天线端与第二天线端之间设置有第二调制单元，所述第一调制单元与第二调制单元分别在标签处于强、弱场环境时，通过调制来改变整流电路输出端或射频标签发射端电感线圈两端的电压，实现无源射频标签芯片调制深度的调节，达到读卡器接收端容易地解调射频标签发送的上行数据信息的目的，即，提高了无源射频标签芯片的灵敏度；同时，整流电路输出端与负载电路输入端及储能电容的正极端之间连接的单向导通单元在射频场能量为波峰时期，可将经过整流后的电流导通输入至负载电路和储能电容，供给负载电路工作，并且储能电容储存电荷，而在射频场能量为波谷时期，储能电容对外输出电荷，由于该单向导通单元处于严格的反向偏置状态，因此电荷无法逆向流动至整流电路和线圈端口，避免了储能电荷的损失，电荷只能输入至负载电路中供给负载电路工作，提高了储能电容的储能电荷利用率， 减少储能电容的使用数量，降低了标签芯片的面积，达到降低芯片成本的目的。本发明有效解决了现有的无源射频标签成本与灵敏度相矛盾的问题，使得标签芯片满足低成本、高性能的市场需求。
附图说明
图1为无源射频标签线圈上感应到的场能量的包络图；
图2是现有无源射频标签负载调制电路结构图；
图3是现有无源射频标签电路结构图；
图4是本发明无源射频标签电路结构框图；
图5是本发明第一调制单元电路结构图；
图6是本发明第一调制单元和单向导通单元第一实施例电路图；
图7是本发明第二调制单元电路结构图；
图8是本发明单向导通单元第二实施例电路图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
如图4所示为本发明无源射频标签电路结构框图，本发明所述一种整流和负载调制组合的射频前端电路，包括整流电路，所述整流电路输入端连接至第一天线端ANTA1与第二天线端ANTB1，输出端连接至负载电路输入端及储能 电容C1的正极端，所述储能电容C1的负极端接地。
所述整流电路输出端与地之间连接有第一调制单元，所述第一调制单元用于在射频标签处于强场环境时，通过所要传输的数据作为逻辑控制信号将第二阈值单元短路或者不短路来改变所述整流电路输出端的电压，使得射频标签具有足够的调制深度，实现读卡器接收端容易地解调射频标签发送的上行数据信息的目的；
所述第一天线端与第二天线端之间连接有第二调制单元，所述第二调制单元用于在射频标签处于弱场环境时，通过所要传输的数据作为逻辑控制信号将下拉电阻接入或者断开来改变射频标签发射端电感线圈两端的电压，使得射频标签具有足够的调制深度，实现读卡器接收端容易地解调射频标签发送的上行数据信息的目的；
所述整流电路输出端与负载电路输入端及储能电容C1的正极端之间还连接有单向导通单元，所述单向导通单元的输入端连接至整流电路输出端，单向导通单元的输出端连接至负载电路输入端及储能电容C1的正极端，单向导通单元的第一控制端ctrl1与第二控制端ctrl2分别连接至所述单向导通单元的输出端，如此结构使得所述单向导通单元形成为由整流电路输出节点向负载电路和储能电容C1方向的单向导通开关。
本发明所述一种整流和负载调制组合的射频前端电路和无源射频标签，在整流电路的输出端设置第一调制单元，在第一天线端与第二天线端之间设置有第二调制单元，所述第一调制单元与第二调制单元分别在标签处于强、弱场环境时，通过调制来改变整流电路输出端或射频标签发射端电感线圈两端的电压，实现无源射频标签芯片调制深度的调节，达到读卡器接收端容易地解调射频标 签发送的上行数据信息的目的，即，提高了无源射频标签芯片的灵敏度；同时，整流电路输出端与负载电路输入端及储能电容的正极端之间连接的单向导通单元在射频场能量为波峰时期，可将经过整流后的电流导通输入至负载电路和储能电容，供给负载电路工作，并且储能电容储存电荷，而在射频场能量为波谷时期，储能电容对外放电，由于该单向导通单元处于严格的反向偏置状态，因此电荷无法逆向流动至整流电路和线圈端口，避免了储能电荷的损失，电荷只能输入至负载电路中供给负载电路工作，提高了储能电容的储能电荷利用率，减少储能电容的使用数量，降低了标签芯片的面积，达到降低芯片成本的目的。本发明有效解决了现有的无源射频标签成本与灵敏度相矛盾的问题，使得标签芯片满足低成本、高性能的市场需求。
如图5所示为本发明第一调制单元电路结构图，所述第一调制单元包括相互串联的第一阈值单元、第二阈值单元、第二N型MOS管NM2，和第七N型MOS管NM7,
所述第一阈值单元输入端连接至所述整流电路输出端，所述第一阈值单元输出端连接至第二阈值单元输入端，所述第二阈值单元输出端连接至第七N型MOS管NM7漏极，第七N型MOS管NM7源极接地，栅极接第一使能信号端enable1，所述第二N型MOS管NM2漏极端连接至所述第二阈值单元的输入端，第二N型MOS管NM2源极端连接至所述第二阈值单元的输出端，所述第二N型MOS管NM2栅极连接至数字信号输出端DATA。
所述第一阈值单元为至少一个二极管，或至少一个P型MOS管，或者是至少一个N型MOS管，
所述至少一个二极管中，任一二极管阴极端与相邻二极管阳极端连接形成串联结构，第一个二极管阳极端连接至整流电路输出端为所述第一阈值单元的输入端，最后一个二极管阴极端连接至第二阈值单元输入端为所述第一阈值单元的输出端；
所述至少一个P型MOS管中，任一P型MOS管漏极端与相邻P型MOS管的源极端连接形成串联结构，各P型MOS管的栅极连接至其漏极，第一个所述P型MOS管的源极连接至整流电路输出端为所述第一阈值单元的输入端，最后一个P型MOS管的漏极连接至第二阈值单元输入端为所述第一阈值单元的输出端；
所述至少一个N型MOS管中，任一N型MOS管源极端与相邻N型MOS管的漏极端连接形成串联结构，各N型MOS管的栅极连接至其漏极，第一个所述N型MOS管的漏极连接至整流电路输出端为所述第一阈值单元的输入端，最后一个N型MOS管的源极连接至第二阈值单元输入端为所述第一阈值单元的输出端。
本实施例第一阈值单元以串联两个P型MOS管为例，如图6所示，第二P型MOS管PM2源极连接至整流电路输出端为所述第一阈值单元的输入端，栅极与漏极相连并连接至第三P型MOS管PM3的源极端，第三P型MOS管PM3的栅极与漏极相连并连接至第二阈值单元输入端作为所述第一阈值单元的输出端。
所述第二阈值单元为至少一个二极管，或至少一个P型MOS管，或者是至少一个N型MOS管，
所述至少一个二极管中，任一二极管阴极端与相邻二极管阳极端连接形成 串联结构，第一个二极管阳极端连接至第一阈值单元输出端为所述第二阈值单元的输入端，最后一个二极管阴极端连接至第七N型MOS管漏极为所述第二阈值单元的输出端；
所述至少一个P型MOS管中，任一P型MOS管漏极端与相邻P型MOS管的源极端连接形成串联结构，各P型MOS管的栅极连接至其漏极，第一个所述P型MOS管的源极连接至第一阈值单元输出端为所述第二阈值单元的输入端，最后一个P型MOS管的漏极连接至第七N型MOS管漏极为所述第二阈值单元的输出端；
所述至少一个N型MOS管中，任一N型MOS管源极端与相邻N型MOS管的漏极端连接形成串联结构，各N型MOS管的栅极连接至其漏极，第一个所述N型MOS管的漏极连接至第一阈值单元输出端为所述第二阈值单元的输入端，最后一个N型MOS管的源极连接至第七N型MOS管漏极为所述第二阈值单元的输出端。
本实施例第二阈值单元以串联两个P型MOS管为例，如图6所示，第五P型MOS管PM5源极连接至第一阈值单元输出端为所述第二阈值单元的输入端，栅极与漏极相连并连接至第六P型MOS管PM6的源极端，第六P型MOS管PM6的栅极与漏极相连并连接至第七N型MOS管NM7漏极作为所述第一阈值单元的输出端。
如图7所示为本发明第二调制单元电路结构图，所述第二调制单元包括第三电阻R3、第四电阻R4，以及第三N型MOS管NM3、第四N型MOS管NM4、第五N型MOS管NM5和第六N型MOS管NM6，
所述第三电阻R3输入端连接至第一天线端ANTA1，输出端连接至第三N 型MOS管NM3的漏极，所述第三N型MOS管NM3的源极连接至第四N型MOS管NM4的漏极，所述第四N型MOS管NM4的源极接地，所述第三N型MOS管NM3栅极连接至数字信号输出端DATA，所述第四N型MOS管NM4栅极连接至第二使能信号端enable2；
所述第四电阻R4输入端连接至第二天线端ANTB1，输出端连接至第五N型MOS管NM5的漏极，所述第五N型MOS管NM5的源极连接至第六N型MOS管NM6的漏极，所述第六N型MOS管NM6的源极接地，所述第五N型MOS管NM5栅极连接至数字信号输出端DATA，所述第六N型MOS管NM6栅极连接至第二使能信号端enable2。
本发明所述第一调制单元与第二调制单元可分别在标签处于强、弱场环境时，交替组合式的对射频标签发送的上行数据信息进行调制，以增加上行数据信息的调制深度，达到读卡器接收端容易地解调射频标签发送的上行数据信息的目的，即，提高了无源射频标签芯片的灵敏度。所述第一调制单元与第二调制单元具体的工作原理为:
当无源射频标签处于强场环境时，整流电路输出端A点电压较高，此时为了对A点电压进行下拉调制而使得射频标签发射端电感线圈两端具有较深的调制深度，数字信号输出端DATA控制第二N型MOS管NM2闭合从而将第二阈值单元短路，同时第一使能信号端enable1控制第七N型MOS管NM7闭合，此时，第一调制单元中只有第一阈值单元接入在电路中，因此，A点电压直接下降了第二阈值单元中单向导通器件数量倍数的阈值电压(n·Vth，其中n为第二阈值单元中单向导通器件的数目),改变了整流电路输出端的电压，即改变了发射端电感线圈两端的电压，实现无源射频标签芯片调制深度的调节。
当无源射频标签处于弱场环境时，整流电路输出端A点电压较低，此时，第一调制单元中由于第一阈值单元与第二阈值单元的阈值特性，导致A点电压达不到第一阈值单元与第二阈值单元中所有单向导通器件的阈值电压Vth之和，因此该第一调制单元处于截止状态，电路中仅有极微弱的电流流动，此种状态下，短接第二阈值单元与否对A点电压几乎没有任何影响，即在弱场环境下该第一调制单元无法实现对无源射频标签芯片调制深度的调节。此时，需要采用第二调制单元进行调制，数字信号输出端DATA控制第三N型MOS管NM3和第五N型MOS管NM5闭合，同时，第二使能信号端enable2控制第四N型MOS管NM4和第六N型MOS管NM6闭合，第三电阻R3和第四电阻R4与地之间形成通路，将第一天线端ANTA1与第二天线端ANTB1之间的电压拉低，实现无源射频标签芯片调制深度的调节。
如上所述，如果仅使用第一调制单元在弱场时无法进行调制，使得标签在弱场时灵敏度差；而相反的，如果仅使用第二调制单元，为了加大在强场时的调制深度，该第三电阻R3和第四电阻R4阻值应设计为较小的数值，但是，该较小阻值的第二调制单元在弱场条件下会造成波谷过低问题，不能满足能量收集的要求，反之，如果考虑弱场条件下的能量收集问题将下拉电阻阻值设计为较大的数值，又会导致标签在强场条件下的下拉程度不明显，使得调制深度不够，即如果仅使用第二调制单元，负载调制用的下拉电阻阻值无法兼顾强弱场两种不同条件下的性能要求，使标签只有在强场或只有在弱场的时候才具有较高的灵敏度，显然这样性能的标签是不具备市场竞争力的。因此，本发明采用第一调制单元与第二调制单元进行交替组合式的调制方式，使标签根据所处的强弱场环境进行自适应的调制，以达到提高标签整体性能的目的。
所述整流电路输出端与负载电路输入端及储能电容C1的正极端之间还连接有单向导通单元，所述单向导通单元的输入端连接至整流电路输出端，单向导通单元的输出端连接至负载电路输入端及储能电容C1的正极端，单向导通单元的第一控制端ctrl1与第二控制端ctrl2分别连接至所述单向导通单元的输出端，如此结构使得所述单向导通单元形成为由整流电路方向向负载电路和储能电容C1方向的单向导通开关。因此在射频场能量为波峰时期，经过整流后的电流可通过该单向导通单元输入至负载电路和储能电容C1，供给负载电路工作，并且储能电容储存电荷；当射频场能量为波谷时期，线圈上的震荡幅度小于整流电路中所有具有单向导通特性的器件的阈值电压(比如正半周时期的二极管D4的阈值电压和单向导通单元阈值电压，或者负半周时期的二极管D3的阈值电压和单向导通单元阈值电压)，此时能量收集停止，射频标签芯片仅仅靠储能电容C1上存储的电荷工作。此时，储能电容C1上的电荷会流动至负载电路，供给负载电路继续工作，而由于单向导通单元处于反向关断状态，电荷无法逆向流动至整流电路和线圈端口，避免了电荷的损失，提高了储能电容C1的储能电荷利用率，即等同于减少了储能电容的使用数量，在保证芯片成本的前提下，实现了标签在远端(或弱场环境下)具有较高灵敏度的目的，解决了现有的无源射频标签成本与灵敏度相矛盾的问题。
图6是本发明所述单向导通单元第一实施例电路图，该实施例中，所述单向导通单元为P型MOS管PM1，所述P型MOS管PM1的源极连接至整流电路输出端，作为所述单向导通单元的输入端，所述P型MOS管PM1的漏极连接至负载电路输入端及储能电容的正极端，作为所述单向导通单元的输出端，所述P 型MOS管PM1的栅极作为单向导通单元的第一控制端ctrl1连接至其漏极，最后，作为本发明技术的关键点，所述P型MOS管PM1的衬底作为单向导通单元的第二控制端ctrl2连接至其漏极。
P型MOS管的传统接法都是将MOS管的衬底接到最高电位，即MOS管的源极，这被称为反向连接。这是因为PMOS管的衬底是N-型掺杂的N-阱区域，在集成度很高的CMOS集成工艺中，为了尽量减少衬底与周围相邻的NMOS管形成寄生的电流正反馈环路而触发不可逆的死锁(Latch-Up)的发生，该N-阱衬底需要接到最高的电压点，以使得衬底形成牢固的反向偏置二极管，杜绝死锁现象。而本专利中，如果该P型MOS管的衬底反向连接，P型MOS管的源极电压会跟着线圈端口电压的降低而降低，储能电容C1的一端对P型MOS管的源极端以及与其相连的衬底端形成正向偏置，储能电容上的电荷会顺着正向偏置流向线圈端口，造成储能电荷的损失，这样周期性的损失影响了***整体的能量收集效率。因此本专利中采取与传统接法相反的结构，避免上述波谷条件下的储能电荷泄露。同时，本技术在本领域中不会造成传统设计所担心的死锁现象，原因包括：
其一，无源射频标签的工作电流基本上都是微安(10-6安培)甚至是纳安(10-9安培)数量级，该数量级的电流实际上不会触发死锁现象；
其二，本设计技术所对应的版图物理设计会有意增加周围的保护环(guard-ring)和有意拉远能够产生寄生正反馈回路的器件与该P型MOS器件的距离，有效地降低了可能形成的反馈回路的增益系数，使其无法达到正反馈的效果。
图8是本发明单向导通单元第二实施例电路图，该实施例中，所述单向导通单元为N型MOS管NM1，所述N型MOS管NM1的漏极连接至整流电路输 出端，作为所述单向导通单元的输入端，所述N型MOS管NM1的源极连接至负载电路输入端及储能电容C1的正极端，作为所述单向导通单元的输出端，所述N型MOS管NM1的栅极作为单向导通单元的第一控制端ctrl1连接至其漏极，最后，作为本发明技术的关键点，所述N型MOS管NM1的衬底作为单向导通单元的第二控制端ctrl2连接至其漏极。
同样原理，如果该N型MOS管NM1按照传统接法将其衬底接到最低电位以避免死锁现象，在波谷的时间段，储能电容C1的正极端，也即N型MOS管NM1的衬底端，会对线圈端口形成正向偏置，电容上的电荷会顺着正向偏置流向线圈端口，造成储能电荷的损失。因此本专利中采取与传统接法相反的结构，避免上述波谷条件下的储能电荷泄露，提高了储能电容的电荷利用率，也即减少储能电容的使用数量以达到降低芯片成本的目的。
同样的，本发明实施例中所采用的开关管，如第一调制单元中的第二N型MOS管NM2，第七N型MOS管NM7，以及第二调制单元中的第三N型MOS管NM3、第四N型MOS管NM4、第五N型MOS管NM5、第六N型MOS管NM6均可以采用P型MOS管来替代，并且相应的，各P型MOS管栅极端的数字控制信号或逻辑控制信号均采用相反的逻辑信号控制。
本发明实施例的另一目的在于提供一种包括上述整流和负载调制组合的射频前端电路的无源射频标签，在整流电路的输出端设置第一调制单元，在第一天线端与第二天线端之间设置有第二调制单元，所述第一调制单元与第二调制单元分别在标签处于强、弱场环境时，通过调制来改变整流电路输出端或射频标签发射端电感线圈两端的电压，实现无源射频标签芯片调制深度的调节，达 到读卡器接收端容易地解调射频标签发送的上行数据信息的目的，即，提高了无源射频标签芯片的灵敏度；同时，整流电路输出端与负载电路输入端及储能电容的正极端之间连接的单向导通单元在射频场能量为波峰时期，可将经过整流后的电流导通输入至负载电路和储能电容，供给负载电路工作，并且储能电容储存电荷；而在射频场能量为波谷时期，储能电容对外放电，由于该单向导通单元处于严格的反向偏置状态，因此电荷无法逆向流动至整流电路和线圈端口，避免了储能电荷的损失，电荷只能输入至负载电路中供给负载电路工作，提高了储能电容的储能电荷利用率，减少储能电容的使用数量，降低了标签芯片的面积，达到降低芯片成本的目的。本发明有效解决了现有的无源射频标签成本与灵敏度相矛盾的问题，使得标签芯片满足低成本、高性能的市场需求。

Claims (8)

  1. 一种整流和负载调制组合的射频前端电路，包括，
    整流电路，所述整流电路输入端连接至第一天线端与第二天线端，输出端连接至负载电路输入端及储能电容的正极端，所述储能电容的负极端接地，其特征在于：
    所述整流电路输出端与地之间连接有第一调制单元，所述第一调制单元用于在射频标签处于强场环境时，通过所要传输的数据作为逻辑控制信号将第二阈值单元短路或者不短路来改变所述整流电路输出端的电压，使得射频标签具有足够的调制深度，实现读卡器接收端容易地解调射频标签发送的上行数据信息的目的；
    所述第一天线端与第二天线端之间连接有第二调制单元，所述第二调制单元用于在射频标签处于弱场环境时，通过所要传输的数据作为逻辑控制信号将下拉电阻接入或者断开来改变射频标签发射端电感线圈两端的电压，使得射频标签具有足够的调制深度，实现读卡器接收端容易地解调射频标签发送的上行数据信息的目的；
    所述整流电路输出端与负载电路输入端及储能电容的正极端之间连接有单向导通单元，所述单向导通单元的输入端连接至整流电路输出端，单向导通单元的输出端连接至负载电路输入端及储能电容的正极端，单向导通单元的第一控制端与第二控制端分别连接至所述单向导通单元的输出端，用于在整流电路与负载电路和储能电容之间形成单向通路，以阻止储能电容的电流回流至整流电路和线圈端口。
  2. 根据权利要求1所述的射频前端电路，其特征在于：所述第一调制单元包括相互串联的第一阈值单元、第二阈值单元、第二N型MOS管，和第七N 型MOS管，
    所述第一阈值单元输入端连接至所述整流电路输出端，所述第一阈值单元输出端连接至第二阈值单元输入端，所述第二阈值单元输出端连接至第七N型MOS管漏极，第七N型MOS管源极接地，栅极接第一使能信号端，所述第二N型MOS管漏极端连接至所述第二阈值单元的输入端，第二N型MOS管源极端连接至所述第二阈值单元的输出端，所述第二N型MOS管栅极连接至数字信号输出端。
  3. 根据权利要求2所述的射频前端电路，其特征在于：所述第一阈值单元为至少一个二极管，或至少一个P型MOS管，或者是至少一个N型MOS管，
    所述至少一个二极管中，任一二极管阴极端与相邻二极管阳极端连接形成串联结构，第一个二极管阳极端连接至整流电路输出端为所述第一阈值单元的输入端，最后一个二极管阴极端连接至第二阈值单元输入端为所述第一阈值单元的输出端；
    所述至少一个P型MOS管中，任一P型MOS管漏极端与相邻P型MOS管的源极端连接形成串联结构，各P型MOS管的栅极连接至其漏极，第一个所述P型MOS管的源极连接至整流电路输出端为所述第一阈值单元的输入端，最后一个P型MOS管的漏极连接至第二阈值单元输入端为所述第一阈值单元的输出端；
    所述至少一个N型MOS管中，任一N型MOS管源极端与相邻N型MOS管的漏极端连接形成串联结构，各N型MOS管的栅极连接至其漏极，第一个所述N型MOS管的漏极连接至整流电路输出端为所述第一阈值单元的输入端，最后一个N型MOS管的源极连接至第二阈值单元输入端为所述第一阈值单元的输 出端。
  4. 根据权利要求2所述的射频前端电路，其特征在于：所述第二阈值单元为至少一个二极管，或至少一个P型MOS管，或者是至少一个N型MOS管，
    所述至少一个二极管中，任一二极管阴极端与相邻二极管阳极端连接形成串联结构，第一个二极管阳极端连接至第一阈值单元输出端为所述第二阈值单元的输入端，最后一个二极管阴极端连接至第七N型MOS管漏极为所述第二阈值单元的输出端；
    所述至少一个P型MOS管中，任一P型MOS管漏极端与相邻P型MOS管的源极端连接形成串联结构，各P型MOS管的栅极连接至其漏极，第一个所述P型MOS管的源极连接至第一阈值单元输出端为所述第二阈值单元的输入端，最后一个P型MOS管的漏极连接至第七N型MOS管漏极为所述第二阈值单元的输出端；
    所述至少一个N型MOS管中，任一N型MOS管源极端与相邻N型MOS管的漏极端连接形成串联结构，各N型MOS管的栅极连接至其漏极，第一个所述N型MOS管的漏极连接至第一阈值单元输出端为所述第二阈值单元的输入端，最后一个N型MOS管的源极连接至第七N型MOS管漏极为所述第二阈值单元的输出端。
  5. 根据权利要求1所述的射频前端电路，其特征在于：所述第二调制单元包括第三电阻、第四电阻，以及第三N型MOS管、第四N型MOS管、第五N型MOS管和第六N型MOS管，
    所述第三电阻输入端连接至第一天线端，输出端连接至第三N型MOS管的漏极，所述第三N型MOS管的源极连接至第四N型MOS管的漏极，所述第四 N型MOS管的源极接地，所述第三N型MOS管栅极连接至数字信号输出端，所述第四N型MOS管栅极连接至第二使能信号端；
    所述第四电阻输入端连接至第二天线端，输出端连接至第五N型MOS管的漏极，所述第五N型MOS管的源极连接至第六N型MOS管的漏极，所述第六N型MOS管的源极接地，所述第五N型MOS管栅极连接至数字信号输出端，所述第六N型MOS管栅极连接至第二使能信号端。
  6. 根据权利要求1所述的射频前端电路，其特征在于，所述单向导通单元为P型MOS管，所述P型MOS管的源极连接至整流电路输出端，作为所述单向导通单元的输入端，所述P型MOS管的漏极连接至负载电路输入端及储能电容的正极端，作为所述单向导通单元的输出端，所述P型MOS管的栅极连接至其漏极，所述P型MOS管的衬底连接至其漏极。
  7. 根据权利要求1所述的射频前端电路，其特征在于，所述单向导通单元为N型MOS管，所述N型MOS管的漏极连接至整流电路输出端，作为所述单向导通单元的输入端，所述N型MOS管的源极连接至负载电路输入端及储能电容的正极端，作为所述单向导通单元的输出端，所述N型MOS管的栅极连接至其漏极，所述N型MOS管的衬底连接至其漏极。
  8. 一种无源射频标签，其特征在于，所述无源射频标签包括如权利要求1-7中任一所述的整流和负载调制组合的射频前端电路。
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CN104834955B (zh) * 2015-04-20 2017-11-14 卓捷创芯科技（深圳）有限公司 一种整流和负载调制组合的射频前端电路和无源射频标签
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