WO2016157935A1 - Method for manufacturing power semiconductor device - Google Patents

Method for manufacturing power semiconductor device Download PDF

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Publication number
WO2016157935A1
WO2016157935A1 PCT/JP2016/051013 JP2016051013W WO2016157935A1 WO 2016157935 A1 WO2016157935 A1 WO 2016157935A1 JP 2016051013 W JP2016051013 W JP 2016051013W WO 2016157935 A1 WO2016157935 A1 WO 2016157935A1
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Prior art keywords
semiconductor substrate
semiconductor device
power semiconductor
concentration
center
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PCT/JP2016/051013
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French (fr)
Japanese (ja)
Inventor
明 清井
政幸 田中
忠玄 湊
政良 多留谷
和豊 高野
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三菱電機株式会社
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Priority to JP2016546111A priority Critical patent/JP6109432B2/en
Publication of WO2016157935A1 publication Critical patent/WO2016157935A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/868—PIN diodes

Definitions

  • the present invention relates to a method for manufacturing a power semiconductor device, and more particularly to a method for manufacturing a power semiconductor device that performs power control and the like.
  • Bipolar power semiconductor devices include IGBTs (Insulated gate Bipolar Transistors), diodes, thyristors, GTOs (Gate Turn-Off Thyristors), and the like.
  • IGBTs Insulated gate Bipolar Transistors
  • diodes diodes
  • thyristors thyristors
  • GTOs Gate Turn-Off Thyristors
  • the carrier recombination lifetime in the drift layer may be shortened. This is because the carriers accumulated in the drift layer at the time of switching can be quickly eliminated by shortening the recombination lifetime.
  • recombination levels such as crystal defects are formed in the drift layer. Conventionally, there are the following two methods for forming a recombination level.
  • Patent Document 1 a metal film such as platinum (Pt) having a relatively large diffusion coefficient is generally formed on a semiconductor substrate, and then the metal such as platinum is diffused into the semiconductor substrate by heating the semiconductor substrate.
  • the metal diffused throughout the semiconductor substrate is replaced with silicon (Si) atoms, whereby recombination levels are formed in the silicon band gap. This recombination level shortens the carrier recombination lifetime.
  • the charged particle beam in this method is an electron beam, a high energy hydrogen ion (proton), or a high energy helium nucleus.
  • This method of irradiating a charged particle beam is disclosed in, for example, Non-Patent Document 1, and lattice defects, composite defects, and impurity defects are formed in the semiconductor substrate by the interaction between the semiconductor substrate and the charged particles.
  • the lattice defect means interstitial silicon, vacancies, and interstitial silicon or vacancies bonded together.
  • a composite defect refers to a combination of impurity atoms present in a semiconductor substrate and lattice defects.
  • an impurity defect means that an electrically neutral impurity present in a semiconductor substrate is electrically activated by irradiation with a charged particle beam.
  • the recombination lifetime of the carriers is shortened by the recombination level due to these defects. This method is disclosed in, for example, Patent Document 3 and Patent Document 4.
  • the power semiconductor is used by using any one of the first method and the second method described above, or by using the first method and the second method in combination.
  • the switching speed of the device is improved.
  • the conventional method for manufacturing a power semiconductor device has a problem that the switching characteristics are not sufficiently stable.
  • that the switching characteristics are stable means that the switching characteristics do not change when the power semiconductor device is energized for a long time.
  • the present invention has been made as part of its development, and an object of the present invention is to provide a method of manufacturing a power semiconductor device capable of obtaining stable switching characteristics.
  • the method for manufacturing a power semiconductor device includes the following steps.
  • the silicon having a region having a carbon concentration of 1 ⁇ 10 14 cm ⁇ 3 or more and 1 ⁇ 10 16 cm ⁇ 3 or less and an oxygen concentration of 1 ⁇ 10 16 cm ⁇ 3 or more and 2 ⁇ 10 18 cm ⁇ 3 or less.
  • a power semiconductor device is formed on a semiconductor substrate.
  • the semiconductor substrate is irradiated with an electron beam.
  • the semiconductor substrate is heat-treated under a temperature condition of 250 ° C. or higher and 400 ° C. or lower.
  • the semiconductor substrate has the prescribed carbon concentration and oxygen concentration, respectively, thereby eliminating defects with low heat resistance and high heat resistance.
  • the C center can be efficiently left. As a result, the switching speed can be improved and the switching characteristics can be stabilized.
  • FIG. 10 is a cross-sectional view showing a step of a method for manufacturing the power semiconductor device in the embodiment.
  • FIG. 3 is a cross-sectional view showing a step performed after the step shown in FIG. 2 in the same embodiment.
  • FIG. 4 is a cross-sectional view showing a step performed after the step shown in FIG. 3 in the same embodiment.
  • FIG. 5 is a cross-sectional view showing a step performed after the step shown in FIG. 4 in the same embodiment.
  • FIG. 6 is a cross-sectional view showing a step performed after the step shown in FIG. 5 in the same embodiment.
  • it is a graph which shows the evaluation result of the relation between the oxygen concentration in a semiconductor substrate, and the concentration of C center. In the same embodiment, it is a graph which shows the evaluation result of the relationship between the oxygen concentration in a semiconductor substrate, and the density
  • FIG. 4 is a graph showing a relationship between a thickness direction of a semiconductor substrate and an oxygen concentration and a relationship between a thickness direction of the semiconductor substrate and a C center concentration in the same embodiment.
  • FIG. 4 is a cross-sectional view of a power semiconductor device in which a diode is formed as the power semiconductor device in the embodiment.
  • a power semiconductor device in this specification is a semiconductor device (power semiconductor device) that controls or supplies power. For example, convert AC to DC, reduce voltage to 5V or 3V, drive motor, charge battery, operate microcomputer (Central processing Unit) or LSI (Large Scale Integrated circuit), etc.
  • the semiconductor device used for this purpose is not a microcomputer or an LSI used for a memory or the like.
  • a semiconductor substrate used for a power semiconductor device contains carbon and oxygen as impurities, and it is necessary to set the carbon concentration and the oxygen concentration to specified values, respectively.
  • carbon does not have an appropriate diffusion source in the treatment after crystal growth of the semiconductor substrate. Therefore, here, when the semiconductor substrate is crystal-grown, a semiconductor substrate containing a prescribed concentration of carbon is used by controlling the growth atmosphere.
  • a silicon semiconductor substrate (silicon wafer) grown by an FZ (Floating-Zone) method is used as the crystal growth method.
  • a silicon semiconductor substrate is a semiconductor substrate containing silicon as a main component, and this semiconductor substrate contains a predetermined impurity or the like that defines a conductivity type.
  • oxygen is added to a semiconductor substrate that has been previously containing carbon.
  • oxygen is diffused into the semiconductor substrate.
  • a power semiconductor device such as an IGBT is formed on the semiconductor substrate.
  • defects are formed in the semiconductor substrate by irradiating the semiconductor substrate with an electron beam.
  • the semiconductor substrate is subjected to a heat treatment to eliminate a part of the defects or to inactivate the defects.
  • FIG. 2 corresponds to the first step S1.
  • a silicon oxide film 2 is formed on the surface of the semiconductor substrate 1 by subjecting the semiconductor substrate 1 to heat treatment (about 1100 ° C.) in an air atmosphere.
  • heat treatment (about 1100 ° C.) is performed on the semiconductor substrate 1 on which the silicon oxide film 2 is formed in a nitrogen atmosphere, thereby diffusing oxygen 3 in the silicon oxide film 2 into the semiconductor substrate 1.
  • the heat treatment is controlled so that the concentration of oxygen in the semiconductor substrate 1 is 1 ⁇ 10 16 cm ⁇ 3 or more and 2 ⁇ 10 18 cm ⁇ 3 or less.
  • FIGS. 3, 4 and 5 correspond to the second step S2.
  • an IGBT is taken as an example of a power semiconductor device and its manufacturing process will be described.
  • p + body regions 5 are formed on one surface side by diffusing p-type impurities such as boron from one surface and the other surface of the semiconductor substrate 1, respectively.
  • a p + collector region 4 is formed on the surface side of the substrate. At this time, the region of the semiconductor substrate 1 sandwiched between the p + collector region 4 and the p + body region 5 becomes the n ⁇ drift layer 6.
  • a resist mask (not shown) is formed on one surface side of the semiconductor substrate 1, and the semiconductor substrate 1 is dry-etched using the resist mask as an etching mask, as shown in FIG. Then, the trench groove 7 is formed. Thereafter, the resist mask is removed.
  • another resist mask (not shown) is formed on one surface side of the semiconductor substrate 1, and the resist mask is used as an etching mask, for example, n-type impurities such as phosphorus are formed on the side of the trench groove 7.
  • the n + emitter region 10 is formed by selective diffusion and heat treatment. Thereafter, the other resist mask is removed.
  • the gate oxide film 8 is formed by selectively oxidizing the bottom and side walls of the trench groove 7.
  • a gate electrode 9 is formed on the gate oxide film 8 by a physical film formation method such as sputtering.
  • an emitter electrode 11 is formed so as to be in contact with the n + emitter region 10 by a physical film formation method such as sputtering.
  • a field insulating film 12 is formed on the entire surface of one surface of the semiconductor substrate 1 so as to cover the emitter electrode 11.
  • the collector electrode 13 is formed so as to be in contact with the p + collector region 4 by using a physical film formation method such as sputtering.
  • an IGBT 21 is formed on the semiconductor substrate 1 as an example of the power semiconductor device 20.
  • a general IGBT manufacturing process has been described as an example.
  • a manufacturing method for example, an ion implantation method may be used instead of the diffusion method.
  • a vapor deposition method may be used instead of the sputtering method, and the method for manufacturing the IGBT is not limited to the method described above.
  • FIG. 6 corresponds to the third step S3.
  • the electron beam 14 is irradiated to one surface side of the semiconductor substrate 1.
  • the incident energy is about 250 keV to 3 MeV
  • the irradiation amount is about 1 ⁇ 10 13 cm ⁇ 2 to 1 ⁇ 10 15 cm ⁇ 2 .
  • incident energy and irradiation amount are changed according to the standard (switching speed, on-resistance) of the target power semiconductor device.
  • the values of the incident energy and the irradiation amount of the electron beam are set high.
  • the range of the incident energy of the electron beam is limited by the depth dependency of the absorbed dose of the electron beam with respect to silicon (semiconductor substrate). That is, the upper limit value and the lower limit value of the incident energy are set in order to reduce the difference in the amount of absorption of the electron beam between the front surface and the back surface of the semiconductor substrate.
  • the temperature rise of the sample (semiconductor substrate, etc.) when irradiated with the electron beam is about several tens of degrees Celsius. For this reason, it is not particularly necessary to control the temperature of the sample when irradiating the electron beam. For example, a process of irradiating at room temperature may be performed.
  • a process of irradiating at room temperature may be performed.
  • lattice defects, composite defects, and impurity defects are generated in the semiconductor substrate 1.
  • a composite defect for example, an E center that is attributed to a vacancy-group V element pair is generated.
  • the impurity defect for example, a G center attributed to a carbon-carbon pair or a C center attributed to an oxygen-carbon pair is generated.
  • the E center recombination level is Ec ⁇ 0.43 eV
  • the G center recombination level is Ev + 0.17 eV
  • the C center recombination level is Ev + 0.33 eV.
  • Ec is the energy at the lower end of the conduction band
  • Ev is the energy at the upper end of the valence band.
  • Defects generated in the semiconductor substrate have the effect of shortening the recombination lifetime of carriers, and in particular, in the band gap (1.11 eV) of silicon (semiconductor substrate), a defect level is formed near the center of the band gap. It is said that the defects possessed have a high effect of shortening the recombination lifetime of the carriers.
  • the C center is preferable to the G center as a defect.
  • the E center is not desirable because it has a level close to the mid gap of silicon and causes reverse bias leakage. Therefore, in the power semiconductor device according to the embodiment, the C center is positively used as a defect in order to shorten the recombination lifetime of the carriers accumulated in the drift layer.
  • lattice defects or composite defects remain in the semiconductor substrate 1. These defects are low in heat resistance and disappear due to current or heat generated when the power semiconductor device is energized with a high current density. For example, characteristics when a power semiconductor device is energized for a long time with a high current density. Will change.
  • the semiconductor substrate 1 is subjected to heat treatment for several hours at a temperature of 250 ° C. or higher and 400 ° C. or lower, preferably 300 ° C. or higher and 400 ° C. or lower. It has been found that the majority of complex defects can be extinguished or made electrically inactive.
  • the time for performing the heat treatment depends on the impurity concentration in the semiconductor substrate and the dose of the electron beam irradiated on the semiconductor substrate. For example, when the impurity concentration is high, impurity defects are easily formed, and lattice defects or composite defects are reduced. Therefore, the heat treatment time is set short. On the other hand, when the electron beam irradiation amount is large, the number of lattice defects or composite defects increases, so the heat treatment time is set longer.
  • the heat treatment is preferably performed in an inert gas such as nitrogen in order to suppress oxidation of the electrode material of the power semiconductor device.
  • the carriers accumulated in the drift layer in the power semiconductor device can be obtained by efficiently remaining the C center.
  • the recombination lifetime can be shortened, and the speed of the power semiconductor device can be increased.
  • the first effect is that a high generation efficiency of the C center can be obtained.
  • the C center is more effective in reducing the lifetime by recombining the carriers as compared with the G center. Therefore, it is desired to increase the generation efficiency of the C center.
  • the generation efficiency is the ratio of the C center to the electron beam irradiation dose, and means to increase this ratio. By increasing the generation efficiency, the amount of electron beam irradiation can be reduced, which can contribute to simplification of the manufacturing process.
  • the inventors evaluated the relationship between the C center concentration and the oxygen concentration in the semiconductor substrate, and the relationship between the G center concentration and the oxygen concentration in the semiconductor substrate, respectively. The evaluation will be described.
  • the carbon concentration is set to a substantially constant concentration (about 3 ⁇ 10 14 cm ⁇ 3 to 9 ⁇ 10 14 cm ⁇ 3 ), and the oxygen concentration is set to 1 ⁇ 10 15 cm ⁇ 3 to 1 ⁇ 10 17 cm.
  • a semiconductor substrate distributed within a range of about ⁇ 3 was used.
  • the semiconductor substrate was irradiated with an electron beam under irradiation conditions of an irradiation energy of 750 keV and an irradiation amount of 1 ⁇ 10 14 cm ⁇ 2, and the C center concentration and the G center concentration in each semiconductor substrate.
  • PL Photoluminescence
  • FIG. 7 shows the relationship between the C center concentration and the oxygen concentration in the semiconductor substrate.
  • FIG. 8 shows the relationship between the concentration of the G center and the oxygen concentration in the semiconductor substrate.
  • FIG. 7 it can be seen that the higher the oxygen concentration in the semiconductor substrate is, the higher the concentration of the C center is, and the generation of the C center is promoted.
  • FIG. 8 it can be seen that the higher the oxygen concentration in the semiconductor substrate, the lower the concentration of the G center, and the generation of the G center is suppressed. From this, it was found that impurity defects (G center and C center) can be controlled by defining the carbon concentration and the oxygen concentration in the semiconductor substrate.
  • the higher the oxygen concentration in the semiconductor substrate the better.
  • the oxygen concentration is It has been found that it is desirable to specify 2 ⁇ 10 18 cm ⁇ 3 (upper limit) or less.
  • the carbon concentration is excessively small, the C center is not generated in the semiconductor substrate. Therefore, in order to surely generate the C center, it is desirable to define the carbon concentration to be 1 ⁇ 10 14 cm ⁇ 3 or more. all right.
  • the upper limit value of the carbon concentration is preferably 1 ⁇ 10 16 cm ⁇ 3 . If the carbon concentration exceeds this upper limit, the generation of the G center is promoted more than the C center. Therefore, it was found that the carbon concentration range is preferably specified to be 1 ⁇ 10 14 cm ⁇ 3 or more and 1 ⁇ 10 16 cm ⁇ 3 or less.
  • the second effect is that the heat resistance of the C center can be increased.
  • the inventors further evaluated the relationship between the C center concentration and the heat treatment temperature (annealing temperature). The evaluation will be described. First, as in the evaluation described above, a semiconductor substrate having a substantially constant carbon concentration and an oxygen concentration distributed within a predetermined range is used as the semiconductor substrate, and the semiconductor substrate is subjected to predetermined irradiation conditions. And irradiated with an electron beam. The semiconductor substrate was subjected to a heat treatment for 20 minutes by distributing the temperature (maximum temperature to 500 ° C.) in the air atmosphere, and the concentration of C center in each semiconductor substrate was measured by the PL method.
  • FIG. 9 shows the relationship between the C center concentration and the annealing temperature.
  • FIG. 10 shows the relationship between the concentration of the G center and the annealing temperature.
  • FIG. 9 it can be seen that when the heat treatment at about 250 ° C. is performed, the concentration of the C center does not decrease in any of the semiconductor substrates. It can also be seen that the semiconductor substrate with a higher oxygen concentration is less likely to decrease the C center concentration even by heat treatment at a higher temperature. This means that the thermal resistance of the C center can be improved by defining the impurity concentration in the semiconductor substrate.
  • By increasing the heat resistance of the C center it is possible to suppress changes during energization of the semiconductor device, set the temperature of the heat treatment in the fourth step high, and eliminate unnecessary defects in a short time.
  • the lower limit value of the oxygen concentration in the semiconductor substrate capable of exhibiting this effect is defined as 1 ⁇ 10 16 cm ⁇ 3 . Therefore, the oxygen concentration in the semiconductor substrate is specified to be 1 ⁇ 10 16 cm ⁇ 3 or more and 2 ⁇ 10 18 cm ⁇ 3 or less together with the upper limit of the oxygen concentration described above.
  • the rate of change is defined as follows. First, let the collector-emitter voltage value be A (initial value) when the inspection gate voltage and emitter voltage flow, respectively, and then load test gate-emitter voltage and collector current flow respectively. When the collector-emitter voltage value is B, the rate of change is represented by (BA) / A.
  • the stability of the switching characteristics was indirectly evaluated using this rate of change. That is, the smaller the rate of change of the saturated emitter-collector voltage, the more stable the power semiconductor device.
  • oxygen has a small diffusion coefficient, so that nonuniformity or non-reproduction of the oxygen concentration in the semiconductor substrate surface is unlikely to occur. Moreover, since the defect is formed by irradiating with an electron beam, the recombination lifetime can be controlled with high accuracy. Further, among lattice defects, composite defects and impurity defects caused by electron beam irradiation, impurity defects having high heat resistance are left to remain, and the remaining lattice defects or composite defects are extinguished or electrically inactive. Can be in a state.
  • the C center has higher heat resistance than lattice defects or composite defects. Furthermore, the heat resistance of the C center is improved when the semiconductor substrate having the above-described oxygen concentration and carbon concentration is used as compared with the case where a semiconductor substrate having a low impurity concentration applied to a normal power semiconductor device is used. I found out that
  • a silicon semiconductor substrate grown by the CZ (Czochralski) method or the MCZ (Magnetic-Field Applied Czochralski) method may be used.
  • CZ Czochralski
  • MCZ Magnetic-Field Applied Czochralski
  • a supplementary description will be given of the difference between a semiconductor substrate grown by the FZ method and a semiconductor substrate grown by the CZ method or the MCZ method.
  • the oxygen concentration distribution decreases as the distance from the diffusion surface increases.
  • the oxygen concentration changes from about 2 ⁇ 10 18 cm ⁇ 3 to about 1 ⁇ 10 15 cm ⁇ 3 at maximum.
  • the change in the thickness direction of the semiconductor substrate is less than about 10%. Become. The result is shown in the upper graph of FIG.
  • the change of the carbon concentration in the thickness direction of the semiconductor substrate is within about 10% for both the semiconductor substrate grown by the FZ method and the semiconductor substrate grown by the CZ method or MCZ method.
  • the C center concentration has almost the same concentration distribution as the oxygen concentration. The result is shown in the lower graph of FIG.
  • the concentration distribution of the C center in the thickness direction of the semiconductor substrate differs between the semiconductor substrate grown by the FZ method and the semiconductor substrate grown by the CZ method or the MCZ method.
  • the loss during switching be small. That is, it is desirable that the switching speed is fast.
  • the switching speed is faster when the C center is distributed over the entire area (thickness direction) of the semiconductor substrate. Therefore, the manufacturing method shown in FIG. 12 using a semiconductor substrate grown by the CZ method or the MCZ method is desirable.
  • the manufacturing method shown in FIG. 1 using a semiconductor substrate grown by the FZ method is desirable.
  • the first modification by using a semiconductor substrate grown by the CZ method or the MCZ method, a power semiconductor device having stable switching characteristics can be manufactured, and the first step is omitted as a manufacturing process. Can contribute to the reduction of the manufacturing process.
  • the power semiconductor device is not limited to the IGBT, and a diode may be formed in addition to the IGBT as shown in FIG.
  • the second step S2 simply replaces the step of forming the IGBT with the step of forming the diode.
  • the diode formed in this way is shown in FIG.
  • a p + layer 34, an n ⁇ drift layer 35 and an n + layer 36 are formed on a semiconductor substrate 31.
  • an anode electrode 32 and a field insulating film 33 are formed so as to be in contact with the p + layer 34.
  • a cathode electrode 37 is formed so as to be in contact with the n + layer 36.
  • This diode 30 can also be stabilized while increasing the switching characteristics as in the case of the IGBT.
  • a power semiconductor device such as a thyristor or GTO may be formed.
  • the present invention is effectively used in a method of manufacturing a power semiconductor device such as an IGBT that performs power control and the like.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Thyristors (AREA)

Abstract

Firstly, in a first step (S1), a semiconductor substrate having a carbon concentration not lower than 1×1014 cm-3 but not higher than 1×1016 cm-3, and an oxygen concentration not lower than 1×1016 cm-3 but not higher than 2×1018 cm-3 is formed. Then, in a second step (S2), for instance, an IGBT is formed on the semiconductor substrate. Then, in a third step (S3), the semiconductor substrate is irradiated with an electron beam. Then, in a fourth step (S4), the semiconductor substrate is subjected to heat treatment under the temperature conditions of 250-400°C.

Description

電力用半導体装置の製造方法Method for manufacturing power semiconductor device
　本発明は、電力用半導体装置の製造方法に関し、特に、電力の制御等を行う電力用半導体装置の製造方法に関するものである。 The present invention relates to a method for manufacturing a power semiconductor device, and more particularly to a method for manufacturing a power semiconductor device that performs power control and the like.
　バイポーラ型の電力半導体装置には、ＩＧＢＴ（Insulated　gate　Bipolar　Transistor）、ダイオード、サイリスタ、ＧＴＯ（Gate　Turn-Off　Thyristor）等がある。このような電力用半導体装置のスイッチング特性を高速化するために、ドリフト層内のキャリアの再結合寿命を短縮することがある。これは、再結合寿命を短縮することで、スイッチング時にドリフト層内に蓄積したキャリアを早く消滅させることができるからである。再結合寿命を短縮させるために、ドリフト層内には、たとえば、結晶欠陥等の再結合準位が形成される。従来、再結合準位を形成する方法としては、次の２つの方法がある。 Bipolar power semiconductor devices include IGBTs (Insulated gate Bipolar Transistors), diodes, thyristors, GTOs (Gate Turn-Off Thyristors), and the like. In order to increase the switching characteristics of such a power semiconductor device, the carrier recombination lifetime in the drift layer may be shortened. This is because the carriers accumulated in the drift layer at the time of switching can be quickly eliminated by shortening the recombination lifetime. In order to shorten the recombination lifetime, for example, recombination levels such as crystal defects are formed in the drift layer. Conventionally, there are the following two methods for forming a recombination level.
　まず、第１の方法として、不純物を半導体基板内に拡散させる方法がある。この方法は、たとえば、特許文献１および特許文献２に開示されている。この方法では、通常、拡散係数が比較的大きい白金（Ｐｔ）等の金属膜を半導体基板に形成した後、半導体基板を加熱することによって、白金等の金属を半導体基板に拡散させる。半導体基板の全体に拡散した金属は、シリコン（Ｓｉ）原子と置換することで、シリコンのバンドギャップ内に再結合準位が形成される。この再結合準位によって、キャリアの再結合寿命が短縮されることになる。 First, as a first method, there is a method of diffusing impurities in a semiconductor substrate. This method is disclosed in Patent Document 1 and Patent Document 2, for example. In this method, a metal film such as platinum (Pt) having a relatively large diffusion coefficient is generally formed on a semiconductor substrate, and then the metal such as platinum is diffused into the semiconductor substrate by heating the semiconductor substrate. The metal diffused throughout the semiconductor substrate is replaced with silicon (Si) atoms, whereby recombination levels are formed in the silicon band gap. This recombination level shortens the carrier recombination lifetime.
　第２の方法として、半導体基板に高エネルギの荷電粒子線を照射する方法がある。この方法における荷電粒子線とは、電子線、高エネルギの水素イオン（プロトン）または高エネルギのヘリウム原子核である。この荷電粒子線を照射する方法は、たとえば、非特許文献１に開示されており、半導体基板と荷電粒子の相互作業によって、半導体基板中に格子欠陥、複合欠陥、不純物欠陥が形成される。 As a second method, there is a method of irradiating a semiconductor substrate with a high energy charged particle beam. The charged particle beam in this method is an electron beam, a high energy hydrogen ion (proton), or a high energy helium nucleus. This method of irradiating a charged particle beam is disclosed in, for example, Non-Patent Document 1, and lattice defects, composite defects, and impurity defects are formed in the semiconductor substrate by the interaction between the semiconductor substrate and the charged particles.
　この場合における格子欠陥とは、格子間シリコン、空孔、および、格子間シリコン同士または空孔同士が結合したもののことをいう。また、複合欠陥とは、半導体基板内に存在する不純物原子と格子欠陥とが結びついたもののことをいう。一方、不純物欠陥とは、半導体基板内に存在する電気的に中性な不純物が、荷電粒子線の照射によって電気的に活性になったもののことをいう。第２の方法では、これらの欠陥による再結合準位によって、キャリアの再結合寿命が短縮される。この方法は、たとえば、特許文献３および特許文献４に開示されている。 In this case, the lattice defect means interstitial silicon, vacancies, and interstitial silicon or vacancies bonded together. In addition, a composite defect refers to a combination of impurity atoms present in a semiconductor substrate and lattice defects. On the other hand, an impurity defect means that an electrically neutral impurity present in a semiconductor substrate is electrically activated by irradiation with a charged particle beam. In the second method, the recombination lifetime of the carriers is shortened by the recombination level due to these defects. This method is disclosed in, for example, Patent Document 3 and Patent Document 4.
　バイポーラ型の電力用半導体装置では、上述した第１の方法および第２の方法のいずれかの方法を用いるか、または、第１の方法と第２の方法とを併用することによって、電力用半導体装置のスイッチング速度の向上が図られている。 In the bipolar type power semiconductor device, the power semiconductor is used by using any one of the first method and the second method described above, or by using the first method and the second method in combination. The switching speed of the device is improved.
特開平０２－０５１２３５号公報Japanese Patent Laid-Open No. 02-051235 特開昭６２－１１３４３２号公報Japanese Patent Laid-Open No. 62-113432 特開平１１－１３５５０９号公報JP-A-11-135509 特開昭６０－１３３７３３号公報JP 60-133733 A
　電力用半導体装置では、スイッチング速度を向上させることに加えて、そのスイッチング特性を安定させることが求められている。従来の電力用半導体装置の製造方法では、スイッチング特性が十分に安定していないという問題があった。ここで、スイッチング特性が安定しているとは、電力用半導体装置に長時間にわたり通電した際に、スイッチング特性が変化しないことを意味する。 In power semiconductor devices, in addition to improving the switching speed, it is required to stabilize the switching characteristics. The conventional method for manufacturing a power semiconductor device has a problem that the switching characteristics are not sufficiently stable. Here, that the switching characteristics are stable means that the switching characteristics do not change when the power semiconductor device is energized for a long time.
　本発明は、その開発の一環としてなされたものであり、その目的は、安定したスイッチング特性が得られる電力半導体装置の製造方法を提供することである。 The present invention has been made as part of its development, and an object of the present invention is to provide a method of manufacturing a power semiconductor device capable of obtaining stable switching characteristics.
　本発明に係る電力用半導体装置の製造方法は、以下の工程を備えている。炭素濃度が１×１０１４ｃｍ－３以上、１×１０１６ｃｍ－３以下であり、酸素濃度が１×１０１６ｃｍ－３以上、２×１０１８ｃｍ－３以下である領域を有するシリコンの半導体基板に、電力用半導体装置を形成する。半導体基板に電子線を照射する。半導体基板に、２５０℃以上、４００℃以下の温度条件のもとで熱処理を行う。 The method for manufacturing a power semiconductor device according to the present invention includes the following steps. The silicon having a region having a carbon concentration of 1 × 10 14 cm −3 or more and 1 × 10 16 cm −3 or less and an oxygen concentration of 1 × 10 16 cm −3 or more and 2 × 10 18 cm −3 or less. A power semiconductor device is formed on a semiconductor substrate. The semiconductor substrate is irradiated with an electron beam. The semiconductor substrate is heat-treated under a temperature condition of 250 ° C. or higher and 400 ° C. or lower.
　本発明に係る電力用半導体装置の製造方法によれば、半導体基板が、それぞれ規定される炭素濃度および酸素濃度を有していることで、熱耐性の低い欠陥を消滅させて、熱耐性の高いＣセンタを効率的に残すことができる。その結果、スイッチング速度を向上させるとともに、そのスイッチング特性を安定させることができる。 According to the method for manufacturing a power semiconductor device of the present invention, the semiconductor substrate has the prescribed carbon concentration and oxygen concentration, respectively, thereby eliminating defects with low heat resistance and high heat resistance. The C center can be efficiently left. As a result, the switching speed can be improved and the switching characteristics can be stabilized.
本発明の実施の形態に係る電力用半導体装置の製造フローの一例を示す図である。It is a figure which shows an example of the manufacturing flow of the power semiconductor device which concerns on embodiment of this invention. 同実施の形態において、電力用半導体装置の製造方法の一工程を示す断面図である。FIG. 10 is a cross-sectional view showing a step of a method for manufacturing the power semiconductor device in the embodiment. 同実施の形態において、図２に示す工程の後に行われる工程を示す断面図である。FIG. 3 is a cross-sectional view showing a step performed after the step shown in FIG. 2 in the same embodiment. 同実施の形態において、図３に示す工程の後に行われる工程を示す断面図である。FIG. 4 is a cross-sectional view showing a step performed after the step shown in FIG. 3 in the same embodiment. 同実施の形態において、図４に示す工程の後に行われる工程を示す断面図である。FIG. 5 is a cross-sectional view showing a step performed after the step shown in FIG. 4 in the same embodiment. 同実施の形態において、図５に示す工程の後に行われる工程を示す断面図である。FIG. 6 is a cross-sectional view showing a step performed after the step shown in FIG. 5 in the same embodiment. 同実施の形態において、半導体基板中の酸素濃度と、Ｃセンタの濃度との関係の評価結果を示すグラフである。In the same embodiment, it is a graph which shows the evaluation result of the relation between the oxygen concentration in a semiconductor substrate, and the concentration of C center. 同実施の形態において、半導体基板中の酸素濃度と、Ｇセンタの濃度との関係の評価結果を示すグラフである。In the same embodiment, it is a graph which shows the evaluation result of the relationship between the oxygen concentration in a semiconductor substrate, and the density | concentration of G center. 同実施の形態において、アニール温度と、Ｃセンタの濃度との関係の評価結果を示すグラフである。In the same embodiment, it is a graph which shows the evaluation result of the relationship between annealing temperature and the density | concentration of C center. 同実施の形態において、アニール温度と、Ｇセンタの濃度との関係の評価結果を示すグラフである。In the same embodiment, it is a graph which shows the evaluation result of the relationship between annealing temperature and the density | concentration of G center. 同実施の形態において、半導体基板中の酸素濃度と、飽和エミッタ－コレクタ間の電圧の変化率との関係を示すグラフである。4 is a graph showing the relationship between the oxygen concentration in a semiconductor substrate and the rate of change in voltage between a saturated emitter and a collector in the same embodiment. 同実施の形態において、第１変形例に係る製造フローを示す図である。In the same embodiment, it is a figure which shows the manufacturing flow which concerns on a 1st modification. 同実施の形態において、半導体基板の厚さ方向と酸素濃度との関係と、半導体基板の厚さ方向とＣセンタ濃度との関係とをそれぞれ示すグラフである。4 is a graph showing a relationship between a thickness direction of a semiconductor substrate and an oxygen concentration and a relationship between a thickness direction of the semiconductor substrate and a C center concentration in the same embodiment. 同実施の形態において、第２変形例に係る製造フローの一部を示す図である。In the same embodiment, it is a figure which shows a part of manufacturing flow which concerns on a 2nd modification. 同実施の形態において、電力用半導体装置として、ダイオードが形成された電力用半導体装置の断面図である。4 is a cross-sectional view of a power semiconductor device in which a diode is formed as the power semiconductor device in the embodiment. FIG.
　実施の形態
　この明細書でいう電力用半導体装置とは、電力の制御または供給を行う半導体装置（電力用半導体装置）である。たとえば、交流を直流に変換する、電圧を５Ｖまたは３Ｖに降圧する等して、モータを駆動させる、バッテリに充電する、マイコン（Central　processing　Unit）またはＬＳＩ（Large　Scale　Integrated　circuit）を動作させる等のために用いられる半導体装置をいい、マイコンそのもの、または、メモリ等に用いられるＬＳＩそのものではない。 Embodiments A power semiconductor device in this specification is a semiconductor device (power semiconductor device) that controls or supplies power. For example, convert AC to DC, reduce voltage to 5V or 3V, drive motor, charge battery, operate microcomputer (Central processing Unit) or LSI (Large Scale Integrated circuit), etc. The semiconductor device used for this purpose is not a microcomputer or an LSI used for a memory or the like.
　はじめに、実施の形態に係る電力用半導体装置の製造方法の基本フローについて、図１に基づいて説明する。 First, a basic flow of a method for manufacturing a power semiconductor device according to an embodiment will be described with reference to FIG.
　まず、電力用半導体装置に使用する半導体基板は、不純物として、炭素と酸素とを含有し、その炭素濃度と酸素濃度とを、それぞれ規定の値に設定する必要がある。これらの不純物のうち、炭素については、半導体基板を結晶成長させた後の処理では、適当な拡散源がない。そこで、ここでは、半導体基板を結晶成長させる際に、成長雰囲気を制御することによって、規定の濃度の炭素を含有させた半導体基板を用いる。具体的には、結晶成長法として、ＦＺ（Floating-Zone）法によって成長させたシリコンの半導体基板（シリコンウェハ）を用いる。なお、シリコンの半導体基板は、シリコンを主成分とする半導体基板であり、この半導体基板は、導電型を規定する所定の不純物等を含有する。 First, a semiconductor substrate used for a power semiconductor device contains carbon and oxygen as impurities, and it is necessary to set the carbon concentration and the oxygen concentration to specified values, respectively. Among these impurities, carbon does not have an appropriate diffusion source in the treatment after crystal growth of the semiconductor substrate. Therefore, here, when the semiconductor substrate is crystal-grown, a semiconductor substrate containing a prescribed concentration of carbon is used by controlling the growth atmosphere. Specifically, a silicon semiconductor substrate (silicon wafer) grown by an FZ (Floating-Zone) method is used as the crystal growth method. Note that a silicon semiconductor substrate is a semiconductor substrate containing silicon as a main component, and this semiconductor substrate contains a predetermined impurity or the like that defines a conductivity type.
　次に、あらかじめ炭素を含有させた半導体基板に酸素を含有させる。図１に示すように、第１工程Ｓ１では、半導体基板内に酸素を拡散させる。次に、第２工程Ｓ２では、半導体基板に、たとえば、ＩＧＢＴ等の電力用半導体装置を形成する。次に、第３工程Ｓ３では、半導体基板に電子線を照射することによって、半導体基板内に欠陥を形成する。次に、第４工程Ｓ４では、半導体基板に熱処理を行うことによって、欠陥の一部を消滅させるか、または、欠陥を不活性化する。 Next, oxygen is added to a semiconductor substrate that has been previously containing carbon. As shown in FIG. 1, in the first step S1, oxygen is diffused into the semiconductor substrate. Next, in the second step S2, a power semiconductor device such as an IGBT is formed on the semiconductor substrate. Next, in a third step S3, defects are formed in the semiconductor substrate by irradiating the semiconductor substrate with an electron beam. Next, in the fourth step S4, the semiconductor substrate is subjected to a heat treatment to eliminate a part of the defects or to inactivate the defects.
　次に、各工程について詳しく説明する。図２は、第１工程Ｓ１に対応する。図２に示すように、まず、大気雰囲気中において、半導体基板１に熱処理（約１１００℃）を施すことにより、半導体基板１の表面にシリコン酸化膜２を形成する。次に、窒素雰囲気中において、シリコン酸化膜２が形成された半導体基板１に熱処理（約１１００℃）を施すことにより、シリコン酸化膜２中の酸素３を、半導体基板１内に拡散させる。このとき、半導体基板１中の酸素の濃度が、１×１０１６ｃｍ－３以上２×１０１８ｃｍ－３以下になるように熱処理を制御する。 Next, each step will be described in detail. FIG. 2 corresponds to the first step S1. As shown in FIG. 2, first, a silicon oxide film 2 is formed on the surface of the semiconductor substrate 1 by subjecting the semiconductor substrate 1 to heat treatment (about 1100 ° C.) in an air atmosphere. Next, heat treatment (about 1100 ° C.) is performed on the semiconductor substrate 1 on which the silicon oxide film 2 is formed in a nitrogen atmosphere, thereby diffusing oxygen 3 in the silicon oxide film 2 into the semiconductor substrate 1. At this time, the heat treatment is controlled so that the concentration of oxygen in the semiconductor substrate 1 is 1 × 10 16 cm −3 or more and 2 × 10 18 cm −3 or less.
　次に、図３、図４および図５は、第２工程Ｓ２に対応する。ここでは、電力用半導体装置としてＩＧＢＴを例に挙げて、その製造工程について説明する。図３に示すように、たとえば、ボロン等のｐ型不純物を半導体基板１の一方の表面と他方の表面とからそれぞれ拡散させることにより、一方の表面の側にｐ＋ボディ領域５を形成し、他方の表面の側にｐ＋コレクタ領域４を形成する。このとき、ｐ＋コレクタ領域４とｐ＋ボディ領域５とによって挟まれた半導体基板１の領域がｎ－ドリフト層６となる。 Next, FIGS. 3, 4 and 5 correspond to the second step S2. Here, an IGBT is taken as an example of a power semiconductor device and its manufacturing process will be described. As shown in FIG. 3, for example, p + body regions 5 are formed on one surface side by diffusing p-type impurities such as boron from one surface and the other surface of the semiconductor substrate 1, respectively. A p + collector region 4 is formed on the surface side of the substrate. At this time, the region of the semiconductor substrate 1 sandwiched between the p + collector region 4 and the p + body region 5 becomes the n− drift layer 6.
　次に、半導体基板１の一方の表面の側にレジストマスク（図示せず）を形成し、そのレジストマスクをエッチングマスクとして、半導体基板１にドライエッチング処理を施すことにより、図４に示すように、トレンチ溝７を形成する。その後、そのレジストマスクを除去する。次に、半導体基板１の一方の表面の側に他のレジストマスク（図示せず）を形成し、そのレジストマスクをエッチングマスクとして、たとえば、リン等のｎ型不純物をトレンチ溝７の側部に選択的に拡散させて、熱処理を施すことにより、ｎ＋エミッタ領域１０を形成する。その後、他のレジストマスクを除去する。 Next, a resist mask (not shown) is formed on one surface side of the semiconductor substrate 1, and the semiconductor substrate 1 is dry-etched using the resist mask as an etching mask, as shown in FIG. Then, the trench groove 7 is formed. Thereafter, the resist mask is removed. Next, another resist mask (not shown) is formed on one surface side of the semiconductor substrate 1, and the resist mask is used as an etching mask, for example, n-type impurities such as phosphorus are formed on the side of the trench groove 7. The n + emitter region 10 is formed by selective diffusion and heat treatment. Thereafter, the other resist mask is removed.
　次に、トレンチ溝７の底部および側壁を選択的に酸化することにより、ゲート酸化膜８を形成する。次に、スパッタ法等の物理成膜法によって、ゲート酸化膜８上にゲート電極９を形成する。次に、図５に示すように、スパッタ法等の物理成膜法によって、ｎ＋エミッタ領域１０に接するようにエミッタ電極１１を形成する。次に、エミッタ電極１１を覆うように、半導体基板１の一方の表面の全面に、フィールド絶縁膜１２を形成する。次に、スパッタ法等の物理成膜法を用いて、ｐ＋コレクタ領域４に接するようにコレクタ電極１３を形成する。こうして、半導体基板１に、電力用半導体装置２０の一例として、ＩＧＢＴ２１が形成される。 Next, the gate oxide film 8 is formed by selectively oxidizing the bottom and side walls of the trench groove 7. Next, a gate electrode 9 is formed on the gate oxide film 8 by a physical film formation method such as sputtering. Next, as shown in FIG. 5, an emitter electrode 11 is formed so as to be in contact with the n + emitter region 10 by a physical film formation method such as sputtering. Next, a field insulating film 12 is formed on the entire surface of one surface of the semiconductor substrate 1 so as to cover the emitter electrode 11. Next, the collector electrode 13 is formed so as to be in contact with the p + collector region 4 by using a physical film formation method such as sputtering. Thus, an IGBT 21 is formed on the semiconductor substrate 1 as an example of the power semiconductor device 20.
　なお、ここでは、一般的なＩＧＢＴの製造工程を例に挙げて説明したが、製造方法としては、たとえば、拡散法に換えてイオン注入方法を用いてもよい。また、スパッタ法に換えて蒸着法を用いてもよく、ＩＧＢＴを製造する方法としては、上述した方法に限られない。 Note that, here, a general IGBT manufacturing process has been described as an example. However, as a manufacturing method, for example, an ion implantation method may be used instead of the diffusion method. Further, a vapor deposition method may be used instead of the sputtering method, and the method for manufacturing the IGBT is not limited to the method described above.
　次に、図６は、第３工程Ｓ３に対応する。図６に示すように、電子線１４を半導体基板１の一方の表面の側に照射する。このときの照射条件として、入射エネルギは、２５０ｋｅＶ～３ＭｅＶ程度であり、照射量は、１×１０１３ｃｍ－２～１×１０１５ｃｍ－２程度である。 Next, FIG. 6 corresponds to the third step S3. As shown in FIG. 6, the electron beam 14 is irradiated to one surface side of the semiconductor substrate 1. As irradiation conditions at this time, the incident energy is about 250 keV to 3 MeV, and the irradiation amount is about 1 × 10 13 cm −2 to 1 × 10 15 cm −2 .
　なお、目的とする電力用半導体装置の規格（スイッチング速度、オン抵抗）に応じて、入射エネルギと照射量を変化させる。たとえば、高速スイッチング仕様の電力用半導体装置の場合には、欠陥を多く生成するために、電子線の入射エネルギおよび照射量のそれぞれの値を高く設定する。また、電子線の入射エネルギの範囲は、シリコン（半導体基板）に対する電子線の吸収線量の深さ依存性によって制限される。すなわち、電子線の半導体基板の表面と裏面とで、電子線の吸収量の差異を小さくするために、上記の入射エネルギの上限値と下限値を設定する。 In addition, incident energy and irradiation amount are changed according to the standard (switching speed, on-resistance) of the target power semiconductor device. For example, in the case of a power semiconductor device with high-speed switching specifications, in order to generate many defects, the values of the incident energy and the irradiation amount of the electron beam are set high. The range of the incident energy of the electron beam is limited by the depth dependency of the absorbed dose of the electron beam with respect to silicon (semiconductor substrate). That is, the upper limit value and the lower limit value of the incident energy are set in order to reduce the difference in the amount of absorption of the electron beam between the front surface and the back surface of the semiconductor substrate.
　上述した電子線の照射条件では、電子線を照射した際の試料（半導体基板等）の温度の上昇は数十℃程度である。このため、電子線を照射する際の試料の温度の制御は、特に必要ではなく、たとえば、室温のもとで照射する処理を行ってよい。電子線を半導体基板１に照射することによって、半導体基板１には、格子欠陥、複合欠陥および不純物欠陥が生成される。複合欠陥として、たとえば、空孔－Ｖ族元素対に起因するとされるＥセンタが生成される。不純物欠陥として、たとえば、炭素－炭素対に起因するとされるＧセンタ、または、酸素－炭素対に起因するとされるＣセンタが生成される。 Under the electron beam irradiation conditions described above, the temperature rise of the sample (semiconductor substrate, etc.) when irradiated with the electron beam is about several tens of degrees Celsius. For this reason, it is not particularly necessary to control the temperature of the sample when irradiating the electron beam. For example, a process of irradiating at room temperature may be performed. By irradiating the semiconductor substrate 1 with an electron beam, lattice defects, composite defects, and impurity defects are generated in the semiconductor substrate 1. As a composite defect, for example, an E center that is attributed to a vacancy-group V element pair is generated. As the impurity defect, for example, a G center attributed to a carbon-carbon pair or a C center attributed to an oxygen-carbon pair is generated.
　シリコンのバンドギャップ内における、Ｅセンタの再結合準位はＥｃ－０．４３ｅＶであり、Ｇセンタの再結合準位はＥｖ＋０．１７ｅＶであり、Ｃセンタの再結合準位はＥｖ＋０．３３ｅＶである。なお、Ｅｃは伝導帯端下端のエネルギであり、Ｅｖは価電子帯端上端のエネルギである。 Within the silicon bandgap, the E center recombination level is Ec−0.43 eV, the G center recombination level is Ev + 0.17 eV, and the C center recombination level is Ev + 0.33 eV. . Ec is the energy at the lower end of the conduction band, and Ev is the energy at the upper end of the valence band.
　半導体基板中に生成された欠陥は、キャリアの再結合寿命を短縮させる効果があり、特に、シリコン（半導体基板）のバンドギャップ（１．１１ｅＶ）内において、バンドギャップの中央付近に欠陥準位を有する欠陥が、キャリアの再結合寿命を短縮させる効果が高いとされる。 Defects generated in the semiconductor substrate have the effect of shortening the recombination lifetime of carriers, and in particular, in the band gap (1.11 eV) of silicon (semiconductor substrate), a defect level is formed near the center of the band gap. It is said that the defects possessed have a high effect of shortening the recombination lifetime of the carriers.
　このため、電力用半導体装置のスイッチング特性を高速化させるためには、欠陥としては、Ｇセンタよりも、Ｃセンタの方が望ましいといえる。また、Ｅセンタは、シリコンのミッドギャップに近い準位を有するため、逆バイアスリークの原因になるため望ましくない。そこで、実施の形態に係る電力用半導体装置では、ドリフト層に蓄積されたキャリアの再結合寿命を短縮させるために、欠陥として、Ｃセンタを積極的に用いる。 Therefore, in order to increase the switching characteristics of the power semiconductor device, it can be said that the C center is preferable to the G center as a defect. The E center is not desirable because it has a level close to the mid gap of silicon and causes reverse bias leakage. Therefore, in the power semiconductor device according to the embodiment, the C center is positively used as a defect in order to shorten the recombination lifetime of the carriers accumulated in the drift layer.
　また、第３工程が終了した後では、半導体基板１中に、格子欠陥または複合欠陥も残留している。これらの欠陥は熱耐性が低く、電力用半導体装置に高い電流密度をもって通電した際に発生する電流または熱によって消滅するため、たとえば、電力用半導体装置を高い電流密度をもって長時間通電する際に特性が変化することになる。 In addition, after the third step is completed, lattice defects or composite defects remain in the semiconductor substrate 1. These defects are low in heat resistance and disappear due to current or heat generated when the power semiconductor device is energized with a high current density. For example, characteristics when a power semiconductor device is energized for a long time with a high current density. Will change.
　このため、第４の工程では、通電前に熱耐性が低い欠陥を熱処理によって消滅させるために、通常より過酷な熱処理を行う。発明者らの評価によれば、半導体基板１に、たとえば、２５０℃以上４００℃以下、好ましくは、３００℃以上４００℃以下の温度のもとで数時間の熱処理を施すことで、格子欠陥または複合欠陥の大部分を消滅させることができること、または、電気的に不活性にすることができることが判明した。 For this reason, in the fourth step, heat treatment that is severer than usual is performed in order to eliminate defects with low heat resistance by heat treatment before energization. According to the evaluation of the inventors, the semiconductor substrate 1 is subjected to heat treatment for several hours at a temperature of 250 ° C. or higher and 400 ° C. or lower, preferably 300 ° C. or higher and 400 ° C. or lower. It has been found that the majority of complex defects can be extinguished or made electrically inactive.
　熱処理を行う時間は、半導体基板中の不純物濃度と、半導体基板に照射された電子線の照射量とに依存性する。たとえば、不純物濃度が高い場合には、不純物欠陥が形成されやすくなることで、格子欠陥または複合欠陥が少なくなるため、熱処理時間を短く設定する。一方、電子線の照射量が多い場合には、格子欠陥または複合欠陥が多くなるため、熱処理時間を長く設定する。 The time for performing the heat treatment depends on the impurity concentration in the semiconductor substrate and the dose of the electron beam irradiated on the semiconductor substrate. For example, when the impurity concentration is high, impurity defects are easily formed, and lattice defects or composite defects are reduced. Therefore, the heat treatment time is set short. On the other hand, when the electron beam irradiation amount is large, the number of lattice defects or composite defects increases, so the heat treatment time is set longer.
　熱処理は、電力用半導体装置の電極材料の酸化を抑制するために、窒素等の不活性ガス中で行うのが望ましい。この熱処理によって、残留している格子欠陥および複合欠陥の大部分とＧセンタとが消滅することになる。 The heat treatment is preferably performed in an inert gas such as nitrogen in order to suppress oxidation of the electrode material of the power semiconductor device. By this heat treatment, most of the remaining lattice defects and composite defects and the G center disappear.
　このように、上述した電力用半導体装置の製造方法では、半導体基板中に生成した種々の欠陥のうち、Ｃセンタを効率的に残留させることで、電力用半導体装置におけるドリフト層に蓄積されたキャリアの再結合寿命を短縮させることができ、電力用半導体装置の高速化を図ることができる。 As described above, in the method for manufacturing the power semiconductor device described above, among the various defects generated in the semiconductor substrate, the carriers accumulated in the drift layer in the power semiconductor device can be obtained by efficiently remaining the C center. The recombination lifetime can be shortened, and the speed of the power semiconductor device can be increased.
　次に、上述した電力用半導体装置の効果と、半導体基板中の炭素濃度および酸素濃度の規定値の根拠について補足説明する。 Next, a supplementary explanation will be given of the effects of the above-described power semiconductor device and the basis of the prescribed values of carbon concentration and oxygen concentration in the semiconductor substrate.
　第１の効果は、Ｃセンタの高い生成効率が得られることにある。上述したように、Ｃセンタは、Ｇセンタと比較して、キャリアを再結合させて寿命を短縮させる効果が高いため、Ｃセンタの生成効率を高くすることが望まれる。ここでいう、生成効率とは、電子線の照射量に対するＣセンタの比であり、この比を高くすることを意味する。生成効率を高くすることで、電子線の照射量を少なくすることができ、製造工程の簡素化に寄与することができる。 The first effect is that a high generation efficiency of the C center can be obtained. As described above, the C center is more effective in reducing the lifetime by recombining the carriers as compared with the G center. Therefore, it is desired to increase the generation efficiency of the C center. Here, the generation efficiency is the ratio of the C center to the electron beam irradiation dose, and means to increase this ratio. By increasing the generation efficiency, the amount of electron beam irradiation can be reduced, which can contribute to simplification of the manufacturing process.
　発明者らは、Ｃセンタの濃度と半導体基板中の酸素濃度との関係と、Ｇセンタの濃度と半導体基板中の酸素濃度との関係について、それぞれ評価を行った。その評価について説明する。 The inventors evaluated the relationship between the C center concentration and the oxygen concentration in the semiconductor substrate, and the relationship between the G center concentration and the oxygen concentration in the semiconductor substrate, respectively. The evaluation will be described.
　まず、半導体基板として、炭素濃度をほぼ一定の濃度（３×１０１４ｃｍ－３～９×１０１４ｃｍ－３程度）とし、酸素濃度を、１×１０１５ｃｍ－３～１×１０１７ｃｍ－３程度の範囲内で振り分けた半導体基板を使用した。その半導体基板に、照射エネルギを７５０ｋｅＶ、照射量を１×１０１４ｃｍ－２とした照射条件のもとで、電子線を照射し、それぞれの半導体基板中のＣセンタの濃度とＧセンタの濃度とを、ＰＬ（Photoluminescence）法によって測定した。このＰＬ法では、フォトルミネッセンスの強度によって、半導体基板内の欠陥の分布および濃度等に関する情報を取得することができる。 First, as a semiconductor substrate, the carbon concentration is set to a substantially constant concentration (about 3 × 10 14 cm −3 to 9 × 10 14 cm −3 ), and the oxygen concentration is set to 1 × 10 15 cm −3 to 1 × 10 17 cm. A semiconductor substrate distributed within a range of about −3 was used. The semiconductor substrate was irradiated with an electron beam under irradiation conditions of an irradiation energy of 750 keV and an irradiation amount of 1 × 10 14 cm −2, and the C center concentration and the G center concentration in each semiconductor substrate. Were measured by PL (Photoluminescence) method. In this PL method, information on the distribution and concentration of defects in the semiconductor substrate can be acquired based on the intensity of photoluminescence.
　評価結果を図７および図８に示す。図７では、Ｃセンタの濃度と半導体基板中の酸素濃度との関係を示す。また、図８では、Ｇセンタの濃度と半導体基板中の酸素濃度との関係を示す。図７に示すように、半導体基板中の酸素濃度が高いほど、Ｃセンタの濃度が高くなっており、Ｃセンタの生成が促進されていることがわかる。一方、図８に示すように、半導体基板中の酸素濃度が高いほど、Ｇセンタの濃度が低くなっており、Ｇセンタの生成が抑制されていることがわかる。このことから、半導体基板中における炭素濃度と酸素濃度とを規定することで、不純物欠陥（ＧセンタおよびＣセンタ）を制御できることが判明した。 Evaluation results are shown in FIG. 7 and FIG. FIG. 7 shows the relationship between the C center concentration and the oxygen concentration in the semiconductor substrate. FIG. 8 shows the relationship between the concentration of the G center and the oxygen concentration in the semiconductor substrate. As shown in FIG. 7, it can be seen that the higher the oxygen concentration in the semiconductor substrate is, the higher the concentration of the C center is, and the generation of the C center is promoted. On the other hand, as shown in FIG. 8, it can be seen that the higher the oxygen concentration in the semiconductor substrate, the lower the concentration of the G center, and the generation of the G center is suppressed. From this, it was found that impurity defects (G center and C center) can be controlled by defining the carbon concentration and the oxygen concentration in the semiconductor substrate.
　Ｃセンタの生成効率を高くするためには、半導体基板中の酸素濃度が高いほど望ましいが、半導体基板（単結晶シリコン）に対する酸素原子の室温下における固溶度の制約からは、酸素濃度は、２×１０１８ｃｍ－３（上限値）以下に規定することが望ましいことがわかった。 In order to increase the generation efficiency of the C center, the higher the oxygen concentration in the semiconductor substrate, the better. However, from the limitation of the solubility of oxygen atoms in the semiconductor substrate (single crystal silicon) at room temperature, the oxygen concentration is It has been found that it is desirable to specify 2 × 10 18 cm −3 (upper limit) or less.
　炭素濃度については、過剰に少ないと半導体基板中にＣセンタが生成されないため、Ｃセンタが確実に生成されるには、炭素濃度を１×１０１４ｃｍ－３以上に規定することが望ましいことがわかった。一方、一般に生産されている半導体基板中の炭素濃度を考慮すると、炭素濃度の上限値は１×１０１６ｃｍ－３であることが望ましい。炭素濃度がこの上限値を超えると、ＣセンタよりもＧセンタの生成が促進される。したがって、炭素濃度の範囲としては、１×１０１４ｃｍ－３以上１×１０１６ｃｍ－３以下に規定することが望ましいことがわかった。 If the carbon concentration is excessively small, the C center is not generated in the semiconductor substrate. Therefore, in order to surely generate the C center, it is desirable to define the carbon concentration to be 1 × 10 14 cm −3 or more. all right. On the other hand, in consideration of the carbon concentration in a generally produced semiconductor substrate, the upper limit value of the carbon concentration is preferably 1 × 10 16 cm −3 . If the carbon concentration exceeds this upper limit, the generation of the G center is promoted more than the C center. Therefore, it was found that the carbon concentration range is preferably specified to be 1 × 10 14 cm −3 or more and 1 × 10 16 cm −3 or less.
　次に、第２の効果は、Ｃセンタの熱耐性を高くできることにある。発明者らは、さらに、Ｃセンタの濃度と熱処理温度（アニール温度）との関係について評価を行った。その評価について説明する。まず、半導体基板として、上述した評価と同様に、炭素濃度をほぼ一定の濃度とし、酸素濃度を、所定の範囲内で振り分けた半導体基板を使用し、その半導体基板に所定の照射条件のもとで電子線を照射した。その半導体基板に、大気雰囲気中において、温度（最高温度～５００℃）を振り分けて２０分間の熱処理を施し、それぞれの半導体基板中のＣセンタの濃度をＰＬ法によって測定した。 Next, the second effect is that the heat resistance of the C center can be increased. The inventors further evaluated the relationship between the C center concentration and the heat treatment temperature (annealing temperature). The evaluation will be described. First, as in the evaluation described above, a semiconductor substrate having a substantially constant carbon concentration and an oxygen concentration distributed within a predetermined range is used as the semiconductor substrate, and the semiconductor substrate is subjected to predetermined irradiation conditions. And irradiated with an electron beam. The semiconductor substrate was subjected to a heat treatment for 20 minutes by distributing the temperature (maximum temperature to 500 ° C.) in the air atmosphere, and the concentration of C center in each semiconductor substrate was measured by the PL method.
　評価結果を図９および図１０に示す。図９では、Ｃセンタの濃度とアニール温度との関係を示す。また、図１０では、Ｇセンタの濃度とアニール温度との関係を示す。図９に示すように、約２５０℃の熱処理を施した場合には、いずれの半導体基板についても、Ｃセンタの濃度は減少していないことがわかる。また、酸素濃度が高い半導体基板ほど、高温度の熱処理によってもＣセンタの濃度が減少しにくいことがわかる。これは、半導体基板中の不純物濃度を規定することで、Ｃセンタの熱耐性を向上できることを意味する。Ｃセンタの熱耐性を高めることで、半導体装置の通電時の変化を抑制するとともに、第４工程における熱処理の温度を高く設定することができ、不要な欠陥を短時間で消滅させることができる。 Evaluation results are shown in FIG. 9 and FIG. FIG. 9 shows the relationship between the C center concentration and the annealing temperature. FIG. 10 shows the relationship between the concentration of the G center and the annealing temperature. As shown in FIG. 9, it can be seen that when the heat treatment at about 250 ° C. is performed, the concentration of the C center does not decrease in any of the semiconductor substrates. It can also be seen that the semiconductor substrate with a higher oxygen concentration is less likely to decrease the C center concentration even by heat treatment at a higher temperature. This means that the thermal resistance of the C center can be improved by defining the impurity concentration in the semiconductor substrate. By increasing the heat resistance of the C center, it is possible to suppress changes during energization of the semiconductor device, set the temperature of the heat treatment in the fourth step high, and eliminate unnecessary defects in a short time.
　そこで、この効果を発現させることができる、半導体基板中の酸素濃度の下限値を、１×１０１６ｃｍ－３に規定した。したがって、上述した酸素濃度の上限値と併せて、半導体基板中の酸素濃度を、１×１０１６ｃｍ－３以上２×１０１８ｃｍ－３以下に規定した。 Therefore, the lower limit value of the oxygen concentration in the semiconductor substrate capable of exhibiting this effect is defined as 1 × 10 16 cm −3 . Therefore, the oxygen concentration in the semiconductor substrate is specified to be 1 × 10 16 cm −3 or more and 2 × 10 18 cm −3 or less together with the upper limit of the oxygen concentration described above.
　一方、図１０に示すように、Ｇセンタの濃度は、約１５０℃付近の熱処理によって消滅することがわかる。また、大部分の格子欠陥または複合欠陥は、２５０℃の温度のもとで熱処理を施すことによって、消滅するか、または、電気的に不活性になる（非特許文献１）。このため、２５０℃以上４００℃以下、好ましくは、３００℃以上４００℃以下の温度のもとで半導体基板に熱処理を施すことで、Ｃセンタを残存させながら、他のＧセンタ等の不純物欠陥、格子欠陥および複合欠陥を消滅させることができることがわかった。 On the other hand, as shown in FIG. 10, it can be seen that the concentration of the G center disappears by heat treatment at about 150 ° C. In addition, most lattice defects or composite defects disappear or become electrically inactive by heat treatment at a temperature of 250 ° C. (Non-patent Document 1). For this reason, by subjecting the semiconductor substrate to heat treatment at a temperature of 250 ° C. to 400 ° C., preferably 300 ° C. to 400 ° C., impurity defects such as other G centers, It was found that lattice defects and composite defects can be eliminated.
　次に、上述した製造方法を適用して製造された、ＩＧＢＴの特性について説明する。
　炭素濃度をほぼ一定にして、酸素濃度を変化させた半導体基板を用いてＩＧＢＴを試作した。試作したＩＧＢＴに対して、酸素濃度と、飽和エミッタ－コレクタ電圧の変化率との関係を評価した。ここで、変化率は、次のように定義される。まず、それぞれ検査用のゲート電圧およびエミッタ電圧を流したときの、コレクタ－エミッタ間電圧の値をＡ（初期値）とし、次に、それぞれ負荷試験用のゲート－エミッタ間電圧およびコレクタ電流を流したときの、コレクタ－エミッタ間電圧の値をＢとすると、変化率は（Ｂ－Ａ）／Ａによって表される。ここでは、この変化率を用いて間接的にスイッチング特性の安定性を評価した。すなわち、飽和エミッタ－コレクタ電圧の変化率が小さいほど、電力用半導体装置として安定していることになる。 Next, characteristics of the IGBT manufactured by applying the above-described manufacturing method will be described.
An IGBT was fabricated using a semiconductor substrate in which the carbon concentration was substantially constant and the oxygen concentration was changed. The relationship between the oxygen concentration and the rate of change of the saturated emitter-collector voltage was evaluated for the prototype IGBT. Here, the rate of change is defined as follows. First, let the collector-emitter voltage value be A (initial value) when the inspection gate voltage and emitter voltage flow, respectively, and then load test gate-emitter voltage and collector current flow respectively. When the collector-emitter voltage value is B, the rate of change is represented by (BA) / A. Here, the stability of the switching characteristics was indirectly evaluated using this rate of change. That is, the smaller the rate of change of the saturated emitter-collector voltage, the more stable the power semiconductor device.
　その結果を図１１に示す。図１１に示すように、酸素濃度が高い半導体基板ほど、飽和エミッタ－コレクタ電圧の変化率が小さくなっていることがわかり、ＩＧＢＴのスイッチング特性が安定していることが判明した。 The result is shown in FIG. As shown in FIG. 11, it was found that the rate of change of the saturation emitter-collector voltage is smaller as the semiconductor substrate has a higher oxygen concentration, and the switching characteristics of the IGBT are more stable.
　上述した電力用半導体装置の製造方法の効果についてまとめる、まず、酸素は拡散係数が小さいために、半導体基板面内における酸素濃度の不均一性または不再現が発生しにくい。また、欠陥は、電子線を照射することによって形成するため、高い精度をもって再結合寿命を制御することが可能になる。また、電子線の照射によって生じる格子欠陥、複合欠陥および不純物欠陥のうち、熱耐性が高い不純物欠陥を残留させて、残りの格子欠陥または複合欠陥を消滅させるか、または、電気的に不活性な状態にすることができる。 Summarizing the effects of the above-described method for manufacturing a power semiconductor device, first, oxygen has a small diffusion coefficient, so that nonuniformity or non-reproduction of the oxygen concentration in the semiconductor substrate surface is unlikely to occur. Moreover, since the defect is formed by irradiating with an electron beam, the recombination lifetime can be controlled with high accuracy. Further, among lattice defects, composite defects and impurity defects caused by electron beam irradiation, impurity defects having high heat resistance are left to remain, and the remaining lattice defects or composite defects are extinguished or electrically inactive. Can be in a state.
　上述した炭素濃度（１×１０１４ｃｍ－３以上１×１０１６ｃｍ－３以下）および酸素濃度（１×１０１６ｃｍ－３以上２×１０１８ｃｍ－３以下）では、電子線を照射する際に、特定の不純物欠陥（Ｃセンタ）が効率的に発生することがわかった。Ｃセンタの再結合準位はＥｖ＋０．３３ｅＶである。この再結合準位は、金属由来の欠陥と比べて、リーク電流を小さくすることができる。 With the above-described carbon concentration (1 × 10 14 cm −3 or more and 1 × 10 16 cm −3 or less) and oxygen concentration (1 × 10 16 cm −3 or more and 2 × 10 18 cm −3 or less), the electron beam is irradiated. At that time, it was found that a specific impurity defect (C center) is efficiently generated. The recombination level of the C center is Ev + 0.33 eV. This recombination level can reduce the leakage current as compared with a metal-derived defect.
　また、Ｃセンタは、格子欠陥または複合欠陥と比べて、熱耐性が高い。さらに、通常の電力用半導体装置に適用される低不純物濃度の半導体基板を使用した場合と比べて、上述した酸素濃度および炭素濃度を有する半導体基板を用いた場合では、Ｃセンタの熱耐性を向上させることができることがわかった。 Also, the C center has higher heat resistance than lattice defects or composite defects. Furthermore, the heat resistance of the C center is improved when the semiconductor substrate having the above-described oxygen concentration and carbon concentration is used as compared with the case where a semiconductor substrate having a low impurity concentration applied to a normal power semiconductor device is used. I found out that
　したがって、上述した電力用半導体装置の製造方法では、熱耐性の低い欠陥を消滅させて、熱耐性の高いＣセンタを効率的に残すことができ、製造のばらつきを抑えることができるとともに、高い電流密度の通電においても、スイッチング特性を安定させることができる。これにより、長寿命の電力用半導体装置を提供することができる。 Therefore, in the above-described method for manufacturing a power semiconductor device, defects with low heat resistance can be eliminated, a C center with high heat resistance can be effectively left, manufacturing variations can be suppressed, and high current can be suppressed. The switching characteristics can be stabilized even when the current is supplied with a high density. Thereby, a long-life power semiconductor device can be provided.
　（第１変形例）
　上述した電力用半導体装置の製造方法では、半導体基板として、ＦＺ法によって成長させた、比較的酸素濃度の低い半導体基板を用い、第１工程において、半導体基板に酸素をさらに拡散させる場合について説明した。 (First modification)
In the power semiconductor device manufacturing method described above, the case where a semiconductor substrate grown by the FZ method and having a relatively low oxygen concentration is used as the semiconductor substrate and oxygen is further diffused into the semiconductor substrate in the first step has been described. .
　半導体基板としては、ＦＺ法によって成長させた半導体基板の他に、ＣＺ（Czochralski）法またはＭＣＺ（Magnetic-Field　Applied　Czochralski）法によって成長させたシリコンの半導体基板を用いてもよい。この場合には、図１２に示すように、ＣＺ法またはＭＣＺ法によって半導体基板を成長させる際に、高濃度の酸素を半導体基板に含有させることができるため、酸素を半導体基板に付加的に拡散させる第１工程を省略する。 As the semiconductor substrate, in addition to the semiconductor substrate grown by the FZ method, a silicon semiconductor substrate grown by the CZ (Czochralski) method or the MCZ (Magnetic-Field Applied Czochralski) method may be used. In this case, as shown in FIG. 12, when the semiconductor substrate is grown by the CZ method or the MCZ method, high concentration oxygen can be contained in the semiconductor substrate, so that oxygen is additionally diffused into the semiconductor substrate. The first step is omitted.
　ここで、ＦＺ法によって成長させた半導体基板と、ＣＺ法またはＭＣＺ法によって成長させた半導体基板との違いについて補足説明する。ＦＺ法によって成長させた半導体基板に酸素を拡散させた場合、酸素の濃度分布は、拡散面から離れるにしたがい減少する分布となる。拡散面と裏面とでは、酸素濃度は、最大で約２×１０１８ｃｍ－３から約１×１０１５ｃｍ－３程度に変化する。 Here, a supplementary description will be given of the difference between a semiconductor substrate grown by the FZ method and a semiconductor substrate grown by the CZ method or the MCZ method. When oxygen is diffused in a semiconductor substrate grown by the FZ method, the oxygen concentration distribution decreases as the distance from the diffusion surface increases. At the diffusion surface and the back surface, the oxygen concentration changes from about 2 × 10 18 cm −3 to about 1 × 10 15 cm −3 at maximum.
　一方、ＣＺ法またはＭＣＺ法によって成長させた半導体基板を用いた場合、半導体基板の成長中に酸素を一定の濃度で導入するため、酸素濃度の半導体基板の厚み方向の変化は１０％程度以内となる。その結果を、図１３の上のグラフに示す。一方、炭素濃度の半導体基板の厚み方向の変化は、ＦＺ法によって成長させた半導体基板でも、ＣＺ法またはＭＣＺ法によって成長させた半導体基板でも、１０％程度以内となる。 On the other hand, when a semiconductor substrate grown by the CZ method or the MCZ method is used, oxygen is introduced at a constant concentration during the growth of the semiconductor substrate. Therefore, the change in the thickness direction of the semiconductor substrate is less than about 10%. Become. The result is shown in the upper graph of FIG. On the other hand, the change of the carbon concentration in the thickness direction of the semiconductor substrate is within about 10% for both the semiconductor substrate grown by the FZ method and the semiconductor substrate grown by the CZ method or MCZ method.
　半導体基板に上述の電子線を照射した場合、Ｃセンタ濃度は、酸素濃度とほぼ同じ濃度分布を有する。その結果を図１３の下のグラフに示す。このように、ＦＺ法によって成長させた半導体基板と、ＣＺ法またはＭＣＺ法によって成長させた半導体基板とでは、半導体基板の厚み方向のＣセンタの濃度分布が異なる。 When the semiconductor substrate is irradiated with the above-described electron beam, the C center concentration has almost the same concentration distribution as the oxygen concentration. The result is shown in the lower graph of FIG. Thus, the concentration distribution of the C center in the thickness direction of the semiconductor substrate differs between the semiconductor substrate grown by the FZ method and the semiconductor substrate grown by the CZ method or the MCZ method.
　高速用途の電力用半導体装置の場合、スイッチ時の損失が小さいことが望まれる。すなわち、スイッチング速度が速いことが望ましい。半導体基板の全域（厚み方向）にＣセンタが分布していた方がスイッチング速度は速くなる。このため、ＣＺ法またはＭＣＺ法によって成長させた半導体基板を用いた図１２に示される製造方法が望ましい。一方、高耐圧用途の電力用半導体装置の場合、欠陥は半導体基板内の一部の領域に存在する状態が望ましい。このため、ＦＺ法によって成長させた半導体基板を用いる図１に示される製造方法が望ましい。 In the case of a power semiconductor device for high-speed applications, it is desirable that the loss during switching be small. That is, it is desirable that the switching speed is fast. The switching speed is faster when the C center is distributed over the entire area (thickness direction) of the semiconductor substrate. Therefore, the manufacturing method shown in FIG. 12 using a semiconductor substrate grown by the CZ method or the MCZ method is desirable. On the other hand, in the case of a power semiconductor device for high withstand voltage applications, it is desirable that the defect exists in a partial region in the semiconductor substrate. For this reason, the manufacturing method shown in FIG. 1 using a semiconductor substrate grown by the FZ method is desirable.
　したがって、第１変形例では、ＣＺ法またはＭＣＺ法によって成長させた半導体基板を用いることで、スイッチング特性の安定した電力用半導体装置を製造することができるとともに、製造工程として、第１工程を省くことができ、製造工程の削減に寄与することができる。 Therefore, in the first modification, by using a semiconductor substrate grown by the CZ method or the MCZ method, a power semiconductor device having stable switching characteristics can be manufactured, and the first step is omitted as a manufacturing process. Can contribute to the reduction of the manufacturing process.
　（第２変形例）
　上述した電力用半導体装置の製造方法では、半導体基板に形成される電力用半導体装置として、縦型のトレンチ構造を有するＩＧＢＴを例に挙げて説明した。 (Second modification)
In the above-described method for manufacturing a power semiconductor device, an IGBT having a vertical trench structure has been described as an example of a power semiconductor device formed on a semiconductor substrate.
　電力用半導体装置としては、ＩＧＢＴに限られるものではなく、図１４に示すように、ＩＧＢＴの他にダイオードを形成してもよい。ダイオードを形成する場合には、第２工程Ｓ２が、ＩＧＢＴを形成する工程から、ダイオードを形成する工程に置き換わるだけである。 The power semiconductor device is not limited to the IGBT, and a diode may be formed in addition to the IGBT as shown in FIG. In the case of forming a diode, the second step S2 simply replaces the step of forming the IGBT with the step of forming the diode.
　このようにして形成されたダイオードを図１５に示す。図１５に示すように、ダイオード３０では、半導体基板３１に、ｐ＋層３４、ｎ－ドリフト層３５およびｎ＋層３６が形成されている。ダイオード３０では、ｐ＋層３４に接触するようにアノード電極３２およびフィールド絶縁膜３３が形成されている。また、ｎ＋層３６に接触するようにカソード電極３７が形成されている。このダイオード３０においても、ＩＧＢＴの場合と同様に、スイッチング特性を高速化させながら、安定させることができる。なお、ＩＧＢＴおよびダイオードの他に、サイリスタまたはＧＴＯ等の電力用半導体装置を形成してもよい。 The diode formed in this way is shown in FIG. As shown in FIG. 15, in the diode 30, a p + layer 34, an n− drift layer 35 and an n + layer 36 are formed on a semiconductor substrate 31. In the diode 30, an anode electrode 32 and a field insulating film 33 are formed so as to be in contact with the p + layer 34. A cathode electrode 37 is formed so as to be in contact with the n + layer 36. This diode 30 can also be stabilized while increasing the switching characteristics as in the case of the IGBT. In addition to the IGBT and the diode, a power semiconductor device such as a thyristor or GTO may be formed.
　今回開示された実施の形態は例示であってこれに制限されるものではない。本発明は上記で説明した範囲ではなく、請求の範囲によって示され、請求の範囲と均等の意味および範囲でのすべての変更が含まれることが意図される。 The embodiment disclosed this time is an example, and the present invention is not limited to this. The present invention is defined by the terms of the claims, rather than the scope described above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
　本発明は、電力の制御等を行う、ＩＧＢＴ等の電力用半導体装置の製造方法に有効に利用される。 The present invention is effectively used in a method of manufacturing a power semiconductor device such as an IGBT that performs power control and the like.
　１　半導体基板、２　シリコン酸化膜、３　酸素、４　ｐ＋コレクタ層、５　ｐ＋ボディ層、６　ｎ－ドリフト層、７　トレンチ溝、８　ゲート酸化膜、９　ゲート電極、１０　ｎ+エミッタ層、１１　エミッタ電極、１２　フィールド絶縁膜、１３　コレクタ電極、１４　電子線、２０　電力用半導体装置、２１　ＩＧＢＴ、３０　ダイオード、３１　半導体基板、３２　アノード電極、３３　フィールド絶縁膜、３４　ｐ＋層、３５　ｎ－ドリフト層、３６　ｎ＋層、３７　カソード電極。 1 semiconductor substrate, 2 silicon oxide film, 3 oxygen, 4 p + collector layer, 5 p + body layer, 6 n− drift layer, 7 trench groove, 8 gate oxide film, 9 gate electrode, 10 n + emitter layer, 11 emitter electrode , 12 field insulating film, 13 collector electrode, 14 electron beam, 20 power semiconductor device, 21 IGBT, 30 diode, 31 semiconductor substrate, 32 anode electrode, 33 field insulating film, 34 p + layer, 35 n-drift layer, 36 n + layer, 37 cathode electrode.

Claims (6)

  1. 　炭素濃度が１×１０１４ｃｍ－３以上、１×１０１６ｃｍ－３以下であり、酸素濃度が１×１０１６ｃｍ－３以上、２×１０１８ｃｍ－３以下である領域を有するシリコンの半導体基板に、電力用半導体装置を形成する工程と、
    　前記半導体基板に電子線を照射する工程と、
    　前記半導体基板に、２５０℃以上、４００℃以下の温度条件のもとで熱処理を行う工程と
    を備えた、電力用半導体装置の製造方法。     The silicon having a region having a carbon concentration of 1 × 10 14 cm −3 or more and 1 × 10 16 cm −3 or less and an oxygen concentration of 1 × 10 16 cm −3 or more and 2 × 10 18 cm −3 or less. Forming a power semiconductor device on a semiconductor substrate;
    Irradiating the semiconductor substrate with an electron beam;
    A method for manufacturing a power semiconductor device, comprising: performing a heat treatment on the semiconductor substrate under a temperature condition of 250 ° C. or higher and 400 ° C. or lower.
  2. 　前記半導体基板を製造する工程は、
    　ＦＺ法によって、第１状態の半導体基板を成長させる工程と、
    　前記第１状態の半導体基板に酸素を拡散させることによって、前記半導体基板としての第２状態の半導体基板を形成する工程と
    を含む、請求項１記載の電力用半導体装置の製造方法。     The step of manufacturing the semiconductor substrate includes:
    Growing a semiconductor substrate in a first state by an FZ method;
    2. The method of manufacturing a power semiconductor device according to claim 1, further comprising: forming a second state semiconductor substrate as the semiconductor substrate by diffusing oxygen in the first state semiconductor substrate.
  3. 　前記第２状態の半導体基板を形成する工程は、
    　前記第１状態の半導体基板を覆うように、シリコン酸化膜を形成する工程と、
    　熱処理を施すことによって、前記シリコン酸化膜中の酸素を前記第１状態の半導体基板に拡散させる工程と
    を含む、請求項２記載の電力用半導体装置の製造方法。     The step of forming the semiconductor substrate in the second state includes
    Forming a silicon oxide film so as to cover the semiconductor substrate in the first state;
    3. The method for manufacturing a power semiconductor device according to claim 2, further comprising a step of diffusing oxygen in the silicon oxide film into the semiconductor substrate in the first state by performing heat treatment.
  4. 　前記領域は、前記半導体基板の厚み方向の全域とされた、請求項１記載の電力用半導体装置の製造方法。 2. The method of manufacturing a power semiconductor device according to claim 1, wherein the region is the entire region in the thickness direction of the semiconductor substrate.
  5. 　前記半導体基板として、ＣＺ法およびＭＣＺ法のいずれかの方法によって成長させた半導体基板を用いる、請求項４記載の電力用半導体装置の製造方法。 The method of manufacturing a power semiconductor device according to claim 4, wherein a semiconductor substrate grown by any one of a CZ method and an MCZ method is used as the semiconductor substrate.
  6. 　前記電力用半導体装置を形成する工程は、ＩＧＢＴおよびダイオードのいずれかを形成する工程を含む、請求項１記載の電力用半導体装置の製造方法。 The method of manufacturing a power semiconductor device according to claim 1, wherein the step of forming the power semiconductor device includes a step of forming either an IGBT or a diode.
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