WO2016150056A1 - 薄膜晶体管及其制造方法、显示装置 - Google Patents

薄膜晶体管及其制造方法、显示装置 Download PDF

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WO2016150056A1
WO2016150056A1 PCT/CN2015/085302 CN2015085302W WO2016150056A1 WO 2016150056 A1 WO2016150056 A1 WO 2016150056A1 CN 2015085302 W CN2015085302 W CN 2015085302W WO 2016150056 A1 WO2016150056 A1 WO 2016150056A1
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layer
drain
source
film transistor
thin film
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PCT/CN2015/085302
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English (en)
French (fr)
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王龙彦
李永谦
曹昆
李全虎
尹静文
张保侠
盖翠丽
吴仲远
王刚
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京东方科技集团股份有限公司
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Priority to US14/913,581 priority Critical patent/US9954070B2/en
Publication of WO2016150056A1 publication Critical patent/WO2016150056A1/zh

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Definitions

  • Embodiments of the present invention relate to a thin film transistor, a method of fabricating the same, and a display device.
  • a thin film transistor TFT Thin Film Transistor having a compound semiconductor represented by a metal oxide as an active layer material has advantages of high mobility, simple fabrication process, good uniformity of large area, low manufacturing cost, and the like, and is considered to be driving active.
  • Active Matrix Organic Light Emitting Diode AMOLED shows the most promising devices. Therefore, compound semiconductor TFTs have received much attention in the industry in recent years and are gradually being applied to AMOLED display panels.
  • the Back Channel Etch (BCE) process is a common process of amorphous silicon TFT, and only four times of photolithography can be used to form a TFT: the first photolithography process forms the gate of the TFT.
  • a second photolithography process forms a semiconductor layer of the TFT, a third photolithography process forms a source and a drain of the TFT, and a fourth photolithography process forms a passivation layer via of the TFT. Due to the number of masks required for the BCE process (four masks) and fewer process steps, it is widely used in existing amorphous silicon (a-Si) TFT panel production lines.
  • a compound semiconductor TFT should be manufactured in the same process as an amorphous silicon TFT, but a compound semiconductor active layer which is weak in chemical stability, whether dry etching or wet etching, is used.
  • the damage causes the device performance, that is, the BCE process damages the compound semiconductor active layer while forming the source and the drain. Therefore, the BCE process cannot be directly used to prepare the compound semiconductor thin film transistor, and needs to be added to protect the compound semiconductor.
  • a thin film transistor includes: a gate, an active layer, a source, and a drain, wherein the source and the drain are formed of at least two materials, the at least two materials A battery reaction can occur in the corresponding etching solution to be etched, and the material of the active layer is not corroded by the etching liquid.
  • a display device including the above thin film transistor is provided.
  • a method of fabricating a thin film transistor includes the following steps:
  • 1 is a composite film layer structure of a source and a drain according to an embodiment of the present invention
  • FIG. 2 is a schematic cross-sectional view of a thin film transistor according to an embodiment of the present invention.
  • 3(a) to 3(d) are schematic views 1 showing a process of fabricating a thin film transistor according to an embodiment of the present invention
  • 4(a) to 4(d) are schematic diagrams showing the preparation process of a thin film transistor according to another embodiment of the present invention.
  • At least one embodiment of the present invention provides a thin film transistor including: a gate, an active layer, a source and a drain, the source and the drain being formed of at least two materials, the source and the drain
  • the electrode forming material can be etched by a battery reaction in the corresponding etching liquid, and the etching liquid does not corrode the active layer.
  • the battery reaction here refers to the separation of two materials in the etching solution. The oxidation reaction and the reduction reaction are carried out, and the two materials are etched during the oxidation reaction and the reduction reaction.
  • At least one embodiment adopts: selecting the material of the source and the drain in the thin film transistor to be available in a certain electrolysis The material in which the battery reacts in the liquid, and the electrolyte corresponding to the battery reaction will occur, and the etching solution is used in the formation process of the source and the drain, and the active layer of the thin film transistor is used when the electrolyte is used as the etching liquid. Not corrosive. It can be understood that the above-mentioned etching liquid does not corrode the active layer, and the specific implementation also includes the case where the etching liquid has a very slow corrosion rate to the active layer and is approximately non-corrosive.
  • the source and drain forming materials should generally include at least two types, one of which generates a positive reaction of the battery positive electrode, the other which generates a chemical reaction of the negative electrode of the battery, and may also include other components having an auxiliary function for the battery reaction, or Other components that are not related to battery reactions.
  • the "corrosion” also includes the above factors and the mechanical or biological factors.
  • the material for forming the source and the drain includes at least two kinds of materials, but the specific film formation manner is not limited, and at least two kinds of materials may be used to form a mixed material film; or a multilayer film may be stacked, and each film is a material. form.
  • the material for forming the source and the drain can be etched by the battery reaction in the corresponding etching solution, and the etching solution is The active layer is not corroded, so that the thin film transistor which originally needs to increase the etching barrier formation process can be directly prepared by the back channel etching process without increasing the etching barrier layer, thereby reducing the number of patterning processes and reducing manufacturing. cost.
  • the battery reaction can simultaneously remove the two layers of materials, and the layers of materials are not separately etched separately, and the battery has a fast etching speed and saves etching time.
  • the source and drain of the thin film transistor are formed by two materials that can react in a certain electrolyte, and the source and the drain are formed by the latter film formation method, as shown in FIG.
  • the method includes: a first film layer 101 formed by one of the two materials, and a second film layer 102 formed by another material of the two materials; the second film layer 102 covers the first Above the film layer 101, the second film layer 102 is provided with small holes for facilitating the penetration of the etching liquid.
  • the second film layer 102 The material of the first film layer 101 can simultaneously generate a battery reaction in the etching liquid (ie, the corresponding electrolyte), speed up the etching rate without increasing the concentration of the etching liquid, and reduce the time for the substrate to be immersed in the etching liquid. Further reducing the risk of the active layer being damaged by the etching solution.
  • the source and drain described above are formed of two materials, including aluminum and indium tin oxide;
  • the etching liquid ie, the electrolyte in which the two materials react with a battery
  • the alkaline solution such as hydrogen peroxide.
  • the specific etching principle is as follows:
  • Cathode In 2 O 3 +3H 2 O+6e ⁇ 2In 3+ +6OH - 2H 2 O+2e ⁇ 2OH - +H 2 , at which time the corresponding active layer is etched away from the alkaline etching solution (or A compound semiconductor is formed with a very slow etching speed.
  • the compound semiconductor includes indium gallium zinc oxide, indium titanium zinc oxide, indium tin zinc oxide, zinc tin oxide, aluminum zinc tin oxide, aluminum zinc oxide, gallium zinc oxide, cadmium sulfide, selenium One or more of cadmium, cadmium telluride, gallium nitride, gallium phosphide, gallium arsenide and molybdenum sulfide.
  • the scheme provided in the above embodiment is also applicable to a TFT in which an active layer is formed based on black phosphorus.
  • the thin film transistor further includes: a metal layer (not shown) provided on the source and the drain to provide protection for the source and the drain in a subsequent process, the metal layer having the source and the drain The same pattern as the drain.
  • the steps of cleaning, drying, etc. are further included, and then the subsequent steps of forming other layers are further required, and the cleaning liquid or other layer etching liquid is also mostly alkaline, and the source and the formed source are
  • the drain causes corrosion, for example, a metal layer having the same pattern as the source and drain is provided over the source and drain to solve the problem of source and drain corrosion.
  • the metal layer can be selected to be more stable in an alkaline solution and removed using an acidic etching solution.
  • At least one embodiment of the present invention also provides a method of fabricating a thin film transistor, comprising the steps of:
  • Forming a gate and a gate insulating layer may be formed by a patterning process, and the patterning process may include coating a photoresist, exposing, developing, etching, etc.;
  • the source and the drain comprising at least two materials capable of undergoing a battery reaction in the corresponding etching solution to be etched And the etching liquid does not corrode the active layer.
  • the compound semiconductor active layer in the BCE structure is easily engraved in the source and drain forming processes
  • the problem of etched liquid damage, the thin film transistor manufacturing method provided by at least one embodiment of the present invention can directly prepare a thin film transistor by using a back channel etching process without adding an etch barrier layer, thereby reducing the number of patterning processes and reducing the manufacturing cost. .
  • the method for fabricating the thin film transistor provided by at least one embodiment of the present invention is applicable to a thin film transistor having a bottom gate structure, but does not exclude a thin film transistor which is also applicable to a top gate structure.
  • the simple changes or substitutions of the steps and the sequence of the method for manufacturing the thin film transistor according to the actual situation are also included in the protection scope of the present invention.
  • the thin film transistor of the present embodiment includes a substrate 20, a gate electrode 21 disposed on the substrate 20 from bottom to bottom, a gate insulating layer 22, an active layer 23, a source electrode 241, a drain electrode 242, and passivation.
  • the active layer 23 includes: Indium Gallium Zinc Oxide (IGZO); the source 241 and the drain 242 are formed of two materials, aluminum and indium tin oxide, and the source 241 and the drain 242 include: aluminum.
  • the first film layer 101 is formed, the second film layer 102 is formed by indium tin oxide; the second film layer 102 is overlaid on the first film layer 101, and the second film layer 102 is provided with a small hole for facilitating the penetration of the etching liquid. .
  • the materials of the first film layer and the second film layer are not necessarily limited as such, and the first film layer may be formed of indium tin oxide, and the second film layer may be formed of aluminum.
  • the active layer material may also be other compound semiconductors that are not etched by an alkaline etching solution (or have a very slow etching rate), such as indium gallium zinc oxide, indium tin zinc oxide, indium titanium zinc oxide, zinc.
  • indium gallium zinc oxide, indium tin zinc oxide, indium titanium zinc oxide, zinc is not etched by an alkaline etching solution (or have a very slow etching rate), such as indium gallium zinc oxide, indium tin zinc oxide, indium titanium zinc oxide, zinc.
  • Some of the above materials (such as IGZO, ITZO, HIZO, etc.) contain indium In, theoretically, battery reactions occur, but due to G (gallium, Ga), T (tin, Sn), H ( ⁇ , Hf The compounds corresponding to these elements have high stability of gallium dioxide Ga 2 O 3 , tin oxide SnO 2 , and hafnium oxide HfO 2 . Therefore, these materials, such as IGZO, ITZO, HIZO, etc., are contained as the material of the active layer 23 Indium, but it does not participate in battery reactions or participate in battery reactions at a very slow rate, so they can all be considered as not corroded in alkaline etching solutions.
  • the active layer is IGZO
  • the material contains Ga 2 O 3 which increases the stability of the IGZO structure
  • the IGZO active layer hardly participates in the battery reaction in the alkaline etching solution, and it is considered that the IGZO is also not alkaline. Corrosion corrosion.
  • the active layer may be formed into a two-layer structure, the lower layer is made of a material containing In such as IGZO, and the upper layer is made of a material containing no In, such as ZTO, AZTO, or GZO, so that the active layer is ensured.
  • the In material does not participate in the battery reaction at all.
  • the above active layer may be formed of one or more of the above materials, but the specific film formation manner is not limited. If the active layer forming material is plural, the mixed material film may be formed from a plurality of materials of the above materials; or the multilayer film may be stacked, and each film is formed of one material, which is not limited in this embodiment.
  • a preparation process of the above thin film transistor is as follows:
  • Step 1 the substrate 20 is provided and a gate metal layer is deposited on the substrate 20, and the gate electrode 21 is formed by a patterning process.
  • a highly conductive film is deposited on the substrate 20, and then exposed and etched to form a bottom gate of the thin film transistor.
  • the material of the highly conductive film may be a metal or a transparent high conductive compound film as shown in Fig. 3 (a) and Fig. 4 (a).
  • Step 2 On the substrate 20 on which the previous process is performed, the gate insulating layer 22 of the thin film transistor, the semiconductor layer and the composite conductive film layer are deposited, and the pattern of the active layer 23 and the source electrode 241 and the drain electrode 242 is formed by a patterning process.
  • a gate insulating layer (Gate Insulator), a layer of compound semiconductor material (such as IGZO), and a set of composite conductive film layers (such as indium tin oxide ITO/aluminum Al) forming a source and a drain are sequentially deposited.
  • the gate insulating layer is an insulating material of a single layer or a multilayer composite structure, such as silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, an organic insulating medium, or the like.
  • the composite conductive film layer of the source and drain materials includes a first film layer 101 formed of Al, a second film layer 102 formed of ITO, and a second film layer 102 over the first film layer 101; or, first The film layer 101 is above the second film layer 102, that is, the first film layer 101 formed of ITO, and the second film layer 102 formed of Al, no matter which material layer is on, and the upper material layer is second. It is necessary to have minute pinholes on the film layer 102 for the etching solution to pass through (for example, Al or ITO can be grown by sputtering to form a pinhole structure therein) so that Al and ITO can be simultaneously in the next process. A battery reaction occurs when an alkaline solution is encountered.
  • the process of forming the second film layer 102 can be selected from sputtering, PECVD, and a solution process depending on the forming material.
  • the materials used in the present embodiment are aluminum and indium tin oxide, so a sputtering process is preferred.
  • Natural terrain can be controlled by controlling the deposition rate of the sputtering process (slightly faster than the normal deposition rate)
  • a photoresist coating, exposure, development, and etching process is performed.
  • the etching process is mainly performed on the composite conductive film layer and the IGZO semiconductor layer which form the source and the drain.
  • the etching of the IGZO semiconductor layer in this step can be performed according to the prior art, and can be dry etching or wet etching or a combination of the two; this step is for forming a composite conductive film layer of the source and the drain.
  • the etching is performed by wet etching, and the etching principle is performed by using the battery reaction described herein. Taking the source and drain composite layers formed by Al and ITO in this embodiment as an example, the etching solution passes through the small holes in the second film layer, and when the Al and ITO simultaneously encounter the alkaline solution, the battery reaction occurs:
  • the etching solution in this embodiment is: sodium hydroxide solution, or potassium hydroxide Solution, or tetramethylammonium hydroxide solution.
  • the active layer is mainly IGZO. Although IGZO contains In, the etching speed is very slow due to the presence of Ga 2 O 3 , IGZO is hardly corroded by alkali, and the IGZO active layer is not affected by etching.
  • a gate insulating layer, a compound semiconductor layer material layer, a composite conductive film layer may be deposited, and then the semiconductor layer and the composite conductive film layer are subjected to a first mask process to form an active layer pattern, as shown in FIG. 3 . (b); then a second masking process is performed on the composite conductive film layer to form a source and drain pattern, as shown in Fig. 3(c).
  • a conventional method may be employed: first depositing a semiconductor layer material layer, and then performing a first masking process on the semiconductor layer material layer to form an active layer pattern; then forming a composite conductive film layer, and performing a composite conductive film layer The secondary mask process forms a pattern of source and drain.
  • the first step is the same as the first step of the first preparation method.
  • Step 2 firstly deposits a gate insulating layer, a layer of compound semiconductor material, a set of composite conductive film layers forming source and drain electrodes, and then passes through a two-tone mask process (also known as a half exposure process, Half-Tone or Gray-Tone), a masking process is performed on the semiconductor layer and the composite conductive film layer to form an active layer and a source and drain pattern, thereby saving a mask.
  • a two-tone mask process also known as a half exposure process, Half-Tone or Gray-Tone
  • a photoresist is coated, and a half exposure is performed in a channel region (which needs to be etched to the active layer 23) to retain a certain thickness of the photoresist; a semiconductor layer other than the thin film transistor, composite The conductive film layer needs to be completely etched, the photoresist of the corresponding region is fully exposed; the source and drain of the thin film transistor are preset The position is not etched, and the photoresist of the entire thickness is retained, and the photoresist of the corresponding region is not exposed, as shown in FIG. 4(b).
  • Step 3 depositing a passivation layer material, and forming a passivation layer 25 and a passivation layer via hole (generally above the drain) by a patterning process, as shown in FIG. 3(d) and FIG. 4(d).
  • a passivation layer is deposited, and then a photoresist is applied, exposed, developed, and etched to form contact holes of the electrodes (ie, passivation layer via holes), and the active layer of IGZO is passivated.
  • the passivation layer is an insulating material of a single layer or a multilayer composite structure, such as silicon oxide, silicon nitride, aluminum oxide, tantalum oxide, an organic insulating medium, or the like.
  • FIGS. 4(a) to 4(d) are second preparation methods, the difference being that when the source and drain active layers are formed
  • the first preparation method uses two mask processes
  • the second preparation method uses a one-time mask process.
  • the composite conductive film layer forming the source and the drain is not eroded in these processes, a layer may be deposited on the composite conductive film layer.
  • the conductive material acts as a protective layer, such as molybdenum (Mo) titanium (Ti), etc., which can block the occurrence of battery reaction. Therefore, the composite layer structure of the source and the drain can also be composed of a layer of electrically conductive material. In the upper sandwich structure, the conductive material may be a metal such as molybdenum (Mo) titanium (Ti) or the like.
  • the portion of the uppermost metal layer to be removed in the source and drain patterning is first etched away with an acidic etching solution.
  • an acidic etching solution By controlling the etching rate of the acidic etching solution, the composite conductive film layer is patterned by using an alkaline solution after the portion of the uppermost metal layer to be etched is completely removed, or when the second film layer is slightly overcut. Forming a source and a drain.
  • This scheme can be applied to both the first preparation scheme and the second preparation scheme.
  • the composite conductive film layer of the second preparation scheme can also be formed by a sputtering process.
  • the thin film transistor and the preparation method thereof provided by at least one embodiment of the present invention can directly prepare a thin film transistor by using a back channel etching process without adding an etch barrier layer, thereby reducing the number of patterning processes and reducing the manufacturing cost.
  • a specific implementation may form a via hole on the gate insulating layer by applying a photoresist, exposure, development, and etching process before depositing the composite conductive film layer forming the source and the drain.
  • the source or the drain is directly connected to the gate through the hole; another specific implementation is to form a via on the passivation layer and the gate insulating layer (step 3), and then pass the source through another layer of highly conductive material
  • the pole or drain and the gate are connected together.
  • At least one embodiment of the present invention provides a display device comprising: any one of the above thin film transistors.
  • the display device has a small number of patterning processes and low cost.
  • the display device may be any product or component having a display function, such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the thin film transistor and the manufacturing method thereof and the display device provided by the embodiments of the present invention define a material for forming a source and a drain of the thin film transistor and an etching liquid used: the source and the drain are formed of at least two materials, and The source and drain forming materials can be etched by a battery reaction in the corresponding etchant, and the etchant does not corrode the active layer.
  • a new back channel TFT structure can be realized, which is particularly suitable for a compound semiconductor TFT using an oxide TFT as an example, and can solve an active layer in a TFT structure such as an oxide thin film transistor.
  • the problem of being easily corroded does not need to increase the etch barrier layer, and the thin film transistor can be directly prepared by the back channel etching process, thereby reducing the number of patterning processes and reducing the manufacturing cost.
  • the battery reaction can simultaneously remove the two layers of materials, and the layers of materials are not separately etched separately, and the battery has a fast etching speed and saves etching time.
  • the first and second words are used to classify similar items, and the first and second words do not limit the invention in terms of quantity, but only for an alternative manner.
  • the first and second words do not limit the invention in terms of quantity, but only for an alternative manner.

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Abstract

一种薄膜晶体管及其制造方法、显示装置。该薄膜晶体管包括：栅极(21)、有源层(23)、源极(241)和漏极(242)，所述源极(241)和漏极(242)由至少两种材料形成，所述源极(241)和漏极(242)的形成材料能在对应的刻蚀液中发生电池反应从而被刻蚀，且所述有源层(23)的材料不被该刻蚀液腐蚀。根据本发明实施例的薄膜晶体管及其制造方法能够解决有源层在源极和漏极的刻蚀工序中易被腐蚀的问题，从而能够采用背沟道刻蚀工艺制备薄膜晶体管器件，减少薄膜晶体管制造的工艺次数，节省制造成本。

Description

薄膜晶体管及其制造方法、显示装置 技术领域
本发明的实施例涉及一种薄膜晶体管及其制造方法、显示装置。
背景技术
以金属氧化物为代表的化合物半导体为有源层材料的薄膜晶体管TFT(Thin Film Transistor)具有迁移率高、制作工艺简单、大面积均匀性好、制造成本低等优点，被认为是驱动有源矩阵有机发光二极管(Active Matrix Organic Light Emitting Diode，AMOLED)显示最具潜力的器件。因此近年来化合物半导体TFT备受业界关注，并逐渐应用于AMOLED显示面板当中。
在TFT的制造技术中，背沟道刻蚀(Back Channel Etch,BCE)工艺是非晶硅TFT常见的工艺，只需四次光刻即可形成TFT：第一道光刻工艺形成TFT的栅极，第二道光刻工艺形成TFT的半导体层，第三道光刻工艺形成TFT的源极和漏极，第四道光刻工艺形成TFT的钝化层过孔。因BCE工艺需要掩膜版数目(四块掩膜版)和工艺步骤较少而被现有非晶硅(a-Si)TFT面板生产线广泛采用。以金属氧化物TFT为例，理论上，化合物半导体TFT的制造工艺应该与非晶硅TFT相同，但是无论是干法刻蚀还是湿法刻蚀都会对化学稳定性较脆弱的化合物半导体有源层造成损伤而最终影响器件性能，即BCE工艺在形成源极和漏极的同时会损伤化合物半导体有源层，因此，BCE工艺不能直接用于制备化合物半导体薄膜晶体管，需要增加用以保护化合物半导体有源层的刻蚀阻挡层的制备过程，但增加刻蚀阻挡层后，导致制备工艺所需的掩膜版数目增多，工艺变得复杂、成本随之提高。
发明内容
根据本发明的一个实施例提供一种薄膜晶体管，包括：栅极、有源层、源极和漏极，其中，所述源极和漏极由至少两种材料形成，所述至少两种材料能在对应的刻蚀液中发生电池反应从而被刻蚀，且所述有源层的材料不被该刻蚀液腐蚀。
根据本发明的另一个实施例提供一种显示装置，包括上述薄膜晶体管。
根据本发明的再一个实施例提供一种薄膜晶体管的制造方法，包括以下步骤：
提供衬底基板；
形成栅极和栅绝缘层；
形成有源层和源极、漏极，所述源极和漏极包括至少两种材料，所述至少两种材料能在对应的刻蚀液中发生电池反应从而被刻蚀，且所述有源层的材料不被所述刻蚀液腐蚀。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为本发明一实施例提供的源极和漏极的复合膜层结构；
图2为本发明一实施例提供的薄膜晶体管的截面结构示意图；
图3(a)～图3(d)为本发明一实施例提供的薄膜晶体管的制备过程示意图一；
图4(a)～图4(d)为本发明另一实施例提供的薄膜晶体管的制备过程示意图二。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明至少一实施例提供一种薄膜晶体管，该薄膜晶体管包括：栅极、有源层、源极和漏极，所述源极和漏极由至少两种材料形成，所述源极和漏极的形成材料能在对应的刻蚀液中发生电池反应从而被刻蚀，且，该刻蚀液对所述有源层不腐蚀。例如，这里的电池反应是指在刻蚀液中，两种材料分 别氧化反应和还原反应，在氧化反应和还原反应的过程中这两种材料被刻蚀。
针对TFT的有源层易被源极和漏极形成工序中使用的刻蚀液腐蚀的问题，本至少一实施例采用：将薄膜晶体管中源极和漏极的材料选择为可在某一电解液中发生电池反应的材料，同时将发生电池反应对应的电解液，在源极和漏极的形成工序中当成刻蚀液使用，且电解液作为刻蚀液使用时对薄膜晶体管的有源层不腐蚀。可以理解的是，上述刻蚀液对有源层不腐蚀的说法，在具体实施时还包括刻蚀液对有源层腐蚀速度非常慢，近似不腐蚀的情况。
另外，源极和漏极的形成材料一般应至少包括两种，其中一种发生电池正极化学反应，另一种发生电池负极化学反应，还可以包括其它对电池反应具有辅助功能的组分，或其他与电池反应不相干的组分。
需要说明的是，“该刻蚀液对所述有源层不腐蚀”是指有源层在所述刻蚀液中(或者在制作源极和漏极的工况条件下)，不会由于与其所处环境介质发生化学或者电化学作用等而引起变质和破坏，有源层的膜层的物理、化学性质也不会发生改变，或者即便发生改变但这种改变对TFT的影响小到可以忽略，其中的“腐蚀”也包括上述因素与力学因素或者生物因素的共同作用。
上述源极和漏极的形成材料包括至少两种，但具体成膜方式不做限定，可以上述的至少两种材料形成混合材料薄膜；也可以多层膜叠加，每一层膜为一种材料形成。无论如何只要保证在源极和漏极的形成工序中，用以形成源极和漏极的膜层材料能在对应的刻蚀液中发生电池反应从而被刻蚀，且，该刻蚀液对有源层不腐蚀，即可使得原本需要增加刻蚀阻挡层形成工序的薄膜晶体管，可以直接采用背沟道刻蚀工艺制备，不需要增加刻蚀阻挡层，因而可以减少构图工艺次数，降低制造成本。并且，形成源极和漏极时电池反应可以将两层材料同时去除，不用单独分开刻蚀各层材料，且电池反应刻蚀速度快，节省刻蚀时间。
示例性地，薄膜晶体管的源极和漏极由两种可在某种电解液中发生电池反应的材料形成，所述源极和漏极采用后一种成膜方式形成，具体如图1所示包括：所述两种材料中的其中一种材料形成的第一膜层101，所述两种材料中的另一种材料形成的第二膜层102；第二膜层102覆盖于第一膜层101之上，第二膜层102上设置有便于刻蚀液渗透的小孔。这样，第二膜层102、 第一膜层101的材料可以同时在刻蚀液(即对应的电解液)中发生电池反应，在不提高刻蚀液浓度的情况下加快刻蚀速率，减少基板在刻蚀液中浸泡的时间，进一步降低有源层被刻蚀液损伤的风险。
示例性地，上述的源极和漏极由两种材料形成，包括铝和氧化铟锡；所述刻蚀液(即这两种材料发生电池反应的电解液)为碱性溶液，例如氢氧化钠溶液，或者氢氧化钾溶液，或者四甲基氢氧化铵溶液。具体刻蚀原理如下：
阳极：Al+4OH-→H2AlO3 -+H2O+3e
阴极：In2O3+3H2O+6e→2In3++6OH-  2H2O+2e→2OH-+H2，此时对应的有源层由不受碱性刻蚀液刻蚀(或刻蚀速度很慢)的化合物半导体形成。
示例性地，化合物半导体包括铟镓锌氧化物、铟钛锌氧化物、铟锡锌氧化物、锌锡氧化物、铝锌锡氧化物、铝锌氧化物、镓锌氧化物、硫化镉、硒化镉、碲化镉、氮化镓、磷化镓、砷化镓和硫化钼中的一种或几种。除了前述的化合物半导体之外，上述实施例中提供的方案还适用于基于黑磷制作有源层的TFT中。
进一步地，所述的薄膜晶体管还包括：设置在源极和漏极之上，在后续工序中为源极和漏极提供防护的金属层(图中未示出)，金属层具有与源极和漏极相同的图形。
在形成源极和漏极后还包括清洗、烘干等步骤，之后还需要继续形成其他层的后续工序，清洗液或其他层刻蚀液也多为碱性，会对已形成的源极和漏极造成腐蚀，例如，在源极和漏极之上设置具有与源极和漏极相同图形的金属层，以解决源极和漏极腐蚀的问题。该金属层可以选择在碱性溶液中较稳定的Mo，并使用酸性刻蚀液去除。
本发明至少一实施例还提供一种薄膜晶体管的制造方法，包括以下步骤：
提供衬底基板；
形成栅极和栅绝缘层，例如，可以通过构图工艺形成栅极和栅绝缘层，构图工艺可以包括涂覆光刻胶、曝光、显影和刻蚀等；
沉积并通过构图工艺形成有源层、源极和漏极，所述源极和漏极包括至少两种材料，所述至少两种材料能在对应的刻蚀液中发生电池反应从而被刻蚀，且所述刻蚀液对所述有源层不腐蚀。
针对BCE结构中化合物半导体有源层在源极和漏极形成工序中易被刻 蚀液损伤的问题，本发明至少一实施例提供的薄膜晶体管制造方法，不需要增加刻蚀阻挡层，可以直接采用背沟道刻蚀工艺制备薄膜晶体管，因而可以减少构图工艺次数，降低制造成本。
需要说明的是，本发明至少一实施例提供的薄膜晶体管的制造方法，适用于底栅结构的薄膜晶体管，但同时也不排除也适用于顶栅结构的薄膜晶体管。具体实施时，本领域技术人员在本发明揭露的技术范围内，根据实际情况对薄膜晶体管的制造方法的各步骤及顺序进行的简单变化或替换，也应涵盖在本发明的保护范围之内。
为了本领域技术人员更好的理解本发明实施例提供的薄膜晶体管及其制备方法，下面通过具体的实施例对本发明提供的技术方案进行详细说明。
如图2所示，本实施例薄膜晶体管包括：基板20，自下而上设置在基板20上的栅极21、栅绝缘层22、有源层23、源极241、漏极242和钝化层25。有源层23包括：铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)；源极241和漏极242由铝和氧化铟锡两种材料形成，所述源极241和漏极242包括：铝形成的第一膜层101，氧化铟锡形成的第二膜层102；第二膜层102覆盖于第一膜层101之上，第二膜层102上设置有便于刻蚀液渗透的小孔。第一膜层和第二膜层的材料并不是必须被如此限定，也可以用氧化铟锡形成第一膜层，铝形成第二膜层。
上述有源层材料还可以是不受碱性刻蚀液刻蚀(或刻蚀速度很慢)的其他化合物半导体，如铟镓锌氧化物、铟锡锌氧化物、铟钛锌氧化物、锌锡氧化物、铝锌锡氧化物、铝锌氧化物、镓锌氧化物、硫化镉、硒化镉、碲化镉、氮化镓、磷化镓、砷化镓和硫化钼中的一种或几种；或者氧化锌ZnO的掺杂体系如HIZO、ITZO、ZTO、AZTO、AZO、GZO等等。以上材料中，有些材料(如IGZO、ITZO、HIZO等)虽然含有铟In元素，理论上也会发生电池反应，但由于G(镓，Ga)、T(锡，Sn)、H(铪，Hf)这些元素对应的化合物三氧化二镓Ga2O3、氧化锡SnO2、二氧化铪HfO2的稳定性高，因此这些材料如IGZO、ITZO、HIZO等作为有源层23的材料时虽含有铟，但也不会参与电池反应或参与电池反应的速率很慢，因此它们都可被认为在碱性刻蚀液中不会被腐蚀。例如上述有源层为IGZO时，因其中含有增加IGZO结构稳定性的材料Ga2O3，在碱性刻蚀液中IGZO有源层几乎不参与电池反 应，可认为IGZO也是不受碱性刻蚀液腐蚀。
在一些示例中，还可以把将有源层做成两层结构，下层采用IGZO等含有In的材料，而上层采用ZTO、AZTO、GZO等不含In的材料，这样可保证有源层中的In材料完全不会参与电池反应。
需要说明的是，上述有源层可以由上述材料中的一种或几种形成，但具体成膜方式不做限定。如果有源层形成材料为多种时，可以由上述材料中的多种材料形成混合材料薄膜；也可以多层膜叠加，每一层膜为一种材料形成，本实施例不做限定。
上述薄膜晶体管的一种制备工艺实施过程如下：
步骤一、首先，提供基板20并在基板20上沉积栅极金属层，并通过构图工艺形成栅极21。
例如，本步骤在基板20上沉积一层高导电薄膜，然后经曝光和刻蚀形成薄膜晶体管的底部栅极(Gate)。高导电薄膜的材料可以为金属或者透明高导电化合物薄膜，如图3(a)和图4(a)所示。
步骤二、在进行过前续工序的基板20上，沉积薄膜晶体管的栅绝缘层22、半导体层和复合导电膜层，进行构图工艺形成有源层23和源极241以及漏极242的图形。
本步骤首先依次沉积一层栅绝缘层(Gate Insulator)，一层化合物半导体材料层(如IGZO)，一组形成源极和漏极的复合导电膜层(如氧化铟锡ITO/铝Al)。所述栅绝缘层(Gate Insulator)为单层或者多层复合结构的绝缘材料，如氧化硅、氮化硅、氧化铝、氧化铪、有机绝缘介质等。源极和漏极材料的复合导电膜层包括由Al形成的第一膜层101，由ITO形成的第二膜层102，第二膜层102在第一膜层101之上；或者，第一膜层101在第二膜层102之上，即由ITO形成的第一膜层101，由Al形成的第二膜层102，无论哪一种材料层在上，在上的材料层即第二膜层102上均需要具有微小的针孔(Pinhole)以供刻蚀溶液穿过(例如，可以通过溅射生长Al或ITO以在其中形成针孔结构)，以便下一工序中Al和ITO同时遇到碱性溶液时，发生电池反应。形成第二膜层102的工艺根据形成材料可以从溅射、PECVD以及溶液制程中选择，本实施例中使用的材料为铝和氧化铟锡，所以优选溅射工艺。通过控制溅射工艺的沉积速度(略快于正常沉积速度)可以自然地形 成具有便于刻蚀液渗透的小孔的铝膜层或氧化铟锡膜层。因此，本步骤采用溅射的方法，在第一材料层(即第一膜层101)上制备第二材料层(即第二膜层102)。
然后，进行光刻胶涂覆、曝光、显影和刻蚀工艺。刻蚀工艺主要是对形成源极和漏极的复合导电膜层和IGZO半导体层进行。本步骤对IGZO半导体层的刻蚀可按现有技术进行，可以是干法刻蚀也可以是湿法刻蚀或两者的结合；本步骤对形成源极和漏极的复合导电膜层的刻蚀则是采用湿法刻蚀，刻蚀原理即采用本文所述的电池反应进行刻蚀。以本实施例中Al和ITO形成的源极和漏极复合材料层为例，刻蚀溶液穿过第二膜层上的小孔，Al和ITO同时遇到碱性溶液时，发生电池反应：
阳极：Al+4OH-→H2AlO3 -+H2O+3e
阴极：In2O3+3H2O+6e→2In3++6OH-  2H2O+2e→2OH-+H2，本实施例中的刻蚀液为：氢氧化钠溶液，或者氢氧化钾溶液，或者四甲基氢氧化铵溶液。有源层主要为IGZO，IGZO虽然含有In，但由于Ga2O3的存在，刻蚀速度很慢，IGZO近似不能被碱液腐蚀，IGZO有源层不受刻蚀影响。
具体而言，本步骤可先沉积栅绝缘层、化合物半导体层材料层、复合导电膜层，然后对半导体层和复合导电膜层进行第一次掩膜工艺形成有源层的图形，如图3(b)所示；然后对单独对复合导电膜层进行第二次掩膜工艺形成源极和漏极的图形，如图3(c)所示。
或者本步骤也可采用常规做法：先沉积半导体层材料层，然后对半导体层材料层进行第一次掩膜工艺形成有源层的图形；继而形成复合导电膜层，对复合导电膜层进行第二次掩膜工艺形成源极和漏极的图形。
在薄膜晶体管的另一种制备方法中，步骤一与第一种制备方法的步骤一相同。步骤二首先依次沉积一层栅绝缘层，一层化合物半导体材料层，一组形成源极和漏极的复合导电膜层，然后通过双色调掩膜工艺(又称半曝光工艺，Half-Tone或Gray-Tone)，对半导体层和复合导电膜层进行一次掩膜工艺，即可形成有源层和源极以及漏极的图形，可以节省一道掩模版。具体如图4(b)，涂覆光刻胶，在沟道区域(需要刻蚀至有源层23露出)进行半曝光，保留一定厚度的光刻胶；薄膜晶体管之外的半导体层、复合导电膜层需要全部刻蚀掉，对应区域的光刻胶全曝光；薄膜晶体管的源极和漏极预设 位置不进行刻蚀，保留全部厚度的光刻胶，对应区域的光刻胶不曝光，如图4(b)所示。进行第一次刻蚀，将薄膜晶体管之外的半导体层、源极和漏极全部刻蚀掉，形成有源层图形；进行灰化处理减薄剩余的光刻胶，使沟道区域的源极241和漏极242露出；进行第二次刻蚀，将沟道区域刻蚀至有源层23露出，形成源极241和漏极242的图形，如图4(c)所示。
步骤三、沉积钝化层材料，并通过构图工艺形成钝化层25以及钝化层过孔(一般位于漏极上方)，如图3(d)和图4(d)所示。
本步骤沉积一层钝化层(Passivation)，然后涂覆光刻胶、曝光、显影和刻蚀形成电极的接触孔(即钝化层过孔)，并对IGZO的有源层进行钝化保护。所述钝化层(Passivation)为单层或者多层复合结构的绝缘材料，如氧化硅、氮化硅、氧化铝、氧化铪、有机绝缘介质等。
图3(a)～图3(d)为第一种制备方法，图4(a)～图4(d)为第二种制备方法，二者区别在于形成源极、漏极有源层时第一种制备方法采用两次掩膜工艺，第二种制备方法采用一次掩膜工艺。
此外，因为工艺过程中的显影液和一些清洗液为碱性，为保证形成源极和漏极的复合导电膜层在这些过程中不被侵蚀，可以在复合导电膜层之上再沉积一层导电材料作为保护层，如钼(Mo)钛(Ti)等，这层材料可以阻挡电池反应的发生，因此，所述源极和漏极的复合层结构还可以为包含一层电导材料在最上层的三明治结构，这层导电材料可以为金属，如钼(Mo)钛(Ti)等。刻蚀上述三明治结构的源极和漏极时，先将最上层的金属层于源极和漏极图案化中所需去除的区域所对应的部分，用酸性刻蚀液刻蚀掉。通过控制酸性刻蚀液的刻蚀速度，在最上层的金属层需要被刻蚀的部分恰好完全去除之后，或者对第二膜层略有过刻时再采用碱性溶液图案化复合导电膜层，形成源极和漏极。该方案可以同时应用于第一种制备方案和第二种制备方案。另外，第二种制备方案的复合导电膜层也可以用溅射工艺形成。
本发明至少一实施例提供的薄膜晶体管及其制备方法，不需要增加刻蚀阻挡层，可以直接采用背沟道刻蚀工艺制备薄膜晶体管，因而可以减少构图工艺次数，降低制造成本。
在某些电路设计中，例如在OLED(有机发光二极管)的驱动电路中，需要将开关TFT的漏极与驱动TFT的栅极相连，这时制备工艺过程还应考 虑如何实现互连，一种具体实现方式可以在沉积形成源极和漏极的复合导电膜层之前，通过涂覆光刻胶、曝光、显影和刻蚀工艺在栅绝缘层上形成过孔，源极或漏极通过该孔直接与栅极连接；另一种具体实现方式在钝化层(Passivation)和栅绝缘层上形成过孔(步骤三)之后，通过另一层高导电材料将源极或漏极和栅极连接在一起。
本发明至少一实施例还提供一种显示装置，包括：上述的任意一种薄膜晶体管。所述显示装置构图工艺次数少，成本低。所述显示装置可以为：液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本发明实施例提供的薄膜晶体管及其制造方法、显示装置，对薄膜晶体管的源极和漏极的形成材料及使用的刻蚀液作出限定：源极和漏极采用至少两种材料形成，并且源极和漏极的形成材料能在对应的刻蚀液中发生电池反应从而被刻蚀，且，该刻蚀液对所述有源层不腐蚀。基于本发明实施例提供的方案，能够实现一种新的背沟道TFT结构，尤其适用于以氧化物TFT为例的化合物半导体TFT中，可以解决氧化物薄膜晶体管等TFT结构中的有源层在源极和漏极的刻蚀工序中易被腐蚀的问题，无需增加刻蚀阻挡层，薄膜晶体管可直接采用背沟道刻蚀工艺制备，因而可以减少构图工艺次数，降低制造成本。并且，形成源极和漏极时电池反应可以将两层材料同时去除，不用单独分开刻蚀各层材料，且电池反应刻蚀速度快，节省刻蚀时间。
为了便于清楚说明，在本发明中采用了第一、第二等字样对相似项进行类别区分，该第一、第二字样并不在数量上对本发明进行限制，只是对一种可选的方式的举例说明，本领域技术人员根据本发明公开的内容，想到的显而易见的相似变形或相关扩展均属于本发明的保护范围内。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。
本申请要求于2015年3月25日递交的中国专利申请第201510134375.1号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (19)

  1. 一种薄膜晶体管，包括：栅极、有源层、源极和漏极，其中，所述源极和漏极由至少两种材料形成，所述至少两种材料能在对应的刻蚀液中发生电池反应从而被刻蚀，且所述有源层的材料不被该刻蚀液腐蚀。
  2. 根据权利要求1所述的薄膜晶体管，其中，所述源极和漏极包括两种材料的叠层，其中：
    所述两种材料中的其中一种材料形成第一膜层，
    所述两种材料中的另一种材料形成第二膜层；
    所述第二膜层覆盖于所述第一膜层之上，所述第二膜层上设置有所述刻蚀液能够渗透的小孔。
  3. 根据权利要求1或2所述的薄膜晶体管，其中，所述两种材料包括铝和氧化铟锡；所述刻蚀液为碱性溶液。
  4. 根据权利要求3所述的薄膜晶体管，其中，所述碱性溶液为氢氧化钠溶液、氢氧化钾溶液和四甲基氢氧化铵溶液中的任一种。
  5. 根据权利要求1-3任一项所述的薄膜晶体管，其中，
    所述有源层包括不受所述碱性溶液腐蚀的化合物半导体材料。
  6. 根据权利要求5所述的薄膜晶体管，其中，所述化合物半导体材料包括铟镓锌氧化物、铟锡锌氧化物、铟钛锌氧化物、锌锡氧化物、铝锌锡氧化物、铝锌氧化物、镓锌氧化物、硫化镉、硒化镉、碲化镉、氮化镓、磷化镓、砷化镓和硫化钼中的一种或几种。
  7. 根据权利要求1-6任一项所述的薄膜晶体管，还包括：
    设置在所述源极和漏极之上的金属层，所述金属层具有与所述源极和漏极相同的图案。
  8. 根据权利要求7所述的薄膜晶体管，其中，所述金属层的材料包括金属钼和金属钛中的至少一种。
  9. 一种显示装置，包括：权利要求1-8任一项所述的薄膜晶体管。
  10. 一种薄膜晶体管的制造方法，包括以下步骤：
    提供衬底基板；
    形成栅极和栅绝缘层；
    形成有源层和源极、漏极，所述源极和漏极包括至少两种材料，所述至少两种材料能在对应的刻蚀液中发生电池反应从而被刻蚀，且所述有源层的材料不被所述刻蚀液腐蚀。
  11. 根据权利要求10所述的制造方法，其中，所述源极和漏极为两种材料形成的复合导电膜层。
  12. 根据权利要求11所述的制造方法，其中，所述复合导电膜层的制作步骤包括：
    形成第一材料层；以及
    采用溅射的方法，在所述第一材料层上制备第二材料层。
  13. 根据权利要求11或12所述的制造方法，所述形成有源层、源极和漏极包括：
    对所述复合导电膜层进行构图，其中所述复合导电膜层中的两种材料在对应的刻蚀液中发生电池反应从而被刻蚀。
  14. 根据权利要求13所述的制造方法，所述形成有源层、源极和漏极包括：
    在所述栅绝缘层上沉积化合物半导体薄膜和所述复合导电膜层；
    利用双色调掩膜工艺对所述化合物半导体薄膜和复合导电膜层进行构图，得到化合物半导体有源层和源极、漏极。
  15. 根据权利要求10-14任一项所述的制造方法，其中，所述至少两种材料包括铝和氧化铟锡；所述刻蚀液为碱性溶液。
  16. 根据权利要求13所述的制造方法，在所述形成复合导电膜层的步骤之后，及对所述复合导电膜层进行构图的步骤之前，还包括：
    在所述复合导电膜层上方形成金属层；
    利用刻蚀工艺对所述金属层进行构图，使得所述源极和漏极对应区域的金属层被保留。
  17. 根据权利要求14所述的制造方法，其中，所述化合物半导体薄膜的材料包括铟镓锌氧化物、铟锡锌氧化物、铟钛锌氧化物、锌锡氧化物、铝锌锡氧化物、铝锌氧化物、镓锌氧化物、硫化镉、硒化镉、碲化镉、氮化镓、磷化镓、砷化镓和硫化钼中的一种或几种。
  18. 根据权利要求16所述的制造方法，其中，所述金属层的材料包括金 属钼和金属钛中的至少一种。
  19. 根据权利要求12所述的制造方法，其中，所述第二材料层通过溅射的方法形成为其中具有刻蚀液能够渗透的小孔。
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